lib/librte_eal/linuxapp/kni/ethtool/igb/igb_regtest.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "LICENSE.GPL".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool register test data */
  29 struct igb_reg_test {
  30         u16 reg;
  31         u16 reg_offset;
  32         u16 array_len;
  33         u16 test_type;
  34         u32 mask;
  35         u32 write;
  36 };
  37
  38 /* In the hardware, registers are laid out either singly, in arrays
  39  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
  40  * most tests take place on arrays or single registers (handled
  41  * as a single-element array) and special-case the tables.
  42  * Table tests are always pattern tests.
  43  *
  44  * We also make provision for some required setup steps by specifying
  45  * registers to be written without any read-back testing.
  46  */
  47
  48 #define PATTERN_TEST    1
  49 #define SET_READ_TEST   2
  50 #define WRITE_NO_TEST   3
  51 #define TABLE32_TEST    4
  52 #define TABLE64_TEST_LO 5
  53 #define TABLE64_TEST_HI 6
  54
  55 /* i210 reg test */
  56 static struct igb_reg_test reg_test_i210[] = {
  57         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  58         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  59         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  60         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  61         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  62         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  63         /* RDH is read-only for i210, only test RDT. */
  64         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  65         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0003FFF0, 0x0003FFF0 },
  66         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  67         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
  68         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  69         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  70         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  71         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  72         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
  73         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
  74         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
  75         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
  76         { E1000_RA,        0, 16, TABLE64_TEST_LO,
  77                                                 0xFFFFFFFF, 0xFFFFFFFF },
  78         { E1000_RA,        0, 16, TABLE64_TEST_HI,
  79                                                 0x900FFFFF, 0xFFFFFFFF },
  80         { E1000_MTA,       0, 128, TABLE32_TEST,
  81                                                 0xFFFFFFFF, 0xFFFFFFFF },
  82         { 0, 0, 0, 0 }
  83 };
  84
  85 /* i350 reg test */
  86 static struct igb_reg_test reg_test_i350[] = {
  87         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  88         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  89         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
  90         /* VET is readonly on i350 */
  91         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  92         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  93         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  94         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
  95         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
  96         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
  97         /* RDH is read-only for i350, only test RDT. */
  98         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
  99         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 100         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 101         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 102         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 103         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 104         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 105         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 106         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 107         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 108         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 109         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 110         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 111         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 112         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 113         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 114         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 115         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 116                                                 0xFFFFFFFF, 0xFFFFFFFF },
 117         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 118                                                 0xC3FFFFFF, 0xFFFFFFFF },
 119         { E1000_RA2,       0, 16, TABLE64_TEST_LO,
 120                                                 0xFFFFFFFF, 0xFFFFFFFF },
 121         { E1000_RA2,       0, 16, TABLE64_TEST_HI,
 122                                                 0xC3FFFFFF, 0xFFFFFFFF },
 123         { E1000_MTA,       0, 128, TABLE32_TEST,
 124                                                 0xFFFFFFFF, 0xFFFFFFFF },
 125         { 0, 0, 0, 0 }
 126 };
 127
 128 /* 82580 reg test */
 129 static struct igb_reg_test reg_test_82580[] = {
 130         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 131         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 132         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 133         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 134         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 135         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 136         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 137         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 138         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 139         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 140         /* RDH is read-only for 82580, only test RDT. */
 141         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 142         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 143         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 144         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 145         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 146         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 147         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 148         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 149         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 150         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 151         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 152         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 153         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 154         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 155         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 156         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 157         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 158         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 159                                                 0xFFFFFFFF, 0xFFFFFFFF },
 160         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 161                                                 0x83FFFFFF, 0xFFFFFFFF },
 162         { E1000_RA2,       0, 8, TABLE64_TEST_LO,
 163                                                 0xFFFFFFFF, 0xFFFFFFFF },
 164         { E1000_RA2,       0, 8, TABLE64_TEST_HI,
 165                                                 0x83FFFFFF, 0xFFFFFFFF },
 166         { E1000_MTA,       0, 128, TABLE32_TEST,
 167                                                 0xFFFFFFFF, 0xFFFFFFFF },
 168         { 0, 0, 0, 0 }
 169 };
 170
 171 /* 82576 reg test */
 172 static struct igb_reg_test reg_test_82576[] = {
 173         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 174         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 175         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 176         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 177         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 178         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 179         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 180         { E1000_RDBAL(4),  0x40,  12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 181         { E1000_RDBAH(4),  0x40,  12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 182         { E1000_RDLEN(4),  0x40,  12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 183         /* Enable all queues before testing. */
 184         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 185         { E1000_RXDCTL(4), 0x40,  12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 186         /* RDH is read-only for 82576, only test RDT. */
 187         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 188         { E1000_RDT(4),    0x40,  12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 189         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
 190         { E1000_RXDCTL(4), 0x40,  12, WRITE_NO_TEST, 0, 0 },
 191         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 192         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 193         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 194         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 195         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 196         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 197         { E1000_TDBAL(4),  0x40,  12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 198         { E1000_TDBAH(4),  0x40,  12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 199         { E1000_TDLEN(4),  0x40,  12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 200         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 201         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 202         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 203         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 204         { E1000_RA,        0, 16, TABLE64_TEST_LO,
 205                                                 0xFFFFFFFF, 0xFFFFFFFF },
 206         { E1000_RA,        0, 16, TABLE64_TEST_HI,
 207                                                 0x83FFFFFF, 0xFFFFFFFF },
 208         { E1000_RA2,       0, 8, TABLE64_TEST_LO,
 209                                                 0xFFFFFFFF, 0xFFFFFFFF },
 210         { E1000_RA2,       0, 8, TABLE64_TEST_HI,
 211                                                 0x83FFFFFF, 0xFFFFFFFF },
 212         { E1000_MTA,       0, 128, TABLE32_TEST,
 213                                                 0xFFFFFFFF, 0xFFFFFFFF },
 214         { 0, 0, 0, 0 }
 215 };
 216
 217 /* 82575 register test */
 218 static struct igb_reg_test reg_test_82575[] = {
 219         { E1000_FCAL,   0x100,  1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 220         { E1000_FCAH,   0x100,  1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 221         { E1000_FCT,    0x100,  1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 222         { E1000_VET,    0x100,  1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 223         { E1000_RDBAL(0),       0x100,  4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 224         { E1000_RDBAH(0),       0x100,  4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 225         { E1000_RDLEN(0),       0x100,  4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 226         /* Enable all four RX queues before testing. */
 227         { E1000_RXDCTL(0),      0x100,  4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 228         /* RDH is read-only for 82575, only test RDT. */
 229         { E1000_RDT(0), 0x100,  4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 230         { E1000_RXDCTL(0),      0x100,  4, WRITE_NO_TEST, 0, 0 },
 231         { E1000_FCRTH,  0x100,  1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 232         { E1000_FCTTV,  0x100,  1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 233         { E1000_TIPG,   0x100,  1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 234         { E1000_TDBAL(0),       0x100,  4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 235         { E1000_TDBAH(0),       0x100,  4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 236         { E1000_TDLEN(0),       0x100,  4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 237         { E1000_RCTL,   0x100,  1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 238         { E1000_RCTL,   0x100,  1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
 239         { E1000_RCTL,   0x100,  1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
 240         { E1000_TCTL,   0x100,  1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 241         { E1000_TXCW,   0x100,  1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
 242         { E1000_RA,     0,      16, TABLE64_TEST_LO,
 243                                                 0xFFFFFFFF, 0xFFFFFFFF },
 244         { E1000_RA,     0,      16, TABLE64_TEST_HI,
 245                                                 0x800FFFFF, 0xFFFFFFFF },
 246         { E1000_MTA,    0,      128, TABLE32_TEST,
 247                                                 0xFFFFFFFF, 0xFFFFFFFF },
 248         { 0, 0, 0, 0 }
 249 };