lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_phy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*******************************************************************************
   3
   4   Intel 10 Gigabit PCI Express Linux driver
   5   Copyright(c) 1999 - 2012 Intel Corporation.
   6
   7   Contact Information:
   8   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   9   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  10
  11 *******************************************************************************/
  12
  13 #include "ixgbe_api.h"
  14 #include "ixgbe_common.h"
  15 #include "ixgbe_phy.h"
  16
  17 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  18 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  19 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  20 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  21 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  22 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  23 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  24 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  25 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  26 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  27 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  28
  29 /**
  30  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  31  *  @hw: pointer to the hardware structure
  32  *
  33  *  Initialize the function pointers.
  34  **/
  35 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  36 {
  37         struct ixgbe_phy_info *phy = &hw->phy;
  38
  39         /* PHY */
  40         phy->ops.identify = &ixgbe_identify_phy_generic;
  41         phy->ops.reset = &ixgbe_reset_phy_generic;
  42         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  43         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  44         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  45         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  46         phy->ops.check_link = NULL;
  47         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  48         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  49         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  50         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  51         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  52         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  53         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  54         phy->sfp_type = ixgbe_sfp_type_unknown;
  55         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  56         return 0;
  57 }
  58
  59 /**
  60  *  ixgbe_identify_phy_generic - Get physical layer module
  61  *  @hw: pointer to hardware structure
  62  *
  63  *  Determines the physical layer module found on the current adapter.
  64  **/
  65 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  66 {
  67         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  68         u32 phy_addr;
  69         u16 ext_ability = 0;
  70
  71         if (hw->phy.type == ixgbe_phy_unknown) {
  72                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  73                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
  74                                 hw->phy.addr = phy_addr;
  75                                 ixgbe_get_phy_id(hw);
  76                                 hw->phy.type =
  77                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  78
  79                                 if (hw->phy.type == ixgbe_phy_unknown) {
  80                                         hw->phy.ops.read_reg(hw,
  81                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
  82                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
  83                                                   &ext_ability);
  84                                         if (ext_ability &
  85                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
  86                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
  87                                                 hw->phy.type =
  88                                                          ixgbe_phy_cu_unknown;
  89                                         else
  90                                                 hw->phy.type =
  91                                                          ixgbe_phy_generic;
  92                                 }
  93
  94                                 status = 0;
  95                                 break;
  96                         }
  97                 }
  98                 /* clear value if nothing found */
  99                 if (status != 0)
 100                         hw->phy.addr = 0;
 101         } else {
 102                 status = 0;
 103         }
 104
 105         return status;
 106 }
 107
 108 /**
 109  *  ixgbe_validate_phy_addr - Determines phy address is valid
 110  *  @hw: pointer to hardware structure
 111  *
 112  **/
 113 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 114 {
 115         u16 phy_id = 0;
 116         bool valid = false;
 117
 118         hw->phy.addr = phy_addr;
 119         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 120                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 121
 122         if (phy_id != 0xFFFF && phy_id != 0x0)
 123                 valid = true;
 124
 125         return valid;
 126 }
 127
 128 /**
 129  *  ixgbe_get_phy_id - Get the phy type
 130  *  @hw: pointer to hardware structure
 131  *
 132  **/
 133 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 134 {
 135         u32 status;
 136         u16 phy_id_high = 0;
 137         u16 phy_id_low = 0;
 138
 139         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 140                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 141                                       &phy_id_high);
 142
 143         if (status == 0) {
 144                 hw->phy.id = (u32)(phy_id_high << 16);
 145                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 146                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 147                                               &phy_id_low);
 148                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 149                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 150         }
 151         return status;
 152 }
 153
 154 /**
 155  *  ixgbe_get_phy_type_from_id - Get the phy type
 156  *  @hw: pointer to hardware structure
 157  *
 158  **/
 159 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 160 {
 161         enum ixgbe_phy_type phy_type;
 162
 163         switch (phy_id) {
 164         case TN1010_PHY_ID:
 165                 phy_type = ixgbe_phy_tn;
 166                 break;
 167         case X540_PHY_ID:
 168                 phy_type = ixgbe_phy_aq;
 169                 break;
 170         case QT2022_PHY_ID:
 171                 phy_type = ixgbe_phy_qt;
 172                 break;
 173         case ATH_PHY_ID:
 174                 phy_type = ixgbe_phy_nl;
 175                 break;
 176         default:
 177                 phy_type = ixgbe_phy_unknown;
 178                 break;
 179         }
 180
 181         hw_dbg(hw, "phy type found is %d\n", phy_type);
 182         return phy_type;
 183 }
 184
 185 /**
 186  *  ixgbe_reset_phy_generic - Performs a PHY reset
 187  *  @hw: pointer to hardware structure
 188  **/
 189 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 190 {
 191         u32 i;
 192         u16 ctrl = 0;
 193         s32 status = 0;
 194
 195         if (hw->phy.type == ixgbe_phy_unknown)
 196                 status = ixgbe_identify_phy_generic(hw);
 197
 198         if (status != 0 || hw->phy.type == ixgbe_phy_none)
 199                 goto out;
 200
 201         /* Don't reset PHY if it's shut down due to overtemp. */
 202         if (!hw->phy.reset_if_overtemp &&
 203             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 204                 goto out;
 205
 206         /*
 207          * Perform soft PHY reset to the PHY_XS.
 208          * This will cause a soft reset to the PHY
 209          */
 210         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 211                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 212                               IXGBE_MDIO_PHY_XS_RESET);
 213
 214         /*
 215          * Poll for reset bit to self-clear indicating reset is complete.
 216          * Some PHYs could take up to 3 seconds to complete and need about
 217          * 1.7 usec delay after the reset is complete.
 218          */
 219         for (i = 0; i < 30; i++) {
 220                 msleep(100);
 221                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 222                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 223                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 224                         udelay(2);
 225                         break;
 226                 }
 227         }
 228
 229         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 230                 status = IXGBE_ERR_RESET_FAILED;
 231                 hw_dbg(hw, "PHY reset polling failed to complete.\n");
 232         }
 233
 234 out:
 235         return status;
 236 }
 237
 238 /**
 239  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 240  *  @hw: pointer to hardware structure
 241  *  @reg_addr: 32 bit address of PHY register to read
 242  *  @phy_data: Pointer to read data from PHY register
 243  **/
 244 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 245                                u32 device_type, u16 *phy_data)
 246 {
 247         u32 command;
 248         u32 i;
 249         u32 data;
 250         s32 status = 0;
 251         u16 gssr;
 252
 253         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 254                 gssr = IXGBE_GSSR_PHY1_SM;
 255         else
 256                 gssr = IXGBE_GSSR_PHY0_SM;
 257
 258         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
 259                 status = IXGBE_ERR_SWFW_SYNC;
 260
 261         if (status == 0) {
 262                 /* Setup and write the address cycle command */
 263                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 264                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 265                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 266                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 267
 268                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 269
 270                 /*
 271                  * Check every 10 usec to see if the address cycle completed.
 272                  * The MDI Command bit will clear when the operation is
 273                  * complete
 274                  */
 275                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 276                         udelay(10);
 277
 278                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 279
 280                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 281                                 break;
 282                 }
 283
 284                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 285                         hw_dbg(hw, "PHY address command did not complete.\n");
 286                         status = IXGBE_ERR_PHY;
 287                 }
 288
 289                 if (status == 0) {
 290                         /*
 291                          * Address cycle complete, setup and write the read
 292                          * command
 293                          */
 294                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 295                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 296                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 297                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 298
 299                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 300
 301                         /*
 302                          * Check every 10 usec to see if the address cycle
 303                          * completed. The MDI Command bit will clear when the
 304                          * operation is complete
 305                          */
 306                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 307                                 udelay(10);
 308
 309                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 310
 311                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 312                                         break;
 313                         }
 314
 315                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 316                                 hw_dbg(hw, "PHY read command didn't complete\n");
 317                                 status = IXGBE_ERR_PHY;
 318                         } else {
 319                                 /*
 320                                  * Read operation is complete.  Get the data
 321                                  * from MSRWD
 322                                  */
 323                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 324                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 325                                 *phy_data = (u16)(data);
 326                         }
 327                 }
 328
 329                 hw->mac.ops.release_swfw_sync(hw, gssr);
 330         }
 331
 332         return status;
 333 }
 334
 335 /**
 336  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 337  *  @hw: pointer to hardware structure
 338  *  @reg_addr: 32 bit PHY register to write
 339  *  @device_type: 5 bit device type
 340  *  @phy_data: Data to write to the PHY register
 341  **/
 342 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 343                                 u32 device_type, u16 phy_data)
 344 {
 345         u32 command;
 346         u32 i;
 347         s32 status = 0;
 348         u16 gssr;
 349
 350         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 351                 gssr = IXGBE_GSSR_PHY1_SM;
 352         else
 353                 gssr = IXGBE_GSSR_PHY0_SM;
 354
 355         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
 356                 status = IXGBE_ERR_SWFW_SYNC;
 357
 358         if (status == 0) {
 359                 /* Put the data in the MDI single read and write data register*/
 360                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 361
 362                 /* Setup and write the address cycle command */
 363                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 364                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 365                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 366                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 367
 368                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 369
 370                 /*
 371                  * Check every 10 usec to see if the address cycle completed.
 372                  * The MDI Command bit will clear when the operation is
 373                  * complete
 374                  */
 375                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 376                         udelay(10);
 377
 378                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 379
 380                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 381                                 break;
 382                 }
 383
 384                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 385                         hw_dbg(hw, "PHY address cmd didn't complete\n");
 386                         status = IXGBE_ERR_PHY;
 387                 }
 388
 389                 if (status == 0) {
 390                         /*
 391                          * Address cycle complete, setup and write the write
 392                          * command
 393                          */
 394                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 395                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 396                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 397                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 398
 399                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 400
 401                         /*
 402                          * Check every 10 usec to see if the address cycle
 403                          * completed. The MDI Command bit will clear when the
 404                          * operation is complete
 405                          */
 406                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 407                                 udelay(10);
 408
 409                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 410
 411                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 412                                         break;
 413                         }
 414
 415                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 416                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 417                                 status = IXGBE_ERR_PHY;
 418                         }
 419                 }
 420
 421                 hw->mac.ops.release_swfw_sync(hw, gssr);
 422         }
 423
 424         return status;
 425 }
 426
 427 /**
 428  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 429  *  @hw: pointer to hardware structure
 430  *
 431  *  Restart autonegotiation and PHY and waits for completion.
 432  **/
 433 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 434 {
 435         s32 status = 0;
 436         u32 time_out;
 437         u32 max_time_out = 10;
 438         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 439         bool autoneg = false;
 440         ixgbe_link_speed speed;
 441
 442         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 443
 444         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 445                 /* Set or unset auto-negotiation 10G advertisement */
 446                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 447                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 448                                      &autoneg_reg);
 449
 450                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 451                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 452                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 453
 454                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 455                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 456                                       autoneg_reg);
 457         }
 458
 459         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 460                 /* Set or unset auto-negotiation 1G advertisement */
 461                 hw->phy.ops.read_reg(hw,
 462                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 463                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 464                                      &autoneg_reg);
 465
 466                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 467                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 468                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 469
 470                 hw->phy.ops.write_reg(hw,
 471                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 472                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 473                                       autoneg_reg);
 474         }
 475
 476         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 477                 /* Set or unset auto-negotiation 100M advertisement */
 478                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 479                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 480                                      &autoneg_reg);
 481
 482                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 483                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 484                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 485                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 486
 487                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 488                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 489                                       autoneg_reg);
 490         }
 491
 492         /* Restart PHY autonegotiation and wait for completion */
 493         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 494                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 495
 496         autoneg_reg |= IXGBE_MII_RESTART;
 497
 498         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 499                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 500
 501         /* Wait for autonegotiation to finish */
 502         for (time_out = 0; time_out < max_time_out; time_out++) {
 503                 udelay(10);
 504                 /* Restart PHY autonegotiation and wait for completion */
 505                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 506                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 507                                               &autoneg_reg);
 508
 509                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 510                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 511                         break;
 512         }
 513
 514         if (time_out == max_time_out) {
 515                 status = IXGBE_ERR_LINK_SETUP;
 516                 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
 517         }
 518
 519         return status;
 520 }
 521
 522 /**
 523  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 524  *  @hw: pointer to hardware structure
 525  *  @speed: new link speed
 526  *  @autoneg: true if autonegotiation enabled
 527  **/
 528 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 529                                        ixgbe_link_speed speed,
 530                                        bool autoneg,
 531                                        bool autoneg_wait_to_complete)
 532 {
 533
 534         /*
 535          * Clear autoneg_advertised and set new values based on input link
 536          * speed.
 537          */
 538         hw->phy.autoneg_advertised = 0;
 539
 540         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 541                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 542
 543         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 544                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 545
 546         if (speed & IXGBE_LINK_SPEED_100_FULL)
 547                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 548
 549         /* Setup link based on the new speed settings */
 550         hw->phy.ops.setup_link(hw);
 551
 552         return 0;
 553 }
 554
 555 /**
 556  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 557  *  @hw: pointer to hardware structure
 558  *  @speed: pointer to link speed
 559  *  @autoneg: boolean auto-negotiation value
 560  *
 561  *  Determines the link capabilities by reading the AUTOC register.
 562  **/
 563 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 564                                                ixgbe_link_speed *speed,
 565                                                bool *autoneg)
 566 {
 567         s32 status = IXGBE_ERR_LINK_SETUP;
 568         u16 speed_ability;
 569
 570         *speed = 0;
 571         *autoneg = true;
 572
 573         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 574                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 575                                       &speed_ability);
 576
 577         if (status == 0) {
 578                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 579                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 580                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 581                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 582                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 583                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 584         }
 585
 586         return status;
 587 }
 588
 589 /**
 590  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 591  *  @hw: pointer to hardware structure
 592  *
 593  *  Reads the VS1 register to determine if link is up and the current speed for
 594  *  the PHY.
 595  **/
 596 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 597                              bool *link_up)
 598 {
 599         s32 status = 0;
 600         u32 time_out;
 601         u32 max_time_out = 10;
 602         u16 phy_link = 0;
 603         u16 phy_speed = 0;
 604         u16 phy_data = 0;
 605
 606         /* Initialize speed and link to default case */
 607         *link_up = false;
 608         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 609
 610         /*
 611          * Check current speed and link status of the PHY register.
 612          * This is a vendor specific register and may have to
 613          * be changed for other copper PHYs.
 614          */
 615         for (time_out = 0; time_out < max_time_out; time_out++) {
 616                 udelay(10);
 617                 status = hw->phy.ops.read_reg(hw,
 618                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 619                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 620                                         &phy_data);
 621                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 622                 phy_speed = phy_data &
 623                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 624                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 625                         *link_up = true;
 626                         if (phy_speed ==
 627                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 628                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 629                         break;
 630                 }
 631         }
 632
 633         return status;
 634 }
 635
 636 /**
 637  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 638  *      @hw: pointer to hardware structure
 639  *
 640  *      Restart autonegotiation and PHY and waits for completion.
 641  **/
 642 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 643 {
 644         s32 status = 0;
 645         u32 time_out;
 646         u32 max_time_out = 10;
 647         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 648         bool autoneg = false;
 649         ixgbe_link_speed speed;
 650
 651         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 652
 653         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 654                 /* Set or unset auto-negotiation 10G advertisement */
 655                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 656                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 657                                      &autoneg_reg);
 658
 659                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 660                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 661                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 662
 663                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 664                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 665                                       autoneg_reg);
 666         }
 667
 668         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 669                 /* Set or unset auto-negotiation 1G advertisement */
 670                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 671                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 672                                      &autoneg_reg);
 673
 674                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 675                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 676                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 677
 678                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 679                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 680                                       autoneg_reg);
 681         }
 682
 683         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 684                 /* Set or unset auto-negotiation 100M advertisement */
 685                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 686                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 687                                      &autoneg_reg);
 688
 689                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 690                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 691                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 692
 693                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 694                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 695                                       autoneg_reg);
 696         }
 697
 698         /* Restart PHY autonegotiation and wait for completion */
 699         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 700                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 701
 702         autoneg_reg |= IXGBE_MII_RESTART;
 703
 704         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 705                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 706
 707         /* Wait for autonegotiation to finish */
 708         for (time_out = 0; time_out < max_time_out; time_out++) {
 709                 udelay(10);
 710                 /* Restart PHY autonegotiation and wait for completion */
 711                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 712                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 713                                               &autoneg_reg);
 714
 715                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 716                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 717                         break;
 718         }
 719
 720         if (time_out == max_time_out) {
 721                 status = IXGBE_ERR_LINK_SETUP;
 722                 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
 723         }
 724
 725         return status;
 726 }
 727
 728 /**
 729  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 730  *  @hw: pointer to hardware structure
 731  *  @firmware_version: pointer to the PHY Firmware Version
 732  **/
 733 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 734                                        u16 *firmware_version)
 735 {
 736         s32 status = 0;
 737
 738         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 739                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 740                                       firmware_version);
 741
 742         return status;
 743 }
 744
 745 /**
 746  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 747  *  @hw: pointer to hardware structure
 748  *  @firmware_version: pointer to the PHY Firmware Version
 749  **/
 750 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 751                                            u16 *firmware_version)
 752 {
 753         s32 status = 0;
 754
 755         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 756                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 757                                       firmware_version);
 758
 759         return status;
 760 }
 761
 762 /**
 763  *  ixgbe_reset_phy_nl - Performs a PHY reset
 764  *  @hw: pointer to hardware structure
 765  **/
 766 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 767 {
 768         u16 phy_offset, control, eword, edata, block_crc;
 769         bool end_data = false;
 770         u16 list_offset, data_offset;
 771         u16 phy_data = 0;
 772         s32 ret_val = 0;
 773         u32 i;
 774
 775         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 776                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 777
 778         /* reset the PHY and poll for completion */
 779         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 780                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 781                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 782
 783         for (i = 0; i < 100; i++) {
 784                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 785                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 786                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 787                         break;
 788                 msleep(10);
 789         }
 790
 791         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 792                 hw_dbg(hw, "PHY reset did not complete.\n");
 793                 ret_val = IXGBE_ERR_PHY;
 794                 goto out;
 795         }
 796
 797         /* Get init offsets */
 798         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 799                                                       &data_offset);
 800         if (ret_val != 0)
 801                 goto out;
 802
 803         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 804         data_offset++;
 805         while (!end_data) {
 806                 /*
 807                  * Read control word from PHY init contents offset
 808                  */
 809                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 810                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 811                            IXGBE_CONTROL_SHIFT_NL;
 812                 edata = eword & IXGBE_DATA_MASK_NL;
 813                 switch (control) {
 814                 case IXGBE_DELAY_NL:
 815                         data_offset++;
 816                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 817                         msleep(edata);
 818                         break;
 819                 case IXGBE_DATA_NL:
 820                         hw_dbg(hw, "DATA:\n");
 821                         data_offset++;
 822                         hw->eeprom.ops.read(hw, data_offset++,
 823                                             &phy_offset);
 824                         for (i = 0; i < edata; i++) {
 825                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 826                                 hw->phy.ops.write_reg(hw, phy_offset,
 827                                                       IXGBE_TWINAX_DEV, eword);
 828                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 829                                           phy_offset);
 830                                 data_offset++;
 831                                 phy_offset++;
 832                         }
 833                         break;
 834                 case IXGBE_CONTROL_NL:
 835                         data_offset++;
 836                         hw_dbg(hw, "CONTROL:\n");
 837                         if (edata == IXGBE_CONTROL_EOL_NL) {
 838                                 hw_dbg(hw, "EOL\n");
 839                                 end_data = true;
 840                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 841                                 hw_dbg(hw, "SOL\n");
 842                         } else {
 843                                 hw_dbg(hw, "Bad control value\n");
 844                                 ret_val = IXGBE_ERR_PHY;
 845                                 goto out;
 846                         }
 847                         break;
 848                 default:
 849                         hw_dbg(hw, "Bad control type\n");
 850                         ret_val = IXGBE_ERR_PHY;
 851                         goto out;
 852                 }
 853         }
 854
 855 out:
 856         return ret_val;
 857 }
 858
 859 /**
 860  *  ixgbe_identify_module_generic - Identifies module type
 861  *  @hw: pointer to hardware structure
 862  *
 863  *  Determines HW type and calls appropriate function.
 864  **/
 865 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 866 {
 867         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 868
 869         switch (hw->mac.ops.get_media_type(hw)) {
 870         case ixgbe_media_type_fiber:
 871                 status = ixgbe_identify_sfp_module_generic(hw);
 872                 break;
 873
 874         case ixgbe_media_type_fiber_qsfp:
 875                 status = ixgbe_identify_qsfp_module_generic(hw);
 876                 break;
 877
 878         default:
 879                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 880                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 881                 break;
 882         }
 883
 884         return status;
 885 }
 886
 887 /**
 888  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 889  *  @hw: pointer to hardware structure
 890  *
 891  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 892  **/
 893 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 894 {
 895         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 896         u32 vendor_oui = 0;
 897         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 898         u8 identifier = 0;
 899         u8 comp_codes_1g = 0;
 900         u8 comp_codes_10g = 0;
 901         u8 oui_bytes[3] = {0, 0, 0};
 902         u8 cable_tech = 0;
 903         u8 cable_spec = 0;
 904         u16 enforce_sfp = 0;
 905
 906         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 907                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 908                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 909                 goto out;
 910         }
 911
 912         status = hw->phy.ops.read_i2c_eeprom(hw,
 913                                              IXGBE_SFF_IDENTIFIER,
 914                                              &identifier);
 915
 916         if (status == IXGBE_ERR_SWFW_SYNC ||
 917             status == IXGBE_ERR_I2C ||
 918             status == IXGBE_ERR_SFP_NOT_PRESENT)
 919                 goto err_read_i2c_eeprom;
 920
 921         /* LAN ID is needed for sfp_type determination */
 922         hw->mac.ops.set_lan_id(hw);
 923
 924         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 925                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 926                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 927         } else {
 928                 status = hw->phy.ops.read_i2c_eeprom(hw,
 929                                                      IXGBE_SFF_1GBE_COMP_CODES,
 930                                                      &comp_codes_1g);
 931
 932                 if (status == IXGBE_ERR_SWFW_SYNC ||
 933                     status == IXGBE_ERR_I2C ||
 934                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 935                         goto err_read_i2c_eeprom;
 936
 937                 status = hw->phy.ops.read_i2c_eeprom(hw,
 938                                                      IXGBE_SFF_10GBE_COMP_CODES,
 939                                                      &comp_codes_10g);
 940
 941                 if (status == IXGBE_ERR_SWFW_SYNC ||
 942                     status == IXGBE_ERR_I2C ||
 943                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 944                         goto err_read_i2c_eeprom;
 945                 status = hw->phy.ops.read_i2c_eeprom(hw,
 946                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
 947                                                      &cable_tech);
 948
 949                 if (status == IXGBE_ERR_SWFW_SYNC ||
 950                     status == IXGBE_ERR_I2C ||
 951                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 952                         goto err_read_i2c_eeprom;
 953
 954                  /* ID Module
 955                   * =========
 956                   * 0   SFP_DA_CU
 957                   * 1   SFP_SR
 958                   * 2   SFP_LR
 959                   * 3   SFP_DA_CORE0 - 82599-specific
 960                   * 4   SFP_DA_CORE1 - 82599-specific
 961                   * 5   SFP_SR/LR_CORE0 - 82599-specific
 962                   * 6   SFP_SR/LR_CORE1 - 82599-specific
 963                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
 964                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
 965                   * 9   SFP_1g_cu_CORE0 - 82599-specific
 966                   * 10  SFP_1g_cu_CORE1 - 82599-specific
 967                   * 11  SFP_1g_sx_CORE0 - 82599-specific
 968                   * 12  SFP_1g_sx_CORE1 - 82599-specific
 969                   */
 970                 if (hw->mac.type == ixgbe_mac_82598EB) {
 971                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 972                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 973                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 974                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
 975                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 976                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
 977                         else
 978                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 979                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
 980                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 981                                 if (hw->bus.lan_id == 0)
 982                                         hw->phy.sfp_type =
 983                                                      ixgbe_sfp_type_da_cu_core0;
 984                                 else
 985                                         hw->phy.sfp_type =
 986                                                      ixgbe_sfp_type_da_cu_core1;
 987                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
 988                                 hw->phy.ops.read_i2c_eeprom(
 989                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
 990                                                 &cable_spec);
 991                                 if (cable_spec &
 992                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
 993                                         if (hw->bus.lan_id == 0)
 994                                                 hw->phy.sfp_type =
 995                                                 ixgbe_sfp_type_da_act_lmt_core0;
 996                                         else
 997                                                 hw->phy.sfp_type =
 998                                                 ixgbe_sfp_type_da_act_lmt_core1;
 999                                 } else {
1000                                         hw->phy.sfp_type =
1001                                                         ixgbe_sfp_type_unknown;
1002                                 }
1003                         } else if (comp_codes_10g &
1004                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1005                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1006                                 if (hw->bus.lan_id == 0)
1007                                         hw->phy.sfp_type =
1008                                                       ixgbe_sfp_type_srlr_core0;
1009                                 else
1010                                         hw->phy.sfp_type =
1011                                                       ixgbe_sfp_type_srlr_core1;
1012                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1013                                 if (hw->bus.lan_id == 0)
1014                                         hw->phy.sfp_type =
1015                                                 ixgbe_sfp_type_1g_cu_core0;
1016                                 else
1017                                         hw->phy.sfp_type =
1018                                                 ixgbe_sfp_type_1g_cu_core1;
1019                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1020                                 if (hw->bus.lan_id == 0)
1021                                         hw->phy.sfp_type =
1022                                                 ixgbe_sfp_type_1g_sx_core0;
1023                                 else
1024                                         hw->phy.sfp_type =
1025                                                 ixgbe_sfp_type_1g_sx_core1;
1026                         } else {
1027                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1028                         }
1029                 }
1030
1031                 if (hw->phy.sfp_type != stored_sfp_type)
1032                         hw->phy.sfp_setup_needed = true;
1033
1034                 /* Determine if the SFP+ PHY is dual speed or not. */
1035                 hw->phy.multispeed_fiber = false;
1036                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1037                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1038                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1039                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1040                         hw->phy.multispeed_fiber = true;
1041
1042                 /* Determine PHY vendor */
1043                 if (hw->phy.type != ixgbe_phy_nl) {
1044                         hw->phy.id = identifier;
1045                         status = hw->phy.ops.read_i2c_eeprom(hw,
1046                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1047                                                     &oui_bytes[0]);
1048
1049                         if (status == IXGBE_ERR_SWFW_SYNC ||
1050                             status == IXGBE_ERR_I2C ||
1051                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1052                                 goto err_read_i2c_eeprom;
1053
1054                         status = hw->phy.ops.read_i2c_eeprom(hw,
1055                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1056                                                     &oui_bytes[1]);
1057
1058                         if (status == IXGBE_ERR_SWFW_SYNC ||
1059                             status == IXGBE_ERR_I2C ||
1060                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1061                                 goto err_read_i2c_eeprom;
1062
1063                         status = hw->phy.ops.read_i2c_eeprom(hw,
1064                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1065                                                     &oui_bytes[2]);
1066
1067                         if (status == IXGBE_ERR_SWFW_SYNC ||
1068                             status == IXGBE_ERR_I2C ||
1069                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1070                                 goto err_read_i2c_eeprom;
1071
1072                         vendor_oui =
1073                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1074                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1075                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1076
1077                         switch (vendor_oui) {
1078                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1079                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1080                                         hw->phy.type =
1081                                                     ixgbe_phy_sfp_passive_tyco;
1082                                 break;
1083                         case IXGBE_SFF_VENDOR_OUI_FTL:
1084                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1085                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1086                                 else
1087                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1088                                 break;
1089                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1090                                 hw->phy.type = ixgbe_phy_sfp_avago;
1091                                 break;
1092                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1093                                 hw->phy.type = ixgbe_phy_sfp_intel;
1094                                 break;
1095                         default:
1096                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1097                                         hw->phy.type =
1098                                                  ixgbe_phy_sfp_passive_unknown;
1099                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1100                                         hw->phy.type =
1101                                                 ixgbe_phy_sfp_active_unknown;
1102                                 else
1103                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1104                                 break;
1105                         }
1106                 }
1107
1108                 /* Allow any DA cable vendor */
1109                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1110                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1111                         status = 0;
1112                         goto out;
1113                 }
1114
1115                 /* Verify supported 1G SFP modules */
1116                 if (comp_codes_10g == 0 &&
1117                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1118                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1119                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0  ||
1120                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1121                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1122                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1123                         goto out;
1124                 }
1125
1126                 /* Anything else 82598-based is supported */
1127                 if (hw->mac.type == ixgbe_mac_82598EB) {
1128                         status = 0;
1129                         goto out;
1130                 }
1131
1132                 ixgbe_get_device_caps(hw, &enforce_sfp);
1133                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1134                     !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1135                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1136                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0)  ||
1137                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1138                         /* Make sure we're a supported PHY type */
1139                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1140                                 status = 0;
1141                         } else {
1142                                 if (hw->allow_unsupported_sfp == true) {
1143                                         EWARN(hw, "WARNING: Intel (R) Network "
1144                                               "Connections are quality tested "
1145                                               "using Intel (R) Ethernet Optics."
1146                                               " Using untested modules is not "
1147                                               "supported and may cause unstable"
1148                                               " operation or damage to the "
1149                                               "module or the adapter. Intel "
1150                                               "Corporation is not responsible "
1151                                               "for any harm caused by using "
1152                                               "untested modules.\n", status);
1153                                         status = 0;
1154                                 } else {
1155                                         hw_dbg(hw, "SFP+ module not supported\n");
1156                                         hw->phy.type =
1157                                                 ixgbe_phy_sfp_unsupported;
1158                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1159                                 }
1160                         }
1161                 } else {
1162                         status = 0;
1163                 }
1164         }
1165
1166 out:
1167         return status;
1168
1169 err_read_i2c_eeprom:
1170         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1171         if (hw->phy.type != ixgbe_phy_nl) {
1172                 hw->phy.id = 0;
1173                 hw->phy.type = ixgbe_phy_unknown;
1174         }
1175         return IXGBE_ERR_SFP_NOT_PRESENT;
1176 }
1177
1178 /**
1179  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1180  *  @hw: pointer to hardware structure
1181  *
1182  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1183  **/
1184 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1185 {
1186         s32 status = 0;
1187
1188         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1189                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1190                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1191         }
1192
1193         return status;
1194 }
1195
1196
1197 /**
1198  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1199  *  @hw: pointer to hardware structure
1200  *  @list_offset: offset to the SFP ID list
1201  *  @data_offset: offset to the SFP data block
1202  *
1203  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1204  *  so it returns the offsets to the phy init sequence block.
1205  **/
1206 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1207                                         u16 *list_offset,
1208                                         u16 *data_offset)
1209 {
1210         u16 sfp_id;
1211         u16 sfp_type = hw->phy.sfp_type;
1212
1213         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1214                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1215
1216         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1217                 return IXGBE_ERR_SFP_NOT_PRESENT;
1218
1219         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1220             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1221                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1222
1223         /*
1224          * Limiting active cables and 1G Phys must be initialized as
1225          * SR modules
1226          */
1227         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1228             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1229             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1230                 sfp_type = ixgbe_sfp_type_srlr_core0;
1231         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1232                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1233                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1234                 sfp_type = ixgbe_sfp_type_srlr_core1;
1235
1236         /* Read offset to PHY init contents */
1237         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1238
1239         if ((!*list_offset) || (*list_offset == 0xFFFF))
1240                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1241
1242         /* Shift offset to first ID word */
1243         (*list_offset)++;
1244
1245         /*
1246          * Find the matching SFP ID in the EEPROM
1247          * and program the init sequence
1248          */
1249         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1250
1251         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1252                 if (sfp_id == sfp_type) {
1253                         (*list_offset)++;
1254                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
1255                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1256                                 hw_dbg(hw, "SFP+ module not supported\n");
1257                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1258                         } else {
1259                                 break;
1260                         }
1261                 } else {
1262                         (*list_offset) += 2;
1263                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1264                                 return IXGBE_ERR_PHY;
1265                 }
1266         }
1267
1268         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1269                 hw_dbg(hw, "No matching SFP+ module found\n");
1270                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1271         }
1272
1273         return 0;
1274 }
1275
1276 /**
1277  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1278  *  @hw: pointer to hardware structure
1279  *  @byte_offset: EEPROM byte offset to read
1280  *  @eeprom_data: value read
1281  *
1282  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1283  **/
1284 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1285                                   u8 *eeprom_data)
1286 {
1287         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1288                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1289                                          eeprom_data);
1290 }
1291
1292 /**
1293  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1294  *  @hw: pointer to hardware structure
1295  *  @byte_offset: EEPROM byte offset to write
1296  *  @eeprom_data: value to write
1297  *
1298  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1299  **/
1300 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1301                                    u8 eeprom_data)
1302 {
1303         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1304                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1305                                           eeprom_data);
1306 }
1307
1308 /**
1309  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1310  *  @hw: pointer to hardware structure
1311  *  @byte_offset: byte offset to read
1312  *  @data: value read
1313  *
1314  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1315  *  a specified device address.
1316  **/
1317 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1318                                 u8 dev_addr, u8 *data)
1319 {
1320         s32 status = 0;
1321         u32 max_retry = 10;
1322         u32 retry = 0;
1323         u16 swfw_mask = 0;
1324         bool nack = 1;
1325         *data = 0;
1326
1327         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1328                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1329         else
1330                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1331
1332         do {
1333                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1334                     != 0) {
1335                         status = IXGBE_ERR_SWFW_SYNC;
1336                         goto read_byte_out;
1337                 }
1338
1339                 ixgbe_i2c_start(hw);
1340
1341                 /* Device Address and write indication */
1342                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1343                 if (status != 0)
1344                         goto fail;
1345
1346                 status = ixgbe_get_i2c_ack(hw);
1347                 if (status != 0)
1348                         goto fail;
1349
1350                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1351                 if (status != 0)
1352                         goto fail;
1353
1354                 status = ixgbe_get_i2c_ack(hw);
1355                 if (status != 0)
1356                         goto fail;
1357
1358                 ixgbe_i2c_start(hw);
1359
1360                 /* Device Address and read indication */
1361                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1362                 if (status != 0)
1363                         goto fail;
1364
1365                 status = ixgbe_get_i2c_ack(hw);
1366                 if (status != 0)
1367                         goto fail;
1368
1369                 status = ixgbe_clock_in_i2c_byte(hw, data);
1370                 if (status != 0)
1371                         goto fail;
1372
1373                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1374                 if (status != 0)
1375                         goto fail;
1376
1377                 ixgbe_i2c_stop(hw);
1378                 break;
1379
1380 fail:
1381                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1382                 msleep(100);
1383                 ixgbe_i2c_bus_clear(hw);
1384                 retry++;
1385                 if (retry < max_retry)
1386                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
1387                 else
1388                         hw_dbg(hw, "I2C byte read error.\n");
1389
1390         } while (retry < max_retry);
1391
1392         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1393
1394 read_byte_out:
1395         return status;
1396 }
1397
1398 /**
1399  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1400  *  @hw: pointer to hardware structure
1401  *  @byte_offset: byte offset to write
1402  *  @data: value to write
1403  *
1404  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1405  *  a specified device address.
1406  **/
1407 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1408                                  u8 dev_addr, u8 data)
1409 {
1410         s32 status = 0;
1411         u32 max_retry = 1;
1412         u32 retry = 0;
1413         u16 swfw_mask = 0;
1414
1415         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1416                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1417         else
1418                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1419
1420         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1421                 status = IXGBE_ERR_SWFW_SYNC;
1422                 goto write_byte_out;
1423         }
1424
1425         do {
1426                 ixgbe_i2c_start(hw);
1427
1428                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1429                 if (status != 0)
1430                         goto fail;
1431
1432                 status = ixgbe_get_i2c_ack(hw);
1433                 if (status != 0)
1434                         goto fail;
1435
1436                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1437                 if (status != 0)
1438                         goto fail;
1439
1440                 status = ixgbe_get_i2c_ack(hw);
1441                 if (status != 0)
1442                         goto fail;
1443
1444                 status = ixgbe_clock_out_i2c_byte(hw, data);
1445                 if (status != 0)
1446                         goto fail;
1447
1448                 status = ixgbe_get_i2c_ack(hw);
1449                 if (status != 0)
1450                         goto fail;
1451
1452                 ixgbe_i2c_stop(hw);
1453                 break;
1454
1455 fail:
1456                 ixgbe_i2c_bus_clear(hw);
1457                 retry++;
1458                 if (retry < max_retry)
1459                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
1460                 else
1461                         hw_dbg(hw, "I2C byte write error.\n");
1462         } while (retry < max_retry);
1463
1464         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1465
1466 write_byte_out:
1467         return status;
1468 }
1469
1470 /**
1471  *  ixgbe_i2c_start - Sets I2C start condition
1472  *  @hw: pointer to hardware structure
1473  *
1474  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1475  **/
1476 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1477 {
1478         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1479
1480         /* Start condition must begin with data and clock high */
1481         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1482         ixgbe_raise_i2c_clk(hw, &i2cctl);
1483
1484         /* Setup time for start condition (4.7us) */
1485         udelay(IXGBE_I2C_T_SU_STA);
1486
1487         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1488
1489         /* Hold time for start condition (4us) */
1490         udelay(IXGBE_I2C_T_HD_STA);
1491
1492         ixgbe_lower_i2c_clk(hw, &i2cctl);
1493
1494         /* Minimum low period of clock is 4.7 us */
1495         udelay(IXGBE_I2C_T_LOW);
1496
1497 }
1498
1499 /**
1500  *  ixgbe_i2c_stop - Sets I2C stop condition
1501  *  @hw: pointer to hardware structure
1502  *
1503  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1504  **/
1505 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1506 {
1507         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1508
1509         /* Stop condition must begin with data low and clock high */
1510         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1511         ixgbe_raise_i2c_clk(hw, &i2cctl);
1512
1513         /* Setup time for stop condition (4us) */
1514         udelay(IXGBE_I2C_T_SU_STO);
1515
1516         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1517
1518         /* bus free time between stop and start (4.7us)*/
1519         udelay(IXGBE_I2C_T_BUF);
1520 }
1521
1522 /**
1523  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1524  *  @hw: pointer to hardware structure
1525  *  @data: data byte to clock in
1526  *
1527  *  Clocks in one byte data via I2C data/clock
1528  **/
1529 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1530 {
1531         s32 i;
1532         bool bit = 0;
1533
1534         for (i = 7; i >= 0; i--) {
1535                 ixgbe_clock_in_i2c_bit(hw, &bit);
1536                 *data |= bit << i;
1537         }
1538
1539         return 0;
1540 }
1541
1542 /**
1543  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1544  *  @hw: pointer to hardware structure
1545  *  @data: data byte clocked out
1546  *
1547  *  Clocks out one byte data via I2C data/clock
1548  **/
1549 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1550 {
1551         s32 status = 0;
1552         s32 i;
1553         u32 i2cctl;
1554         bool bit = 0;
1555
1556         for (i = 7; i >= 0; i--) {
1557                 bit = (data >> i) & 0x1;
1558                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1559
1560                 if (status != 0)
1561                         break;
1562         }
1563
1564         /* Release SDA line (set high) */
1565         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1566         i2cctl |= IXGBE_I2C_DATA_OUT;
1567         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1568         IXGBE_WRITE_FLUSH(hw);
1569
1570         return status;
1571 }
1572
1573 /**
1574  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1575  *  @hw: pointer to hardware structure
1576  *
1577  *  Clocks in/out one bit via I2C data/clock
1578  **/
1579 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1580 {
1581         s32 status = 0;
1582         u32 i = 0;
1583         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1584         u32 timeout = 10;
1585         bool ack = 1;
1586
1587         ixgbe_raise_i2c_clk(hw, &i2cctl);
1588
1589
1590         /* Minimum high period of clock is 4us */
1591         udelay(IXGBE_I2C_T_HIGH);
1592
1593         /* Poll for ACK.  Note that ACK in I2C spec is
1594          * transition from 1 to 0 */
1595         for (i = 0; i < timeout; i++) {
1596                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1597                 ack = ixgbe_get_i2c_data(&i2cctl);
1598
1599                 udelay(1);
1600                 if (ack == 0)
1601                         break;
1602         }
1603
1604         if (ack == 1) {
1605                 hw_dbg(hw, "I2C ack was not received.\n");
1606                 status = IXGBE_ERR_I2C;
1607         }
1608
1609         ixgbe_lower_i2c_clk(hw, &i2cctl);
1610
1611         /* Minimum low period of clock is 4.7 us */
1612         udelay(IXGBE_I2C_T_LOW);
1613
1614         return status;
1615 }
1616
1617 /**
1618  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1619  *  @hw: pointer to hardware structure
1620  *  @data: read data value
1621  *
1622  *  Clocks in one bit via I2C data/clock
1623  **/
1624 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1625 {
1626         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1627
1628         ixgbe_raise_i2c_clk(hw, &i2cctl);
1629
1630         /* Minimum high period of clock is 4us */
1631         udelay(IXGBE_I2C_T_HIGH);
1632
1633         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1634         *data = ixgbe_get_i2c_data(&i2cctl);
1635
1636         ixgbe_lower_i2c_clk(hw, &i2cctl);
1637
1638         /* Minimum low period of clock is 4.7 us */
1639         udelay(IXGBE_I2C_T_LOW);
1640
1641         return 0;
1642 }
1643
1644 /**
1645  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1646  *  @hw: pointer to hardware structure
1647  *  @data: data value to write
1648  *
1649  *  Clocks out one bit via I2C data/clock
1650  **/
1651 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1652 {
1653         s32 status;
1654         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1655
1656         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1657         if (status == 0) {
1658                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1659
1660                 /* Minimum high period of clock is 4us */
1661                 udelay(IXGBE_I2C_T_HIGH);
1662
1663                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1664
1665                 /* Minimum low period of clock is 4.7 us.
1666                  * This also takes care of the data hold time.
1667                  */
1668                 udelay(IXGBE_I2C_T_LOW);
1669         } else {
1670                 status = IXGBE_ERR_I2C;
1671                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1672         }
1673
1674         return status;
1675 }
1676 /**
1677  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1678  *  @hw: pointer to hardware structure
1679  *  @i2cctl: Current value of I2CCTL register
1680  *
1681  *  Raises the I2C clock line '0'->'1'
1682  **/
1683 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1684 {
1685         u32 i = 0;
1686         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1687         u32 i2cctl_r = 0;
1688
1689         for (i = 0; i < timeout; i++) {
1690                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1691
1692                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1693                 IXGBE_WRITE_FLUSH(hw);
1694                 /* SCL rise time (1000ns) */
1695                 udelay(IXGBE_I2C_T_RISE);
1696
1697                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1698                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1699                         break;
1700         }
1701 }
1702
1703 /**
1704  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1705  *  @hw: pointer to hardware structure
1706  *  @i2cctl: Current value of I2CCTL register
1707  *
1708  *  Lowers the I2C clock line '1'->'0'
1709  **/
1710 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1711 {
1712
1713         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1714
1715         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1716         IXGBE_WRITE_FLUSH(hw);
1717
1718         /* SCL fall time (300ns) */
1719         udelay(IXGBE_I2C_T_FALL);
1720 }
1721
1722 /**
1723  *  ixgbe_set_i2c_data - Sets the I2C data bit
1724  *  @hw: pointer to hardware structure
1725  *  @i2cctl: Current value of I2CCTL register
1726  *  @data: I2C data value (0 or 1) to set
1727  *
1728  *  Sets the I2C data bit
1729  **/
1730 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1731 {
1732         s32 status = 0;
1733
1734         if (data)
1735                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1736         else
1737                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1738
1739         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1740         IXGBE_WRITE_FLUSH(hw);
1741
1742         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1743         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1744
1745         /* Verify data was set correctly */
1746         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1747         if (data != ixgbe_get_i2c_data(i2cctl)) {
1748                 status = IXGBE_ERR_I2C;
1749                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1750         }
1751
1752         return status;
1753 }
1754
1755 /**
1756  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1757  *  @hw: pointer to hardware structure
1758  *  @i2cctl: Current value of I2CCTL register
1759  *
1760  *  Returns the I2C data bit value
1761  **/
1762 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1763 {
1764         bool data;
1765
1766         if (*i2cctl & IXGBE_I2C_DATA_IN)
1767                 data = 1;
1768         else
1769                 data = 0;
1770
1771         return data;
1772 }
1773
1774 /**
1775  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1776  *  @hw: pointer to hardware structure
1777  *
1778  *  Clears the I2C bus by sending nine clock pulses.
1779  *  Used when data line is stuck low.
1780  **/
1781 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1782 {
1783         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1784         u32 i;
1785
1786         ixgbe_i2c_start(hw);
1787
1788         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1789
1790         for (i = 0; i < 9; i++) {
1791                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1792
1793                 /* Min high period of clock is 4us */
1794                 udelay(IXGBE_I2C_T_HIGH);
1795
1796                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1797
1798                 /* Min low period of clock is 4.7us*/
1799                 udelay(IXGBE_I2C_T_LOW);
1800         }
1801
1802         ixgbe_i2c_start(hw);
1803
1804         /* Put the i2c bus back to default state */
1805         ixgbe_i2c_stop(hw);
1806 }
1807
1808 /**
1809  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1810  *  @hw: pointer to hardware structure
1811  *
1812  *  Checks if the LASI temp alarm status was triggered due to overtemp
1813  **/
1814 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1815 {
1816         s32 status = 0;
1817         u16 phy_data = 0;
1818
1819         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1820                 goto out;
1821
1822         /* Check that the LASI temp alarm status was triggered */
1823         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1824                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1825
1826         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1827                 goto out;
1828
1829         status = IXGBE_ERR_OVERTEMP;
1830 out:
1831         return status;
1832 }