lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include "ixgbe_api.h"
  29 #include "ixgbe_common.h"
  30 #include "ixgbe_phy.h"
  31
  32 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  33 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  34 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  35 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  36 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  37 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  38 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  39 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  40 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  41 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  42 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  43
  44 /**
  45  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  46  *  @hw: pointer to the hardware structure
  47  *
  48  *  Initialize the function pointers.
  49  **/
  50 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  51 {
  52         struct ixgbe_phy_info *phy = &hw->phy;
  53
  54         /* PHY */
  55         phy->ops.identify = &ixgbe_identify_phy_generic;
  56         phy->ops.reset = &ixgbe_reset_phy_generic;
  57         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  58         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  59         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  60         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  61         phy->ops.check_link = NULL;
  62         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  63         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  64         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  65         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  66         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  67         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  68         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  69         phy->sfp_type = ixgbe_sfp_type_unknown;
  70         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  71         return 0;
  72 }
  73
  74 /**
  75  *  ixgbe_identify_phy_generic - Get physical layer module
  76  *  @hw: pointer to hardware structure
  77  *
  78  *  Determines the physical layer module found on the current adapter.
  79  **/
  80 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  81 {
  82         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  83         u32 phy_addr;
  84         u16 ext_ability = 0;
  85
  86         if (hw->phy.type == ixgbe_phy_unknown) {
  87                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  88                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
  89                                 hw->phy.addr = phy_addr;
  90                                 ixgbe_get_phy_id(hw);
  91                                 hw->phy.type =
  92                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  93
  94                                 if (hw->phy.type == ixgbe_phy_unknown) {
  95                                         hw->phy.ops.read_reg(hw,
  96                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
  97                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
  98                                                   &ext_ability);
  99                                         if (ext_ability &
 100                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 101                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 102                                                 hw->phy.type =
 103                                                          ixgbe_phy_cu_unknown;
 104                                         else
 105                                                 hw->phy.type =
 106                                                          ixgbe_phy_generic;
 107                                 }
 108
 109                                 status = 0;
 110                                 break;
 111                         }
 112                 }
 113                 /* clear value if nothing found */
 114                 if (status != 0)
 115                         hw->phy.addr = 0;
 116         } else {
 117                 status = 0;
 118         }
 119
 120         return status;
 121 }
 122
 123 /**
 124  *  ixgbe_validate_phy_addr - Determines phy address is valid
 125  *  @hw: pointer to hardware structure
 126  *
 127  **/
 128 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 129 {
 130         u16 phy_id = 0;
 131         bool valid = false;
 132
 133         hw->phy.addr = phy_addr;
 134         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 135                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 136
 137         if (phy_id != 0xFFFF && phy_id != 0x0)
 138                 valid = true;
 139
 140         return valid;
 141 }
 142
 143 /**
 144  *  ixgbe_get_phy_id - Get the phy type
 145  *  @hw: pointer to hardware structure
 146  *
 147  **/
 148 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 149 {
 150         u32 status;
 151         u16 phy_id_high = 0;
 152         u16 phy_id_low = 0;
 153
 154         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 155                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 156                                       &phy_id_high);
 157
 158         if (status == 0) {
 159                 hw->phy.id = (u32)(phy_id_high << 16);
 160                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 161                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 162                                               &phy_id_low);
 163                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 164                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 165         }
 166         return status;
 167 }
 168
 169 /**
 170  *  ixgbe_get_phy_type_from_id - Get the phy type
 171  *  @hw: pointer to hardware structure
 172  *
 173  **/
 174 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 175 {
 176         enum ixgbe_phy_type phy_type;
 177
 178         switch (phy_id) {
 179         case TN1010_PHY_ID:
 180                 phy_type = ixgbe_phy_tn;
 181                 break;
 182         case X540_PHY_ID:
 183                 phy_type = ixgbe_phy_aq;
 184                 break;
 185         case QT2022_PHY_ID:
 186                 phy_type = ixgbe_phy_qt;
 187                 break;
 188         case ATH_PHY_ID:
 189                 phy_type = ixgbe_phy_nl;
 190                 break;
 191         default:
 192                 phy_type = ixgbe_phy_unknown;
 193                 break;
 194         }
 195
 196         hw_dbg(hw, "phy type found is %d\n", phy_type);
 197         return phy_type;
 198 }
 199
 200 /**
 201  *  ixgbe_reset_phy_generic - Performs a PHY reset
 202  *  @hw: pointer to hardware structure
 203  **/
 204 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 205 {
 206         u32 i;
 207         u16 ctrl = 0;
 208         s32 status = 0;
 209
 210         if (hw->phy.type == ixgbe_phy_unknown)
 211                 status = ixgbe_identify_phy_generic(hw);
 212
 213         if (status != 0 || hw->phy.type == ixgbe_phy_none)
 214                 goto out;
 215
 216         /* Don't reset PHY if it's shut down due to overtemp. */
 217         if (!hw->phy.reset_if_overtemp &&
 218             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 219                 goto out;
 220
 221         /*
 222          * Perform soft PHY reset to the PHY_XS.
 223          * This will cause a soft reset to the PHY
 224          */
 225         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 226                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 227                               IXGBE_MDIO_PHY_XS_RESET);
 228
 229         /*
 230          * Poll for reset bit to self-clear indicating reset is complete.
 231          * Some PHYs could take up to 3 seconds to complete and need about
 232          * 1.7 usec delay after the reset is complete.
 233          */
 234         for (i = 0; i < 30; i++) {
 235                 msleep(100);
 236                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 237                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 238                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 239                         udelay(2);
 240                         break;
 241                 }
 242         }
 243
 244         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 245                 status = IXGBE_ERR_RESET_FAILED;
 246                 hw_dbg(hw, "PHY reset polling failed to complete.\n");
 247         }
 248
 249 out:
 250         return status;
 251 }
 252
 253 /**
 254  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 255  *  @hw: pointer to hardware structure
 256  *  @reg_addr: 32 bit address of PHY register to read
 257  *  @phy_data: Pointer to read data from PHY register
 258  **/
 259 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 260                                u32 device_type, u16 *phy_data)
 261 {
 262         u32 command;
 263         u32 i;
 264         u32 data;
 265         s32 status = 0;
 266         u16 gssr;
 267
 268         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 269                 gssr = IXGBE_GSSR_PHY1_SM;
 270         else
 271                 gssr = IXGBE_GSSR_PHY0_SM;
 272
 273         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
 274                 status = IXGBE_ERR_SWFW_SYNC;
 275
 276         if (status == 0) {
 277                 /* Setup and write the address cycle command */
 278                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 279                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 280                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 281                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 282
 283                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 284
 285                 /*
 286                  * Check every 10 usec to see if the address cycle completed.
 287                  * The MDI Command bit will clear when the operation is
 288                  * complete
 289                  */
 290                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 291                         udelay(10);
 292
 293                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 294
 295                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 296                                 break;
 297                 }
 298
 299                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 300                         hw_dbg(hw, "PHY address command did not complete.\n");
 301                         status = IXGBE_ERR_PHY;
 302                 }
 303
 304                 if (status == 0) {
 305                         /*
 306                          * Address cycle complete, setup and write the read
 307                          * command
 308                          */
 309                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 310                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 311                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 312                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 313
 314                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 315
 316                         /*
 317                          * Check every 10 usec to see if the address cycle
 318                          * completed. The MDI Command bit will clear when the
 319                          * operation is complete
 320                          */
 321                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 322                                 udelay(10);
 323
 324                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 325
 326                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 327                                         break;
 328                         }
 329
 330                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 331                                 hw_dbg(hw, "PHY read command didn't complete\n");
 332                                 status = IXGBE_ERR_PHY;
 333                         } else {
 334                                 /*
 335                                  * Read operation is complete.  Get the data
 336                                  * from MSRWD
 337                                  */
 338                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 339                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 340                                 *phy_data = (u16)(data);
 341                         }
 342                 }
 343
 344                 hw->mac.ops.release_swfw_sync(hw, gssr);
 345         }
 346
 347         return status;
 348 }
 349
 350 /**
 351  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 352  *  @hw: pointer to hardware structure
 353  *  @reg_addr: 32 bit PHY register to write
 354  *  @device_type: 5 bit device type
 355  *  @phy_data: Data to write to the PHY register
 356  **/
 357 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 358                                 u32 device_type, u16 phy_data)
 359 {
 360         u32 command;
 361         u32 i;
 362         s32 status = 0;
 363         u16 gssr;
 364
 365         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 366                 gssr = IXGBE_GSSR_PHY1_SM;
 367         else
 368                 gssr = IXGBE_GSSR_PHY0_SM;
 369
 370         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
 371                 status = IXGBE_ERR_SWFW_SYNC;
 372
 373         if (status == 0) {
 374                 /* Put the data in the MDI single read and write data register*/
 375                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 376
 377                 /* Setup and write the address cycle command */
 378                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 379                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 380                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 381                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 382
 383                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 384
 385                 /*
 386                  * Check every 10 usec to see if the address cycle completed.
 387                  * The MDI Command bit will clear when the operation is
 388                  * complete
 389                  */
 390                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 391                         udelay(10);
 392
 393                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 394
 395                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 396                                 break;
 397                 }
 398
 399                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 400                         hw_dbg(hw, "PHY address cmd didn't complete\n");
 401                         status = IXGBE_ERR_PHY;
 402                 }
 403
 404                 if (status == 0) {
 405                         /*
 406                          * Address cycle complete, setup and write the write
 407                          * command
 408                          */
 409                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 410                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 411                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 412                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 413
 414                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 415
 416                         /*
 417                          * Check every 10 usec to see if the address cycle
 418                          * completed. The MDI Command bit will clear when the
 419                          * operation is complete
 420                          */
 421                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 422                                 udelay(10);
 423
 424                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 425
 426                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 427                                         break;
 428                         }
 429
 430                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 431                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 432                                 status = IXGBE_ERR_PHY;
 433                         }
 434                 }
 435
 436                 hw->mac.ops.release_swfw_sync(hw, gssr);
 437         }
 438
 439         return status;
 440 }
 441
 442 /**
 443  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 444  *  @hw: pointer to hardware structure
 445  *
 446  *  Restart autonegotiation and PHY and waits for completion.
 447  **/
 448 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 449 {
 450         s32 status = 0;
 451         u32 time_out;
 452         u32 max_time_out = 10;
 453         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 454         bool autoneg = false;
 455         ixgbe_link_speed speed;
 456
 457         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 458
 459         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 460                 /* Set or unset auto-negotiation 10G advertisement */
 461                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 462                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 463                                      &autoneg_reg);
 464
 465                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 466                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 467                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 468
 469                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 470                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 471                                       autoneg_reg);
 472         }
 473
 474         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 475                 /* Set or unset auto-negotiation 1G advertisement */
 476                 hw->phy.ops.read_reg(hw,
 477                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 478                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 479                                      &autoneg_reg);
 480
 481                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 482                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 483                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 484
 485                 hw->phy.ops.write_reg(hw,
 486                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 487                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 488                                       autoneg_reg);
 489         }
 490
 491         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 492                 /* Set or unset auto-negotiation 100M advertisement */
 493                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 494                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 495                                      &autoneg_reg);
 496
 497                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 498                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 499                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 500                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 501
 502                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 503                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 504                                       autoneg_reg);
 505         }
 506
 507         /* Restart PHY autonegotiation and wait for completion */
 508         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 509                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 510
 511         autoneg_reg |= IXGBE_MII_RESTART;
 512
 513         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 514                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 515
 516         /* Wait for autonegotiation to finish */
 517         for (time_out = 0; time_out < max_time_out; time_out++) {
 518                 udelay(10);
 519                 /* Restart PHY autonegotiation and wait for completion */
 520                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 521                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 522                                               &autoneg_reg);
 523
 524                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 525                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 526                         break;
 527         }
 528
 529         if (time_out == max_time_out) {
 530                 status = IXGBE_ERR_LINK_SETUP;
 531                 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
 532         }
 533
 534         return status;
 535 }
 536
 537 /**
 538  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 539  *  @hw: pointer to hardware structure
 540  *  @speed: new link speed
 541  *  @autoneg: true if autonegotiation enabled
 542  **/
 543 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 544                                        ixgbe_link_speed speed,
 545                                        bool autoneg,
 546                                        bool autoneg_wait_to_complete)
 547 {
 548
 549         /*
 550          * Clear autoneg_advertised and set new values based on input link
 551          * speed.
 552          */
 553         hw->phy.autoneg_advertised = 0;
 554
 555         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 556                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 557
 558         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 559                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 560
 561         if (speed & IXGBE_LINK_SPEED_100_FULL)
 562                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 563
 564         /* Setup link based on the new speed settings */
 565         hw->phy.ops.setup_link(hw);
 566
 567         return 0;
 568 }
 569
 570 /**
 571  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 572  *  @hw: pointer to hardware structure
 573  *  @speed: pointer to link speed
 574  *  @autoneg: boolean auto-negotiation value
 575  *
 576  *  Determines the link capabilities by reading the AUTOC register.
 577  **/
 578 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 579                                                ixgbe_link_speed *speed,
 580                                                bool *autoneg)
 581 {
 582         s32 status = IXGBE_ERR_LINK_SETUP;
 583         u16 speed_ability;
 584
 585         *speed = 0;
 586         *autoneg = true;
 587
 588         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 589                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 590                                       &speed_ability);
 591
 592         if (status == 0) {
 593                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 594                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 595                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 596                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 597                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 598                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 599         }
 600
 601         return status;
 602 }
 603
 604 /**
 605  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 606  *  @hw: pointer to hardware structure
 607  *
 608  *  Reads the VS1 register to determine if link is up and the current speed for
 609  *  the PHY.
 610  **/
 611 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 612                              bool *link_up)
 613 {
 614         s32 status = 0;
 615         u32 time_out;
 616         u32 max_time_out = 10;
 617         u16 phy_link = 0;
 618         u16 phy_speed = 0;
 619         u16 phy_data = 0;
 620
 621         /* Initialize speed and link to default case */
 622         *link_up = false;
 623         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 624
 625         /*
 626          * Check current speed and link status of the PHY register.
 627          * This is a vendor specific register and may have to
 628          * be changed for other copper PHYs.
 629          */
 630         for (time_out = 0; time_out < max_time_out; time_out++) {
 631                 udelay(10);
 632                 status = hw->phy.ops.read_reg(hw,
 633                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 634                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 635                                         &phy_data);
 636                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 637                 phy_speed = phy_data &
 638                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 639                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 640                         *link_up = true;
 641                         if (phy_speed ==
 642                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 643                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 644                         break;
 645                 }
 646         }
 647
 648         return status;
 649 }
 650
 651 /**
 652  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 653  *      @hw: pointer to hardware structure
 654  *
 655  *      Restart autonegotiation and PHY and waits for completion.
 656  **/
 657 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 658 {
 659         s32 status = 0;
 660         u32 time_out;
 661         u32 max_time_out = 10;
 662         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 663         bool autoneg = false;
 664         ixgbe_link_speed speed;
 665
 666         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 667
 668         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 669                 /* Set or unset auto-negotiation 10G advertisement */
 670                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 671                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 672                                      &autoneg_reg);
 673
 674                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 675                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 676                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 677
 678                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 679                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 680                                       autoneg_reg);
 681         }
 682
 683         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 684                 /* Set or unset auto-negotiation 1G advertisement */
 685                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 686                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 687                                      &autoneg_reg);
 688
 689                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 690                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 691                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 692
 693                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 694                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 695                                       autoneg_reg);
 696         }
 697
 698         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 699                 /* Set or unset auto-negotiation 100M advertisement */
 700                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 701                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 702                                      &autoneg_reg);
 703
 704                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 705                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 706                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 707
 708                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 709                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 710                                       autoneg_reg);
 711         }
 712
 713         /* Restart PHY autonegotiation and wait for completion */
 714         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 715                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 716
 717         autoneg_reg |= IXGBE_MII_RESTART;
 718
 719         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 720                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 721
 722         /* Wait for autonegotiation to finish */
 723         for (time_out = 0; time_out < max_time_out; time_out++) {
 724                 udelay(10);
 725                 /* Restart PHY autonegotiation and wait for completion */
 726                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 727                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 728                                               &autoneg_reg);
 729
 730                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 731                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 732                         break;
 733         }
 734
 735         if (time_out == max_time_out) {
 736                 status = IXGBE_ERR_LINK_SETUP;
 737                 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
 738         }
 739
 740         return status;
 741 }
 742
 743 /**
 744  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 745  *  @hw: pointer to hardware structure
 746  *  @firmware_version: pointer to the PHY Firmware Version
 747  **/
 748 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 749                                        u16 *firmware_version)
 750 {
 751         s32 status = 0;
 752
 753         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 754                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 755                                       firmware_version);
 756
 757         return status;
 758 }
 759
 760 /**
 761  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 762  *  @hw: pointer to hardware structure
 763  *  @firmware_version: pointer to the PHY Firmware Version
 764  **/
 765 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 766                                            u16 *firmware_version)
 767 {
 768         s32 status = 0;
 769
 770         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 771                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 772                                       firmware_version);
 773
 774         return status;
 775 }
 776
 777 /**
 778  *  ixgbe_reset_phy_nl - Performs a PHY reset
 779  *  @hw: pointer to hardware structure
 780  **/
 781 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 782 {
 783         u16 phy_offset, control, eword, edata, block_crc;
 784         bool end_data = false;
 785         u16 list_offset, data_offset;
 786         u16 phy_data = 0;
 787         s32 ret_val = 0;
 788         u32 i;
 789
 790         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 791                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 792
 793         /* reset the PHY and poll for completion */
 794         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 795                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 796                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 797
 798         for (i = 0; i < 100; i++) {
 799                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 800                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 801                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 802                         break;
 803                 msleep(10);
 804         }
 805
 806         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 807                 hw_dbg(hw, "PHY reset did not complete.\n");
 808                 ret_val = IXGBE_ERR_PHY;
 809                 goto out;
 810         }
 811
 812         /* Get init offsets */
 813         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 814                                                       &data_offset);
 815         if (ret_val != 0)
 816                 goto out;
 817
 818         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 819         data_offset++;
 820         while (!end_data) {
 821                 /*
 822                  * Read control word from PHY init contents offset
 823                  */
 824                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 825                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 826                            IXGBE_CONTROL_SHIFT_NL;
 827                 edata = eword & IXGBE_DATA_MASK_NL;
 828                 switch (control) {
 829                 case IXGBE_DELAY_NL:
 830                         data_offset++;
 831                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 832                         msleep(edata);
 833                         break;
 834                 case IXGBE_DATA_NL:
 835                         hw_dbg(hw, "DATA:\n");
 836                         data_offset++;
 837                         hw->eeprom.ops.read(hw, data_offset++,
 838                                             &phy_offset);
 839                         for (i = 0; i < edata; i++) {
 840                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 841                                 hw->phy.ops.write_reg(hw, phy_offset,
 842                                                       IXGBE_TWINAX_DEV, eword);
 843                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 844                                           phy_offset);
 845                                 data_offset++;
 846                                 phy_offset++;
 847                         }
 848                         break;
 849                 case IXGBE_CONTROL_NL:
 850                         data_offset++;
 851                         hw_dbg(hw, "CONTROL:\n");
 852                         if (edata == IXGBE_CONTROL_EOL_NL) {
 853                                 hw_dbg(hw, "EOL\n");
 854                                 end_data = true;
 855                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 856                                 hw_dbg(hw, "SOL\n");
 857                         } else {
 858                                 hw_dbg(hw, "Bad control value\n");
 859                                 ret_val = IXGBE_ERR_PHY;
 860                                 goto out;
 861                         }
 862                         break;
 863                 default:
 864                         hw_dbg(hw, "Bad control type\n");
 865                         ret_val = IXGBE_ERR_PHY;
 866                         goto out;
 867                 }
 868         }
 869
 870 out:
 871         return ret_val;
 872 }
 873
 874 /**
 875  *  ixgbe_identify_module_generic - Identifies module type
 876  *  @hw: pointer to hardware structure
 877  *
 878  *  Determines HW type and calls appropriate function.
 879  **/
 880 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 881 {
 882         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 883
 884         switch (hw->mac.ops.get_media_type(hw)) {
 885         case ixgbe_media_type_fiber:
 886                 status = ixgbe_identify_sfp_module_generic(hw);
 887                 break;
 888
 889         case ixgbe_media_type_fiber_qsfp:
 890                 status = ixgbe_identify_qsfp_module_generic(hw);
 891                 break;
 892
 893         default:
 894                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 895                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 896                 break;
 897         }
 898
 899         return status;
 900 }
 901
 902 /**
 903  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 904  *  @hw: pointer to hardware structure
 905  *
 906  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 907  **/
 908 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 909 {
 910         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 911         u32 vendor_oui = 0;
 912         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 913         u8 identifier = 0;
 914         u8 comp_codes_1g = 0;
 915         u8 comp_codes_10g = 0;
 916         u8 oui_bytes[3] = {0, 0, 0};
 917         u8 cable_tech = 0;
 918         u8 cable_spec = 0;
 919         u16 enforce_sfp = 0;
 920
 921         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 922                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 923                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 924                 goto out;
 925         }
 926
 927         status = hw->phy.ops.read_i2c_eeprom(hw,
 928                                              IXGBE_SFF_IDENTIFIER,
 929                                              &identifier);
 930
 931         if (status == IXGBE_ERR_SWFW_SYNC ||
 932             status == IXGBE_ERR_I2C ||
 933             status == IXGBE_ERR_SFP_NOT_PRESENT)
 934                 goto err_read_i2c_eeprom;
 935
 936         /* LAN ID is needed for sfp_type determination */
 937         hw->mac.ops.set_lan_id(hw);
 938
 939         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 940                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 941                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 942         } else {
 943                 status = hw->phy.ops.read_i2c_eeprom(hw,
 944                                                      IXGBE_SFF_1GBE_COMP_CODES,
 945                                                      &comp_codes_1g);
 946
 947                 if (status == IXGBE_ERR_SWFW_SYNC ||
 948                     status == IXGBE_ERR_I2C ||
 949                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 950                         goto err_read_i2c_eeprom;
 951
 952                 status = hw->phy.ops.read_i2c_eeprom(hw,
 953                                                      IXGBE_SFF_10GBE_COMP_CODES,
 954                                                      &comp_codes_10g);
 955
 956                 if (status == IXGBE_ERR_SWFW_SYNC ||
 957                     status == IXGBE_ERR_I2C ||
 958                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 959                         goto err_read_i2c_eeprom;
 960                 status = hw->phy.ops.read_i2c_eeprom(hw,
 961                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
 962                                                      &cable_tech);
 963
 964                 if (status == IXGBE_ERR_SWFW_SYNC ||
 965                     status == IXGBE_ERR_I2C ||
 966                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 967                         goto err_read_i2c_eeprom;
 968
 969                  /* ID Module
 970                   * =========
 971                   * 0   SFP_DA_CU
 972                   * 1   SFP_SR
 973                   * 2   SFP_LR
 974                   * 3   SFP_DA_CORE0 - 82599-specific
 975                   * 4   SFP_DA_CORE1 - 82599-specific
 976                   * 5   SFP_SR/LR_CORE0 - 82599-specific
 977                   * 6   SFP_SR/LR_CORE1 - 82599-specific
 978                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
 979                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
 980                   * 9   SFP_1g_cu_CORE0 - 82599-specific
 981                   * 10  SFP_1g_cu_CORE1 - 82599-specific
 982                   * 11  SFP_1g_sx_CORE0 - 82599-specific
 983                   * 12  SFP_1g_sx_CORE1 - 82599-specific
 984                   */
 985                 if (hw->mac.type == ixgbe_mac_82598EB) {
 986                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 987                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 988                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 989                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
 990                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 991                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
 992                         else
 993                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 994                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
 995                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 996                                 if (hw->bus.lan_id == 0)
 997                                         hw->phy.sfp_type =
 998                                                      ixgbe_sfp_type_da_cu_core0;
 999                                 else
1000                                         hw->phy.sfp_type =
1001                                                      ixgbe_sfp_type_da_cu_core1;
1002                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1003                                 hw->phy.ops.read_i2c_eeprom(
1004                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1005                                                 &cable_spec);
1006                                 if (cable_spec &
1007                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1008                                         if (hw->bus.lan_id == 0)
1009                                                 hw->phy.sfp_type =
1010                                                 ixgbe_sfp_type_da_act_lmt_core0;
1011                                         else
1012                                                 hw->phy.sfp_type =
1013                                                 ixgbe_sfp_type_da_act_lmt_core1;
1014                                 } else {
1015                                         hw->phy.sfp_type =
1016                                                         ixgbe_sfp_type_unknown;
1017                                 }
1018                         } else if (comp_codes_10g &
1019                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1020                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1021                                 if (hw->bus.lan_id == 0)
1022                                         hw->phy.sfp_type =
1023                                                       ixgbe_sfp_type_srlr_core0;
1024                                 else
1025                                         hw->phy.sfp_type =
1026                                                       ixgbe_sfp_type_srlr_core1;
1027                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1028                                 if (hw->bus.lan_id == 0)
1029                                         hw->phy.sfp_type =
1030                                                 ixgbe_sfp_type_1g_cu_core0;
1031                                 else
1032                                         hw->phy.sfp_type =
1033                                                 ixgbe_sfp_type_1g_cu_core1;
1034                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1035                                 if (hw->bus.lan_id == 0)
1036                                         hw->phy.sfp_type =
1037                                                 ixgbe_sfp_type_1g_sx_core0;
1038                                 else
1039                                         hw->phy.sfp_type =
1040                                                 ixgbe_sfp_type_1g_sx_core1;
1041                         } else {
1042                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1043                         }
1044                 }
1045
1046                 if (hw->phy.sfp_type != stored_sfp_type)
1047                         hw->phy.sfp_setup_needed = true;
1048
1049                 /* Determine if the SFP+ PHY is dual speed or not. */
1050                 hw->phy.multispeed_fiber = false;
1051                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1052                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1053                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1054                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1055                         hw->phy.multispeed_fiber = true;
1056
1057                 /* Determine PHY vendor */
1058                 if (hw->phy.type != ixgbe_phy_nl) {
1059                         hw->phy.id = identifier;
1060                         status = hw->phy.ops.read_i2c_eeprom(hw,
1061                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1062                                                     &oui_bytes[0]);
1063
1064                         if (status == IXGBE_ERR_SWFW_SYNC ||
1065                             status == IXGBE_ERR_I2C ||
1066                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1067                                 goto err_read_i2c_eeprom;
1068
1069                         status = hw->phy.ops.read_i2c_eeprom(hw,
1070                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1071                                                     &oui_bytes[1]);
1072
1073                         if (status == IXGBE_ERR_SWFW_SYNC ||
1074                             status == IXGBE_ERR_I2C ||
1075                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1076                                 goto err_read_i2c_eeprom;
1077
1078                         status = hw->phy.ops.read_i2c_eeprom(hw,
1079                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1080                                                     &oui_bytes[2]);
1081
1082                         if (status == IXGBE_ERR_SWFW_SYNC ||
1083                             status == IXGBE_ERR_I2C ||
1084                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1085                                 goto err_read_i2c_eeprom;
1086
1087                         vendor_oui =
1088                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1089                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1090                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1091
1092                         switch (vendor_oui) {
1093                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1094                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1095                                         hw->phy.type =
1096                                                     ixgbe_phy_sfp_passive_tyco;
1097                                 break;
1098                         case IXGBE_SFF_VENDOR_OUI_FTL:
1099                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1100                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1101                                 else
1102                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1103                                 break;
1104                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1105                                 hw->phy.type = ixgbe_phy_sfp_avago;
1106                                 break;
1107                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1108                                 hw->phy.type = ixgbe_phy_sfp_intel;
1109                                 break;
1110                         default:
1111                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1112                                         hw->phy.type =
1113                                                  ixgbe_phy_sfp_passive_unknown;
1114                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1115                                         hw->phy.type =
1116                                                 ixgbe_phy_sfp_active_unknown;
1117                                 else
1118                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1119                                 break;
1120                         }
1121                 }
1122
1123                 /* Allow any DA cable vendor */
1124                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1125                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1126                         status = 0;
1127                         goto out;
1128                 }
1129
1130                 /* Verify supported 1G SFP modules */
1131                 if (comp_codes_10g == 0 &&
1132                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1133                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1134                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0  ||
1135                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1136                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1137                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1138                         goto out;
1139                 }
1140
1141                 /* Anything else 82598-based is supported */
1142                 if (hw->mac.type == ixgbe_mac_82598EB) {
1143                         status = 0;
1144                         goto out;
1145                 }
1146
1147                 ixgbe_get_device_caps(hw, &enforce_sfp);
1148                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1149                     !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1150                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1151                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0)  ||
1152                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1153                         /* Make sure we're a supported PHY type */
1154                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1155                                 status = 0;
1156                         } else {
1157                                 if (hw->allow_unsupported_sfp == true) {
1158                                         EWARN(hw, "WARNING: Intel (R) Network "
1159                                               "Connections are quality tested "
1160                                               "using Intel (R) Ethernet Optics."
1161                                               " Using untested modules is not "
1162                                               "supported and may cause unstable"
1163                                               " operation or damage to the "
1164                                               "module or the adapter. Intel "
1165                                               "Corporation is not responsible "
1166                                               "for any harm caused by using "
1167                                               "untested modules.\n", status);
1168                                         status = 0;
1169                                 } else {
1170                                         hw_dbg(hw, "SFP+ module not supported\n");
1171                                         hw->phy.type =
1172                                                 ixgbe_phy_sfp_unsupported;
1173                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1174                                 }
1175                         }
1176                 } else {
1177                         status = 0;
1178                 }
1179         }
1180
1181 out:
1182         return status;
1183
1184 err_read_i2c_eeprom:
1185         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1186         if (hw->phy.type != ixgbe_phy_nl) {
1187                 hw->phy.id = 0;
1188                 hw->phy.type = ixgbe_phy_unknown;
1189         }
1190         return IXGBE_ERR_SFP_NOT_PRESENT;
1191 }
1192
1193 /**
1194  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1195  *  @hw: pointer to hardware structure
1196  *
1197  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1198  **/
1199 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1200 {
1201         s32 status = 0;
1202
1203         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1204                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1205                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1206         }
1207
1208         return status;
1209 }
1210
1211
1212 /**
1213  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1214  *  @hw: pointer to hardware structure
1215  *  @list_offset: offset to the SFP ID list
1216  *  @data_offset: offset to the SFP data block
1217  *
1218  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1219  *  so it returns the offsets to the phy init sequence block.
1220  **/
1221 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1222                                         u16 *list_offset,
1223                                         u16 *data_offset)
1224 {
1225         u16 sfp_id;
1226         u16 sfp_type = hw->phy.sfp_type;
1227
1228         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1229                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1230
1231         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1232                 return IXGBE_ERR_SFP_NOT_PRESENT;
1233
1234         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1235             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1236                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1237
1238         /*
1239          * Limiting active cables and 1G Phys must be initialized as
1240          * SR modules
1241          */
1242         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1243             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1244             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1245                 sfp_type = ixgbe_sfp_type_srlr_core0;
1246         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1247                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1248                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1249                 sfp_type = ixgbe_sfp_type_srlr_core1;
1250
1251         /* Read offset to PHY init contents */
1252         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1253
1254         if ((!*list_offset) || (*list_offset == 0xFFFF))
1255                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1256
1257         /* Shift offset to first ID word */
1258         (*list_offset)++;
1259
1260         /*
1261          * Find the matching SFP ID in the EEPROM
1262          * and program the init sequence
1263          */
1264         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1265
1266         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1267                 if (sfp_id == sfp_type) {
1268                         (*list_offset)++;
1269                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
1270                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1271                                 hw_dbg(hw, "SFP+ module not supported\n");
1272                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1273                         } else {
1274                                 break;
1275                         }
1276                 } else {
1277                         (*list_offset) += 2;
1278                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1279                                 return IXGBE_ERR_PHY;
1280                 }
1281         }
1282
1283         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1284                 hw_dbg(hw, "No matching SFP+ module found\n");
1285                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1286         }
1287
1288         return 0;
1289 }
1290
1291 /**
1292  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1293  *  @hw: pointer to hardware structure
1294  *  @byte_offset: EEPROM byte offset to read
1295  *  @eeprom_data: value read
1296  *
1297  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1298  **/
1299 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1300                                   u8 *eeprom_data)
1301 {
1302         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1303                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1304                                          eeprom_data);
1305 }
1306
1307 /**
1308  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1309  *  @hw: pointer to hardware structure
1310  *  @byte_offset: EEPROM byte offset to write
1311  *  @eeprom_data: value to write
1312  *
1313  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1314  **/
1315 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1316                                    u8 eeprom_data)
1317 {
1318         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1319                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1320                                           eeprom_data);
1321 }
1322
1323 /**
1324  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1325  *  @hw: pointer to hardware structure
1326  *  @byte_offset: byte offset to read
1327  *  @data: value read
1328  *
1329  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1330  *  a specified device address.
1331  **/
1332 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1333                                 u8 dev_addr, u8 *data)
1334 {
1335         s32 status = 0;
1336         u32 max_retry = 10;
1337         u32 retry = 0;
1338         u16 swfw_mask = 0;
1339         bool nack = 1;
1340         *data = 0;
1341
1342         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1343                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1344         else
1345                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1346
1347         do {
1348                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1349                     != 0) {
1350                         status = IXGBE_ERR_SWFW_SYNC;
1351                         goto read_byte_out;
1352                 }
1353
1354                 ixgbe_i2c_start(hw);
1355
1356                 /* Device Address and write indication */
1357                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1358                 if (status != 0)
1359                         goto fail;
1360
1361                 status = ixgbe_get_i2c_ack(hw);
1362                 if (status != 0)
1363                         goto fail;
1364
1365                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1366                 if (status != 0)
1367                         goto fail;
1368
1369                 status = ixgbe_get_i2c_ack(hw);
1370                 if (status != 0)
1371                         goto fail;
1372
1373                 ixgbe_i2c_start(hw);
1374
1375                 /* Device Address and read indication */
1376                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1377                 if (status != 0)
1378                         goto fail;
1379
1380                 status = ixgbe_get_i2c_ack(hw);
1381                 if (status != 0)
1382                         goto fail;
1383
1384                 status = ixgbe_clock_in_i2c_byte(hw, data);
1385                 if (status != 0)
1386                         goto fail;
1387
1388                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1389                 if (status != 0)
1390                         goto fail;
1391
1392                 ixgbe_i2c_stop(hw);
1393                 break;
1394
1395 fail:
1396                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1397                 msleep(100);
1398                 ixgbe_i2c_bus_clear(hw);
1399                 retry++;
1400                 if (retry < max_retry)
1401                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
1402                 else
1403                         hw_dbg(hw, "I2C byte read error.\n");
1404
1405         } while (retry < max_retry);
1406
1407         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1408
1409 read_byte_out:
1410         return status;
1411 }
1412
1413 /**
1414  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1415  *  @hw: pointer to hardware structure
1416  *  @byte_offset: byte offset to write
1417  *  @data: value to write
1418  *
1419  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1420  *  a specified device address.
1421  **/
1422 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1423                                  u8 dev_addr, u8 data)
1424 {
1425         s32 status = 0;
1426         u32 max_retry = 1;
1427         u32 retry = 0;
1428         u16 swfw_mask = 0;
1429
1430         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1431                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1432         else
1433                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1434
1435         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1436                 status = IXGBE_ERR_SWFW_SYNC;
1437                 goto write_byte_out;
1438         }
1439
1440         do {
1441                 ixgbe_i2c_start(hw);
1442
1443                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1444                 if (status != 0)
1445                         goto fail;
1446
1447                 status = ixgbe_get_i2c_ack(hw);
1448                 if (status != 0)
1449                         goto fail;
1450
1451                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1452                 if (status != 0)
1453                         goto fail;
1454
1455                 status = ixgbe_get_i2c_ack(hw);
1456                 if (status != 0)
1457                         goto fail;
1458
1459                 status = ixgbe_clock_out_i2c_byte(hw, data);
1460                 if (status != 0)
1461                         goto fail;
1462
1463                 status = ixgbe_get_i2c_ack(hw);
1464                 if (status != 0)
1465                         goto fail;
1466
1467                 ixgbe_i2c_stop(hw);
1468                 break;
1469
1470 fail:
1471                 ixgbe_i2c_bus_clear(hw);
1472                 retry++;
1473                 if (retry < max_retry)
1474                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
1475                 else
1476                         hw_dbg(hw, "I2C byte write error.\n");
1477         } while (retry < max_retry);
1478
1479         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1480
1481 write_byte_out:
1482         return status;
1483 }
1484
1485 /**
1486  *  ixgbe_i2c_start - Sets I2C start condition
1487  *  @hw: pointer to hardware structure
1488  *
1489  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1490  **/
1491 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1492 {
1493         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1494
1495         /* Start condition must begin with data and clock high */
1496         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1497         ixgbe_raise_i2c_clk(hw, &i2cctl);
1498
1499         /* Setup time for start condition (4.7us) */
1500         udelay(IXGBE_I2C_T_SU_STA);
1501
1502         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1503
1504         /* Hold time for start condition (4us) */
1505         udelay(IXGBE_I2C_T_HD_STA);
1506
1507         ixgbe_lower_i2c_clk(hw, &i2cctl);
1508
1509         /* Minimum low period of clock is 4.7 us */
1510         udelay(IXGBE_I2C_T_LOW);
1511
1512 }
1513
1514 /**
1515  *  ixgbe_i2c_stop - Sets I2C stop condition
1516  *  @hw: pointer to hardware structure
1517  *
1518  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1519  **/
1520 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1521 {
1522         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1523
1524         /* Stop condition must begin with data low and clock high */
1525         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1526         ixgbe_raise_i2c_clk(hw, &i2cctl);
1527
1528         /* Setup time for stop condition (4us) */
1529         udelay(IXGBE_I2C_T_SU_STO);
1530
1531         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1532
1533         /* bus free time between stop and start (4.7us)*/
1534         udelay(IXGBE_I2C_T_BUF);
1535 }
1536
1537 /**
1538  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1539  *  @hw: pointer to hardware structure
1540  *  @data: data byte to clock in
1541  *
1542  *  Clocks in one byte data via I2C data/clock
1543  **/
1544 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1545 {
1546         s32 i;
1547         bool bit = 0;
1548
1549         for (i = 7; i >= 0; i--) {
1550                 ixgbe_clock_in_i2c_bit(hw, &bit);
1551                 *data |= bit << i;
1552         }
1553
1554         return 0;
1555 }
1556
1557 /**
1558  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1559  *  @hw: pointer to hardware structure
1560  *  @data: data byte clocked out
1561  *
1562  *  Clocks out one byte data via I2C data/clock
1563  **/
1564 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1565 {
1566         s32 status = 0;
1567         s32 i;
1568         u32 i2cctl;
1569         bool bit = 0;
1570
1571         for (i = 7; i >= 0; i--) {
1572                 bit = (data >> i) & 0x1;
1573                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1574
1575                 if (status != 0)
1576                         break;
1577         }
1578
1579         /* Release SDA line (set high) */
1580         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1581         i2cctl |= IXGBE_I2C_DATA_OUT;
1582         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1583         IXGBE_WRITE_FLUSH(hw);
1584
1585         return status;
1586 }
1587
1588 /**
1589  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1590  *  @hw: pointer to hardware structure
1591  *
1592  *  Clocks in/out one bit via I2C data/clock
1593  **/
1594 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1595 {
1596         s32 status = 0;
1597         u32 i = 0;
1598         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1599         u32 timeout = 10;
1600         bool ack = 1;
1601
1602         ixgbe_raise_i2c_clk(hw, &i2cctl);
1603
1604
1605         /* Minimum high period of clock is 4us */
1606         udelay(IXGBE_I2C_T_HIGH);
1607
1608         /* Poll for ACK.  Note that ACK in I2C spec is
1609          * transition from 1 to 0 */
1610         for (i = 0; i < timeout; i++) {
1611                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1612                 ack = ixgbe_get_i2c_data(&i2cctl);
1613
1614                 udelay(1);
1615                 if (ack == 0)
1616                         break;
1617         }
1618
1619         if (ack == 1) {
1620                 hw_dbg(hw, "I2C ack was not received.\n");
1621                 status = IXGBE_ERR_I2C;
1622         }
1623
1624         ixgbe_lower_i2c_clk(hw, &i2cctl);
1625
1626         /* Minimum low period of clock is 4.7 us */
1627         udelay(IXGBE_I2C_T_LOW);
1628
1629         return status;
1630 }
1631
1632 /**
1633  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1634  *  @hw: pointer to hardware structure
1635  *  @data: read data value
1636  *
1637  *  Clocks in one bit via I2C data/clock
1638  **/
1639 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1640 {
1641         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1642
1643         ixgbe_raise_i2c_clk(hw, &i2cctl);
1644
1645         /* Minimum high period of clock is 4us */
1646         udelay(IXGBE_I2C_T_HIGH);
1647
1648         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1649         *data = ixgbe_get_i2c_data(&i2cctl);
1650
1651         ixgbe_lower_i2c_clk(hw, &i2cctl);
1652
1653         /* Minimum low period of clock is 4.7 us */
1654         udelay(IXGBE_I2C_T_LOW);
1655
1656         return 0;
1657 }
1658
1659 /**
1660  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1661  *  @hw: pointer to hardware structure
1662  *  @data: data value to write
1663  *
1664  *  Clocks out one bit via I2C data/clock
1665  **/
1666 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1667 {
1668         s32 status;
1669         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1670
1671         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1672         if (status == 0) {
1673                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1674
1675                 /* Minimum high period of clock is 4us */
1676                 udelay(IXGBE_I2C_T_HIGH);
1677
1678                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1679
1680                 /* Minimum low period of clock is 4.7 us.
1681                  * This also takes care of the data hold time.
1682                  */
1683                 udelay(IXGBE_I2C_T_LOW);
1684         } else {
1685                 status = IXGBE_ERR_I2C;
1686                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1687         }
1688
1689         return status;
1690 }
1691 /**
1692  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1693  *  @hw: pointer to hardware structure
1694  *  @i2cctl: Current value of I2CCTL register
1695  *
1696  *  Raises the I2C clock line '0'->'1'
1697  **/
1698 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1699 {
1700         u32 i = 0;
1701         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1702         u32 i2cctl_r = 0;
1703
1704         for (i = 0; i < timeout; i++) {
1705                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1706
1707                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1708                 IXGBE_WRITE_FLUSH(hw);
1709                 /* SCL rise time (1000ns) */
1710                 udelay(IXGBE_I2C_T_RISE);
1711
1712                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1713                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1714                         break;
1715         }
1716 }
1717
1718 /**
1719  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1720  *  @hw: pointer to hardware structure
1721  *  @i2cctl: Current value of I2CCTL register
1722  *
1723  *  Lowers the I2C clock line '1'->'0'
1724  **/
1725 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1726 {
1727
1728         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1729
1730         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1731         IXGBE_WRITE_FLUSH(hw);
1732
1733         /* SCL fall time (300ns) */
1734         udelay(IXGBE_I2C_T_FALL);
1735 }
1736
1737 /**
1738  *  ixgbe_set_i2c_data - Sets the I2C data bit
1739  *  @hw: pointer to hardware structure
1740  *  @i2cctl: Current value of I2CCTL register
1741  *  @data: I2C data value (0 or 1) to set
1742  *
1743  *  Sets the I2C data bit
1744  **/
1745 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1746 {
1747         s32 status = 0;
1748
1749         if (data)
1750                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1751         else
1752                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1753
1754         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1755         IXGBE_WRITE_FLUSH(hw);
1756
1757         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1758         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1759
1760         /* Verify data was set correctly */
1761         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1762         if (data != ixgbe_get_i2c_data(i2cctl)) {
1763                 status = IXGBE_ERR_I2C;
1764                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1765         }
1766
1767         return status;
1768 }
1769
1770 /**
1771  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1772  *  @hw: pointer to hardware structure
1773  *  @i2cctl: Current value of I2CCTL register
1774  *
1775  *  Returns the I2C data bit value
1776  **/
1777 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1778 {
1779         bool data;
1780
1781         if (*i2cctl & IXGBE_I2C_DATA_IN)
1782                 data = 1;
1783         else
1784                 data = 0;
1785
1786         return data;
1787 }
1788
1789 /**
1790  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1791  *  @hw: pointer to hardware structure
1792  *
1793  *  Clears the I2C bus by sending nine clock pulses.
1794  *  Used when data line is stuck low.
1795  **/
1796 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1797 {
1798         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1799         u32 i;
1800
1801         ixgbe_i2c_start(hw);
1802
1803         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1804
1805         for (i = 0; i < 9; i++) {
1806                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1807
1808                 /* Min high period of clock is 4us */
1809                 udelay(IXGBE_I2C_T_HIGH);
1810
1811                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1812
1813                 /* Min low period of clock is 4.7us*/
1814                 udelay(IXGBE_I2C_T_LOW);
1815         }
1816
1817         ixgbe_i2c_start(hw);
1818
1819         /* Put the i2c bus back to default state */
1820         ixgbe_i2c_stop(hw);
1821 }
1822
1823 /**
1824  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1825  *  @hw: pointer to hardware structure
1826  *
1827  *  Checks if the LASI temp alarm status was triggered due to overtemp
1828  **/
1829 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1830 {
1831         s32 status = 0;
1832         u16 phy_data = 0;
1833
1834         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1835                 goto out;
1836
1837         /* Check that the LASI temp alarm status was triggered */
1838         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1839                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1840
1841         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1842                 goto out;
1843
1844         status = IXGBE_ERR_OVERTEMP;
1845 out:
1846         return status;
1847 }