build/external/patches/dpdk_20.02/0013-net-iavf-support-flow-mark-in-AVX-path.patch

   1 From f5de510dd842be737259ef31d1300b57890ae90e Mon Sep 17 00:00:00 2001
   2 From: Leyi Rong <leyi.rong@intel.com>
   3 Date: Wed, 8 Apr 2020 14:22:07 +0800
   4 Subject: [DPDK 13/17] net/iavf: support flow mark in AVX path
   5
   6 Support Flow Director mark ID parsing from Flex
   7 Rx descriptor in AVX path.
   8
   9 Signed-off-by: Leyi Rong <leyi.rong@intel.com>
  10 ---
  11  drivers/net/iavf/iavf_rxtx_vec_avx2.c | 72 +++++++++++++++++++++++++--
  12  1 file changed, 67 insertions(+), 5 deletions(-)
  13
  14 diff --git a/drivers/net/iavf/iavf_rxtx_vec_avx2.c b/drivers/net/iavf/iavf_rxtx_vec_avx2.c
  15 index b23188fd3..3bf5833fa 100644
  16 --- a/drivers/net/iavf/iavf_rxtx_vec_avx2.c
  17 +++ b/drivers/net/iavf/iavf_rxtx_vec_avx2.c
  18 @@ -616,6 +616,25 @@ _iavf_recv_raw_pkts_vec_avx2(struct iavf_rx_queue *rxq,
  19         return received;
  20  }
  21
  22 +static inline __m256i
  23 +flex_rxd_to_fdir_flags_vec_avx2(const __m256i fdir_id0_7)
  24 +{
  25 +#define FDID_MIS_MAGIC 0xFFFFFFFF
  26 +       RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));
  27 +       RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
  28 +       const __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR |
  29 +                       PKT_RX_FDIR_ID);
  30 +       /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
  31 +       const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
  32 +       __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
  33 +                       fdir_mis_mask);
  34 +       /* this XOR op results to bit-reverse the fdir_mask */
  35 +       fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
  36 +       const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
  37 +
  38 +       return fdir_flags;
  39 +}
  40 +
  41  static inline uint16_t
  42  _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,
  43                                       struct rte_mbuf **rx_pkts,
  44 @@ -678,8 +697,8 @@ _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,
  45         const __m256i shuf_msk =
  46                 _mm256_set_epi8
  47                         (/* first descriptor */
  48 -                        15, 14,
  49 -                        13, 12,        /* octet 12~15, 32 bits rss */
  50 +                        0xFF, 0xFF,
  51 +                        0xFF, 0xFF,    /* rss not supported */
  52                          11, 10,        /* octet 10~11, 16 bits vlan_macip */
  53                          5, 4,          /* octet 4~5, 16 bits data_len */
  54                          0xFF, 0xFF,    /* skip hi 16 bits pkt_len, zero out */
  55 @@ -687,8 +706,8 @@ _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,
  56                          0xFF, 0xFF,    /* pkt_type set as unknown */
  57                          0xFF, 0xFF,    /*pkt_type set as unknown */
  58                          /* second descriptor */
  59 -                        15, 14,
  60 -                        13, 12,        /* octet 12~15, 32 bits rss */
  61 +                        0xFF, 0xFF,
  62 +                        0xFF, 0xFF,    /* rss not supported */
  63                          11, 10,        /* octet 10~11, 16 bits vlan_macip */
  64                          5, 4,          /* octet 4~5, 16 bits data_len */
  65                          0xFF, 0xFF,    /* skip hi 16 bits pkt_len, zero out */
  66 @@ -930,8 +949,51 @@ _iavf_recv_raw_pkts_vec_avx2_flex_rxd(struct iavf_rx_queue *rxq,
  67                                             rss_vlan_flag_bits);
  68
  69                 /* merge flags */
  70 -               const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
  71 +               __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
  72                                 rss_vlan_flags);
  73 +
  74 +               if (rxq->fdir_enabled) {
  75 +                       const __m256i fdir_id4_7 =
  76 +                               _mm256_unpackhi_epi32(raw_desc6_7, raw_desc4_5);
  77 +
  78 +                       const __m256i fdir_id0_3 =
  79 +                               _mm256_unpackhi_epi32(raw_desc2_3, raw_desc0_1);
  80 +
  81 +                       const __m256i fdir_id0_7 =
  82 +                               _mm256_unpackhi_epi64(fdir_id4_7, fdir_id0_3);
  83 +
  84 +                       const __m256i fdir_flags =
  85 +                               flex_rxd_to_fdir_flags_vec_avx2(fdir_id0_7);
  86 +
  87 +                       /* merge with fdir_flags */
  88 +                       mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);
  89 +
  90 +                       /* write to mbuf: have to use scalar store here */
  91 +                       rx_pkts[i + 0]->hash.fdir.hi =
  92 +                               _mm256_extract_epi32(fdir_id0_7, 3);
  93 +
  94 +                       rx_pkts[i + 1]->hash.fdir.hi =
  95 +                               _mm256_extract_epi32(fdir_id0_7, 7);
  96 +
  97 +                       rx_pkts[i + 2]->hash.fdir.hi =
  98 +                               _mm256_extract_epi32(fdir_id0_7, 2);
  99 +
 100 +                       rx_pkts[i + 3]->hash.fdir.hi =
 101 +                               _mm256_extract_epi32(fdir_id0_7, 6);
 102 +
 103 +                       rx_pkts[i + 4]->hash.fdir.hi =
 104 +                               _mm256_extract_epi32(fdir_id0_7, 1);
 105 +
 106 +                       rx_pkts[i + 5]->hash.fdir.hi =
 107 +                               _mm256_extract_epi32(fdir_id0_7, 5);
 108 +
 109 +                       rx_pkts[i + 6]->hash.fdir.hi =
 110 +                               _mm256_extract_epi32(fdir_id0_7, 0);
 111 +
 112 +                       rx_pkts[i + 7]->hash.fdir.hi =
 113 +                               _mm256_extract_epi32(fdir_id0_7, 4);
 114 +               } /* if() on fdir_enabled */
 115 +
 116                 /**
 117                  * At this point, we have the 8 sets of flags in the low 16-bits
 118                  * of each 32-bit value in vlan0.
 119 --
 120 2.17.1
 121