2 * Copyright (c) 2022 Arm and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #include <vnet/vnet.h>
17 #include <vppinfra/linux/sysfs.h>
18 #include <perfmon/perfmon.h>
19 #include <perfmon/arm/events.h>
21 /* as per .events[n] in PERFMON_REGISTER_BUNDLE */
31 format_arm_cache_data_tlb (u8 *s, va_list *args)
33 perfmon_node_stats_t *ns = va_arg (*args, perfmon_node_stats_t *);
34 int row = va_arg (*args, int);
39 s = format (s, "%.2f", (f64) ns->value[L1D_TLB] / ns->n_packets);
43 s = format (s, "%.2f", (f64) ns->value[L1D_TLB_REFILL] / ns->n_packets);
47 s = format (s, "%.2f%%",
48 (ns->value[L1D_TLB] ? (f64) ns->value[L1D_TLB_REFILL] /
49 ns->value[L1D_TLB] * 100 :
54 s = format (s, "%.2f", (f64) ns->value[L2D_TLB] / ns->n_packets);
58 s = format (s, "%.2f", (f64) ns->value[L2D_TLB_REFILL] / ns->n_packets);
62 s = format (s, "%.2f%%",
63 (ns->value[L2D_TLB] ? (f64) ns->value[L2D_TLB_REFILL] /
64 ns->value[L2D_TLB] * 100 :
69 s = format (s, "%llu", ns->n_packets);
75 PERFMON_REGISTER_BUNDLE (arm_cache_data_tlb) = {
76 .name = "cache-data-tlb",
77 .description = "L1/L2 data TLB cache accesses, refills, walks per packet",
79 .type = PERFMON_BUNDLE_TYPE_NODE,
80 .events[0] = ARMV8_PMUV3_L1D_TLB,
81 .events[1] = ARMV8_PMUV3_L1D_TLB_REFILL,
82 .events[2] = ARMV8_PMUV3_L2D_TLB,
83 .events[3] = ARMV8_PMUV3_L2D_TLB_REFILL,
86 .format_fn = format_arm_cache_data_tlb,
87 .column_headers = PERFMON_STRINGS ("L1D-TLB: access", "refill", "\%*",
88 "L2D-TLB: access", "refill", "\%*",
91 * set a bit for every event used in each column
92 * this allows us to disable columns at bundle registration if an
93 * event is not supported
95 .column_events = PERFMON_COLUMN_EVENTS (
96 SET_BIT (L1D_TLB), SET_BIT (L1D_TLB_REFILL),
97 SET_BIT (L1D_TLB) | SET_BIT (L1D_TLB_REFILL), SET_BIT (L2D_TLB),
98 SET_BIT (L2D_TLB_REFILL), SET_BIT (L2D_TLB) | SET_BIT (L2D_TLB_REFILL), 0),
100 "all stats are per packet except refill rates (\%)\n"
101 "*\% percentage shown is total refills/accesses\n\n"
102 "TLB: Memory-read operation or Memory-write operation that"
103 " causes a TLB access to at least the Level 1/2 data or unified TLB.\n"
104 "- See Armv8-A Architecture Reference Manual, D7.10 PMU events and"
105 " event numbers for full description.\n"