2 * Copyright (c) 2020 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #ifndef __perfmon_intel_h
17 #define __perfmon_intel_h
19 #define PERF_INTEL_CODE(event, umask, edge, any, inv, cmask) \
20 ((event) | (umask) << 8 | (edge) << 18 | (any) << 21 | (inv) << 23 | \
23 /* EventCode, UMask, EdgeDetect, AnyThread, Invert, CounterMask
24 * counter_unit, name, suffix, description */
25 #define foreach_perf_intel_core_event \
26 _ (0x00, 0x02, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, THREAD, \
27 "Core cycles when the thread is not in halt state") \
28 _ (0x00, 0x03, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, REF_TSC, \
29 "Reference cycles when the core is not in halt state.") \
30 _ (0x03, 0x02, 0, 0, 0, 0x00, LD_BLOCKS, STORE_FORWARD, \
31 "Loads blocked due to overlapping with a preceding store that cannot be" \
33 _ (0x03, 0x08, 0, 0, 0, 0x00, LD_BLOCKS, NO_SR, \
34 "The number of times that split load operations are temporarily " \
36 "because all resources for handling the split accesses are in use.") \
37 _ (0x07, 0x01, 0, 0, 0, 0x00, LD_BLOCKS_PARTIAL, ADDRESS_ALIAS, \
38 "False dependencies in MOB due to partial compare on address.") \
39 _ (0x08, 0x01, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, MISS_CAUSES_A_WALK, \
40 "Load misses in all DTLB levels that cause page walks") \
41 _ (0x08, 0x02, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_4K, \
42 "Page walk completed due to a demand data load to a 4K page") \
43 _ (0x08, 0x04, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_2M_4M, \
44 "Page walk completed due to a demand data load to a 2M/4M page") \
45 _ (0x08, 0x08, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED_1G, \
46 "Page walk completed due to a demand data load to a 1G page") \
47 _ (0x08, 0x0E, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_COMPLETED, \
48 "Load miss in all TLB levels causes a page walk that completes. (All " \
50 _ (0x08, 0x10, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, WALK_PENDING, \
51 "Counts 1 per cycle for each PMH that is busy with a page walk for a " \
52 "load. EPT page walk duration are excluded in Skylake.") \
53 _ (0x08, 0x20, 0, 0, 0, 0x00, DTLB_LOAD_MISSES, STLB_HIT, \
54 "Loads that miss the DTLB and hit the STLB.") \
55 _ (0x0D, 0x01, 0, 0, 0, 0x00, INT_MISC, RECOVERY_CYCLES, \
56 "Core cycles the allocator was stalled due to recovery from earlier " \
57 "clear event for this thread (e.g. misprediction or memory nuke)") \
58 _ (0x0E, 0x01, 0, 0, 0, 0x00, UOPS_ISSUED, ANY, \
59 "Uops that Resource Allocation Table (RAT) issues to Reservation " \
61 _ (0x28, 0x07, 0, 0, 0, 0x00, CORE_POWER, LVL0_TURBO_LICENSE, \
62 "Core cycles where the core was running in a manner where Turbo may be " \
63 "clipped to the Non-AVX turbo schedule.") \
64 _ (0x28, 0x18, 0, 0, 0, 0x00, CORE_POWER, LVL1_TURBO_LICENSE, \
65 "Core cycles where the core was running in a manner where Turbo may be " \
66 "clipped to the AVX2 turbo schedule.") \
67 _ (0x28, 0x20, 0, 0, 0, 0x00, CORE_POWER, LVL2_TURBO_LICENSE, \
68 "Core cycles where the core was running in a manner where Turbo may be " \
69 "clipped to the AVX512 turbo schedule.") \
70 _ (0x28, 0x40, 0, 0, 0, 0x00, CORE_POWER, THROTTLE, \
71 "Core cycles the core was throttled due to a pending power level " \
73 _ (0x3C, 0x00, 0, 0, 0, 0x00, CPU_CLK_UNHALTED, THREAD_P, \
74 "Thread cycles when thread is not in halt state") \
75 _ (0x3C, 0x00, 0, 1, 0, 0x00, CPU_CLK_UNHALTED, THREAD_P_ANY, \
76 "Core cycles when at least one thread on the physical core is not in " \
78 _ (0x3C, 0x00, 1, 0, 0, 0x01, CPU_CLK_UNHALTED, RING0_TRANS, \
79 "Counts when there is a transition from ring 1, 2 or 3 to ring 0.") \
80 _ (0x48, 0x01, 0, 0, 0, 0x01, L1D_PEND_MISS, PENDING_CYCLES, \
81 "Cycles with L1D load Misses outstanding.") \
82 _ (0x48, 0x01, 0, 0, 0, 0x00, L1D_PEND_MISS, PENDING, \
83 "L1D miss outstandings duration in cycles") \
84 _ (0x48, 0x02, 0, 0, 0, 0x00, L1D_PEND_MISS, FB_FULL, \
85 "Number of times a request needed a FB entry but there was no entry " \
86 "available for it. That is the FB unavailability was dominant reason " \
87 "for blocking the request. A request includes cacheable/uncacheable " \
88 "demands that is load, store or SW prefetch.") \
89 _ (0x51, 0x01, 0, 0, 0, 0x00, L1D, REPLACEMENT, \
90 "L1D data line replacements") \
91 _ (0x51, 0x04, 0, 0, 0, 0x00, L1D, M_EVICT, "L1D data line evictions") \
92 _ (0x83, 0x02, 0, 0, 0, 0x00, ICACHE_64B, IFTAG_MISS, \
93 "Instruction fetch tag lookups that miss in the instruction cache " \
94 "(L1I). Counts at 64-byte cache-line granularity.") \
95 _ (0x9C, 0x01, 0, 0, 0, 0x00, IDQ_UOPS_NOT_DELIVERED, CORE, \
96 "Uops not delivered to Resource Allocation Table (RAT) per thread when " \
97 "backend of the machine is not stalled") \
98 _ (0xC0, 0x00, 0, 0, 0, 0x00, INST_RETIRED, ANY_P, \
99 "Number of instructions retired. General Counter - architectural event") \
100 _ (0xC2, 0x02, 0, 0, 0, 0x00, UOPS_RETIRED, RETIRE_SLOTS, \
101 "Retirement slots used.") \
102 _ (0xD0, 0x81, 0, 0, 0, 0x00, MEM_INST_RETIRED, ALL_LOADS, \
103 "All retired load instructions.") \
104 _ (0xD0, 0x82, 0, 0, 0, 0x00, MEM_INST_RETIRED, ALL_STORES, \
105 "All retired store instructions.") \
106 _ (0xD1, 0x01, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L1_HIT, \
107 "Retired load instructions with L1 cache hits as data sources") \
108 _ (0xD1, 0x02, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L2_HIT, \
109 "Retired load instructions with L2 cache hits as data sources") \
110 _ (0xD1, 0x04, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L3_HIT, \
111 "Retired load instructions with L3 cache hits as data sources") \
112 _ (0xD1, 0x08, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L1_MISS, \
113 "Retired load instructions missed L1 cache as data sources") \
114 _ (0xD1, 0x10, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L2_MISS, \
115 "Retired load instructions missed L2 cache as data sources") \
116 _ (0xD1, 0x20, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, L3_MISS, \
117 "Retired load instructions missed L3 cache as data sources") \
118 _ (0xD1, 0x40, 0, 0, 0, 0x00, MEM_LOAD_RETIRED, FB_HIT, \
119 "Retired load instructions which data sources were load missed L1 but " \
120 "hit FB due to preceding miss to the same cache line with data not " \
122 _ (0xD2, 0x01, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_MISS, \
123 "Retired load instructions which data sources were L3 hit and cross-" \
124 "core snoop missed in on-pkg core cache.") \
125 _ (0xD2, 0x02, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_HIT, \
126 "Retired load instructions which data sources were L3 and cross-core " \
127 "snoop hits in on-pkg core cache") \
128 _ (0xD2, 0x04, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_HITM, \
129 "Retired load instructions which data sources were HitM responses from " \
131 _ (0xD2, 0x08, 0, 0, 0, 0x00, MEM_LOAD_L3_HIT_RETIRED, XSNP_NONE, \
132 "Retired load instructions which data sources were hits in L3 without " \
134 _ (0xD3, 0x01, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, LOCAL_DRAM, \
135 "Retired load instructions which data sources missed L3 but serviced " \
137 _ (0xD3, 0x02, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_DRAM, \
138 "Retired load instructions which data sources missed L3 but serviced " \
139 "from remote dram") \
140 _ (0xD3, 0x04, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_HITM, \
141 "Retired load instructions whose data sources was remote HITM") \
142 _ (0xD3, 0x08, 0, 0, 0, 0x00, MEM_LOAD_L3_MISS_RETIRED, REMOTE_FWD, \
143 "Retired load instructions whose data sources was forwarded from a " \
145 _ (0xF0, 0x40, 0, 0, 0, 0x00, L2_TRANS, L2_WB, \
146 "L2 writebacks that access L2 cache") \
147 _ (0xF1, 0x1F, 0, 0, 0, 0x00, L2_LINES_IN, ALL, \
148 "L2 cache lines filling L2") \
149 _ (0xFE, 0x02, 0, 0, 0, 0x00, IDI_MISC, WB_UPGRADE, \
150 "Counts number of cache lines that are allocated and written back to L3" \
151 " with the intention that they are more likely to be reused shortly") \
152 _ (0xFE, 0x04, 0, 0, 0, 0x00, IDI_MISC, WB_DOWNGRADE, \
153 "Counts number of cache lines that are dropped and not written back to " \
154 "L3 as they are deemed to be less likely to be reused shortly")
158 #define _(event, umask, edge, any, inv, cmask, name, suffix, desc) \
159 INTEL_CORE_E_##name##_##suffix,
160 foreach_perf_intel_core_event
163 } perf_intel_core_event_t;