2 * Copyright (c) 2020 Cisco and/or its affiliates.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at:
7 * http://www.apache.org/licenses/LICENSE-2.0
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
16 #ifndef __perfmon_intel_uncore_h__
17 #define __perfmon_intel_uncore_h__
19 #define foreach_intel_uncore_unit_type \
20 _ (IMC, "imc", "integrated Memory Controller (iMC)", "iMC%u/%u") \
21 _ (UPI, "upi", "Ultra Path Interconnect (UPI)", "UPI%u/%u")
25 #define _(t, n, name, fmt) INTEL_UNCORE_UNIT_##t,
26 foreach_intel_uncore_unit_type
29 } intel_uncore_unit_type_t;
31 #define PERF_INTEL_CODE(event, umask, edge, any, inv, cmask) \
32 ((event) | (umask) << 8 | (edge) << 18 | (any) << 21 | (inv) << 23 | \
35 /* Type, EventCode, UMask, name, suffix, description */
36 #define foreach_intel_uncore_event \
37 _ (IMC, 0x04, 0x03, UNC_M_CAS_COUNT, RD, \
38 "All DRAM Read CAS Commands issued (including underfills)") \
39 _ (IMC, 0x04, 0x0c, UNC_M_CAS_COUNT, WR, \
40 "All DRAM Write CAS commands issued") \
41 _ (IMC, 0x04, 0x0f, UNC_M_CAS_COUNT, ALL, "All DRAM CAS commands issued")
45 #define _(unit, event, umask, name, suffix, desc) \
46 INTEL_UNCORE_E_##unit##_##name##_##suffix,
47 foreach_intel_uncore_event
49 INTEL_UNCORE_N_EVENTS,
50 } perfmon_intel_uncore_event_index_t;