2 *------------------------------------------------------------------
3 * Copyright (c) 2018 Cisco and/or its affiliates.
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at:
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 *------------------------------------------------------------------
21 #include <infiniband/verbs.h>
23 #include <vlib/pci/pci.h>
24 #include <vnet/interface.h>
25 #include <vnet/ethernet/mac_address.h>
26 #include <rdma/rdma_mlx5dv.h>
28 #define foreach_rdma_device_flags \
29 _(0, ERROR, "error") \
30 _(1, ADMIN_UP, "admin-up") \
31 _(2, LINK_UP, "link-up") \
32 _(3, PROMISC, "promiscuous") \
33 _(4, MLX5DV, "mlx5dv")
37 #define _(a, b, c) RDMA_DEVICE_F_##b = (1 << a),
38 foreach_rdma_device_flags
44 CLIB_ALIGN_MARK (align0, MLX5_SEND_WQE_BB);
45 struct mlx5_wqe_ctrl_seg ctrl;
46 struct mlx5_wqe_eth_seg eseg;
47 struct mlx5_wqe_data_seg dseg;
49 #define RDMA_MLX5_WQE_SZ sizeof(rdma_mlx5_wqe_t)
50 #define RDMA_MLX5_WQE_DS (RDMA_MLX5_WQE_SZ/sizeof(struct mlx5_wqe_data_seg))
51 STATIC_ASSERT (RDMA_MLX5_WQE_SZ == MLX5_SEND_WQE_BB &&
52 RDMA_MLX5_WQE_SZ % sizeof (struct mlx5_wqe_data_seg) == 0,
57 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
80 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
82 /* following fields are accessed in datapath */
89 /* ibverb datapath. Cache of cq, sq below */
90 struct ibv_cq *ibv_cq;
91 struct ibv_qp *ibv_qp;
95 /* direct verbs datapath */
96 rdma_mlx5_wqe_t *dv_sq_wqes;
97 volatile u32 *dv_sq_dbrec;
98 volatile u64 *dv_sq_db;
99 struct mlx5_cqe64 *dv_cq_cqes;
100 volatile u32 *dv_cq_dbrec;
104 u32 *bufs; /* vlib_buffer ring buffer */
107 u16 dv_cq_idx; /* monotonic CQE index (valid only for direct verbs) */
108 u8 bufs_log2sz; /* log2 vlib_buffer entries */
109 u8 dv_sq_log2sz:4; /* log2 SQ WQE entries (valid only for direct verbs) */
110 u8 dv_cq_log2sz:4; /* log2 CQ CQE entries (valid only for direct verbs) */
111 STRUCT_MARK (cacheline1);
113 /* WQE template (valid only for direct verbs) */
116 /* end of 2nd 64-bytes cacheline (or 1st 128-bytes cacheline) */
117 STRUCT_MARK (cacheline2);
119 /* fields below are not accessed in datapath */
124 STATIC_ASSERT_OFFSET_OF (rdma_txq_t, cacheline1, 64);
125 STATIC_ASSERT_OFFSET_OF (rdma_txq_t, cacheline2, 128);
127 #define RDMA_TXQ_DV_INVALID_ID 0xffffffff
129 #define RDMA_TXQ_BUF_SZ(txq) (1U << (txq)->bufs_log2sz)
130 #define RDMA_TXQ_DV_SQ_SZ(txq) (1U << (txq)->dv_sq_log2sz)
131 #define RDMA_TXQ_DV_CQ_SZ(txq) (1U << (txq)->dv_cq_log2sz)
133 #define RDMA_TXQ_USED_SZ(head, tail) ((u16)((u16)(tail) - (u16)(head)))
134 #define RDMA_TXQ_AVAIL_SZ(txq, head, tail) ((u16)(RDMA_TXQ_BUF_SZ (txq) - RDMA_TXQ_USED_SZ (head, tail)))
138 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
140 /* following fields are accessed in datapath */
144 u32 per_interface_next_index;
147 u32 lkey; /* cache of mr->lkey */
148 u8 pool; /* buffer pool index */
150 /* fields below are not accessed in datapath */
151 vlib_pci_device_info_t *pci;
154 mac_address_t hwaddr;
155 u32 async_event_clib_file_index;
158 struct ibv_context *ctx;
161 struct ibv_qp *rx_qp;
162 struct ibv_rwq_ind_table *rx_rwq_ind_tbl;
163 struct ibv_flow *flow_ucast;
164 struct ibv_flow *flow_mcast;
171 CLIB_CACHE_LINE_ALIGN_MARK (cacheline0);
174 u16 cqe_flags[VLIB_FRAME_SIZE];
175 u16x8 cqe_flags8[VLIB_FRAME_SIZE / 8];
176 u16x16 cqe_flags16[VLIB_FRAME_SIZE / 16];
178 vlib_buffer_t buffer_template;
179 } rdma_per_thread_data_t;
183 rdma_per_thread_data_t *per_thread_data;
184 rdma_device_t *devices;
185 vlib_log_class_t log_class;
189 extern rdma_main_t rdma_main;
211 } rdma_create_if_args_t;
213 void rdma_create_if (vlib_main_t * vm, rdma_create_if_args_t * args);
214 void rdma_delete_if (vlib_main_t * vm, rdma_device_t * rd);
216 extern vlib_node_registration_t rdma_input_node;
217 extern vnet_device_class_t rdma_device_class;
219 format_function_t format_rdma_device;
220 format_function_t format_rdma_device_name;
221 format_function_t format_rdma_input_trace;
222 format_function_t format_rdma_rxq;
223 unformat_function_t unformat_rdma_create_if_args;
230 } rdma_input_trace_t;
232 #define foreach_rdma_tx_func_error \
233 _(SEGMENT_SIZE_EXCEEDED, "segment size exceeded") \
234 _(NO_FREE_SLOTS, "no free tx slots") \
235 _(SUBMISSION, "tx submission errors") \
236 _(COMPLETION, "tx completion errors")
240 #define _(f,s) RDMA_TX_ERROR_##f,
241 foreach_rdma_tx_func_error
244 } rdma_tx_func_error_t;
246 #endif /* _RDMA_H_ */
249 * fd.io coding-style-patch-verification: ON
252 * eval: (c-set-style "gnu")