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(parent: ecadf6a) | patch
vlib: fix buffer pool alignment size 75/32875/2
authorTianyu Li <tianyu.li@arm.com>
Wed, 23 Jun 2021 07:35:03 +0000 (07:35 +0000)
committerDamjan Marion <dmarion@me.com>
Fri, 2 Jul 2021 14:28:24 +0000 (14:28 +0000)
commit70b1cbdf2bd7687f840a59475ca769c9bab907c9
tree911e87072e23cb58243293f126281b8613a50896tree | snapshot
parentecadf6a5395968092e093f7fa1d40a17762ebac1commit | diff
vlib: fix buffer pool alignment size

Alignment size should be CLIB_CACHE_LINE_BYTES(64)
instead of CLIB_LOG2_CACHE_LINE_BYTES(6)

Type: fix

Signed-off-by: Tianyu Li <tianyu.li@arm.com>
Change-Id: If2d5ae324093be64454377866297f5e76ccddc93
src/vlib/buffer.c diff | blob | history
Vector Packet Processing