vlib: fix buffer pool alignment size 75/32875/2
authorTianyu Li <tianyu.li@arm.com>
Wed, 23 Jun 2021 07:35:03 +0000 (07:35 +0000)
committerDamjan Marion <dmarion@me.com>
Fri, 2 Jul 2021 14:28:24 +0000 (14:28 +0000)
Alignment size should be CLIB_CACHE_LINE_BYTES(64)
instead of CLIB_LOG2_CACHE_LINE_BYTES(6)

Type: fix

Signed-off-by: Tianyu Li <tianyu.li@arm.com>
Change-Id: If2d5ae324093be64454377866297f5e76ccddc93

src/vlib/buffer.c

index ae88b4e..adaafa3 100644 (file)
@@ -509,7 +509,7 @@ vlib_buffer_pool_create (vlib_main_t * vm, char *name, u32 data_size,
   if (vec_len (bm->buffer_pools) >= 255)
     return ~0;
 
-  vec_add2_aligned (bm->buffer_pools, bp, 1, CLIB_LOG2_CACHE_LINE_BYTES);
+  vec_add2_aligned (bm->buffer_pools, bp, 1, CLIB_CACHE_LINE_BYTES);
 
   if (bm->buffer_mem_size == 0)
     {