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(parent: c0a9314) | patch
L2-learn; cache prefetch fix 40/14740/4
authorNeale Ranns <nranns@cisco.com>
Sun, 9 Sep 2018 08:41:02 +0000 (04:41 -0400)
committerDamjan Marion <dmarion@me.com>
Tue, 11 Sep 2018 17:24:07 +0000 (17:24 +0000)
commiteb1525f1060569cc3dc03aca7696ce05e1401a09
treeb9fffe456cf81f250c103535215db00645fe9d0etree | snapshot
parentc0a93143412b4be7bba087bf633855aeeaee7c56commit | diff
L2-learn; cache prefetch fix

the header is written (STORE) the data is only read (LOAD)

Change-Id: Ia3ac0c81224a0db736c329ed3e2e55b7417f08a0
Signed-off-by: Neale Ranns <nranns@cisco.com>
src/vnet/CMakeLists.txt diff | blob | history
src/vnet/l2/l2_fib.h diff | blob | history
src/vnet/l2/l2_learn.c diff | blob | history
Vector Packet Processing