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build: add support for intel alderlake and sapphirerapids, part 2
90/38490/1
author
Damjan Marion
<damarion@cisco.com>
Wed, 15 Mar 2023 11:08:53 +0000
(11:08 +0000)
committer
Damjan Marion
<damarion@cisco.com>
Wed, 15 Mar 2023 11:10:24 +0000
(11:10 +0000)
Type: improvement
Change-Id: I64ca5bd3a959190111f61c5311a908d242c10bad
Signed-off-by: Damjan Marion <damarion@cisco.com>
src/vppinfra/cpu.h
patch
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diff --git
a/src/vppinfra/cpu.h
b/src/vppinfra/cpu.h
index
efa85ad
..
a30401a
100644
(file)
--- a/
src/vppinfra/cpu.h
+++ b/
src/vppinfra/cpu.h
@@
-24,7
+24,9
@@
_ (hsw, "Intel Haswell") \
_ (trm, "Intel Tremont") \
_ (skx, "Intel Skylake (server) / Cascade Lake") \
- _ (icl, "Intel Ice Lake")
+ _ (icl, "Intel Ice Lake") \
+ _ (adl, "Intel Alder Lake") \
+ _ (spr, "Intel Sapphire Rapids")
#elif defined(__aarch64__)
#define foreach_march_variant \
_ (octeontx2, "Marvell Octeon TX2") \