#define CLASSIFY_TRACE 0
-#ifdef CLIB_HAVE_VEC128
-#define CLASSIFY_USE_SSE //Allow usage of SSE operations
-#endif
-
#define U32X4_ALIGNED(p) PREDICT_TRUE((((intptr_t)p) & 0xf) == 0)
/*
ASSERT (t);
mask = t->mask;
-#ifdef CLASSIFY_USE_SSE
+#ifdef CLIB_HAVE_VEC128
if (U32X4_ALIGNED (h))
{ //SSE can't handle unaligned data
u32x4 *data = (u32x4 *) h;
}
}
else
-#endif /* CLASSIFY_USE_SSE */
+#endif /* CLIB_HAVE_VEC128 */
{
u32 skip_u64 = t->skip_n_vectors * 2;
u64 *data64 = (u64 *) h;
v = vnet_classify_entry_at_index (t, v, value_index);
-#ifdef CLASSIFY_USE_SSE
+#ifdef CLIB_HAVE_VEC128
if (U32X4_ALIGNED (h))
{
u32x4 *data = (u32x4 *) h;
}
}
else
-#endif /* CLASSIFY_USE_SSE */
+#endif /* CLIB_HAVE_VEC128 */
{
u32 skip_u64 = t->skip_n_vectors * 2;
u64 *data64 = (u64 *) h;
return (u32) (vgetq_lane_u64 (merge3, 1) << 8) + vgetq_lane_u64 (merge3, 0);
}
+always_inline u32
+u8x16_zero_byte_mask (u8x16 input)
+{
+ return u16x8_zero_byte_mask ((u16x8) input);
+}
+
+always_inline u32
+u32x4_zero_byte_mask (u32x4 input)
+{
+ return u16x8_zero_byte_mask ((u16x8) input);
+}
+
+always_inline u32
+u64x2_zero_byte_mask (u64x2 input)
+{
+ return u16x8_zero_byte_mask ((u16x8) input);
+}
+
+
+
#endif /* included_vector_neon_h */
/*