SOURCES
perfmon.c
perfmon_periodic.c
- parse_util.c
-)
-
-install(
- FILES PerfmonTables.tar.xz
- DESTINATION share/vpp/plugins/perfmon
- COMPONENT vpp-dev
+ perfmon_intel_bdw.c
+ perfmon_intel_bdw_de.c
+ perfmon_intel_bdx.c
+ perfmon_intel_bnl.c
+ perfmon_intel_clx.c
+ perfmon_intel_hsw.c
+ perfmon_intel_hsx.c
+ perfmon_intel_ivb.c
+ perfmon_intel_nhm_ep.c
+ perfmon_intel_nhm_ex.c
+ perfmon_intel_skl.c
+ perfmon_intel_skx.c
+ perfmon_intel_slm.c
+ perfmon_intel_snb.c
+ perfmon_intel_wsm_ep_dp.c
+ perfmon_intel_wsm_ep_sp.c
+ perfmon_intel_wsm_ex.c
)
option(VPP_BUILD_MAPFILE_TOOL "Build perfmon mapfile utility." OFF)
--- /dev/null
+#!/usr/bin/env python3
+
+import json, argparse
+
+p = argparse.ArgumentParser()
+
+p.add_argument('-i', '--input', action="store",
+ help="input JSON file name", required = True)
+
+p.add_argument('-o', '--output', action="store",
+ help="output C file name", required = True)
+
+p.add_argument('-m', '--model', action="append",
+ help="CPU model in format: model[,stepping0]",
+ required = True)
+
+r = p.parse_args()
+
+with open(r.input, 'r') as fp:
+ objects = json.load(fp)
+
+c = open(r.output, 'w')
+
+c.write ("""
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+""")
+
+for v in r.model:
+ if "," in v:
+ (m, s) = v.split(",")
+ m = int(m, 0)
+ s = int(s, 0)
+ c.write (" {}0x{:02X}, 0x{:02X}, 1{},\n".format("{", m, s, "}"))
+ else:
+ m = int(v, 0)
+ c.write (" {}0x{:02X}, 0x00, 0{},\n".format("{", m, "}"))
+c.write ("""
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+""")
+
+for obj in objects:
+ MSRIndex = obj["MSRIndex"]
+ if MSRIndex != "0":
+ continue
+
+ EventCode = obj["EventCode"]
+ UMask = obj["UMask"]
+ EventName = obj["EventName"].lower()
+ if "," in EventCode:
+ continue
+
+ c.write (" {\n")
+ c.write (" .event_code = {}{}{},\n".format("{", EventCode, "}"))
+ c.write (" .umask = {},\n".format(UMask))
+ c.write (" .event_name = \"{}\",\n".format(EventName))
+ c.write (" },\n")
+
+
+c.write (""" {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
+""")
+
+c.close()
+++ /dev/null
-/*
- * parse_util.c - halfhearted json parser
- *
- * Copyright (c) 2018 Cisco Systems and/or its affiliates
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <perfmon/perfmon.h>
-#include <vppinfra/unix.h>
-
-typedef enum
-{
- STATE_START,
- STATE_READ_NAME,
- STATE_READ_VALUE,
-} parse_state_t;
-
-static u8 *
-downcase (u8 * s)
-{
- u8 *rv = 0;
- u8 c;
- int i;
-
- for (i = 0; i < vec_len (s); i++)
- {
- c = s[i];
- if (c >= 'A' && c <= 'Z')
- c = c + ('a' - 'A');
- vec_add1 (rv, c);
- }
- return (rv);
-}
-
-uword *
-perfmon_parse_table (perfmon_main_t * pm, char *path, char *table_name)
-{
- u8 *cp;
- u8 *event_name;
- int state = STATE_START;
- uword *ht;
- name_value_pair_t *nvp = 0;
- name_value_pair_t **nvps = 0;
- u8 *v;
- int i;
- u8 *json_filename;
- clib_error_t *error;
-
- /* Create the name/value hash table in any case... */
- ht = hash_create_string (0, sizeof (uword));
-
- json_filename = format (0, "%s/%s%c", path, table_name, 0);
-
- vlib_log_debug (pm->log_class, "Try to read perfmon events from %s",
- json_filename);
-
- error = unix_proc_file_contents ((char *) json_filename, &cp);
-
- if (error)
- {
- vlib_log_err (pm->log_class,
- "Failed to read CPU-specific counter table %s",
- json_filename);
- vlib_log_err (pm->log_class,
- "Please install the vpp-dev package and then:");
- vlib_log_err
- (pm->log_class, "cd %s; sudo tar Jxf PerfmonTables.tar.xz", path);
- vlib_log_err (pm->log_class, "and restart vpp.");
-
- vec_free (json_filename);
- clib_error_report (error);
- return ht;
- }
- vlib_log_debug (pm->log_class, "Read OK, parse the event table...");
- vec_free (json_filename);
-
-again:
- while (*cp)
- {
- switch (state)
- {
- case STATE_START:
- while (*cp && *cp != '{' && *cp != '}' && *cp != ',')
- cp++;
- if (*cp == 0)
- goto done;
-
- /* Look for a new event */
- if (*cp == '{')
- {
- if (*cp == 0)
- {
- error:
- clib_warning ("parse fail");
- hash_free (ht);
- return 0;
- }
- cp++;
- state = STATE_READ_NAME;
- goto again;
- }
- else if (*cp == '}') /* end of event */
- {
- /* Look for the "EventName" nvp */
- for (i = 0; i < vec_len (nvps); i++)
- {
- nvp = nvps[i];
- if (!strncmp ((char *) nvp->name, "EventName", 9))
- {
- event_name = nvp->value;
- goto found;
- }
- }
- /* no name? */
- for (i = 0; i < vec_len (nvps); i++)
- {
- vec_free (nvps[i]->name);
- vec_free (nvps[i]->value);
- }
- vec_free (nvps);
- cp++;
- goto again;
-
- found:
- event_name = downcase (event_name);
- hash_set_mem (ht, event_name, nvps);
- nvp = 0;
- nvps = 0;
- cp++;
- goto again;
- }
- else if (*cp == ',') /* punctuation */
- {
- cp++;
- goto again;
- }
- else /* should never happen... */
- cp++;
- goto again;
-
- case STATE_READ_NAME:
- vec_validate (nvp, 0);
- v = 0;
- while (*cp && *cp != '"')
- cp++;
-
- if (*cp == 0)
- {
- vec_free (nvp);
- goto error;
- }
-
- cp++;
- while (*cp && *cp != '"')
- {
- vec_add1 (v, *cp);
- cp++;
- }
- if (*cp == 0)
- {
- vec_free (v);
- goto error;
- }
- cp++;
- vec_add1 (v, 0);
- nvp->name = v;
- state = STATE_READ_VALUE;
- goto again;
-
- case STATE_READ_VALUE:
- while (*cp && *cp != ':')
- cp++;
- if (*cp == 0)
- {
- vec_free (nvp->name);
- goto error;
- }
- while (*cp && *cp != '"')
- cp++;
- if (*cp == 0)
- {
- vec_free (nvp->name);
- goto error;
- }
- else
- cp++;
- v = 0;
- while (*cp && *cp != '"')
- {
- vec_add1 (v, *cp);
- cp++;
- }
- if (*cp == 0)
- {
- vec_free (nvp->name);
- vec_free (v);
- goto error;
- }
- vec_add1 (v, 0);
- nvp->value = v;
- vec_add1 (nvps, nvp);
- while (*cp && *cp != ',' && *cp != '}')
- cp++;
- if (*cp == 0)
- {
- vec_free (nvp->name);
- vec_free (nvp->value);
- goto error;
- }
- else if (*cp == '}')
- state = STATE_START;
- else
- {
- cp++;
- state = STATE_READ_NAME;
- }
- nvp = 0;
- goto again;
- }
- }
-
-done:
- return (ht);
-}
-
-/*
- * fd.io coding-style-patch-verification: ON
- *
- * Local Variables:
- * eval: (c-set-style "gnu")
- * End:
- */
#include <vnet/vnet.h>
#include <vnet/plugin/plugin.h>
#include <perfmon/perfmon.h>
+#include <perfmon/perfmon_intel.h>
#include <vlibapi/api.h>
#include <vlibmemory/api.h>
perfmon_main_t perfmon_main;
-static char *perfmon_json_path = "/usr/share/vpp/plugins/perfmon";
-
-typedef struct
+void
+perfmon_register_intel_pmc (perfmon_intel_pmc_cpu_model_t * m, int n_models,
+ perfmon_intel_pmc_event_t * e, int n_events)
{
- u8 model;
- u8 stepping;
- u8 has_stepping;
- char *filename;
-} file_by_model_and_stepping_t;
-
-/* Created by parsing mapfile.csv, see mapfile_tool.c */
-
-static const file_by_model_and_stepping_t fms_table[] = {
- /* model, stepping, stepping valid, file */
- {0x2E, 0x0, 0, "NehalemEX_core_V2.json"},
- {0x1E, 0x0, 0, "NehalemEP_core_V2.json"},
- {0x1F, 0x0, 0, "NehalemEP_core_V2.json"},
- {0x1A, 0x0, 0, "NehalemEP_core_V2.json"},
- {0x2F, 0x0, 0, "WestmereEX_core_V2.json"},
- {0x25, 0x0, 0, "WestmereEP-SP_core_V2.json"},
- {0x2C, 0x0, 0, "WestmereEP-DP_core_V2.json"},
- {0x37, 0x0, 0, "Silvermont_core_V14.json"},
- {0x4D, 0x0, 0, "Silvermont_core_V14.json"},
- {0x4C, 0x0, 0, "Silvermont_core_V14.json"},
- {0x5C, 0x0, 0, "goldmont_core_v13.json"},
- {0x5F, 0x0, 0, "goldmont_core_v13.json"},
- {0x1C, 0x0, 0, "Bonnell_core_V4.json"},
- {0x26, 0x0, 0, "Bonnell_core_V4.json"},
- {0x27, 0x0, 0, "Bonnell_core_V4.json"},
- {0x36, 0x0, 0, "Bonnell_core_V4.json"},
- {0x35, 0x0, 0, "Bonnell_core_V4.json"},
- {0x2A, 0x0, 0, "sandybridge_core_v16.json"},
- {0x2D, 0x0, 0, "Jaketown_core_V20.json"},
- {0x3A, 0x0, 0, "ivybridge_core_v21.json"},
- {0x3E, 0x0, 0, "ivytown_core_v20.json"},
- {0x3C, 0x0, 0, "haswell_core_v28.json"},
- {0x45, 0x0, 0, "haswell_core_v28.json"},
- {0x46, 0x0, 0, "haswell_core_v28.json"},
- {0x3F, 0x0, 0, "haswellx_core_v20.json"},
- {0x3D, 0x0, 0, "broadwell_core_v23.json"},
- {0x47, 0x0, 0, "broadwell_core_v23.json"},
- {0x4F, 0x0, 0, "broadwellx_core_v14.json"},
- {0x56, 0x0, 0, "broadwellde_core_v7.json"},
- {0x4E, 0x0, 0, "skylake_core_v42.json"},
- {0x5E, 0x0, 0, "skylake_core_v42.json"},
- {0x8E, 0x0, 0, "skylake_core_v42.json"},
- {0x9E, 0x0, 0, "skylake_core_v42.json"},
- {0x57, 0x0, 0, "KnightsLanding_core_V9.json"},
- {0x85, 0x0, 0, "KnightsLanding_core_V9.json"},
- {0x55, 0x0, 1, "skylakex_core_v1.12.json"},
- {0x55, 0x1, 1, "skylakex_core_v1.12.json"},
- {0x55, 0x2, 1, "skylakex_core_v1.12.json"},
- {0x55, 0x3, 1, "skylakex_core_v1.12.json"},
- {0x55, 0x4, 1, "skylakex_core_v1.12.json"},
- {0x55, 0x5, 1, "cascadelakex_core_v1.00.json"},
- {0x55, 0x6, 1, "cascadelakex_core_v1.00.json"},
- {0x55, 0x7, 1, "cascadelakex_core_v1.00.json"},
- {0x55, 0x8, 1, "cascadelakex_core_v1.00.json"},
- {0x55, 0x9, 1, "cascadelakex_core_v1.00.json"},
- {0x55, 0xA, 1, "cascadelakex_core_v1.00.json"},
- {0x55, 0xB, 1, "cascadelakex_core_v1.00.json"},
- {0x55, 0xC, 1, "cascadelakex_core_v1.00.json"},
- {0x55, 0xD, 1, "cascadelakex_core_v1.00.json"},
- {0x55, 0xE, 1, "cascadelakex_core_v1.00.json"},
- {0x55, 0xF, 1, "cascadelakex_core_v1.00.json"},
- {0x7A, 0x0, 0, "goldmontplus_core_v1.01.json"},
-};
+ perfmon_main_t *pm = &perfmon_main;
+ perfmon_intel_pmc_registration_t r;
-static void
-set_perfmon_json_path ()
-{
- char *p, path[PATH_MAX];
- int rv;
- u8 *s;
-
- /* find executable path */
- if ((rv = readlink ("/proc/self/exe", path, PATH_MAX - 1)) == -1)
- return;
-
- /* readlink doesn't provide null termination */
- path[rv] = 0;
-
- /* strip filename */
- if ((p = strrchr (path, '/')) == 0)
- return;
- *p = 0;
-
- /* strip bin/ */
- if ((p = strrchr (path, '/')) == 0)
- return;
- *p = 0;
-
- /* cons up the .json file path */
- s = format (0, "%s/share/vpp/plugins/perfmon", path);
- vec_add1 (s, 0);
- perfmon_json_path = (char *) s;
+ r.events = e;
+ r.models = m;
+ r.n_events = n_events;
+ r.n_models = n_models;
+
+ vec_add1 (pm->perfmon_tables, r);
}
static inline u32
#endif
}
+static int
+perfmon_cpu_model_matches (perfmon_intel_pmc_cpu_model_t * mt,
+ u32 n_models, u8 model, u8 stepping)
+{
+ u32 i;
+ for (i = 0; i < n_models; i++)
+ {
+ if (mt[i].model != model)
+ continue;
+
+ if (mt[i].has_stepping)
+ {
+ if (mt[i].stepping != stepping)
+ continue;
+ }
+
+ return 1;
+ }
+ return 0;
+}
+
+static perfmon_intel_pmc_event_t *
+perfmon_find_table_by_model_stepping (perfmon_main_t * pm,
+ u8 model, u8 stepping)
+{
+ perfmon_intel_pmc_registration_t *rt;
+
+ vec_foreach (rt, pm->perfmon_tables)
+ {
+ if (perfmon_cpu_model_matches (rt->models, rt->n_models, model, stepping))
+ return rt->events;
+ }
+ return 0;
+}
+
static clib_error_t *
perfmon_init (vlib_main_t * vm)
{
perfmon_main_t *pm = &perfmon_main;
clib_error_t *error = 0;
u32 cpuid;
- uword *ht;
- int found_a_table = 0;
- int i;
u8 model, stepping;
+ perfmon_intel_pmc_event_t *ev;
pm->vlib_main = vm;
pm->vnet_main = vnet_get_main ();
vec_validate (pm->rdpmc_indices[1], vec_len (vlib_mains) - 1);
pm->page_size = getpagesize ();
- ht = pm->perfmon_table = 0;
-
- set_perfmon_json_path ();
+ pm->perfmon_table = 0;
+ pm->pmc_event_by_name = 0;
cpuid = get_cpuid ();
+ model = ((cpuid >> 12) & 0xf0) | ((cpuid >> 4) & 0xf);
+ stepping = cpuid & 0xf;
- for (i = 0; i < ARRAY_LEN (fms_table); i++)
- {
- model = ((cpuid >> 12) & 0xf0) | ((cpuid >> 4) & 0xf);
- stepping = cpuid & 0xf;
+ pm->perfmon_table = perfmon_find_table_by_model_stepping (pm,
+ model, stepping);
- if (fms_table[i].model != model)
- continue;
-
- if (fms_table[i].has_stepping)
- {
- if (fms_table[i].stepping != stepping)
- continue;
- }
-
- found_a_table = 1;
- ht = perfmon_parse_table (pm, perfmon_json_path, fms_table[i].filename);
- break;
- }
- pm->perfmon_table = ht;
-
- if (found_a_table == 0 || pm->perfmon_table == 0 || hash_elts (ht) == 0)
+ if (pm->perfmon_table == 0)
{
vlib_log_err (pm->log_class, "No table for cpuid %x", cpuid);
vlib_log_err (pm->log_class, " model %x, stepping %x",
model, stepping);
}
+ else
+ {
+ pm->pmc_event_by_name = hash_create_string (0, sizeof (u32));
+ ev = pm->perfmon_table;
+
+ for (; ev->event_name; ev++)
+ {
+ hash_set_mem (pm->pmc_event_by_name, ev->event_name,
+ ev - pm->perfmon_table);
+ }
+ }
return error;
}
};
/* *INDENT-ON* */
-static uword
-atox (u8 * s)
-{
- uword rv = 0;
-
- while (*s)
- {
- if (*s >= '0' && *s <= '9')
- rv = (rv << 4) | (*s - '0');
- else if (*s >= 'a' && *s <= 'f')
- rv = (rv << 4) | (*s - 'a' + 10);
- else if (*s >= 'A' && *s <= 'A')
- rv = (rv << 4) | (*s - 'A' + 10);
- else if (*s == 'x')
- ;
- else
- break;
- s++;
- }
- return rv;
-}
-
static uword
unformat_processor_event (unformat_input_t * input, va_list * args)
{
perfmon_main_t *pm = va_arg (*args, perfmon_main_t *);
perfmon_event_config_t *ep = va_arg (*args, perfmon_event_config_t *);
u8 *s = 0;
- name_value_pair_t **nvps, *nvp;
hash_pair_t *hp;
- int i;
- int set_values = 0;
+ u32 idx;
u32 pe_config = 0;
- if (pm->perfmon_table == 0)
+ if (pm->perfmon_table == 0 || pm->pmc_event_by_name == 0)
return 0;
if (!unformat (input, "%s", &s))
return 0;
- hp = hash_get_pair_mem (pm->perfmon_table, s);
+ hp = hash_get_pair_mem (pm->pmc_event_by_name, s);
vec_free (s);
if (hp == 0)
return 0;
- nvps = (name_value_pair_t **) (hp->value[0]);
-
- for (i = 0; i < vec_len (nvps); i++)
- {
- nvp = nvps[i];
- if (!strncmp ((char *) nvp->name, "EventCode", 9))
- {
- pe_config |= atox (nvp->value);
- set_values++;
- }
- else if (!strncmp ((char *) nvp->name, "UMask", 5))
- {
- pe_config |= (atox (nvp->value) << 8);
- set_values++;
- }
- if (set_values == 2)
- break;
- }
+ idx = (u32) (hp->value[0]);
- if (set_values != 2)
- {
- clib_warning ("BUG: only found %d values", set_values);
- return 0;
- }
+ pe_config |= pm->perfmon_table[idx].event_code[0];
+ pe_config |= pm->perfmon_table[idx].umask << 8;
ep->name = (char *) hp->key;
ep->pe_type = PERF_TYPE_RAW;
typedef struct
{
u8 *name;
- name_value_pair_t **nvps;
+ u32 index;
} sort_nvp_t;
static int
return strcmp ((char *) nvp1->name, (char *) nvp2->name);
}
+static u8 *
+format_pmc_event (u8 * s, va_list * args)
+{
+ perfmon_intel_pmc_event_t *ev = va_arg (*args, perfmon_intel_pmc_event_t *);
+
+ s = format (s, "%s\n", ev->event_name);
+ s = format (s, " umask: 0x%x\n", ev->umask);
+ s = format (s, " code: 0x%x", ev->event_code[0]);
+
+ if (ev->event_code[1])
+ s = format (s, " , 0x%x\n", ev->event_code[1]);
+ else
+ s = format (s, "\n");
+
+ return s;
+}
+
static u8 *
format_processor_events (u8 * s, va_list * args)
{
perfmon_main_t *pm = va_arg (*args, perfmon_main_t *);
int verbose = va_arg (*args, int);
- int i, j;
sort_nvp_t *sort_nvps = 0;
sort_nvp_t *sn;
u8 *key;
- name_value_pair_t **value;
+ u32 value;
/* *INDENT-OFF* */
- hash_foreach_mem (key, value, pm->perfmon_table,
+ hash_foreach_mem (key, value, pm->pmc_event_by_name,
({
vec_add2 (sort_nvps, sn, 1);
sn->name = key;
- sn->nvps = value;
+ sn->index = value;
}));
vec_sort_with_function (sort_nvps, sort_nvps_by_name);
if (verbose == 0)
{
- for (i = 0; i < vec_len (sort_nvps); i++)
- s = format (s, "\n %s ", sort_nvps[i].name);
+ vec_foreach (sn, sort_nvps)
+ s = format (s, "\n %s ", sn->name);
}
else
{
- for (i = 0; i < vec_len (sort_nvps); i++)
- {
- name_value_pair_t **nvps;
- s = format (s, "\n %s:", sort_nvps[i].name);
-
- nvps = sort_nvps[i].nvps;
-
- for (j = 0; j < vec_len (nvps); j++)
- s = format (s, "\n %s = %s", nvps[j]->name, nvps[j]->value);
- }
+ vec_foreach (sn, sort_nvps)
+ s = format(s, "%U", format_pmc_event, &pm->perfmon_table[sn->index]);
}
vec_free (sort_nvps);
return s;
#include <vppinfra/error.h>
#include <linux/perf_event.h>
+#include <perfmon/perfmon_intel.h>
#define foreach_perfmon_event \
_(PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, "cpu-cycles") \
u64 *vectors_this_counter;
} perfmon_capture_t;
-typedef struct
-{
- u32 cpuid;
- const char **table;
-} perfmon_cpuid_and_table_t;
-
typedef struct
{
u8 *name;
perfmon_capture_t *capture_pool;
uword *capture_by_thread_and_node_name;
- /* CPU-specific event tables, hash table of selected table (if any) */
- perfmon_cpuid_and_table_t *perfmon_tables;
- uword *perfmon_table;
+ /* vector of registered perfmon tables */
+ perfmon_intel_pmc_registration_t *perfmon_tables;
+
+ /* active table */
+ perfmon_intel_pmc_event_t *perfmon_table;
+
+ uword *pmc_event_by_name;
/* vector of single events to collect */
perfmon_event_config_t *single_events_to_collect;
--- /dev/null
+/*
+ *------------------------------------------------------------------
+ * Copyright (c) 2019 Cisco and/or its affiliates.
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *------------------------------------------------------------------
+ */
+
+#ifndef _PERFMON_INTEL_H_
+#define _PERFMON_INTEL_H_
+
+#include <vppinfra/clib.h>
+#include <vppinfra/format.h>
+
+typedef struct
+{
+ u8 event_code[2];
+ u8 umask;
+ char *event_name;
+} perfmon_intel_pmc_event_t;
+
+typedef struct
+{
+ u8 model;
+ u8 stepping;
+ u8 has_stepping;
+} perfmon_intel_pmc_cpu_model_t;
+
+typedef struct
+{
+ perfmon_intel_pmc_event_t *events;
+ perfmon_intel_pmc_cpu_model_t *models;
+ u32 n_events;
+ u32 n_models;
+} perfmon_intel_pmc_registration_t;
+
+
+void
+perfmon_register_intel_pmc (perfmon_intel_pmc_cpu_model_t * m, int n_models,
+ perfmon_intel_pmc_event_t * e, int n_events);
+
+#define PERFMON_REGISTER_INTEL_PMC(m, e) \
+static void __clib_constructor \
+perfmon_register_intel_pmc_constructor() \
+{ \
+ perfmon_register_intel_pmc (m, ARRAY_LEN(m), e, ARRAY_LEN (e)); \
+}
+
+#endif /* _PERFMON_INTEL_H_ */
+
+/*
+ * fd.io coding-style-patch-verification: ON
+ *
+ * Local Variables:
+ * eval: (c-set-style "gnu")
+ * End:
+ */
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x3D, 0x00, 0},
+ {0x47, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread_any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "ld_blocks.store_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "ld_blocks.no_sr",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x01,
+ .event_name = "misalign_mem_ref.loads",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x02,
+ .event_name = "misalign_mem_ref.stores",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x01,
+ .event_name = "ld_blocks_partial.address_alias",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x01,
+ .event_name = "dtlb_load_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x02,
+ .event_name = "dtlb_load_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x04,
+ .event_name = "dtlb_load_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x08,
+ .event_name = "dtlb_load_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x0e,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.walk_duration",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x40,
+ .event_name = "dtlb_load_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x60,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles_any",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x08,
+ .event_name = "int_misc.rat_stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x10,
+ .event_name = "uops_issued.flags_merge",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x20,
+ .event_name = "uops_issued.slow_lea",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x40,
+ .event_name = "uops_issued.single_mul",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x01,
+ .event_name = "arith.fpu_div_active",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x21,
+ .event_name = "l2_rqsts.demand_data_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x22,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x24,
+ .event_name = "l2_rqsts.code_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x27,
+ .event_name = "l2_rqsts.all_demand_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.l2_pf_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3F,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc1,
+ .event_name = "l2_rqsts.demand_data_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc2,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc4,
+ .event_name = "l2_rqsts.code_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xd0,
+ .event_name = "l2_rqsts.l2_pf_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE1,
+ .event_name = "l2_rqsts.all_demand_data_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE2,
+ .event_name = "l2_rqsts.all_rfo",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE4,
+ .event_name = "l2_rqsts.all_code_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xe7,
+ .event_name = "l2_rqsts.all_demand_references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xF8,
+ .event_name = "l2_rqsts.all_pf",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x50,
+ .event_name = "l2_demand_rqsts.wb_hit",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3c},
+ .umask = 0x02,
+ .event_name = "cpu_clk_thread_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x01,
+ .event_name = "dtlb_store_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x02,
+ .event_name = "dtlb_store_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x04,
+ .event_name = "dtlb_store_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x08,
+ .event_name = "dtlb_store_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x0e,
+ .event_name = "dtlb_store_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_store_misses.walk_duration",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x20,
+ .event_name = "dtlb_store_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x40,
+ .event_name = "dtlb_store_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x60,
+ .event_name = "dtlb_store_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x4c},
+ .umask = 0x01,
+ .event_name = "load_hit_pre.sw_pf",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x02,
+ .event_name = "load_hit_pre.hw_pf",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_cycles",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x01,
+ .event_name = "l1d.replacement",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x01,
+ .event_name = "tx_mem.abort_conflict",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x02,
+ .event_name = "tx_mem.abort_capacity_write",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x04,
+ .event_name = "tx_mem.abort_hle_store_to_elided_lock",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x08,
+ .event_name = "tx_mem.abort_hle_elision_buffer_not_empty",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x10,
+ .event_name = "tx_mem.abort_hle_elision_buffer_mismatch",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x20,
+ .event_name = "tx_mem.abort_hle_elision_buffer_unsupported_alignment",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x40,
+ .event_name = "tx_mem.hle_elision_buffer_full",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x01,
+ .event_name = "move_elimination.int_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x02,
+ .event_name = "move_elimination.simd_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x04,
+ .event_name = "move_elimination.int_not_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x08,
+ .event_name = "move_elimination.simd_not_eliminated",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0_trans",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x02,
+ .event_name = "cpl_cycles.ring123",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x01,
+ .event_name = "tx_exec.misc1",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x02,
+ .event_name = "tx_exec.misc2",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x04,
+ .event_name = "tx_exec.misc3",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x08,
+ .event_name = "tx_exec.misc4",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x10,
+ .event_name = "tx_exec.misc5",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_cycles",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_end",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.all_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.cycles_with_data_rd",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x01,
+ .event_name = "lock_cycles.split_lock_uc_lock_duration",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x02,
+ .event_name = "lock_cycles.cache_lock_duration",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x02,
+ .event_name = "idq.empty",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_occur",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x20,
+ .event_name = "idq.ms_mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_switches",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x3C,
+ .event_name = "idq.mite_all_uops",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x01,
+ .event_name = "icache.hit",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x02,
+ .event_name = "icache.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache.ifdata_stall",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x01,
+ .event_name = "itlb_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x02,
+ .event_name = "itlb_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x04,
+ .event_name = "itlb_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x08,
+ .event_name = "itlb_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x0e,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_duration",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x20,
+ .event_name = "itlb_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x40,
+ .event_name = "itlb_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x60,
+ .event_name = "itlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x01,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x41,
+ .event_name = "br_inst_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x81,
+ .event_name = "br_inst_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x82,
+ .event_name = "br_inst_exec.taken_direct_jump",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x84,
+ .event_name = "br_inst_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x88,
+ .event_name = "br_inst_exec.taken_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x90,
+ .event_name = "br_inst_exec.taken_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xA0,
+ .event_name = "br_inst_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC1,
+ .event_name = "br_inst_exec.all_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC2,
+ .event_name = "br_inst_exec.all_direct_jmp",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC4,
+ .event_name = "br_inst_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC8,
+ .event_name = "br_inst_exec.all_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xD0,
+ .event_name = "br_inst_exec.all_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xFF,
+ .event_name = "br_inst_exec.all_branches",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x41,
+ .event_name = "br_misp_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x81,
+ .event_name = "br_misp_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x84,
+ .event_name = "br_misp_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x88,
+ .event_name = "br_misp_exec.taken_return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xA0,
+ .event_name = "br_misp_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC1,
+ .event_name = "br_misp_exec.all_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC4,
+ .event_name = "br_misp_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xFF,
+ .event_name = "br_misp_exec.all_branches",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_0_uops_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_2_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_3_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_fe_was_ok",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_executed_port.port_0_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_executed_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_executed_port.port_1_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_executed_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_dispatched_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_executed_port.port_2_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_executed_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_dispatched_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_executed_port.port_3_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_executed_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_dispatched_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_executed_port.port_4_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_executed_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_dispatched_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_executed_port.port_5_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_executed_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_executed_port.port_6_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_executed_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_7",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_executed_port.port_7_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_executed_port.port_7",
+ },
+ {
+ .event_code = {0xa2},
+ .umask = 0x01,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x04,
+ .event_name = "resource_stalls.rs",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x08,
+ .event_name = "resource_stalls.sb",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x02,
+ .event_name = "cycle_activity.cycles_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.cycles_no_execute",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x06,
+ .event_name = "cycle_activity.stalls_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x08,
+ .event_name = "cycle_activity.cycles_l1d_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x0C,
+ .event_name = "cycle_activity.stalls_l1d_pending",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_4_uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_active",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x02,
+ .event_name = "dsb2mite_switches.penalty_cycles",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x01,
+ .event_name = "itlb.itlb_flush",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x01,
+ .event_name = "offcore_requests.demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x02,
+ .event_name = "offcore_requests.demand_code_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x04,
+ .event_name = "offcore_requests.demand_rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x08,
+ .event_name = "offcore_requests.all_data_rd",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.thread",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_1_uop_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_2_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_3_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_4_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_1",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_2",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_3",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_4",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_none",
+ },
+ {
+ .event_code = {0xb2},
+ .umask = 0x01,
+ .event_name = "offcore_requests_buffer.sq_full",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x11,
+ .event_name = "page_walker_loads.dtlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x12,
+ .event_name = "page_walker_loads.dtlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x14,
+ .event_name = "page_walker_loads.dtlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x18,
+ .event_name = "page_walker_loads.dtlb_memory",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x21,
+ .event_name = "page_walker_loads.itlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x22,
+ .event_name = "page_walker_loads.itlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x24,
+ .event_name = "page_walker_loads.itlb_l3",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x01,
+ .event_name = "tlb_flush.dtlb_thread",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x20,
+ .event_name = "tlb_flush.stlb_any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.prec_dist",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x02,
+ .event_name = "inst_retired.x87",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x08,
+ .event_name = "other_assists.avx_to_sse",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x10,
+ .event_name = "other_assists.sse_to_avx",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x40,
+ .event_name = "other_assists.any_wb_assist",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.all",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.count",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x20,
+ .event_name = "machine_clears.maskmov",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x01,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call_r3",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x04,
+ .event_name = "br_inst_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x08,
+ .event_name = "br_inst_retired.near_return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x10,
+ .event_name = "br_inst_retired.not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x20,
+ .event_name = "br_inst_retired.near_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x40,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x01,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x04,
+ .event_name = "br_misp_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x08,
+ .event_name = "br_misp_retired.ret",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x20,
+ .event_name = "br_misp_retired.near_taken",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x01,
+ .event_name = "fp_arith_inst_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x02,
+ .event_name = "fp_arith_inst_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x04,
+ .event_name = "fp_arith_inst_retired.128b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x08,
+ .event_name = "fp_arith_inst_retired.128b_packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "fp_arith_inst_retired.256b_packed_double",
+ },
+ {
+ .event_code = {0xc7},
+ .umask = 0x20,
+ .event_name = "fp_arith_inst_retired.256b_packed_single",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x01,
+ .event_name = "hle_retired.start",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x02,
+ .event_name = "hle_retired.commit",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x04,
+ .event_name = "hle_retired.aborted",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x08,
+ .event_name = "hle_retired.aborted_misc1",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x10,
+ .event_name = "hle_retired.aborted_misc2",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x20,
+ .event_name = "hle_retired.aborted_misc3",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x40,
+ .event_name = "hle_retired.aborted_misc4",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x80,
+ .event_name = "hle_retired.aborted_misc5",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x01,
+ .event_name = "rtm_retired.start",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x02,
+ .event_name = "rtm_retired.commit",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x04,
+ .event_name = "rtm_retired.aborted",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x08,
+ .event_name = "rtm_retired.aborted_misc1",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x10,
+ .event_name = "rtm_retired.aborted_misc2",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x20,
+ .event_name = "rtm_retired.aborted_misc3",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x40,
+ .event_name = "rtm_retired.aborted_misc4",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x80,
+ .event_name = "rtm_retired.aborted_misc5",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x02,
+ .event_name = "fp_assist.x87_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x04,
+ .event_name = "fp_assist.x87_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x08,
+ .event_name = "fp_assist.simd_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x10,
+ .event_name = "fp_assist.simd_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1E,
+ .event_name = "fp_assist.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x20,
+ .event_name = "rob_misc_events.lbr_inserts",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x11,
+ .event_name = "mem_uops_retired.stlb_miss_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x12,
+ .event_name = "mem_uops_retired.stlb_miss_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x21,
+ .event_name = "mem_uops_retired.lock_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x41,
+ .event_name = "mem_uops_retired.split_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x42,
+ .event_name = "mem_uops_retired.split_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x81,
+ .event_name = "mem_uops_retired.all_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x82,
+ .event_name = "mem_uops_retired.all_stores",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_retired.l1_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_retired.l2_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_retired.l3_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_retired.l1_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x10,
+ .event_name = "mem_load_uops_retired.l2_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x20,
+ .event_name = "mem_load_uops_retired.l3_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x40,
+ .event_name = "mem_load_uops_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_miss",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_hitm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_none",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_l3_miss_retired.local_dram",
+ },
+ {
+ .event_code = {0xe6},
+ .umask = 0x1f,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x01,
+ .event_name = "l2_trans.demand_data_rd",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x02,
+ .event_name = "l2_trans.rfo",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x04,
+ .event_name = "l2_trans.code_rd",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x08,
+ .event_name = "l2_trans.all_pf",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x10,
+ .event_name = "l2_trans.l1d_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x20,
+ .event_name = "l2_trans.l2_fill",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_trans.l2_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x80,
+ .event_name = "l2_trans.all_requests",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x01,
+ .event_name = "l2_lines_in.i",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x02,
+ .event_name = "l2_lines_in.s",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x04,
+ .event_name = "l2_lines_in.e",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x07,
+ .event_name = "l2_lines_in.all",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x05,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xf4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x56, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread_any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "ld_blocks.store_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "ld_blocks.no_sr",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x01,
+ .event_name = "misalign_mem_ref.loads",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x02,
+ .event_name = "misalign_mem_ref.stores",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x01,
+ .event_name = "ld_blocks_partial.address_alias",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x01,
+ .event_name = "dtlb_load_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x02,
+ .event_name = "dtlb_load_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x04,
+ .event_name = "dtlb_load_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x08,
+ .event_name = "dtlb_load_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x0e,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.walk_duration",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x40,
+ .event_name = "dtlb_load_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x60,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles_any",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x08,
+ .event_name = "int_misc.rat_stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x10,
+ .event_name = "uops_issued.flags_merge",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x20,
+ .event_name = "uops_issued.slow_lea",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x40,
+ .event_name = "uops_issued.single_mul",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x01,
+ .event_name = "arith.fpu_div_active",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x21,
+ .event_name = "l2_rqsts.demand_data_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x22,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x24,
+ .event_name = "l2_rqsts.code_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x27,
+ .event_name = "l2_rqsts.all_demand_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.l2_pf_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3F,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x41,
+ .event_name = "l2_rqsts.demand_data_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x42,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x44,
+ .event_name = "l2_rqsts.code_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x50,
+ .event_name = "l2_rqsts.l2_pf_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE1,
+ .event_name = "l2_rqsts.all_demand_data_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE2,
+ .event_name = "l2_rqsts.all_rfo",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE4,
+ .event_name = "l2_rqsts.all_code_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xe7,
+ .event_name = "l2_rqsts.all_demand_references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xF8,
+ .event_name = "l2_rqsts.all_pf",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x50,
+ .event_name = "l2_demand_rqsts.wb_hit",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3c},
+ .umask = 0x02,
+ .event_name = "cpu_clk_thread_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles_any",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x02,
+ .event_name = "l1d_pend_miss.fb_full",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x01,
+ .event_name = "dtlb_store_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x02,
+ .event_name = "dtlb_store_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x04,
+ .event_name = "dtlb_store_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x08,
+ .event_name = "dtlb_store_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x0e,
+ .event_name = "dtlb_store_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_store_misses.walk_duration",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x20,
+ .event_name = "dtlb_store_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x40,
+ .event_name = "dtlb_store_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x60,
+ .event_name = "dtlb_store_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x4c},
+ .umask = 0x01,
+ .event_name = "load_hit_pre.sw_pf",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x02,
+ .event_name = "load_hit_pre.hw_pf",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_cycles",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x01,
+ .event_name = "l1d.replacement",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x01,
+ .event_name = "tx_mem.abort_conflict",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x02,
+ .event_name = "tx_mem.abort_capacity_write",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x04,
+ .event_name = "tx_mem.abort_hle_store_to_elided_lock",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x08,
+ .event_name = "tx_mem.abort_hle_elision_buffer_not_empty",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x10,
+ .event_name = "tx_mem.abort_hle_elision_buffer_mismatch",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x20,
+ .event_name = "tx_mem.abort_hle_elision_buffer_unsupported_alignment",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x40,
+ .event_name = "tx_mem.hle_elision_buffer_full",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x01,
+ .event_name = "move_elimination.int_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x02,
+ .event_name = "move_elimination.simd_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x04,
+ .event_name = "move_elimination.int_not_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x08,
+ .event_name = "move_elimination.simd_not_eliminated",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0_trans",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x02,
+ .event_name = "cpl_cycles.ring123",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x01,
+ .event_name = "tx_exec.misc1",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x02,
+ .event_name = "tx_exec.misc2",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x04,
+ .event_name = "tx_exec.misc3",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x08,
+ .event_name = "tx_exec.misc4",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x10,
+ .event_name = "tx_exec.misc5",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_cycles",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_end",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd_ge_6",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.all_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.cycles_with_data_rd",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x01,
+ .event_name = "lock_cycles.split_lock_uc_lock_duration",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x02,
+ .event_name = "lock_cycles.cache_lock_duration",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x02,
+ .event_name = "idq.empty",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_occur",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x20,
+ .event_name = "idq.ms_mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_switches",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x3C,
+ .event_name = "idq.mite_all_uops",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x01,
+ .event_name = "icache.hit",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x02,
+ .event_name = "icache.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache.ifdata_stall",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x01,
+ .event_name = "itlb_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x02,
+ .event_name = "itlb_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x04,
+ .event_name = "itlb_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x08,
+ .event_name = "itlb_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x0e,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_duration",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x20,
+ .event_name = "itlb_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x40,
+ .event_name = "itlb_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x60,
+ .event_name = "itlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x01,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x41,
+ .event_name = "br_inst_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x81,
+ .event_name = "br_inst_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x82,
+ .event_name = "br_inst_exec.taken_direct_jump",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x84,
+ .event_name = "br_inst_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x88,
+ .event_name = "br_inst_exec.taken_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x90,
+ .event_name = "br_inst_exec.taken_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xA0,
+ .event_name = "br_inst_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC1,
+ .event_name = "br_inst_exec.all_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC2,
+ .event_name = "br_inst_exec.all_direct_jmp",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC4,
+ .event_name = "br_inst_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC8,
+ .event_name = "br_inst_exec.all_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xD0,
+ .event_name = "br_inst_exec.all_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xFF,
+ .event_name = "br_inst_exec.all_branches",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x41,
+ .event_name = "br_misp_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x81,
+ .event_name = "br_misp_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x84,
+ .event_name = "br_misp_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x88,
+ .event_name = "br_misp_exec.taken_return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xA0,
+ .event_name = "br_misp_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC1,
+ .event_name = "br_misp_exec.all_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC4,
+ .event_name = "br_misp_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xFF,
+ .event_name = "br_misp_exec.all_branches",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_0_uops_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_2_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_3_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_fe_was_ok",
+ },
+ {
+ .event_code = {0xA0},
+ .umask = 0x03,
+ .event_name = "uop_dispatches_cancelled.simd_prf",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_executed_port.port_0_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_executed_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_executed_port.port_1_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_executed_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_dispatched_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_executed_port.port_2_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_executed_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_dispatched_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_executed_port.port_3_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_executed_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_dispatched_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_executed_port.port_4_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_executed_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_dispatched_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_executed_port.port_5_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_executed_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_executed_port.port_6_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_executed_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_7",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_executed_port.port_7_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_executed_port.port_7",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x01,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x04,
+ .event_name = "resource_stalls.rs",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x08,
+ .event_name = "resource_stalls.sb",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x02,
+ .event_name = "cycle_activity.cycles_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x02,
+ .event_name = "cycle_activity.cycles_mem_any",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.cycles_no_execute",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.stalls_total",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x06,
+ .event_name = "cycle_activity.stalls_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x06,
+ .event_name = "cycle_activity.stalls_mem_any",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x08,
+ .event_name = "cycle_activity.cycles_l1d_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x08,
+ .event_name = "cycle_activity.cycles_l1d_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x0C,
+ .event_name = "cycle_activity.stalls_l1d_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x0C,
+ .event_name = "cycle_activity.stalls_l1d_miss",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_4_uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_active",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x02,
+ .event_name = "dsb2mite_switches.penalty_cycles",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x01,
+ .event_name = "itlb.itlb_flush",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x01,
+ .event_name = "offcore_requests.demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x02,
+ .event_name = "offcore_requests.demand_code_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x04,
+ .event_name = "offcore_requests.demand_rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x08,
+ .event_name = "offcore_requests.all_data_rd",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.thread",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_1_uop_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_2_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_3_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_4_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_1",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_2",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_3",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_4",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_none",
+ },
+ {
+ .event_code = {0xb2},
+ .umask = 0x01,
+ .event_name = "offcore_requests_buffer.sq_full",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x11,
+ .event_name = "page_walker_loads.dtlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x12,
+ .event_name = "page_walker_loads.dtlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x14,
+ .event_name = "page_walker_loads.dtlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x18,
+ .event_name = "page_walker_loads.dtlb_memory",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x21,
+ .event_name = "page_walker_loads.itlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x22,
+ .event_name = "page_walker_loads.itlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x24,
+ .event_name = "page_walker_loads.itlb_l3",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x01,
+ .event_name = "tlb_flush.dtlb_thread",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x20,
+ .event_name = "tlb_flush.stlb_any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.prec_dist",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x02,
+ .event_name = "inst_retired.x87",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x08,
+ .event_name = "other_assists.avx_to_sse",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x10,
+ .event_name = "other_assists.sse_to_avx",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x40,
+ .event_name = "other_assists.any_wb_assist",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.all",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.count",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x20,
+ .event_name = "machine_clears.maskmov",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x01,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call_r3",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x04,
+ .event_name = "br_inst_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x08,
+ .event_name = "br_inst_retired.near_return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x10,
+ .event_name = "br_inst_retired.not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x20,
+ .event_name = "br_inst_retired.near_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x40,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x01,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x04,
+ .event_name = "br_misp_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x08,
+ .event_name = "br_misp_retired.ret",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x20,
+ .event_name = "br_misp_retired.near_taken",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x01,
+ .event_name = "fp_arith_inst_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x02,
+ .event_name = "fp_arith_inst_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x03,
+ .event_name = "fp_arith_inst_retired.scalar",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x04,
+ .event_name = "fp_arith_inst_retired.128b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x08,
+ .event_name = "fp_arith_inst_retired.128b_packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "fp_arith_inst_retired.256b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x15,
+ .event_name = "fp_arith_inst_retired.double",
+ },
+ {
+ .event_code = {0xc7},
+ .umask = 0x20,
+ .event_name = "fp_arith_inst_retired.256b_packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x2A,
+ .event_name = "fp_arith_inst_retired.single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x3C,
+ .event_name = "fp_arith_inst_retired.packed",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x01,
+ .event_name = "hle_retired.start",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x02,
+ .event_name = "hle_retired.commit",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x04,
+ .event_name = "hle_retired.aborted",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x08,
+ .event_name = "hle_retired.aborted_misc1",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x10,
+ .event_name = "hle_retired.aborted_misc2",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x20,
+ .event_name = "hle_retired.aborted_misc3",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x40,
+ .event_name = "hle_retired.aborted_misc4",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x80,
+ .event_name = "hle_retired.aborted_misc5",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x01,
+ .event_name = "rtm_retired.start",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x02,
+ .event_name = "rtm_retired.commit",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x04,
+ .event_name = "rtm_retired.aborted",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x08,
+ .event_name = "rtm_retired.aborted_misc1",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x10,
+ .event_name = "rtm_retired.aborted_misc2",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x20,
+ .event_name = "rtm_retired.aborted_misc3",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x40,
+ .event_name = "rtm_retired.aborted_misc4",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x80,
+ .event_name = "rtm_retired.aborted_misc5",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x02,
+ .event_name = "fp_assist.x87_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x04,
+ .event_name = "fp_assist.x87_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x08,
+ .event_name = "fp_assist.simd_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x10,
+ .event_name = "fp_assist.simd_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1E,
+ .event_name = "fp_assist.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x20,
+ .event_name = "rob_misc_events.lbr_inserts",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x11,
+ .event_name = "mem_uops_retired.stlb_miss_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x12,
+ .event_name = "mem_uops_retired.stlb_miss_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x21,
+ .event_name = "mem_uops_retired.lock_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x41,
+ .event_name = "mem_uops_retired.split_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x42,
+ .event_name = "mem_uops_retired.split_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x81,
+ .event_name = "mem_uops_retired.all_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x82,
+ .event_name = "mem_uops_retired.all_stores",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_retired.l1_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_retired.l2_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_retired.l3_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_retired.l1_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x10,
+ .event_name = "mem_load_uops_retired.l2_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x20,
+ .event_name = "mem_load_uops_retired.l3_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x40,
+ .event_name = "mem_load_uops_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_miss",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_hitm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_none",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_l3_miss_retired.local_dram",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_l3_miss_retired.remote_dram",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x10,
+ .event_name = "mem_load_uops_l3_miss_retired.remote_hitm",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x20,
+ .event_name = "mem_load_uops_l3_miss_retired.remote_fwd",
+ },
+ {
+ .event_code = {0xe6},
+ .umask = 0x1f,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x01,
+ .event_name = "l2_trans.demand_data_rd",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x02,
+ .event_name = "l2_trans.rfo",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x04,
+ .event_name = "l2_trans.code_rd",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x08,
+ .event_name = "l2_trans.all_pf",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x10,
+ .event_name = "l2_trans.l1d_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x20,
+ .event_name = "l2_trans.l2_fill",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_trans.l2_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x80,
+ .event_name = "l2_trans.all_requests",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x01,
+ .event_name = "l2_lines_in.i",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x02,
+ .event_name = "l2_lines_in.s",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x04,
+ .event_name = "l2_lines_in.e",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x07,
+ .event_name = "l2_lines_in.all",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x05,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xf4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x4F, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread_any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "ld_blocks.store_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "ld_blocks.no_sr",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x01,
+ .event_name = "misalign_mem_ref.loads",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x02,
+ .event_name = "misalign_mem_ref.stores",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x01,
+ .event_name = "ld_blocks_partial.address_alias",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x01,
+ .event_name = "dtlb_load_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x02,
+ .event_name = "dtlb_load_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x04,
+ .event_name = "dtlb_load_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x08,
+ .event_name = "dtlb_load_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x0e,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.walk_duration",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x40,
+ .event_name = "dtlb_load_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x60,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles_any",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x08,
+ .event_name = "int_misc.rat_stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x10,
+ .event_name = "uops_issued.flags_merge",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x20,
+ .event_name = "uops_issued.slow_lea",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x40,
+ .event_name = "uops_issued.single_mul",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x01,
+ .event_name = "arith.fpu_div_active",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x21,
+ .event_name = "l2_rqsts.demand_data_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x22,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x24,
+ .event_name = "l2_rqsts.code_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x27,
+ .event_name = "l2_rqsts.all_demand_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.l2_pf_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3F,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc1,
+ .event_name = "l2_rqsts.demand_data_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc2,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc4,
+ .event_name = "l2_rqsts.code_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xd0,
+ .event_name = "l2_rqsts.l2_pf_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE1,
+ .event_name = "l2_rqsts.all_demand_data_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE2,
+ .event_name = "l2_rqsts.all_rfo",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE4,
+ .event_name = "l2_rqsts.all_code_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xe7,
+ .event_name = "l2_rqsts.all_demand_references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xF8,
+ .event_name = "l2_rqsts.all_pf",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x50,
+ .event_name = "l2_demand_rqsts.wb_hit",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3c},
+ .umask = 0x02,
+ .event_name = "cpu_clk_thread_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x01,
+ .event_name = "dtlb_store_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x02,
+ .event_name = "dtlb_store_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x04,
+ .event_name = "dtlb_store_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x08,
+ .event_name = "dtlb_store_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x0e,
+ .event_name = "dtlb_store_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_store_misses.walk_duration",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x20,
+ .event_name = "dtlb_store_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x40,
+ .event_name = "dtlb_store_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x60,
+ .event_name = "dtlb_store_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x4c},
+ .umask = 0x01,
+ .event_name = "load_hit_pre.sw_pf",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x02,
+ .event_name = "load_hit_pre.hw_pf",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_cycles",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x01,
+ .event_name = "l1d.replacement",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x01,
+ .event_name = "tx_mem.abort_conflict",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x02,
+ .event_name = "tx_mem.abort_capacity_write",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x04,
+ .event_name = "tx_mem.abort_hle_store_to_elided_lock",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x08,
+ .event_name = "tx_mem.abort_hle_elision_buffer_not_empty",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x10,
+ .event_name = "tx_mem.abort_hle_elision_buffer_mismatch",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x20,
+ .event_name = "tx_mem.abort_hle_elision_buffer_unsupported_alignment",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x40,
+ .event_name = "tx_mem.hle_elision_buffer_full",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x01,
+ .event_name = "move_elimination.int_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x02,
+ .event_name = "move_elimination.simd_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x04,
+ .event_name = "move_elimination.int_not_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x08,
+ .event_name = "move_elimination.simd_not_eliminated",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0_trans",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x02,
+ .event_name = "cpl_cycles.ring123",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x01,
+ .event_name = "tx_exec.misc1",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x02,
+ .event_name = "tx_exec.misc2",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x04,
+ .event_name = "tx_exec.misc3",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x08,
+ .event_name = "tx_exec.misc4",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x10,
+ .event_name = "tx_exec.misc5",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_cycles",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_end",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.all_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.cycles_with_data_rd",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x01,
+ .event_name = "lock_cycles.split_lock_uc_lock_duration",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x02,
+ .event_name = "lock_cycles.cache_lock_duration",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x02,
+ .event_name = "idq.empty",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_occur",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x20,
+ .event_name = "idq.ms_mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_switches",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x3C,
+ .event_name = "idq.mite_all_uops",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x01,
+ .event_name = "icache.hit",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x02,
+ .event_name = "icache.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache.ifdata_stall",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x01,
+ .event_name = "itlb_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x02,
+ .event_name = "itlb_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x04,
+ .event_name = "itlb_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x08,
+ .event_name = "itlb_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x0e,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_duration",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x20,
+ .event_name = "itlb_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x40,
+ .event_name = "itlb_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x60,
+ .event_name = "itlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x01,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x41,
+ .event_name = "br_inst_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x81,
+ .event_name = "br_inst_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x82,
+ .event_name = "br_inst_exec.taken_direct_jump",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x84,
+ .event_name = "br_inst_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x88,
+ .event_name = "br_inst_exec.taken_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x90,
+ .event_name = "br_inst_exec.taken_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xA0,
+ .event_name = "br_inst_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC1,
+ .event_name = "br_inst_exec.all_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC2,
+ .event_name = "br_inst_exec.all_direct_jmp",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC4,
+ .event_name = "br_inst_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC8,
+ .event_name = "br_inst_exec.all_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xD0,
+ .event_name = "br_inst_exec.all_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xFF,
+ .event_name = "br_inst_exec.all_branches",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x41,
+ .event_name = "br_misp_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x81,
+ .event_name = "br_misp_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x84,
+ .event_name = "br_misp_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x88,
+ .event_name = "br_misp_exec.taken_return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xA0,
+ .event_name = "br_misp_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC1,
+ .event_name = "br_misp_exec.all_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC4,
+ .event_name = "br_misp_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xFF,
+ .event_name = "br_misp_exec.all_branches",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_0_uops_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_2_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_3_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_fe_was_ok",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_executed_port.port_0_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_executed_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_executed_port.port_1_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_executed_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_dispatched_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_executed_port.port_2_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_executed_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_dispatched_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_executed_port.port_3_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_executed_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_dispatched_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_executed_port.port_4_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_executed_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_dispatched_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_executed_port.port_5_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_executed_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_executed_port.port_6_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_executed_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_7",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_executed_port.port_7_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_executed_port.port_7",
+ },
+ {
+ .event_code = {0xa2},
+ .umask = 0x01,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x04,
+ .event_name = "resource_stalls.rs",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x08,
+ .event_name = "resource_stalls.sb",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x02,
+ .event_name = "cycle_activity.cycles_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.cycles_no_execute",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x06,
+ .event_name = "cycle_activity.stalls_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x08,
+ .event_name = "cycle_activity.cycles_l1d_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x0C,
+ .event_name = "cycle_activity.stalls_l1d_pending",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_4_uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_active",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x02,
+ .event_name = "dsb2mite_switches.penalty_cycles",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x01,
+ .event_name = "itlb.itlb_flush",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x01,
+ .event_name = "offcore_requests.demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x02,
+ .event_name = "offcore_requests.demand_code_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x04,
+ .event_name = "offcore_requests.demand_rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x08,
+ .event_name = "offcore_requests.all_data_rd",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.thread",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_1_uop_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_2_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_3_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_4_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_1",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_2",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_3",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_4",
+ },
+ {
+ .event_code = {0xb1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_none",
+ },
+ {
+ .event_code = {0xb2},
+ .umask = 0x01,
+ .event_name = "offcore_requests_buffer.sq_full",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x11,
+ .event_name = "page_walker_loads.dtlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x12,
+ .event_name = "page_walker_loads.dtlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x14,
+ .event_name = "page_walker_loads.dtlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x18,
+ .event_name = "page_walker_loads.dtlb_memory",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x21,
+ .event_name = "page_walker_loads.itlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x22,
+ .event_name = "page_walker_loads.itlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x24,
+ .event_name = "page_walker_loads.itlb_l3",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x01,
+ .event_name = "tlb_flush.dtlb_thread",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x20,
+ .event_name = "tlb_flush.stlb_any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.prec_dist",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x02,
+ .event_name = "inst_retired.x87",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x08,
+ .event_name = "other_assists.avx_to_sse",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x10,
+ .event_name = "other_assists.sse_to_avx",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x40,
+ .event_name = "other_assists.any_wb_assist",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.all",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.count",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x20,
+ .event_name = "machine_clears.maskmov",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x01,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call_r3",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x04,
+ .event_name = "br_inst_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x08,
+ .event_name = "br_inst_retired.near_return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x10,
+ .event_name = "br_inst_retired.not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x20,
+ .event_name = "br_inst_retired.near_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x40,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x01,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x04,
+ .event_name = "br_misp_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x08,
+ .event_name = "br_misp_retired.ret",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x20,
+ .event_name = "br_misp_retired.near_taken",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x01,
+ .event_name = "fp_arith_inst_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x02,
+ .event_name = "fp_arith_inst_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x04,
+ .event_name = "fp_arith_inst_retired.128b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x08,
+ .event_name = "fp_arith_inst_retired.128b_packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "fp_arith_inst_retired.256b_packed_double",
+ },
+ {
+ .event_code = {0xc7},
+ .umask = 0x20,
+ .event_name = "fp_arith_inst_retired.256b_packed_single",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x01,
+ .event_name = "hle_retired.start",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x02,
+ .event_name = "hle_retired.commit",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x04,
+ .event_name = "hle_retired.aborted",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x08,
+ .event_name = "hle_retired.aborted_misc1",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x10,
+ .event_name = "hle_retired.aborted_misc2",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x20,
+ .event_name = "hle_retired.aborted_misc3",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x40,
+ .event_name = "hle_retired.aborted_misc4",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x80,
+ .event_name = "hle_retired.aborted_misc5",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x01,
+ .event_name = "rtm_retired.start",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x02,
+ .event_name = "rtm_retired.commit",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x04,
+ .event_name = "rtm_retired.aborted",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x08,
+ .event_name = "rtm_retired.aborted_misc1",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x10,
+ .event_name = "rtm_retired.aborted_misc2",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x20,
+ .event_name = "rtm_retired.aborted_misc3",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x40,
+ .event_name = "rtm_retired.aborted_misc4",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x80,
+ .event_name = "rtm_retired.aborted_misc5",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x02,
+ .event_name = "fp_assist.x87_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x04,
+ .event_name = "fp_assist.x87_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x08,
+ .event_name = "fp_assist.simd_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x10,
+ .event_name = "fp_assist.simd_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1E,
+ .event_name = "fp_assist.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x20,
+ .event_name = "rob_misc_events.lbr_inserts",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x11,
+ .event_name = "mem_uops_retired.stlb_miss_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x12,
+ .event_name = "mem_uops_retired.stlb_miss_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x21,
+ .event_name = "mem_uops_retired.lock_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x41,
+ .event_name = "mem_uops_retired.split_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x42,
+ .event_name = "mem_uops_retired.split_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x81,
+ .event_name = "mem_uops_retired.all_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x82,
+ .event_name = "mem_uops_retired.all_stores",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_retired.l1_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_retired.l2_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_retired.l3_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_retired.l1_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x10,
+ .event_name = "mem_load_uops_retired.l2_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x20,
+ .event_name = "mem_load_uops_retired.l3_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x40,
+ .event_name = "mem_load_uops_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_miss",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_hitm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_none",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_l3_miss_retired.local_dram",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_l3_miss_retired.remote_dram",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x10,
+ .event_name = "mem_load_uops_l3_miss_retired.remote_hitm",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x20,
+ .event_name = "mem_load_uops_l3_miss_retired.remote_fwd",
+ },
+ {
+ .event_code = {0xe6},
+ .umask = 0x1f,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x01,
+ .event_name = "l2_trans.demand_data_rd",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x02,
+ .event_name = "l2_trans.rfo",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x04,
+ .event_name = "l2_trans.code_rd",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x08,
+ .event_name = "l2_trans.all_pf",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x10,
+ .event_name = "l2_trans.l1d_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x20,
+ .event_name = "l2_trans.l2_fill",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_trans.l2_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x80,
+ .event_name = "l2_trans.all_requests",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x01,
+ .event_name = "l2_lines_in.i",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x02,
+ .event_name = "l2_lines_in.s",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x04,
+ .event_name = "l2_lines_in.e",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x07,
+ .event_name = "l2_lines_in.all",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x05,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xf4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x1C, 0x00, 0},
+ {0x26, 0x00, 0},
+ {0x27, 0x00, 0},
+ {0x36, 0x00, 0},
+ {0x35, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x2},
+ .umask = 0x83,
+ .event_name = "store_forwards.any",
+ },
+ {
+ .event_code = {0x2},
+ .umask = 0x81,
+ .event_name = "store_forwards.good",
+ },
+ {
+ .event_code = {0x3},
+ .umask = 0x7F,
+ .event_name = "reissue.any",
+ },
+ {
+ .event_code = {0x3},
+ .umask = 0xFF,
+ .event_name = "reissue.any.ar",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0xF,
+ .event_name = "misalign_mem_ref.split",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x9,
+ .event_name = "misalign_mem_ref.ld_split",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0xA,
+ .event_name = "misalign_mem_ref.st_split",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x8F,
+ .event_name = "misalign_mem_ref.split.ar",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x89,
+ .event_name = "misalign_mem_ref.ld_split.ar",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x8A,
+ .event_name = "misalign_mem_ref.st_split.ar",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x8C,
+ .event_name = "misalign_mem_ref.rmw_split",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x97,
+ .event_name = "misalign_mem_ref.bubble",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x91,
+ .event_name = "misalign_mem_ref.ld_bubble",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x92,
+ .event_name = "misalign_mem_ref.st_bubble",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x94,
+ .event_name = "misalign_mem_ref.rmw_bubble",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x80,
+ .event_name = "segment_reg_loads.any",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x81,
+ .event_name = "prefetch.prefetcht0",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x82,
+ .event_name = "prefetch.prefetcht1",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x84,
+ .event_name = "prefetch.prefetcht2",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x86,
+ .event_name = "prefetch.sw_l2",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x88,
+ .event_name = "prefetch.prefetchnta",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x10,
+ .event_name = "prefetch.hw_prefetch",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0xF,
+ .event_name = "prefetch.software_prefetch",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x8F,
+ .event_name = "prefetch.software_prefetch.ar",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x7,
+ .event_name = "data_tlb_misses.dtlb_miss",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x5,
+ .event_name = "data_tlb_misses.dtlb_miss_ld",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x9,
+ .event_name = "data_tlb_misses.l0_dtlb_miss_ld",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x6,
+ .event_name = "data_tlb_misses.dtlb_miss_st",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0xA,
+ .event_name = "data_tlb_misses.l0_dtlb_miss_st",
+ },
+ {
+ .event_code = {0x9},
+ .umask = 0x20,
+ .event_name = "dispatch_blocked.any",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x3,
+ .event_name = "page_walks.walks",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x3,
+ .event_name = "page_walks.cycles",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x1,
+ .event_name = "page_walks.d_side_walks",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x1,
+ .event_name = "page_walks.d_side_cycles",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x2,
+ .event_name = "page_walks.i_side_walks",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x2,
+ .event_name = "page_walks.i_side_cycles",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x1,
+ .event_name = "x87_comp_ops_exe.any.s",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x81,
+ .event_name = "x87_comp_ops_exe.any.ar",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x2,
+ .event_name = "x87_comp_ops_exe.fxch.s",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x82,
+ .event_name = "x87_comp_ops_exe.fxch.ar",
+ },
+ {
+ .event_code = {0x11},
+ .umask = 0x1,
+ .event_name = "fp_assist.s",
+ },
+ {
+ .event_code = {0x11},
+ .umask = 0x81,
+ .event_name = "fp_assist.ar",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x1,
+ .event_name = "mul.s",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x81,
+ .event_name = "mul.ar",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x1,
+ .event_name = "div.s",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x81,
+ .event_name = "div.ar",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "cycles_div_busy",
+ },
+ {
+ .event_code = {0x21},
+ .umask = 0x40,
+ .event_name = "l2_ads.self",
+ },
+ {
+ .event_code = {0x22},
+ .umask = 0x40,
+ .event_name = "l2_dbus_busy.self",
+ },
+ {
+ .event_code = {0x23},
+ .umask = 0x40,
+ .event_name = "l2_dbus_busy_rd.self",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x70,
+ .event_name = "l2_lines_in.self.any",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x40,
+ .event_name = "l2_lines_in.self.demand",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x50,
+ .event_name = "l2_lines_in.self.prefetch",
+ },
+ {
+ .event_code = {0x25},
+ .umask = 0x40,
+ .event_name = "l2_m_lines_in.self",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x70,
+ .event_name = "l2_lines_out.self.any",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x40,
+ .event_name = "l2_lines_out.self.demand",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x50,
+ .event_name = "l2_lines_out.self.prefetch",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x70,
+ .event_name = "l2_m_lines_out.self.any",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x40,
+ .event_name = "l2_m_lines_out.self.demand",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x50,
+ .event_name = "l2_m_lines_out.self.prefetch",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x44,
+ .event_name = "l2_ifetch.self.e_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x41,
+ .event_name = "l2_ifetch.self.i_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x48,
+ .event_name = "l2_ifetch.self.m_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x42,
+ .event_name = "l2_ifetch.self.s_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x4F,
+ .event_name = "l2_ifetch.self.mesi",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x74,
+ .event_name = "l2_ld.self.any.e_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x71,
+ .event_name = "l2_ld.self.any.i_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x78,
+ .event_name = "l2_ld.self.any.m_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x72,
+ .event_name = "l2_ld.self.any.s_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x7F,
+ .event_name = "l2_ld.self.any.mesi",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x44,
+ .event_name = "l2_ld.self.demand.e_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x41,
+ .event_name = "l2_ld.self.demand.i_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x48,
+ .event_name = "l2_ld.self.demand.m_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x42,
+ .event_name = "l2_ld.self.demand.s_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x4F,
+ .event_name = "l2_ld.self.demand.mesi",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x54,
+ .event_name = "l2_ld.self.prefetch.e_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x51,
+ .event_name = "l2_ld.self.prefetch.i_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x58,
+ .event_name = "l2_ld.self.prefetch.m_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x52,
+ .event_name = "l2_ld.self.prefetch.s_state",
+ },
+ {
+ .event_code = {0x29},
+ .umask = 0x5F,
+ .event_name = "l2_ld.self.prefetch.mesi",
+ },
+ {
+ .event_code = {0x2A},
+ .umask = 0x44,
+ .event_name = "l2_st.self.e_state",
+ },
+ {
+ .event_code = {0x2A},
+ .umask = 0x41,
+ .event_name = "l2_st.self.i_state",
+ },
+ {
+ .event_code = {0x2A},
+ .umask = 0x48,
+ .event_name = "l2_st.self.m_state",
+ },
+ {
+ .event_code = {0x2A},
+ .umask = 0x42,
+ .event_name = "l2_st.self.s_state",
+ },
+ {
+ .event_code = {0x2A},
+ .umask = 0x4F,
+ .event_name = "l2_st.self.mesi",
+ },
+ {
+ .event_code = {0x2B},
+ .umask = 0x44,
+ .event_name = "l2_lock.self.e_state",
+ },
+ {
+ .event_code = {0x2B},
+ .umask = 0x41,
+ .event_name = "l2_lock.self.i_state",
+ },
+ {
+ .event_code = {0x2B},
+ .umask = 0x48,
+ .event_name = "l2_lock.self.m_state",
+ },
+ {
+ .event_code = {0x2B},
+ .umask = 0x42,
+ .event_name = "l2_lock.self.s_state",
+ },
+ {
+ .event_code = {0x2B},
+ .umask = 0x4F,
+ .event_name = "l2_lock.self.mesi",
+ },
+ {
+ .event_code = {0x2C},
+ .umask = 0x44,
+ .event_name = "l2_data_rqsts.self.e_state",
+ },
+ {
+ .event_code = {0x2C},
+ .umask = 0x41,
+ .event_name = "l2_data_rqsts.self.i_state",
+ },
+ {
+ .event_code = {0x2C},
+ .umask = 0x48,
+ .event_name = "l2_data_rqsts.self.m_state",
+ },
+ {
+ .event_code = {0x2C},
+ .umask = 0x42,
+ .event_name = "l2_data_rqsts.self.s_state",
+ },
+ {
+ .event_code = {0x2C},
+ .umask = 0x4F,
+ .event_name = "l2_data_rqsts.self.mesi",
+ },
+ {
+ .event_code = {0x2D},
+ .umask = 0x44,
+ .event_name = "l2_ld_ifetch.self.e_state",
+ },
+ {
+ .event_code = {0x2D},
+ .umask = 0x41,
+ .event_name = "l2_ld_ifetch.self.i_state",
+ },
+ {
+ .event_code = {0x2D},
+ .umask = 0x48,
+ .event_name = "l2_ld_ifetch.self.m_state",
+ },
+ {
+ .event_code = {0x2D},
+ .umask = 0x42,
+ .event_name = "l2_ld_ifetch.self.s_state",
+ },
+ {
+ .event_code = {0x2D},
+ .umask = 0x4F,
+ .event_name = "l2_ld_ifetch.self.mesi",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x74,
+ .event_name = "l2_rqsts.self.any.e_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x71,
+ .event_name = "l2_rqsts.self.any.i_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x78,
+ .event_name = "l2_rqsts.self.any.m_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x72,
+ .event_name = "l2_rqsts.self.any.s_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x7F,
+ .event_name = "l2_rqsts.self.any.mesi",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x44,
+ .event_name = "l2_rqsts.self.demand.e_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x48,
+ .event_name = "l2_rqsts.self.demand.m_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x42,
+ .event_name = "l2_rqsts.self.demand.s_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x54,
+ .event_name = "l2_rqsts.self.prefetch.e_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x51,
+ .event_name = "l2_rqsts.self.prefetch.i_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x58,
+ .event_name = "l2_rqsts.self.prefetch.m_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x52,
+ .event_name = "l2_rqsts.self.prefetch.s_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x5F,
+ .event_name = "l2_rqsts.self.prefetch.mesi",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "l2_rqsts.self.demand.i_state",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "l2_rqsts.self.demand.mesi",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x74,
+ .event_name = "l2_reject_busq.self.any.e_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x71,
+ .event_name = "l2_reject_busq.self.any.i_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x78,
+ .event_name = "l2_reject_busq.self.any.m_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x72,
+ .event_name = "l2_reject_busq.self.any.s_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x7F,
+ .event_name = "l2_reject_busq.self.any.mesi",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x44,
+ .event_name = "l2_reject_busq.self.demand.e_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x41,
+ .event_name = "l2_reject_busq.self.demand.i_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x48,
+ .event_name = "l2_reject_busq.self.demand.m_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x42,
+ .event_name = "l2_reject_busq.self.demand.s_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x4F,
+ .event_name = "l2_reject_busq.self.demand.mesi",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x54,
+ .event_name = "l2_reject_busq.self.prefetch.e_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x51,
+ .event_name = "l2_reject_busq.self.prefetch.i_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x58,
+ .event_name = "l2_reject_busq.self.prefetch.m_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x52,
+ .event_name = "l2_reject_busq.self.prefetch.s_state",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x5F,
+ .event_name = "l2_reject_busq.self.prefetch.mesi",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x40,
+ .event_name = "l2_no_req.self",
+ },
+ {
+ .event_code = {0x3A},
+ .umask = 0x0,
+ .event_name = "eist_trans",
+ },
+ {
+ .event_code = {0x3B},
+ .umask = 0xC0,
+ .event_name = "thermal_trip",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.core_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x1,
+ .event_name = "cpu_clk_unhalted.bus",
+ },
+ {
+ .event_code = {0xA},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.core",
+ },
+ {
+ .event_code = {0xA},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.ref",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0xA1,
+ .event_name = "l1d_cache.ld",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0xA2,
+ .event_name = "l1d_cache.st",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x83,
+ .event_name = "l1d_cache.all_ref",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0xA3,
+ .event_name = "l1d_cache.all_cache_ref",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x8,
+ .event_name = "l1d_cache.repl",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x48,
+ .event_name = "l1d_cache.replm",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x10,
+ .event_name = "l1d_cache.evict",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0xE0,
+ .event_name = "bus_request_outstanding.all_agents",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x40,
+ .event_name = "bus_request_outstanding.self",
+ },
+ {
+ .event_code = {0x61},
+ .umask = 0x20,
+ .event_name = "bus_bnr_drv.all_agents",
+ },
+ {
+ .event_code = {0x61},
+ .umask = 0x0,
+ .event_name = "bus_bnr_drv.this_agent",
+ },
+ {
+ .event_code = {0x62},
+ .umask = 0x20,
+ .event_name = "bus_drdy_clocks.all_agents",
+ },
+ {
+ .event_code = {0x62},
+ .umask = 0x0,
+ .event_name = "bus_drdy_clocks.this_agent",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0xE0,
+ .event_name = "bus_lock_clocks.all_agents",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x40,
+ .event_name = "bus_lock_clocks.self",
+ },
+ {
+ .event_code = {0x64},
+ .umask = 0x40,
+ .event_name = "bus_data_rcv.self",
+ },
+ {
+ .event_code = {0x65},
+ .umask = 0xE0,
+ .event_name = "bus_trans_brd.all_agents",
+ },
+ {
+ .event_code = {0x65},
+ .umask = 0x40,
+ .event_name = "bus_trans_brd.self",
+ },
+ {
+ .event_code = {0x66},
+ .umask = 0xE0,
+ .event_name = "bus_trans_rfo.all_agents",
+ },
+ {
+ .event_code = {0x66},
+ .umask = 0x40,
+ .event_name = "bus_trans_rfo.self",
+ },
+ {
+ .event_code = {0x67},
+ .umask = 0xE0,
+ .event_name = "bus_trans_wb.all_agents",
+ },
+ {
+ .event_code = {0x67},
+ .umask = 0x40,
+ .event_name = "bus_trans_wb.self",
+ },
+ {
+ .event_code = {0x68},
+ .umask = 0xE0,
+ .event_name = "bus_trans_ifetch.all_agents",
+ },
+ {
+ .event_code = {0x68},
+ .umask = 0x40,
+ .event_name = "bus_trans_ifetch.self",
+ },
+ {
+ .event_code = {0x69},
+ .umask = 0xE0,
+ .event_name = "bus_trans_inval.all_agents",
+ },
+ {
+ .event_code = {0x69},
+ .umask = 0x40,
+ .event_name = "bus_trans_inval.self",
+ },
+ {
+ .event_code = {0x6A},
+ .umask = 0xE0,
+ .event_name = "bus_trans_pwr.all_agents",
+ },
+ {
+ .event_code = {0x6A},
+ .umask = 0x40,
+ .event_name = "bus_trans_pwr.self",
+ },
+ {
+ .event_code = {0x6B},
+ .umask = 0xE0,
+ .event_name = "bus_trans_p.all_agents",
+ },
+ {
+ .event_code = {0x6B},
+ .umask = 0x40,
+ .event_name = "bus_trans_p.self",
+ },
+ {
+ .event_code = {0x6C},
+ .umask = 0xE0,
+ .event_name = "bus_trans_io.all_agents",
+ },
+ {
+ .event_code = {0x6C},
+ .umask = 0x40,
+ .event_name = "bus_trans_io.self",
+ },
+ {
+ .event_code = {0x6D},
+ .umask = 0xE0,
+ .event_name = "bus_trans_def.all_agents",
+ },
+ {
+ .event_code = {0x6D},
+ .umask = 0x40,
+ .event_name = "bus_trans_def.self",
+ },
+ {
+ .event_code = {0x6E},
+ .umask = 0xE0,
+ .event_name = "bus_trans_burst.all_agents",
+ },
+ {
+ .event_code = {0x6E},
+ .umask = 0x40,
+ .event_name = "bus_trans_burst.self",
+ },
+ {
+ .event_code = {0x6F},
+ .umask = 0xE0,
+ .event_name = "bus_trans_mem.all_agents",
+ },
+ {
+ .event_code = {0x6F},
+ .umask = 0x40,
+ .event_name = "bus_trans_mem.self",
+ },
+ {
+ .event_code = {0x70},
+ .umask = 0xE0,
+ .event_name = "bus_trans_any.all_agents",
+ },
+ {
+ .event_code = {0x70},
+ .umask = 0x40,
+ .event_name = "bus_trans_any.self",
+ },
+ {
+ .event_code = {0x77},
+ .umask = 0xB,
+ .event_name = "ext_snoop.this_agent.any",
+ },
+ {
+ .event_code = {0x77},
+ .umask = 0x1,
+ .event_name = "ext_snoop.this_agent.clean",
+ },
+ {
+ .event_code = {0x77},
+ .umask = 0x2,
+ .event_name = "ext_snoop.this_agent.hit",
+ },
+ {
+ .event_code = {0x77},
+ .umask = 0x8,
+ .event_name = "ext_snoop.this_agent.hitm",
+ },
+ {
+ .event_code = {0x77},
+ .umask = 0x2B,
+ .event_name = "ext_snoop.all_agents.any",
+ },
+ {
+ .event_code = {0x77},
+ .umask = 0x21,
+ .event_name = "ext_snoop.all_agents.clean",
+ },
+ {
+ .event_code = {0x77},
+ .umask = 0x22,
+ .event_name = "ext_snoop.all_agents.hit",
+ },
+ {
+ .event_code = {0x77},
+ .umask = 0x28,
+ .event_name = "ext_snoop.all_agents.hitm",
+ },
+ {
+ .event_code = {0x7A},
+ .umask = 0x20,
+ .event_name = "bus_hit_drv.all_agents",
+ },
+ {
+ .event_code = {0x7A},
+ .umask = 0x0,
+ .event_name = "bus_hit_drv.this_agent",
+ },
+ {
+ .event_code = {0x7B},
+ .umask = 0x20,
+ .event_name = "bus_hitm_drv.all_agents",
+ },
+ {
+ .event_code = {0x7B},
+ .umask = 0x0,
+ .event_name = "bus_hitm_drv.this_agent",
+ },
+ {
+ .event_code = {0x7D},
+ .umask = 0x40,
+ .event_name = "busq_empty.self",
+ },
+ {
+ .event_code = {0x7E},
+ .umask = 0xE0,
+ .event_name = "snoop_stall_drv.all_agents",
+ },
+ {
+ .event_code = {0x7E},
+ .umask = 0x40,
+ .event_name = "snoop_stall_drv.self",
+ },
+ {
+ .event_code = {0x7F},
+ .umask = 0x40,
+ .event_name = "bus_io_wait.self",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x3,
+ .event_name = "icache.accesses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x1,
+ .event_name = "icache.hit",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x2,
+ .event_name = "icache.misses",
+ },
+ {
+ .event_code = {0x82},
+ .umask = 0x1,
+ .event_name = "itlb.hit",
+ },
+ {
+ .event_code = {0x82},
+ .umask = 0x4,
+ .event_name = "itlb.flush",
+ },
+ {
+ .event_code = {0x82},
+ .umask = 0x2,
+ .event_name = "itlb.misses",
+ },
+ {
+ .event_code = {0x86},
+ .umask = 0x1,
+ .event_name = "cycles_icache_mem_stalled.icache_mem_stalled",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x1,
+ .event_name = "decode_stall.pfb_empty",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x2,
+ .event_name = "decode_stall.iq_full",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x1,
+ .event_name = "br_inst_type_retired.cond",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x2,
+ .event_name = "br_inst_type_retired.uncond",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x4,
+ .event_name = "br_inst_type_retired.ind",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x8,
+ .event_name = "br_inst_type_retired.ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x10,
+ .event_name = "br_inst_type_retired.dir_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x20,
+ .event_name = "br_inst_type_retired.ind_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x41,
+ .event_name = "br_inst_type_retired.cond_taken",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x1,
+ .event_name = "br_missp_type_retired.cond",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x2,
+ .event_name = "br_missp_type_retired.ind",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x4,
+ .event_name = "br_missp_type_retired.return",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x8,
+ .event_name = "br_missp_type_retired.ind_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x11,
+ .event_name = "br_missp_type_retired.cond_taken",
+ },
+ {
+ .event_code = {0xAA},
+ .umask = 0x1,
+ .event_name = "macro_insts.non_cisc_decoded",
+ },
+ {
+ .event_code = {0xAA},
+ .umask = 0x2,
+ .event_name = "macro_insts.cisc_decoded",
+ },
+ {
+ .event_code = {0xAA},
+ .umask = 0x3,
+ .event_name = "macro_insts.all_decoded",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x0,
+ .event_name = "simd_uops_exec.s",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x80,
+ .event_name = "simd_uops_exec.ar",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x0,
+ .event_name = "simd_sat_uop_exec.s",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x80,
+ .event_name = "simd_sat_uop_exec.ar",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x1,
+ .event_name = "simd_uop_type_exec.mul.s",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x81,
+ .event_name = "simd_uop_type_exec.mul.ar",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x2,
+ .event_name = "simd_uop_type_exec.shift.s",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x82,
+ .event_name = "simd_uop_type_exec.shift.ar",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x4,
+ .event_name = "simd_uop_type_exec.pack.s",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x84,
+ .event_name = "simd_uop_type_exec.pack.ar",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x8,
+ .event_name = "simd_uop_type_exec.unpack.s",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x88,
+ .event_name = "simd_uop_type_exec.unpack.ar",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x10,
+ .event_name = "simd_uop_type_exec.logical.s",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x90,
+ .event_name = "simd_uop_type_exec.logical.ar",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x20,
+ .event_name = "simd_uop_type_exec.arithmetic.s",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0xA0,
+ .event_name = "simd_uop_type_exec.arithmetic.ar",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x0,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xA},
+ .umask = 0x0,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x10,
+ .event_name = "uops_retired.any",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x10,
+ .event_name = "uops_retired.stalled_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x10,
+ .event_name = "uops_retired.stalls",
+ },
+ {
+ .event_code = {0xA9},
+ .umask = 0x1,
+ .event_name = "uops.ms_cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x1,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x0,
+ .event_name = "br_inst_retired.any",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x1,
+ .event_name = "br_inst_retired.pred_not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x2,
+ .event_name = "br_inst_retired.mispred_not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x4,
+ .event_name = "br_inst_retired.pred_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x8,
+ .event_name = "br_inst_retired.mispred_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0xC,
+ .event_name = "br_inst_retired.taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0xF,
+ .event_name = "br_inst_retired.any1",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x0,
+ .event_name = "br_inst_retired.mispred",
+ },
+ {
+ .event_code = {0xC6},
+ .umask = 0x1,
+ .event_name = "cycles_int_masked.cycles_int_masked",
+ },
+ {
+ .event_code = {0xC6},
+ .umask = 0x2,
+ .event_name = "cycles_int_masked.cycles_int_pending_and_masked",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x1,
+ .event_name = "simd_inst_retired.packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x2,
+ .event_name = "simd_inst_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x8,
+ .event_name = "simd_inst_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "simd_inst_retired.vector",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x0,
+ .event_name = "hw_int_rcv",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1,
+ .event_name = "simd_comp_inst_retired.packed_single",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x2,
+ .event_name = "simd_comp_inst_retired.scalar_single",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x8,
+ .event_name = "simd_comp_inst_retired.scalar_double",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x1,
+ .event_name = "mem_load_retired.l2_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x2,
+ .event_name = "mem_load_retired.l2_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x4,
+ .event_name = "mem_load_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0xCD},
+ .umask = 0x0,
+ .event_name = "simd_assist",
+ },
+ {
+ .event_code = {0xCE},
+ .umask = 0x0,
+ .event_name = "simd_instr_retired",
+ },
+ {
+ .event_code = {0xCF},
+ .umask = 0x0,
+ .event_name = "simd_sat_instr_retired",
+ },
+ {
+ .event_code = {0xDC},
+ .umask = 0x2,
+ .event_name = "resource_stalls.div_busy",
+ },
+ {
+ .event_code = {0xE0},
+ .umask = 0x1,
+ .event_name = "br_inst_decoded",
+ },
+ {
+ .event_code = {0xE4},
+ .umask = 0x1,
+ .event_name = "bogus_br",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x1,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0x3},
+ .umask = 0x1,
+ .event_name = "reissue.overlap_store",
+ },
+ {
+ .event_code = {0x3},
+ .umask = 0x81,
+ .event_name = "reissue.overlap_store.ar",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x55, 0x05, 1},
+ {0x55, 0x06, 1},
+ {0x55, 0x07, 1},
+ {0x55, 0x08, 1},
+ {0x55, 0x09, 1},
+ {0x55, 0x0A, 1},
+ {0x55, 0x0B, 1},
+ {0x55, 0x0C, 1},
+ {0x55, 0x0D, 1},
+ {0x55, 0x0E, 1},
+ {0x55, 0x0F, 1},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread_any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "ld_blocks.store_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "ld_blocks.no_sr",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x01,
+ .event_name = "ld_blocks_partial.address_alias",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x01,
+ .event_name = "dtlb_load_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x02,
+ .event_name = "dtlb_load_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x04,
+ .event_name = "dtlb_load_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x08,
+ .event_name = "dtlb_load_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x0E,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.walk_pending",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x09},
+ .umask = 0x01,
+ .event_name = "memory_disambiguation.history_reset",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x01,
+ .event_name = "int_misc.recovery_cycles",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x01,
+ .event_name = "int_misc.recovery_cycles_any",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x80,
+ .event_name = "int_misc.clear_resteer_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x20,
+ .event_name = "uops_issued.slow_lea",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x01,
+ .event_name = "arith.divider_active",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x21,
+ .event_name = "l2_rqsts.demand_data_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x22,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x24,
+ .event_name = "l2_rqsts.code_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x27,
+ .event_name = "l2_rqsts.all_demand_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x38,
+ .event_name = "l2_rqsts.pf_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3F,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc1,
+ .event_name = "l2_rqsts.demand_data_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc2,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc4,
+ .event_name = "l2_rqsts.code_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xd8,
+ .event_name = "l2_rqsts.pf_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE1,
+ .event_name = "l2_rqsts.all_demand_data_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE2,
+ .event_name = "l2_rqsts.all_rfo",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE4,
+ .event_name = "l2_rqsts.all_code_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xe7,
+ .event_name = "l2_rqsts.all_demand_references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xF8,
+ .event_name = "l2_rqsts.all_pf",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x07,
+ .event_name = "core_power.lvl0_turbo_license",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x18,
+ .event_name = "core_power.lvl1_turbo_license",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x20,
+ .event_name = "core_power.lvl2_turbo_license",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x40,
+ .event_name = "core_power.throttle",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x01,
+ .event_name = "sw_prefetch_access.nta",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x02,
+ .event_name = "sw_prefetch_access.t0",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x04,
+ .event_name = "sw_prefetch_access.t1_t2",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x08,
+ .event_name = "sw_prefetch_access.prefetchw",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.ring0_trans",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x02,
+ .event_name = "cpu_clk_thread_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x02,
+ .event_name = "l1d_pend_miss.fb_full",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x01,
+ .event_name = "dtlb_store_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x02,
+ .event_name = "dtlb_store_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x04,
+ .event_name = "dtlb_store_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x08,
+ .event_name = "dtlb_store_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x0E,
+ .event_name = "dtlb_store_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_store_misses.walk_pending",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x20,
+ .event_name = "dtlb_store_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x01,
+ .event_name = "load_hit_pre.sw_pf",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_pending",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x01,
+ .event_name = "l1d.replacement",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x01,
+ .event_name = "tx_mem.abort_conflict",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x02,
+ .event_name = "tx_mem.abort_capacity",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x04,
+ .event_name = "tx_mem.abort_hle_store_to_elided_lock",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x08,
+ .event_name = "tx_mem.abort_hle_elision_buffer_not_empty",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x10,
+ .event_name = "tx_mem.abort_hle_elision_buffer_mismatch",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x20,
+ .event_name = "tx_mem.abort_hle_elision_buffer_unsupported_alignment",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x40,
+ .event_name = "tx_mem.hle_elision_buffer_full",
+ },
+ {
+ .event_code = {0x59},
+ .umask = 0x01,
+ .event_name = "partial_rat_stalls.scoreboard",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x01,
+ .event_name = "tx_exec.misc1",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x02,
+ .event_name = "tx_exec.misc2",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x04,
+ .event_name = "tx_exec.misc3",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x08,
+ .event_name = "tx_exec.misc4",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x10,
+ .event_name = "tx_exec.misc5",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_end",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_cycles",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.cycles_with_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.all_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x10,
+ .event_name = "offcore_requests_outstanding.l3_miss_demand_data_rd",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x20,
+ .event_name = "idq.ms_mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_switches",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache_16b.ifdata_stall",
+ },
+ {
+ .event_code = {0x83},
+ .umask = 0x01,
+ .event_name = "icache_64b.iftag_hit",
+ },
+ {
+ .event_code = {0x83},
+ .umask = 0x02,
+ .event_name = "icache_64b.iftag_miss",
+ },
+ {
+ .event_code = {0x83},
+ .umask = 0x04,
+ .event_name = "icache_64b.iftag_stall",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x01,
+ .event_name = "itlb_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x02,
+ .event_name = "itlb_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x04,
+ .event_name = "itlb_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x08,
+ .event_name = "itlb_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x0E,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_pending",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_active",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x20,
+ .event_name = "itlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x01,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_fe_was_ok",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_3_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_2_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_0_uops_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_dispatched_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_dispatched_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_dispatched_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_dispatched_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_7",
+ },
+ {
+ .event_code = {0xa2},
+ .umask = 0x01,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x08,
+ .event_name = "resource_stalls.sb",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.stalls_total",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x08,
+ .event_name = "cycle_activity.cycles_l1d_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x0C,
+ .event_name = "cycle_activity.stalls_l1d_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x10,
+ .event_name = "cycle_activity.cycles_mem_any",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x14,
+ .event_name = "cycle_activity.stalls_mem_any",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x01,
+ .event_name = "exe_activity.exe_bound_0_ports",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x02,
+ .event_name = "exe_activity.1_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x04,
+ .event_name = "exe_activity.2_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x08,
+ .event_name = "exe_activity.3_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x10,
+ .event_name = "exe_activity.4_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x40,
+ .event_name = "exe_activity.bound_on_stores",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_4_uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_active",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x02,
+ .event_name = "dsb2mite_switches.penalty_cycles",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x01,
+ .event_name = "itlb.itlb_flush",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x01,
+ .event_name = "offcore_requests.demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x02,
+ .event_name = "offcore_requests.demand_code_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x04,
+ .event_name = "offcore_requests.demand_rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x08,
+ .event_name = "offcore_requests.all_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x10,
+ .event_name = "offcore_requests.l3_miss_demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x80,
+ .event_name = "offcore_requests.all_requests",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_4_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_3_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_2_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_1_uop_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.thread",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_none",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_4",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_3",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_2",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_1",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x10,
+ .event_name = "uops_executed.x87",
+ },
+ {
+ .event_code = {0xB2},
+ .umask = 0x01,
+ .event_name = "offcore_requests_buffer.sq_full",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x01,
+ .event_name = "tlb_flush.dtlb_thread",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x20,
+ .event_name = "tlb_flush.stlb_any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.prec_dist",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.total_cycles_ps",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.count",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x01,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x04,
+ .event_name = "br_inst_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x08,
+ .event_name = "br_inst_retired.near_return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x10,
+ .event_name = "br_inst_retired.not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x20,
+ .event_name = "br_inst_retired.near_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x40,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x01,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x02,
+ .event_name = "br_misp_retired.near_call",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x04,
+ .event_name = "br_misp_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x20,
+ .event_name = "br_misp_retired.near_taken",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x01,
+ .event_name = "fp_arith_inst_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x02,
+ .event_name = "fp_arith_inst_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x04,
+ .event_name = "fp_arith_inst_retired.128b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x08,
+ .event_name = "fp_arith_inst_retired.128b_packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "fp_arith_inst_retired.256b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x20,
+ .event_name = "fp_arith_inst_retired.256b_packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x40,
+ .event_name = "fp_arith_inst_retired.512b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x80,
+ .event_name = "fp_arith_inst_retired.512b_packed_single",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x01,
+ .event_name = "hle_retired.start",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x02,
+ .event_name = "hle_retired.commit",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x04,
+ .event_name = "hle_retired.aborted",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x08,
+ .event_name = "hle_retired.aborted_mem",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x10,
+ .event_name = "hle_retired.aborted_timer",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x20,
+ .event_name = "hle_retired.aborted_unfriendly",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x40,
+ .event_name = "hle_retired.aborted_memtype",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x80,
+ .event_name = "hle_retired.aborted_events",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x01,
+ .event_name = "rtm_retired.start",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x02,
+ .event_name = "rtm_retired.commit",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x04,
+ .event_name = "rtm_retired.aborted",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x08,
+ .event_name = "rtm_retired.aborted_mem",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x10,
+ .event_name = "rtm_retired.aborted_timer",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x20,
+ .event_name = "rtm_retired.aborted_unfriendly",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x40,
+ .event_name = "rtm_retired.aborted_memtype",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x80,
+ .event_name = "rtm_retired.aborted_events",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1E,
+ .event_name = "fp_assist.any",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x01,
+ .event_name = "hw_interrupts.received",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x20,
+ .event_name = "rob_misc_events.lbr_inserts",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x40,
+ .event_name = "rob_misc_events.pause_inst",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x11,
+ .event_name = "mem_inst_retired.stlb_miss_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x12,
+ .event_name = "mem_inst_retired.stlb_miss_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x21,
+ .event_name = "mem_inst_retired.lock_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x41,
+ .event_name = "mem_inst_retired.split_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x42,
+ .event_name = "mem_inst_retired.split_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x81,
+ .event_name = "mem_inst_retired.all_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x82,
+ .event_name = "mem_inst_retired.all_stores",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x01,
+ .event_name = "mem_load_retired.l1_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x02,
+ .event_name = "mem_load_retired.l2_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x04,
+ .event_name = "mem_load_retired.l3_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x08,
+ .event_name = "mem_load_retired.l1_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x10,
+ .event_name = "mem_load_retired.l2_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x20,
+ .event_name = "mem_load_retired.l3_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x40,
+ .event_name = "mem_load_retired.fb_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x80,
+ .event_name = "mem_load_retired.local_pmm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x01,
+ .event_name = "mem_load_l3_hit_retired.xsnp_miss",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x02,
+ .event_name = "mem_load_l3_hit_retired.xsnp_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x04,
+ .event_name = "mem_load_l3_hit_retired.xsnp_hitm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x08,
+ .event_name = "mem_load_l3_hit_retired.xsnp_none",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x01,
+ .event_name = "mem_load_l3_miss_retired.local_dram",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x02,
+ .event_name = "mem_load_l3_miss_retired.remote_dram",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x04,
+ .event_name = "mem_load_l3_miss_retired.remote_hitm",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x08,
+ .event_name = "mem_load_l3_miss_retired.remote_fwd",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x10,
+ .event_name = "mem_load_l3_miss_retired.remote_pmm",
+ },
+ {
+ .event_code = {0xD4},
+ .umask = 0x04,
+ .event_name = "mem_load_misc_retired.uc",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x01,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x01,
+ .event_name = "core_snoop_response.rsp_ihiti",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x02,
+ .event_name = "core_snoop_response.rsp_ihitfse",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x04,
+ .event_name = "core_snoop_response.rsp_shitfse",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x08,
+ .event_name = "core_snoop_response.rsp_sfwdm",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x10,
+ .event_name = "core_snoop_response.rsp_ifwdm",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x20,
+ .event_name = "core_snoop_response.rsp_ifwdfe",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x40,
+ .event_name = "core_snoop_response.rsp_sfwdfe",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_trans.l2_wb",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x1F,
+ .event_name = "l2_lines_in.all",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x01,
+ .event_name = "l2_lines_out.silent",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x02,
+ .event_name = "l2_lines_out.non_silent",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x04,
+ .event_name = "l2_lines_out.useless_pref",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x04,
+ .event_name = "l2_lines_out.useless_hwpf",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_code = {0xFE},
+ .umask = 0x02,
+ .event_name = "idi_misc.wb_upgrade",
+ },
+ {
+ .event_code = {0xFE},
+ .umask = 0x04,
+ .event_name = "idi_misc.wb_downgrade",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x3C, 0x00, 0},
+ {0x45, 0x00, 0},
+ {0x46, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread_any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "ld_blocks.store_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "ld_blocks.no_sr",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x01,
+ .event_name = "misalign_mem_ref.loads",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x02,
+ .event_name = "misalign_mem_ref.stores",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x01,
+ .event_name = "ld_blocks_partial.address_alias",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x01,
+ .event_name = "dtlb_load_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x02,
+ .event_name = "dtlb_load_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x04,
+ .event_name = "dtlb_load_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x08,
+ .event_name = "dtlb_load_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x0e,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.walk_duration",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x40,
+ .event_name = "dtlb_load_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x60,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x80,
+ .event_name = "dtlb_load_misses.pde_cache_miss",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles_any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.core_stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x10,
+ .event_name = "uops_issued.flags_merge",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x20,
+ .event_name = "uops_issued.slow_lea",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x40,
+ .event_name = "uops_issued.single_mul",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x02,
+ .event_name = "arith.divider_uops",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x21,
+ .event_name = "l2_rqsts.demand_data_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x22,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x24,
+ .event_name = "l2_rqsts.code_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x27,
+ .event_name = "l2_rqsts.all_demand_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.l2_pf_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3F,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc1,
+ .event_name = "l2_rqsts.demand_data_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc2,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc4,
+ .event_name = "l2_rqsts.code_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xd0,
+ .event_name = "l2_rqsts.l2_pf_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE1,
+ .event_name = "l2_rqsts.all_demand_data_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE2,
+ .event_name = "l2_rqsts.all_rfo",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE4,
+ .event_name = "l2_rqsts.all_code_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xe7,
+ .event_name = "l2_rqsts.all_demand_references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xF8,
+ .event_name = "l2_rqsts.all_pf",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x50,
+ .event_name = "l2_demand_rqsts.wb_hit",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3c},
+ .umask = 0x02,
+ .event_name = "cpu_clk_thread_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x02,
+ .event_name = "l1d_pend_miss.request_fb_full",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x01,
+ .event_name = "dtlb_store_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x02,
+ .event_name = "dtlb_store_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x04,
+ .event_name = "dtlb_store_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x08,
+ .event_name = "dtlb_store_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x0e,
+ .event_name = "dtlb_store_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_store_misses.walk_duration",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x20,
+ .event_name = "dtlb_store_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x40,
+ .event_name = "dtlb_store_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x60,
+ .event_name = "dtlb_store_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x80,
+ .event_name = "dtlb_store_misses.pde_cache_miss",
+ },
+ {
+ .event_code = {0x4c},
+ .umask = 0x01,
+ .event_name = "load_hit_pre.sw_pf",
+ },
+ {
+ .event_code = {0x4c},
+ .umask = 0x02,
+ .event_name = "load_hit_pre.hw_pf",
+ },
+ {
+ .event_code = {0x4f},
+ .umask = 0x10,
+ .event_name = "ept.walk_cycles",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x01,
+ .event_name = "l1d.replacement",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x01,
+ .event_name = "tx_mem.abort_conflict",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x02,
+ .event_name = "tx_mem.abort_capacity_write",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x04,
+ .event_name = "tx_mem.abort_hle_store_to_elided_lock",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x08,
+ .event_name = "tx_mem.abort_hle_elision_buffer_not_empty",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x10,
+ .event_name = "tx_mem.abort_hle_elision_buffer_mismatch",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x20,
+ .event_name = "tx_mem.abort_hle_elision_buffer_unsupported_alignment",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x40,
+ .event_name = "tx_mem.hle_elision_buffer_full",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x01,
+ .event_name = "move_elimination.int_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x02,
+ .event_name = "move_elimination.simd_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x04,
+ .event_name = "move_elimination.int_not_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x08,
+ .event_name = "move_elimination.simd_not_eliminated",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0_trans",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x02,
+ .event_name = "cpl_cycles.ring123",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x01,
+ .event_name = "tx_exec.misc1",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x02,
+ .event_name = "tx_exec.misc2",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x04,
+ .event_name = "tx_exec.misc3",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x08,
+ .event_name = "tx_exec.misc4",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x10,
+ .event_name = "tx_exec.misc5",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_cycles",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_end",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.all_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.cycles_with_data_rd",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x01,
+ .event_name = "lock_cycles.split_lock_uc_lock_duration",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x02,
+ .event_name = "lock_cycles.cache_lock_duration",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x02,
+ .event_name = "idq.empty",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_occur",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x20,
+ .event_name = "idq.ms_mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_switches",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x3c,
+ .event_name = "idq.mite_all_uops",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x01,
+ .event_name = "icache.hit",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x02,
+ .event_name = "icache.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache.ifetch_stall",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache.ifdata_stall",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x01,
+ .event_name = "itlb_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x02,
+ .event_name = "itlb_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x04,
+ .event_name = "itlb_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x08,
+ .event_name = "itlb_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x0e,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_duration",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x20,
+ .event_name = "itlb_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x40,
+ .event_name = "itlb_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x60,
+ .event_name = "itlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x01,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x04,
+ .event_name = "ild_stall.iq_full",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x41,
+ .event_name = "br_inst_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x81,
+ .event_name = "br_inst_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x82,
+ .event_name = "br_inst_exec.taken_direct_jump",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x84,
+ .event_name = "br_inst_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x88,
+ .event_name = "br_inst_exec.taken_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x90,
+ .event_name = "br_inst_exec.taken_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xA0,
+ .event_name = "br_inst_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC1,
+ .event_name = "br_inst_exec.all_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC2,
+ .event_name = "br_inst_exec.all_direct_jmp",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC4,
+ .event_name = "br_inst_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC8,
+ .event_name = "br_inst_exec.all_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xD0,
+ .event_name = "br_inst_exec.all_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xFF,
+ .event_name = "br_inst_exec.all_branches",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x41,
+ .event_name = "br_misp_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x81,
+ .event_name = "br_misp_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x84,
+ .event_name = "br_misp_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x88,
+ .event_name = "br_misp_exec.taken_return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xA0,
+ .event_name = "br_misp_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC1,
+ .event_name = "br_misp_exec.all_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC4,
+ .event_name = "br_misp_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xFF,
+ .event_name = "br_misp_exec.all_branches",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_0_uops_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_2_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_3_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_fe_was_ok",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_executed_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_executed_port.port_0_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_executed_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_executed_port.port_1_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_executed_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_executed_port.port_2_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_dispatched_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_executed_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_executed_port.port_3_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_dispatched_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_executed_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_executed_port.port_4_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_dispatched_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_executed_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_executed_port.port_5_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_dispatched_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_executed_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_executed_port.port_6_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_executed_port.port_7",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_executed_port.port_7_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_7",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x01,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x04,
+ .event_name = "resource_stalls.rs",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x08,
+ .event_name = "resource_stalls.sb",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x02,
+ .event_name = "cycle_activity.cycles_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.cycles_no_execute",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x06,
+ .event_name = "cycle_activity.stalls_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x08,
+ .event_name = "cycle_activity.cycles_l1d_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x0C,
+ .event_name = "cycle_activity.stalls_l1d_pending",
+ },
+ {
+ .event_code = {0xa8},
+ .umask = 0x01,
+ .event_name = "lsd.uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_active",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_4_uops",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x02,
+ .event_name = "dsb2mite_switches.penalty_cycles",
+ },
+ {
+ .event_code = {0xae},
+ .umask = 0x01,
+ .event_name = "itlb.itlb_flush",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x01,
+ .event_name = "offcore_requests.demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x02,
+ .event_name = "offcore_requests.demand_code_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x04,
+ .event_name = "offcore_requests.demand_rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x08,
+ .event_name = "offcore_requests.all_data_rd",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_1_uop_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_2_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_3_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_4_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core",
+ },
+ {
+ .event_code = {0xb2},
+ .umask = 0x01,
+ .event_name = "offcore_requests_buffer.sq_full",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x11,
+ .event_name = "page_walker_loads.dtlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x12,
+ .event_name = "page_walker_loads.dtlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x14,
+ .event_name = "page_walker_loads.dtlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x18,
+ .event_name = "page_walker_loads.dtlb_memory",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x21,
+ .event_name = "page_walker_loads.itlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x22,
+ .event_name = "page_walker_loads.itlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x24,
+ .event_name = "page_walker_loads.itlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x28,
+ .event_name = "page_walker_loads.itlb_memory",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x41,
+ .event_name = "page_walker_loads.ept_dtlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x42,
+ .event_name = "page_walker_loads.ept_dtlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x44,
+ .event_name = "page_walker_loads.ept_dtlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x48,
+ .event_name = "page_walker_loads.ept_dtlb_memory",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x81,
+ .event_name = "page_walker_loads.ept_itlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x82,
+ .event_name = "page_walker_loads.ept_itlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x84,
+ .event_name = "page_walker_loads.ept_itlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x88,
+ .event_name = "page_walker_loads.ept_itlb_memory",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x01,
+ .event_name = "tlb_flush.dtlb_thread",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x20,
+ .event_name = "tlb_flush.stlb_any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.prec_dist",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x02,
+ .event_name = "inst_retired.x87",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x08,
+ .event_name = "other_assists.avx_to_sse",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x10,
+ .event_name = "other_assists.sse_to_avx",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x40,
+ .event_name = "other_assists.any_wb_assist",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.all",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.core_stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.count",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x20,
+ .event_name = "machine_clears.maskmov",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x01,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call_r3",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x04,
+ .event_name = "br_inst_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x08,
+ .event_name = "br_inst_retired.near_return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x10,
+ .event_name = "br_inst_retired.not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x20,
+ .event_name = "br_inst_retired.near_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x40,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x01,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x04,
+ .event_name = "br_misp_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x20,
+ .event_name = "br_misp_retired.near_taken",
+ },
+ {
+ .event_code = {0xC6},
+ .umask = 0x07,
+ .event_name = "avx_insts.all",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x01,
+ .event_name = "hle_retired.start",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x02,
+ .event_name = "hle_retired.commit",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x04,
+ .event_name = "hle_retired.aborted",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x08,
+ .event_name = "hle_retired.aborted_misc1",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x10,
+ .event_name = "hle_retired.aborted_misc2",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x20,
+ .event_name = "hle_retired.aborted_misc3",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x40,
+ .event_name = "hle_retired.aborted_misc4",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x80,
+ .event_name = "hle_retired.aborted_misc5",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x01,
+ .event_name = "rtm_retired.start",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x02,
+ .event_name = "rtm_retired.commit",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x04,
+ .event_name = "rtm_retired.aborted",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x08,
+ .event_name = "rtm_retired.aborted_misc1",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x10,
+ .event_name = "rtm_retired.aborted_misc2",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x20,
+ .event_name = "rtm_retired.aborted_misc3",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x40,
+ .event_name = "rtm_retired.aborted_misc4",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x80,
+ .event_name = "rtm_retired.aborted_misc5",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x02,
+ .event_name = "fp_assist.x87_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x04,
+ .event_name = "fp_assist.x87_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x08,
+ .event_name = "fp_assist.simd_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x10,
+ .event_name = "fp_assist.simd_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1E,
+ .event_name = "fp_assist.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x20,
+ .event_name = "rob_misc_events.lbr_inserts",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x11,
+ .event_name = "mem_uops_retired.stlb_miss_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x12,
+ .event_name = "mem_uops_retired.stlb_miss_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x21,
+ .event_name = "mem_uops_retired.lock_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x41,
+ .event_name = "mem_uops_retired.split_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x42,
+ .event_name = "mem_uops_retired.split_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x81,
+ .event_name = "mem_uops_retired.all_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x82,
+ .event_name = "mem_uops_retired.all_stores",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_retired.l1_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_retired.l2_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_retired.l3_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_retired.l1_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x10,
+ .event_name = "mem_load_uops_retired.l2_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x20,
+ .event_name = "mem_load_uops_retired.l3_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x40,
+ .event_name = "mem_load_uops_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_miss",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_hitm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_none",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_l3_miss_retired.local_dram",
+ },
+ {
+ .event_code = {0xe6},
+ .umask = 0x1f,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x01,
+ .event_name = "l2_trans.demand_data_rd",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x02,
+ .event_name = "l2_trans.rfo",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x04,
+ .event_name = "l2_trans.code_rd",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x08,
+ .event_name = "l2_trans.all_pf",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x10,
+ .event_name = "l2_trans.l1d_wb",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x20,
+ .event_name = "l2_trans.l2_fill",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x40,
+ .event_name = "l2_trans.l2_wb",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x80,
+ .event_name = "l2_trans.all_requests",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x01,
+ .event_name = "l2_lines_in.i",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x02,
+ .event_name = "l2_lines_in.s",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x04,
+ .event_name = "l2_lines_in.e",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x07,
+ .event_name = "l2_lines_in.all",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x05,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x06,
+ .event_name = "l2_lines_out.demand_dirty",
+ },
+ {
+ .event_code = {0xf4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x3F, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread_any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "ld_blocks.store_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "ld_blocks.no_sr",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x01,
+ .event_name = "misalign_mem_ref.loads",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x02,
+ .event_name = "misalign_mem_ref.stores",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x01,
+ .event_name = "ld_blocks_partial.address_alias",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x01,
+ .event_name = "dtlb_load_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x02,
+ .event_name = "dtlb_load_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x04,
+ .event_name = "dtlb_load_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x08,
+ .event_name = "dtlb_load_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x0e,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.walk_duration",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x40,
+ .event_name = "dtlb_load_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x60,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x80,
+ .event_name = "dtlb_load_misses.pde_cache_miss",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles_any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.core_stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x10,
+ .event_name = "uops_issued.flags_merge",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x20,
+ .event_name = "uops_issued.slow_lea",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x40,
+ .event_name = "uops_issued.single_mul",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x02,
+ .event_name = "arith.divider_uops",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x21,
+ .event_name = "l2_rqsts.demand_data_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x22,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x24,
+ .event_name = "l2_rqsts.code_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x27,
+ .event_name = "l2_rqsts.all_demand_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.l2_pf_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3F,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc1,
+ .event_name = "l2_rqsts.demand_data_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc2,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc4,
+ .event_name = "l2_rqsts.code_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xd0,
+ .event_name = "l2_rqsts.l2_pf_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE1,
+ .event_name = "l2_rqsts.all_demand_data_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE2,
+ .event_name = "l2_rqsts.all_rfo",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE4,
+ .event_name = "l2_rqsts.all_code_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xe7,
+ .event_name = "l2_rqsts.all_demand_references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xF8,
+ .event_name = "l2_rqsts.all_pf",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x50,
+ .event_name = "l2_demand_rqsts.wb_hit",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3c},
+ .umask = 0x02,
+ .event_name = "cpu_clk_thread_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x02,
+ .event_name = "l1d_pend_miss.request_fb_full",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x01,
+ .event_name = "dtlb_store_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x02,
+ .event_name = "dtlb_store_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x04,
+ .event_name = "dtlb_store_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x08,
+ .event_name = "dtlb_store_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x0e,
+ .event_name = "dtlb_store_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_store_misses.walk_duration",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x20,
+ .event_name = "dtlb_store_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x40,
+ .event_name = "dtlb_store_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x60,
+ .event_name = "dtlb_store_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x80,
+ .event_name = "dtlb_store_misses.pde_cache_miss",
+ },
+ {
+ .event_code = {0x4c},
+ .umask = 0x01,
+ .event_name = "load_hit_pre.sw_pf",
+ },
+ {
+ .event_code = {0x4c},
+ .umask = 0x02,
+ .event_name = "load_hit_pre.hw_pf",
+ },
+ {
+ .event_code = {0x4f},
+ .umask = 0x10,
+ .event_name = "ept.walk_cycles",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x01,
+ .event_name = "l1d.replacement",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x01,
+ .event_name = "tx_mem.abort_conflict",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x02,
+ .event_name = "tx_mem.abort_capacity_write",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x04,
+ .event_name = "tx_mem.abort_hle_store_to_elided_lock",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x08,
+ .event_name = "tx_mem.abort_hle_elision_buffer_not_empty",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x10,
+ .event_name = "tx_mem.abort_hle_elision_buffer_mismatch",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x20,
+ .event_name = "tx_mem.abort_hle_elision_buffer_unsupported_alignment",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x40,
+ .event_name = "tx_mem.hle_elision_buffer_full",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x01,
+ .event_name = "move_elimination.int_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x02,
+ .event_name = "move_elimination.simd_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x04,
+ .event_name = "move_elimination.int_not_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x08,
+ .event_name = "move_elimination.simd_not_eliminated",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0_trans",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x02,
+ .event_name = "cpl_cycles.ring123",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x01,
+ .event_name = "tx_exec.misc1",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x02,
+ .event_name = "tx_exec.misc2",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x04,
+ .event_name = "tx_exec.misc3",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x08,
+ .event_name = "tx_exec.misc4",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x10,
+ .event_name = "tx_exec.misc5",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_cycles",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_end",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.all_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.cycles_with_data_rd",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x01,
+ .event_name = "lock_cycles.split_lock_uc_lock_duration",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x02,
+ .event_name = "lock_cycles.cache_lock_duration",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x02,
+ .event_name = "idq.empty",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_occur",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x20,
+ .event_name = "idq.ms_mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_switches",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x3c,
+ .event_name = "idq.mite_all_uops",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x01,
+ .event_name = "icache.hit",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x02,
+ .event_name = "icache.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache.ifetch_stall",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache.ifdata_stall",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x01,
+ .event_name = "itlb_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x02,
+ .event_name = "itlb_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x04,
+ .event_name = "itlb_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x08,
+ .event_name = "itlb_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x0e,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_duration",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x20,
+ .event_name = "itlb_misses.stlb_hit_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x40,
+ .event_name = "itlb_misses.stlb_hit_2m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x60,
+ .event_name = "itlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x01,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x04,
+ .event_name = "ild_stall.iq_full",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x41,
+ .event_name = "br_inst_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x81,
+ .event_name = "br_inst_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x82,
+ .event_name = "br_inst_exec.taken_direct_jump",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x84,
+ .event_name = "br_inst_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x88,
+ .event_name = "br_inst_exec.taken_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x90,
+ .event_name = "br_inst_exec.taken_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xA0,
+ .event_name = "br_inst_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC1,
+ .event_name = "br_inst_exec.all_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC2,
+ .event_name = "br_inst_exec.all_direct_jmp",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC4,
+ .event_name = "br_inst_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC8,
+ .event_name = "br_inst_exec.all_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xD0,
+ .event_name = "br_inst_exec.all_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xFF,
+ .event_name = "br_inst_exec.all_branches",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x41,
+ .event_name = "br_misp_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x81,
+ .event_name = "br_misp_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x84,
+ .event_name = "br_misp_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x88,
+ .event_name = "br_misp_exec.taken_return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xA0,
+ .event_name = "br_misp_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC1,
+ .event_name = "br_misp_exec.all_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC4,
+ .event_name = "br_misp_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xFF,
+ .event_name = "br_misp_exec.all_branches",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_0_uops_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_2_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_3_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_fe_was_ok",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_executed_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_executed_port.port_0_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_executed_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_executed_port.port_1_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_executed_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_executed_port.port_2_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_dispatched_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_executed_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_executed_port.port_3_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_dispatched_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_executed_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_executed_port.port_4_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_dispatched_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_executed_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_executed_port.port_5_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_dispatched_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_executed_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_executed_port.port_6_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_executed_port.port_7",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_executed_port.port_7_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_7",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x01,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x04,
+ .event_name = "resource_stalls.rs",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x08,
+ .event_name = "resource_stalls.sb",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x02,
+ .event_name = "cycle_activity.cycles_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.cycles_no_execute",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x06,
+ .event_name = "cycle_activity.stalls_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x08,
+ .event_name = "cycle_activity.cycles_l1d_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x0C,
+ .event_name = "cycle_activity.stalls_l1d_pending",
+ },
+ {
+ .event_code = {0xa8},
+ .umask = 0x01,
+ .event_name = "lsd.uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_active",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_4_uops",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x02,
+ .event_name = "dsb2mite_switches.penalty_cycles",
+ },
+ {
+ .event_code = {0xae},
+ .umask = 0x01,
+ .event_name = "itlb.itlb_flush",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x01,
+ .event_name = "offcore_requests.demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x02,
+ .event_name = "offcore_requests.demand_code_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x04,
+ .event_name = "offcore_requests.demand_rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x08,
+ .event_name = "offcore_requests.all_data_rd",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_1_uop_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_2_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_3_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_4_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core",
+ },
+ {
+ .event_code = {0xb2},
+ .umask = 0x01,
+ .event_name = "offcore_requests_buffer.sq_full",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x11,
+ .event_name = "page_walker_loads.dtlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x12,
+ .event_name = "page_walker_loads.dtlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x14,
+ .event_name = "page_walker_loads.dtlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x18,
+ .event_name = "page_walker_loads.dtlb_memory",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x21,
+ .event_name = "page_walker_loads.itlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x22,
+ .event_name = "page_walker_loads.itlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x24,
+ .event_name = "page_walker_loads.itlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x28,
+ .event_name = "page_walker_loads.itlb_memory",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x41,
+ .event_name = "page_walker_loads.ept_dtlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x42,
+ .event_name = "page_walker_loads.ept_dtlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x44,
+ .event_name = "page_walker_loads.ept_dtlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x48,
+ .event_name = "page_walker_loads.ept_dtlb_memory",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x81,
+ .event_name = "page_walker_loads.ept_itlb_l1",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x82,
+ .event_name = "page_walker_loads.ept_itlb_l2",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x84,
+ .event_name = "page_walker_loads.ept_itlb_l3",
+ },
+ {
+ .event_code = {0xBC},
+ .umask = 0x88,
+ .event_name = "page_walker_loads.ept_itlb_memory",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x01,
+ .event_name = "tlb_flush.dtlb_thread",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x20,
+ .event_name = "tlb_flush.stlb_any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.prec_dist",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x02,
+ .event_name = "inst_retired.x87",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x08,
+ .event_name = "other_assists.avx_to_sse",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x10,
+ .event_name = "other_assists.sse_to_avx",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x40,
+ .event_name = "other_assists.any_wb_assist",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.all",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.core_stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.count",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x20,
+ .event_name = "machine_clears.maskmov",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x01,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call_r3",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x04,
+ .event_name = "br_inst_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x08,
+ .event_name = "br_inst_retired.near_return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x10,
+ .event_name = "br_inst_retired.not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x20,
+ .event_name = "br_inst_retired.near_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x40,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x01,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x04,
+ .event_name = "br_misp_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x20,
+ .event_name = "br_misp_retired.near_taken",
+ },
+ {
+ .event_code = {0xC6},
+ .umask = 0x07,
+ .event_name = "avx_insts.all",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x01,
+ .event_name = "hle_retired.start",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x02,
+ .event_name = "hle_retired.commit",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x04,
+ .event_name = "hle_retired.aborted",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x08,
+ .event_name = "hle_retired.aborted_misc1",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x10,
+ .event_name = "hle_retired.aborted_misc2",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x20,
+ .event_name = "hle_retired.aborted_misc3",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x40,
+ .event_name = "hle_retired.aborted_misc4",
+ },
+ {
+ .event_code = {0xc8},
+ .umask = 0x80,
+ .event_name = "hle_retired.aborted_misc5",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x01,
+ .event_name = "rtm_retired.start",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x02,
+ .event_name = "rtm_retired.commit",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x04,
+ .event_name = "rtm_retired.aborted",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x08,
+ .event_name = "rtm_retired.aborted_misc1",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x10,
+ .event_name = "rtm_retired.aborted_misc2",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x20,
+ .event_name = "rtm_retired.aborted_misc3",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x40,
+ .event_name = "rtm_retired.aborted_misc4",
+ },
+ {
+ .event_code = {0xc9},
+ .umask = 0x80,
+ .event_name = "rtm_retired.aborted_misc5",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x02,
+ .event_name = "fp_assist.x87_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x04,
+ .event_name = "fp_assist.x87_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x08,
+ .event_name = "fp_assist.simd_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x10,
+ .event_name = "fp_assist.simd_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1E,
+ .event_name = "fp_assist.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x20,
+ .event_name = "rob_misc_events.lbr_inserts",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x11,
+ .event_name = "mem_uops_retired.stlb_miss_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x12,
+ .event_name = "mem_uops_retired.stlb_miss_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x21,
+ .event_name = "mem_uops_retired.lock_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x41,
+ .event_name = "mem_uops_retired.split_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x42,
+ .event_name = "mem_uops_retired.split_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x81,
+ .event_name = "mem_uops_retired.all_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x82,
+ .event_name = "mem_uops_retired.all_stores",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_retired.l1_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_retired.l2_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_retired.l3_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_retired.l1_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x10,
+ .event_name = "mem_load_uops_retired.l2_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x20,
+ .event_name = "mem_load_uops_retired.l3_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x40,
+ .event_name = "mem_load_uops_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_miss",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_hitm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_l3_hit_retired.xsnp_none",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_l3_miss_retired.local_dram",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_l3_miss_retired.remote_dram",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x10,
+ .event_name = "mem_load_uops_l3_miss_retired.remote_hitm",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x20,
+ .event_name = "mem_load_uops_l3_miss_retired.remote_fwd",
+ },
+ {
+ .event_code = {0xe6},
+ .umask = 0x1f,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x01,
+ .event_name = "l2_trans.demand_data_rd",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x02,
+ .event_name = "l2_trans.rfo",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x04,
+ .event_name = "l2_trans.code_rd",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x08,
+ .event_name = "l2_trans.all_pf",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x10,
+ .event_name = "l2_trans.l1d_wb",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x20,
+ .event_name = "l2_trans.l2_fill",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x40,
+ .event_name = "l2_trans.l2_wb",
+ },
+ {
+ .event_code = {0xf0},
+ .umask = 0x80,
+ .event_name = "l2_trans.all_requests",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x01,
+ .event_name = "l2_lines_in.i",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x02,
+ .event_name = "l2_lines_in.s",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x04,
+ .event_name = "l2_lines_in.e",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x07,
+ .event_name = "l2_lines_in.all",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x05,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x06,
+ .event_name = "l2_lines_out.demand_dirty",
+ },
+ {
+ .event_code = {0xf4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x3A, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread_any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "ld_blocks.store_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "ld_blocks.no_sr",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x01,
+ .event_name = "misalign_mem_ref.loads",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x02,
+ .event_name = "misalign_mem_ref.stores",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x01,
+ .event_name = "ld_blocks_partial.address_alias",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x81,
+ .event_name = "dtlb_load_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x82,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x84,
+ .event_name = "dtlb_load_misses.walk_duration",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x88,
+ .event_name = "dtlb_load_misses.large_page_walk_completed",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_stalls_count",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles_any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.core_stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x10,
+ .event_name = "uops_issued.flags_merge",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x20,
+ .event_name = "uops_issued.slow_lea",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x40,
+ .event_name = "uops_issued.single_mul",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x01,
+ .event_name = "fp_comp_ops_exe.x87",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x10,
+ .event_name = "fp_comp_ops_exe.sse_packed_double",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x20,
+ .event_name = "fp_comp_ops_exe.sse_scalar_single",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x40,
+ .event_name = "fp_comp_ops_exe.sse_packed_single",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x80,
+ .event_name = "fp_comp_ops_exe.sse_scalar_double",
+ },
+ {
+ .event_code = {0x11},
+ .umask = 0x01,
+ .event_name = "simd_fp_256.packed_single",
+ },
+ {
+ .event_code = {0x11},
+ .umask = 0x02,
+ .event_name = "simd_fp_256.packed_double",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x01,
+ .event_name = "arith.fpu_div_active",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x04,
+ .event_name = "arith.fpu_div",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x01,
+ .event_name = "l2_rqsts.demand_data_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x03,
+ .event_name = "l2_rqsts.all_demand_data_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x04,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x08,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x0C,
+ .event_name = "l2_rqsts.all_rfo",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x10,
+ .event_name = "l2_rqsts.code_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x20,
+ .event_name = "l2_rqsts.code_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.all_code_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x40,
+ .event_name = "l2_rqsts.pf_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x80,
+ .event_name = "l2_rqsts.pf_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC0,
+ .event_name = "l2_rqsts.all_pf",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x01,
+ .event_name = "l2_store_lock_rqsts.miss",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x08,
+ .event_name = "l2_store_lock_rqsts.hit_m",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x0F,
+ .event_name = "l2_store_lock_rqsts.all",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x01,
+ .event_name = "l2_l1d_wb_rqsts.miss",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x04,
+ .event_name = "l2_l1d_wb_rqsts.hit_e",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x08,
+ .event_name = "l2_l1d_wb_rqsts.hit_m",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x0F,
+ .event_name = "l2_l1d_wb_rqsts.all",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x02,
+ .event_name = "cpu_clk_thread_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x01,
+ .event_name = "dtlb_store_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x02,
+ .event_name = "dtlb_store_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x04,
+ .event_name = "dtlb_store_misses.walk_duration",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_store_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x01,
+ .event_name = "load_hit_pre.sw_pf",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x02,
+ .event_name = "load_hit_pre.hw_pf",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_cycles",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x01,
+ .event_name = "l1d.replacement",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x01,
+ .event_name = "move_elimination.int_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x02,
+ .event_name = "move_elimination.simd_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x04,
+ .event_name = "move_elimination.int_not_eliminated",
+ },
+ {
+ .event_code = {0x58},
+ .umask = 0x08,
+ .event_name = "move_elimination.simd_not_eliminated",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0_trans",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x02,
+ .event_name = "cpl_cycles.ring123",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_cycles",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_end",
+ },
+ {
+ .event_code = {0x5F},
+ .umask = 0x04,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.all_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.cycles_with_data_rd",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x01,
+ .event_name = "lock_cycles.split_lock_uc_lock_duration",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x02,
+ .event_name = "lock_cycles.cache_lock_duration",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x02,
+ .event_name = "idq.empty",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_occur",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x20,
+ .event_name = "idq.ms_mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_switches",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x3C,
+ .event_name = "idq.mite_all_uops",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x01,
+ .event_name = "icache.hit",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x02,
+ .event_name = "icache.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache.ifetch_stall",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x01,
+ .event_name = "itlb_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x02,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x04,
+ .event_name = "itlb_misses.walk_duration",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x80,
+ .event_name = "itlb_misses.large_page_walk_completed",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x01,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x04,
+ .event_name = "ild_stall.iq_full",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x41,
+ .event_name = "br_inst_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x81,
+ .event_name = "br_inst_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x82,
+ .event_name = "br_inst_exec.taken_direct_jump",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x84,
+ .event_name = "br_inst_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x88,
+ .event_name = "br_inst_exec.taken_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x90,
+ .event_name = "br_inst_exec.taken_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xA0,
+ .event_name = "br_inst_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC1,
+ .event_name = "br_inst_exec.all_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC2,
+ .event_name = "br_inst_exec.all_direct_jmp",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC4,
+ .event_name = "br_inst_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC8,
+ .event_name = "br_inst_exec.all_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xD0,
+ .event_name = "br_inst_exec.all_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xFF,
+ .event_name = "br_inst_exec.all_branches",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x41,
+ .event_name = "br_misp_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x81,
+ .event_name = "br_misp_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x84,
+ .event_name = "br_misp_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x88,
+ .event_name = "br_misp_exec.taken_return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xA0,
+ .event_name = "br_misp_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC1,
+ .event_name = "br_misp_exec.all_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC4,
+ .event_name = "br_misp_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xFF,
+ .event_name = "br_misp_exec.all_branches",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_0_uops_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_2_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_3_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_fe_was_ok",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x0C,
+ .event_name = "uops_dispatched_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x0C,
+ .event_name = "uops_dispatched_port.port_2_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x30,
+ .event_name = "uops_dispatched_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x30,
+ .event_name = "uops_dispatched_port.port_3_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_4_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_5_core",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x01,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x04,
+ .event_name = "resource_stalls.rs",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x08,
+ .event_name = "resource_stalls.sb",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x02,
+ .event_name = "cycle_activity.cycles_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.cycles_no_execute",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x06,
+ .event_name = "cycle_activity.stalls_ldm_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x08,
+ .event_name = "cycle_activity.cycles_l1d_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x0C,
+ .event_name = "cycle_activity.stalls_l1d_pending",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_active",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_4_uops",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x01,
+ .event_name = "dsb2mite_switches.count",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x02,
+ .event_name = "dsb2mite_switches.penalty_cycles",
+ },
+ {
+ .event_code = {0xAC},
+ .umask = 0x08,
+ .event_name = "dsb_fill.exceed_dsb_lines",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x01,
+ .event_name = "itlb.itlb_flush",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x01,
+ .event_name = "offcore_requests.demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x02,
+ .event_name = "offcore_requests.demand_code_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x04,
+ .event_name = "offcore_requests.demand_rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x08,
+ .event_name = "offcore_requests.all_data_rd",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.thread",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_1_uop_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_2_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_3_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_4_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core",
+ },
+ {
+ .event_code = {0xB2},
+ .umask = 0x01,
+ .event_name = "offcore_requests_buffer.sq_full",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x01,
+ .event_name = "tlb_flush.dtlb_thread",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x20,
+ .event_name = "tlb_flush.stlb_any",
+ },
+ {
+ .event_code = {0xBE},
+ .umask = 0x01,
+ .event_name = "page_walks.llc_miss",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.prec_dist",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x08,
+ .event_name = "other_assists.avx_store",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x10,
+ .event_name = "other_assists.avx_to_sse",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x20,
+ .event_name = "other_assists.sse_to_avx",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x80,
+ .event_name = "other_assists.any_wb_assist",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.all",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.core_stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.count",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x20,
+ .event_name = "machine_clears.maskmov",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x01,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call_r3",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x04,
+ .event_name = "br_inst_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x08,
+ .event_name = "br_inst_retired.near_return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x10,
+ .event_name = "br_inst_retired.not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x20,
+ .event_name = "br_inst_retired.near_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x40,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x01,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x04,
+ .event_name = "br_misp_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x20,
+ .event_name = "br_misp_retired.near_taken",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x02,
+ .event_name = "fp_assist.x87_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x04,
+ .event_name = "fp_assist.x87_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x08,
+ .event_name = "fp_assist.simd_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x10,
+ .event_name = "fp_assist.simd_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1E,
+ .event_name = "fp_assist.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x20,
+ .event_name = "rob_misc_events.lbr_inserts",
+ },
+ {
+ .event_code = {0xCD},
+ .umask = 0x02,
+ .event_name = "mem_trans_retired.precise_store",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x11,
+ .event_name = "mem_uops_retired.stlb_miss_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x12,
+ .event_name = "mem_uops_retired.stlb_miss_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x21,
+ .event_name = "mem_uops_retired.lock_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x41,
+ .event_name = "mem_uops_retired.split_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x42,
+ .event_name = "mem_uops_retired.split_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x81,
+ .event_name = "mem_uops_retired.all_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x82,
+ .event_name = "mem_uops_retired.all_stores",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_retired.l1_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_retired.l2_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_retired.llc_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_retired.l1_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x10,
+ .event_name = "mem_load_uops_retired.l2_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x20,
+ .event_name = "mem_load_uops_retired.llc_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x40,
+ .event_name = "mem_load_uops_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_llc_hit_retired.xsnp_miss",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_llc_hit_retired.xsnp_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_llc_hit_retired.xsnp_hitm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_llc_hit_retired.xsnp_none",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_llc_miss_retired.local_dram",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x1F,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x01,
+ .event_name = "l2_trans.demand_data_rd",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x02,
+ .event_name = "l2_trans.rfo",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x04,
+ .event_name = "l2_trans.code_rd",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x08,
+ .event_name = "l2_trans.all_pf",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x10,
+ .event_name = "l2_trans.l1d_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x20,
+ .event_name = "l2_trans.l2_fill",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_trans.l2_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x80,
+ .event_name = "l2_trans.all_requests",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x01,
+ .event_name = "l2_lines_in.i",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x02,
+ .event_name = "l2_lines_in.s",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x04,
+ .event_name = "l2_lines_in.e",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x07,
+ .event_name = "l2_lines_in.all",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x01,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x02,
+ .event_name = "l2_lines_out.demand_dirty",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x04,
+ .event_name = "l2_lines_out.pf_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x08,
+ .event_name = "l2_lines_out.pf_dirty",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x0A,
+ .event_name = "l2_lines_out.dirty_all",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x1E, 0x00, 0},
+ {0x1F, 0x00, 0},
+ {0x1A, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "arith.cycles_div_busy",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "arith.div",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x2,
+ .event_name = "arith.mul",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x2,
+ .event_name = "baclear.bad_target",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x1,
+ .event_name = "baclear.clear",
+ },
+ {
+ .event_code = {0xA7},
+ .umask = 0x1,
+ .event_name = "baclear_force_iq",
+ },
+ {
+ .event_code = {0xE8},
+ .umask = 0x1,
+ .event_name = "bpu_clears.early",
+ },
+ {
+ .event_code = {0xE8},
+ .umask = 0x2,
+ .event_name = "bpu_clears.late",
+ },
+ {
+ .event_code = {0xE5},
+ .umask = 0x1,
+ .event_name = "bpu_missed_call_ret",
+ },
+ {
+ .event_code = {0xE0},
+ .umask = 0x1,
+ .event_name = "br_inst_decoded",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x7F,
+ .event_name = "br_inst_exec.any",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x1,
+ .event_name = "br_inst_exec.cond",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x2,
+ .event_name = "br_inst_exec.direct",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x10,
+ .event_name = "br_inst_exec.direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x20,
+ .event_name = "br_inst_exec.indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x4,
+ .event_name = "br_inst_exec.indirect_non_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x30,
+ .event_name = "br_inst_exec.near_calls",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x7,
+ .event_name = "br_inst_exec.non_calls",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x8,
+ .event_name = "br_inst_exec.return_near",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x40,
+ .event_name = "br_inst_exec.taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x4,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x1,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x2,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x7F,
+ .event_name = "br_misp_exec.any",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x1,
+ .event_name = "br_misp_exec.cond",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x2,
+ .event_name = "br_misp_exec.direct",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x10,
+ .event_name = "br_misp_exec.direct_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x20,
+ .event_name = "br_misp_exec.indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x4,
+ .event_name = "br_misp_exec.indirect_non_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x30,
+ .event_name = "br_misp_exec.near_calls",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x7,
+ .event_name = "br_misp_exec.non_calls",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x8,
+ .event_name = "br_misp_exec.return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x40,
+ .event_name = "br_misp_exec.taken",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x2,
+ .event_name = "br_misp_retired.near_call",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x2,
+ .event_name = "cache_lock_cycles.l1d",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x1,
+ .event_name = "cache_lock_cycles.l1d_l2",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.ref",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x1,
+ .event_name = "cpu_clk_unhalted.ref_p",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.total_cycles",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x1,
+ .event_name = "dtlb_load_misses.any",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.pde_miss",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x2,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x1,
+ .event_name = "dtlb_misses.any",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x2,
+ .event_name = "dtlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0xD5},
+ .umask = 0x1,
+ .event_name = "es_reg_renames",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x1,
+ .event_name = "fp_assist.all",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x4,
+ .event_name = "fp_assist.input",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x2,
+ .event_name = "fp_assist.output",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x2,
+ .event_name = "fp_comp_ops_exe.mmx",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x80,
+ .event_name = "fp_comp_ops_exe.sse_double_precision",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x4,
+ .event_name = "fp_comp_ops_exe.sse_fp",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x10,
+ .event_name = "fp_comp_ops_exe.sse_fp_packed",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x20,
+ .event_name = "fp_comp_ops_exe.sse_fp_scalar",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x40,
+ .event_name = "fp_comp_ops_exe.sse_single_precision",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x8,
+ .event_name = "fp_comp_ops_exe.sse2_integer",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x1,
+ .event_name = "fp_comp_ops_exe.x87",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x3,
+ .event_name = "fp_mmx_trans.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x1,
+ .event_name = "fp_mmx_trans.to_fp",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x2,
+ .event_name = "fp_mmx_trans.to_mmx",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0xF,
+ .event_name = "ild_stall.any",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x4,
+ .event_name = "ild_stall.iq_full",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x1,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x2,
+ .event_name = "ild_stall.mru",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x8,
+ .event_name = "ild_stall.regen",
+ },
+ {
+ .event_code = {0x18},
+ .umask = 0x1,
+ .event_name = "inst_decoded.dec0",
+ },
+ {
+ .event_code = {0x1E},
+ .umask = 0x1,
+ .event_name = "inst_queue_write_cycles",
+ },
+ {
+ .event_code = {0x17},
+ .umask = 0x1,
+ .event_name = "inst_queue_writes",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x4,
+ .event_name = "inst_retired.mmx",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x2,
+ .event_name = "inst_retired.x87",
+ },
+ {
+ .event_code = {0x6C},
+ .umask = 0x1,
+ .event_name = "io_transactions",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x1,
+ .event_name = "itlb_flush",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x20,
+ .event_name = "itlb_miss_retired",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x1,
+ .event_name = "itlb_misses.any",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x2,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x4,
+ .event_name = "l1d.m_evict",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x2,
+ .event_name = "l1d.m_repl",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x8,
+ .event_name = "l1d.m_snoop_evict",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x1,
+ .event_name = "l1d.repl",
+ },
+ {
+ .event_code = {0x43},
+ .umask = 0x1,
+ .event_name = "l1d_all_ref.any",
+ },
+ {
+ .event_code = {0x43},
+ .umask = 0x2,
+ .event_name = "l1d_all_ref.cacheable",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x4,
+ .event_name = "l1d_cache_ld.e_state",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x1,
+ .event_name = "l1d_cache_ld.i_state",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x8,
+ .event_name = "l1d_cache_ld.m_state",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0xF,
+ .event_name = "l1d_cache_ld.mesi",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x2,
+ .event_name = "l1d_cache_ld.s_state",
+ },
+ {
+ .event_code = {0x42},
+ .umask = 0x4,
+ .event_name = "l1d_cache_lock.e_state",
+ },
+ {
+ .event_code = {0x42},
+ .umask = 0x1,
+ .event_name = "l1d_cache_lock.hit",
+ },
+ {
+ .event_code = {0x42},
+ .umask = 0x8,
+ .event_name = "l1d_cache_lock.m_state",
+ },
+ {
+ .event_code = {0x42},
+ .umask = 0x2,
+ .event_name = "l1d_cache_lock.s_state",
+ },
+ {
+ .event_code = {0x53},
+ .umask = 0x1,
+ .event_name = "l1d_cache_lock_fb_hit",
+ },
+ {
+ .event_code = {0x52},
+ .umask = 0x1,
+ .event_name = "l1d_cache_prefetch_lock_fb_hit",
+ },
+ {
+ .event_code = {0x41},
+ .umask = 0x4,
+ .event_name = "l1d_cache_st.e_state",
+ },
+ {
+ .event_code = {0x41},
+ .umask = 0x8,
+ .event_name = "l1d_cache_st.m_state",
+ },
+ {
+ .event_code = {0x41},
+ .umask = 0x2,
+ .event_name = "l1d_cache_st.s_state",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x2,
+ .event_name = "l1d_prefetch.miss",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x1,
+ .event_name = "l1d_prefetch.requests",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x4,
+ .event_name = "l1d_prefetch.triggers",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x4,
+ .event_name = "l1d_wb_l2.e_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x1,
+ .event_name = "l1d_wb_l2.i_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x8,
+ .event_name = "l1d_wb_l2.m_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0xF,
+ .event_name = "l1d_wb_l2.mesi",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x2,
+ .event_name = "l1d_wb_l2.s_state",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x4,
+ .event_name = "l1i.cycles_stalled",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x1,
+ .event_name = "l1i.hits",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x2,
+ .event_name = "l1i.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x3,
+ .event_name = "l1i.reads",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xFF,
+ .event_name = "l2_data_rqsts.any",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x4,
+ .event_name = "l2_data_rqsts.demand.e_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x1,
+ .event_name = "l2_data_rqsts.demand.i_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x8,
+ .event_name = "l2_data_rqsts.demand.m_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xF,
+ .event_name = "l2_data_rqsts.demand.mesi",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x2,
+ .event_name = "l2_data_rqsts.demand.s_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x40,
+ .event_name = "l2_data_rqsts.prefetch.e_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x10,
+ .event_name = "l2_data_rqsts.prefetch.i_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x80,
+ .event_name = "l2_data_rqsts.prefetch.m_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xF0,
+ .event_name = "l2_data_rqsts.prefetch.mesi",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x20,
+ .event_name = "l2_data_rqsts.prefetch.s_state",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x7,
+ .event_name = "l2_lines_in.any",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x4,
+ .event_name = "l2_lines_in.e_state",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x2,
+ .event_name = "l2_lines_in.s_state",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0xF,
+ .event_name = "l2_lines_out.any",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x1,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x2,
+ .event_name = "l2_lines_out.demand_dirty",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x4,
+ .event_name = "l2_lines_out.prefetch_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x8,
+ .event_name = "l2_lines_out.prefetch_dirty",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x10,
+ .event_name = "l2_rqsts.ifetch_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x20,
+ .event_name = "l2_rqsts.ifetch_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.ifetches",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x1,
+ .event_name = "l2_rqsts.ld_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x2,
+ .event_name = "l2_rqsts.ld_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3,
+ .event_name = "l2_rqsts.loads",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xAA,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x40,
+ .event_name = "l2_rqsts.prefetch_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x80,
+ .event_name = "l2_rqsts.prefetch_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC0,
+ .event_name = "l2_rqsts.prefetches",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x4,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x8,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC,
+ .event_name = "l2_rqsts.rfos",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x80,
+ .event_name = "l2_transactions.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x20,
+ .event_name = "l2_transactions.fill",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x4,
+ .event_name = "l2_transactions.ifetch",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x10,
+ .event_name = "l2_transactions.l1d_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x1,
+ .event_name = "l2_transactions.load",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x8,
+ .event_name = "l2_transactions.prefetch",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x2,
+ .event_name = "l2_transactions.rfo",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_transactions.wb",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x40,
+ .event_name = "l2_write.lock.e_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xE0,
+ .event_name = "l2_write.lock.hit",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x10,
+ .event_name = "l2_write.lock.i_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x80,
+ .event_name = "l2_write.lock.m_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xF0,
+ .event_name = "l2_write.lock.mesi",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x20,
+ .event_name = "l2_write.lock.s_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xE,
+ .event_name = "l2_write.rfo.hit",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x1,
+ .event_name = "l2_write.rfo.i_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x8,
+ .event_name = "l2_write.rfo.m_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xF,
+ .event_name = "l2_write.rfo.mesi",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x2,
+ .event_name = "l2_write.rfo.s_state",
+ },
+ {
+ .event_code = {0x82},
+ .umask = 0x1,
+ .event_name = "large_itlb.hit",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x7,
+ .event_name = "load_dispatch.any",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x4,
+ .event_name = "load_dispatch.mob",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x1,
+ .event_name = "load_dispatch.rs",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x2,
+ .event_name = "load_dispatch.rs_delayed",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x1,
+ .event_name = "load_hit_pre",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x1,
+ .event_name = "lsd.active",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x1,
+ .event_name = "lsd.inactive",
+ },
+ {
+ .event_code = {0x20},
+ .umask = 0x1,
+ .event_name = "lsd_overflow",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x1,
+ .event_name = "machine_clears.cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x2,
+ .event_name = "machine_clears.mem_order",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x4,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x1,
+ .event_name = "macro_insts.decoded",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x1,
+ .event_name = "macro_insts.fusions_decoded",
+ },
+ {
+ .event_code = {0xB},
+ .umask = 0x1,
+ .event_name = "mem_inst_retired.loads",
+ },
+ {
+ .event_code = {0xB},
+ .umask = 0x2,
+ .event_name = "mem_inst_retired.stores",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x80,
+ .event_name = "mem_load_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x40,
+ .event_name = "mem_load_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x1,
+ .event_name = "mem_load_retired.l1d_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x2,
+ .event_name = "mem_load_retired.l2_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x10,
+ .event_name = "mem_load_retired.llc_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x4,
+ .event_name = "mem_load_retired.llc_unshared_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x8,
+ .event_name = "mem_load_retired.other_core_l2_hit_hitm",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x1,
+ .event_name = "mem_store_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x20,
+ .event_name = "mem_uncore_retired.local_dram",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x2,
+ .event_name = "mem_uncore_retired.other_core_l2_hitm",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x8,
+ .event_name = "mem_uncore_retired.remote_cache_local_home_hit",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x10,
+ .event_name = "mem_uncore_retired.remote_dram",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x80,
+ .event_name = "mem_uncore_retired.uncacheable",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x40,
+ .event_name = "offcore_requests.l1d_writeback",
+ },
+ {
+ .event_code = {0xB2},
+ .umask = 0x1,
+ .event_name = "offcore_requests_sq_full",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x1,
+ .event_name = "partial_address_alias",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0xF,
+ .event_name = "rat_stalls.any",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x1,
+ .event_name = "rat_stalls.flags",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x2,
+ .event_name = "rat_stalls.registers",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x4,
+ .event_name = "rat_stalls.rob_read_port",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x8,
+ .event_name = "rat_stalls.scoreboard",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x1,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x20,
+ .event_name = "resource_stalls.fpcw",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x2,
+ .event_name = "resource_stalls.load",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x40,
+ .event_name = "resource_stalls.mxcsr",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x80,
+ .event_name = "resource_stalls.other",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob_full",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x4,
+ .event_name = "resource_stalls.rs_full",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x8,
+ .event_name = "resource_stalls.store",
+ },
+ {
+ .event_code = {0x4},
+ .umask = 0x7,
+ .event_name = "sb_drain.any",
+ },
+ {
+ .event_code = {0xD4},
+ .umask = 0x1,
+ .event_name = "seg_rename_stalls",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x4,
+ .event_name = "simd_int_128.pack",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x20,
+ .event_name = "simd_int_128.packed_arith",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x10,
+ .event_name = "simd_int_128.packed_logical",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x1,
+ .event_name = "simd_int_128.packed_mpy",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x2,
+ .event_name = "simd_int_128.packed_shift",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x40,
+ .event_name = "simd_int_128.shuffle_move",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x8,
+ .event_name = "simd_int_128.unpack",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x4,
+ .event_name = "simd_int_64.pack",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x20,
+ .event_name = "simd_int_64.packed_arith",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x10,
+ .event_name = "simd_int_64.packed_logical",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x1,
+ .event_name = "simd_int_64.packed_mpy",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x2,
+ .event_name = "simd_int_64.packed_shift",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x40,
+ .event_name = "simd_int_64.shuffle_move",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x8,
+ .event_name = "simd_int_64.unpack",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x1,
+ .event_name = "snoop_response.hit",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x2,
+ .event_name = "snoop_response.hite",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x4,
+ .event_name = "snoop_response.hitm",
+ },
+ {
+ .event_code = {0xF6},
+ .umask = 0x1,
+ .event_name = "sq_full_stall_cycles",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x4,
+ .event_name = "ssex_uops_retired.packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x1,
+ .event_name = "ssex_uops_retired.packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x8,
+ .event_name = "ssex_uops_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x2,
+ .event_name = "ssex_uops_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "ssex_uops_retired.vector_integer",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x4,
+ .event_name = "store_blocks.at_ret",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x8,
+ .event_name = "store_blocks.l1d_block",
+ },
+ {
+ .event_code = {0x19},
+ .umask = 0x1,
+ .event_name = "two_uop_insts_decoded",
+ },
+ {
+ .event_code = {0xDB},
+ .umask = 0x1,
+ .event_name = "uop_unfusion",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x4,
+ .event_name = "uops_decoded.esp_folding",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x8,
+ .event_name = "uops_decoded.esp_sync",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x2,
+ .event_name = "uops_decoded.ms_cycles_active",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x1,
+ .event_name = "uops_decoded.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_active_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_active_cycles_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_stall_count",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_stall_count_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_stall_cycles_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1,
+ .event_name = "uops_executed.port0",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x40,
+ .event_name = "uops_executed.port015",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x40,
+ .event_name = "uops_executed.port015_stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x2,
+ .event_name = "uops_executed.port1",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x4,
+ .event_name = "uops_executed.port2_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x80,
+ .event_name = "uops_executed.port234_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x8,
+ .event_name = "uops_executed.port3_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x10,
+ .event_name = "uops_executed.port4_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x20,
+ .event_name = "uops_executed.port5",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.core_stall_cycles",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.cycles_all_threads",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x2,
+ .event_name = "uops_issued.fused",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.active_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.any",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x4,
+ .event_name = "uops_retired.macro_fused",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x2,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.total_cycles_ps",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x2E, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "arith.cycles_div_busy",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "arith.div",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x2,
+ .event_name = "arith.mul",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x2,
+ .event_name = "baclear.bad_target",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x1,
+ .event_name = "baclear.clear",
+ },
+ {
+ .event_code = {0xA7},
+ .umask = 0x1,
+ .event_name = "baclear_force_iq",
+ },
+ {
+ .event_code = {0xE8},
+ .umask = 0x1,
+ .event_name = "bpu_clears.early",
+ },
+ {
+ .event_code = {0xE8},
+ .umask = 0x2,
+ .event_name = "bpu_clears.late",
+ },
+ {
+ .event_code = {0xE5},
+ .umask = 0x1,
+ .event_name = "bpu_missed_call_ret",
+ },
+ {
+ .event_code = {0xE0},
+ .umask = 0x1,
+ .event_name = "br_inst_decoded",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x7F,
+ .event_name = "br_inst_exec.any",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x1,
+ .event_name = "br_inst_exec.cond",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x2,
+ .event_name = "br_inst_exec.direct",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x10,
+ .event_name = "br_inst_exec.direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x20,
+ .event_name = "br_inst_exec.indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x4,
+ .event_name = "br_inst_exec.indirect_non_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x30,
+ .event_name = "br_inst_exec.near_calls",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x7,
+ .event_name = "br_inst_exec.non_calls",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x8,
+ .event_name = "br_inst_exec.return_near",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x40,
+ .event_name = "br_inst_exec.taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x4,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x1,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x2,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x7F,
+ .event_name = "br_misp_exec.any",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x1,
+ .event_name = "br_misp_exec.cond",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x2,
+ .event_name = "br_misp_exec.direct",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x10,
+ .event_name = "br_misp_exec.direct_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x20,
+ .event_name = "br_misp_exec.indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x4,
+ .event_name = "br_misp_exec.indirect_non_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x30,
+ .event_name = "br_misp_exec.near_calls",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x7,
+ .event_name = "br_misp_exec.non_calls",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x8,
+ .event_name = "br_misp_exec.return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x40,
+ .event_name = "br_misp_exec.taken",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x2,
+ .event_name = "br_misp_retired.near_call",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x2,
+ .event_name = "cache_lock_cycles.l1d",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x1,
+ .event_name = "cache_lock_cycles.l1d_l2",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.ref",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x1,
+ .event_name = "cpu_clk_unhalted.ref_p",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.total_cycles",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x1,
+ .event_name = "dtlb_load_misses.any",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.pde_miss",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x2,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x1,
+ .event_name = "dtlb_misses.any",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x2,
+ .event_name = "dtlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0xD5},
+ .umask = 0x1,
+ .event_name = "es_reg_renames",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x1,
+ .event_name = "fp_assist.all",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x4,
+ .event_name = "fp_assist.input",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x2,
+ .event_name = "fp_assist.output",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x2,
+ .event_name = "fp_comp_ops_exe.mmx",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x80,
+ .event_name = "fp_comp_ops_exe.sse_double_precision",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x4,
+ .event_name = "fp_comp_ops_exe.sse_fp",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x10,
+ .event_name = "fp_comp_ops_exe.sse_fp_packed",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x20,
+ .event_name = "fp_comp_ops_exe.sse_fp_scalar",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x40,
+ .event_name = "fp_comp_ops_exe.sse_single_precision",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x8,
+ .event_name = "fp_comp_ops_exe.sse2_integer",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x1,
+ .event_name = "fp_comp_ops_exe.x87",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x3,
+ .event_name = "fp_mmx_trans.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x1,
+ .event_name = "fp_mmx_trans.to_fp",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x2,
+ .event_name = "fp_mmx_trans.to_mmx",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0xF,
+ .event_name = "ild_stall.any",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x4,
+ .event_name = "ild_stall.iq_full",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x1,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x2,
+ .event_name = "ild_stall.mru",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x8,
+ .event_name = "ild_stall.regen",
+ },
+ {
+ .event_code = {0x18},
+ .umask = 0x1,
+ .event_name = "inst_decoded.dec0",
+ },
+ {
+ .event_code = {0x1E},
+ .umask = 0x1,
+ .event_name = "inst_queue_write_cycles",
+ },
+ {
+ .event_code = {0x17},
+ .umask = 0x1,
+ .event_name = "inst_queue_writes",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x4,
+ .event_name = "inst_retired.mmx",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x2,
+ .event_name = "inst_retired.x87",
+ },
+ {
+ .event_code = {0x6C},
+ .umask = 0x1,
+ .event_name = "io_transactions",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x1,
+ .event_name = "itlb_flush",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x20,
+ .event_name = "itlb_miss_retired",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x1,
+ .event_name = "itlb_misses.any",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x2,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x4,
+ .event_name = "l1d.m_evict",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x2,
+ .event_name = "l1d.m_repl",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x8,
+ .event_name = "l1d.m_snoop_evict",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x1,
+ .event_name = "l1d.repl",
+ },
+ {
+ .event_code = {0x43},
+ .umask = 0x1,
+ .event_name = "l1d_all_ref.any",
+ },
+ {
+ .event_code = {0x43},
+ .umask = 0x2,
+ .event_name = "l1d_all_ref.cacheable",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x4,
+ .event_name = "l1d_cache_ld.e_state",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x1,
+ .event_name = "l1d_cache_ld.i_state",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x8,
+ .event_name = "l1d_cache_ld.m_state",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0xF,
+ .event_name = "l1d_cache_ld.mesi",
+ },
+ {
+ .event_code = {0x40},
+ .umask = 0x2,
+ .event_name = "l1d_cache_ld.s_state",
+ },
+ {
+ .event_code = {0x42},
+ .umask = 0x4,
+ .event_name = "l1d_cache_lock.e_state",
+ },
+ {
+ .event_code = {0x42},
+ .umask = 0x1,
+ .event_name = "l1d_cache_lock.hit",
+ },
+ {
+ .event_code = {0x42},
+ .umask = 0x8,
+ .event_name = "l1d_cache_lock.m_state",
+ },
+ {
+ .event_code = {0x42},
+ .umask = 0x2,
+ .event_name = "l1d_cache_lock.s_state",
+ },
+ {
+ .event_code = {0x53},
+ .umask = 0x1,
+ .event_name = "l1d_cache_lock_fb_hit",
+ },
+ {
+ .event_code = {0x52},
+ .umask = 0x1,
+ .event_name = "l1d_cache_prefetch_lock_fb_hit",
+ },
+ {
+ .event_code = {0x41},
+ .umask = 0x4,
+ .event_name = "l1d_cache_st.e_state",
+ },
+ {
+ .event_code = {0x41},
+ .umask = 0x8,
+ .event_name = "l1d_cache_st.m_state",
+ },
+ {
+ .event_code = {0x41},
+ .umask = 0x2,
+ .event_name = "l1d_cache_st.s_state",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x2,
+ .event_name = "l1d_prefetch.miss",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x1,
+ .event_name = "l1d_prefetch.requests",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x4,
+ .event_name = "l1d_prefetch.triggers",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x4,
+ .event_name = "l1d_wb_l2.e_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x1,
+ .event_name = "l1d_wb_l2.i_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x8,
+ .event_name = "l1d_wb_l2.m_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0xF,
+ .event_name = "l1d_wb_l2.mesi",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x2,
+ .event_name = "l1d_wb_l2.s_state",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x4,
+ .event_name = "l1i.cycles_stalled",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x1,
+ .event_name = "l1i.hits",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x2,
+ .event_name = "l1i.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x3,
+ .event_name = "l1i.reads",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xFF,
+ .event_name = "l2_data_rqsts.any",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x4,
+ .event_name = "l2_data_rqsts.demand.e_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x1,
+ .event_name = "l2_data_rqsts.demand.i_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x8,
+ .event_name = "l2_data_rqsts.demand.m_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xF,
+ .event_name = "l2_data_rqsts.demand.mesi",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x2,
+ .event_name = "l2_data_rqsts.demand.s_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x40,
+ .event_name = "l2_data_rqsts.prefetch.e_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x10,
+ .event_name = "l2_data_rqsts.prefetch.i_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x80,
+ .event_name = "l2_data_rqsts.prefetch.m_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xF0,
+ .event_name = "l2_data_rqsts.prefetch.mesi",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x20,
+ .event_name = "l2_data_rqsts.prefetch.s_state",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x7,
+ .event_name = "l2_lines_in.any",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x4,
+ .event_name = "l2_lines_in.e_state",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x2,
+ .event_name = "l2_lines_in.s_state",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0xF,
+ .event_name = "l2_lines_out.any",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x1,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x2,
+ .event_name = "l2_lines_out.demand_dirty",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x4,
+ .event_name = "l2_lines_out.prefetch_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x8,
+ .event_name = "l2_lines_out.prefetch_dirty",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x10,
+ .event_name = "l2_rqsts.ifetch_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x20,
+ .event_name = "l2_rqsts.ifetch_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.ifetches",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x1,
+ .event_name = "l2_rqsts.ld_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x2,
+ .event_name = "l2_rqsts.ld_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3,
+ .event_name = "l2_rqsts.loads",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xAA,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x40,
+ .event_name = "l2_rqsts.prefetch_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x80,
+ .event_name = "l2_rqsts.prefetch_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC0,
+ .event_name = "l2_rqsts.prefetches",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x4,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x8,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC,
+ .event_name = "l2_rqsts.rfos",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x80,
+ .event_name = "l2_transactions.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x20,
+ .event_name = "l2_transactions.fill",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x4,
+ .event_name = "l2_transactions.ifetch",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x10,
+ .event_name = "l2_transactions.l1d_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x1,
+ .event_name = "l2_transactions.load",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x8,
+ .event_name = "l2_transactions.prefetch",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x2,
+ .event_name = "l2_transactions.rfo",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_transactions.wb",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x40,
+ .event_name = "l2_write.lock.e_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xE0,
+ .event_name = "l2_write.lock.hit",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x10,
+ .event_name = "l2_write.lock.i_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x80,
+ .event_name = "l2_write.lock.m_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xF0,
+ .event_name = "l2_write.lock.mesi",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x20,
+ .event_name = "l2_write.lock.s_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xE,
+ .event_name = "l2_write.rfo.hit",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x1,
+ .event_name = "l2_write.rfo.i_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x8,
+ .event_name = "l2_write.rfo.m_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xF,
+ .event_name = "l2_write.rfo.mesi",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x2,
+ .event_name = "l2_write.rfo.s_state",
+ },
+ {
+ .event_code = {0x82},
+ .umask = 0x1,
+ .event_name = "large_itlb.hit",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x7,
+ .event_name = "load_dispatch.any",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x4,
+ .event_name = "load_dispatch.mob",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x1,
+ .event_name = "load_dispatch.rs",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x2,
+ .event_name = "load_dispatch.rs_delayed",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x1,
+ .event_name = "load_hit_pre",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x1,
+ .event_name = "lsd.active",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x1,
+ .event_name = "lsd.inactive",
+ },
+ {
+ .event_code = {0x20},
+ .umask = 0x1,
+ .event_name = "lsd_overflow",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x1,
+ .event_name = "machine_clears.cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x2,
+ .event_name = "machine_clears.mem_order",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x4,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x1,
+ .event_name = "macro_insts.decoded",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x1,
+ .event_name = "macro_insts.fusions_decoded",
+ },
+ {
+ .event_code = {0xB},
+ .umask = 0x1,
+ .event_name = "mem_inst_retired.loads",
+ },
+ {
+ .event_code = {0xB},
+ .umask = 0x2,
+ .event_name = "mem_inst_retired.stores",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x80,
+ .event_name = "mem_load_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x40,
+ .event_name = "mem_load_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x1,
+ .event_name = "mem_load_retired.l1d_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x2,
+ .event_name = "mem_load_retired.l2_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x10,
+ .event_name = "mem_load_retired.llc_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x4,
+ .event_name = "mem_load_retired.llc_unshared_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x8,
+ .event_name = "mem_load_retired.other_core_l2_hit_hitm",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x1,
+ .event_name = "mem_store_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x40,
+ .event_name = "offcore_requests.l1d_writeback",
+ },
+ {
+ .event_code = {0xB2},
+ .umask = 0x1,
+ .event_name = "offcore_requests_sq_full",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x1,
+ .event_name = "partial_address_alias",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0xF,
+ .event_name = "rat_stalls.any",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x1,
+ .event_name = "rat_stalls.flags",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x2,
+ .event_name = "rat_stalls.registers",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x4,
+ .event_name = "rat_stalls.rob_read_port",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x8,
+ .event_name = "rat_stalls.scoreboard",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x1,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x20,
+ .event_name = "resource_stalls.fpcw",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x2,
+ .event_name = "resource_stalls.load",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x40,
+ .event_name = "resource_stalls.mxcsr",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x80,
+ .event_name = "resource_stalls.other",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob_full",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x4,
+ .event_name = "resource_stalls.rs_full",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x8,
+ .event_name = "resource_stalls.store",
+ },
+ {
+ .event_code = {0x4},
+ .umask = 0x7,
+ .event_name = "sb_drain.any",
+ },
+ {
+ .event_code = {0xD4},
+ .umask = 0x1,
+ .event_name = "seg_rename_stalls",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x4,
+ .event_name = "simd_int_128.pack",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x20,
+ .event_name = "simd_int_128.packed_arith",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x10,
+ .event_name = "simd_int_128.packed_logical",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x1,
+ .event_name = "simd_int_128.packed_mpy",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x2,
+ .event_name = "simd_int_128.packed_shift",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x40,
+ .event_name = "simd_int_128.shuffle_move",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x8,
+ .event_name = "simd_int_128.unpack",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x4,
+ .event_name = "simd_int_64.pack",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x20,
+ .event_name = "simd_int_64.packed_arith",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x10,
+ .event_name = "simd_int_64.packed_logical",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x1,
+ .event_name = "simd_int_64.packed_mpy",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x2,
+ .event_name = "simd_int_64.packed_shift",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x40,
+ .event_name = "simd_int_64.shuffle_move",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x8,
+ .event_name = "simd_int_64.unpack",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x1,
+ .event_name = "snoop_response.hit",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x2,
+ .event_name = "snoop_response.hite",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x4,
+ .event_name = "snoop_response.hitm",
+ },
+ {
+ .event_code = {0xF6},
+ .umask = 0x1,
+ .event_name = "sq_full_stall_cycles",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x4,
+ .event_name = "ssex_uops_retired.packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x1,
+ .event_name = "ssex_uops_retired.packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x8,
+ .event_name = "ssex_uops_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x2,
+ .event_name = "ssex_uops_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "ssex_uops_retired.vector_integer",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x4,
+ .event_name = "store_blocks.at_ret",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x8,
+ .event_name = "store_blocks.l1d_block",
+ },
+ {
+ .event_code = {0x19},
+ .umask = 0x1,
+ .event_name = "two_uop_insts_decoded",
+ },
+ {
+ .event_code = {0xDB},
+ .umask = 0x1,
+ .event_name = "uop_unfusion",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x4,
+ .event_name = "uops_decoded.esp_folding",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x8,
+ .event_name = "uops_decoded.esp_sync",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x2,
+ .event_name = "uops_decoded.ms_cycles_active",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x1,
+ .event_name = "uops_decoded.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_active_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_active_cycles_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_stall_count",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_stall_count_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_stall_cycles_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1,
+ .event_name = "uops_executed.port0",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x40,
+ .event_name = "uops_executed.port015",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x40,
+ .event_name = "uops_executed.port015_stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x2,
+ .event_name = "uops_executed.port1",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x4,
+ .event_name = "uops_executed.port2_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x80,
+ .event_name = "uops_executed.port234_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x8,
+ .event_name = "uops_executed.port3_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x10,
+ .event_name = "uops_executed.port4_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x20,
+ .event_name = "uops_executed.port5",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.core_stall_cycles",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.cycles_all_threads",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x2,
+ .event_name = "uops_issued.fused",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.active_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.any",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x4,
+ .event_name = "uops_retired.macro_fused",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x2,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.total_cycles_ps",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x4E, 0x00, 0},
+ {0x5E, 0x00, 0},
+ {0x8E, 0x00, 0},
+ {0x9E, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread_any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "ld_blocks.store_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "ld_blocks.no_sr",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x01,
+ .event_name = "ld_blocks_partial.address_alias",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x01,
+ .event_name = "dtlb_load_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x02,
+ .event_name = "dtlb_load_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x04,
+ .event_name = "dtlb_load_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x08,
+ .event_name = "dtlb_load_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x0E,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.walk_pending",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x01,
+ .event_name = "int_misc.recovery_cycles",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x01,
+ .event_name = "int_misc.recovery_cycles_any",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x80,
+ .event_name = "int_misc.clear_resteer_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x20,
+ .event_name = "uops_issued.slow_lea",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x01,
+ .event_name = "arith.divider_active",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x21,
+ .event_name = "l2_rqsts.demand_data_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x22,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x24,
+ .event_name = "l2_rqsts.code_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x27,
+ .event_name = "l2_rqsts.all_demand_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x38,
+ .event_name = "l2_rqsts.pf_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3F,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc1,
+ .event_name = "l2_rqsts.demand_data_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc2,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc4,
+ .event_name = "l2_rqsts.code_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xd8,
+ .event_name = "l2_rqsts.pf_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE1,
+ .event_name = "l2_rqsts.all_demand_data_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE2,
+ .event_name = "l2_rqsts.all_rfo",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE4,
+ .event_name = "l2_rqsts.all_code_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xe7,
+ .event_name = "l2_rqsts.all_demand_references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xF8,
+ .event_name = "l2_rqsts.all_pf",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x01,
+ .event_name = "sw_prefetch_access.nta",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x02,
+ .event_name = "sw_prefetch_access.t0",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x04,
+ .event_name = "sw_prefetch_access.t1_t2",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x08,
+ .event_name = "sw_prefetch_access.prefetchw",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.ring0_trans",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x02,
+ .event_name = "cpu_clk_thread_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x02,
+ .event_name = "l1d_pend_miss.fb_full",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x01,
+ .event_name = "dtlb_store_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x02,
+ .event_name = "dtlb_store_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x04,
+ .event_name = "dtlb_store_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x08,
+ .event_name = "dtlb_store_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x0E,
+ .event_name = "dtlb_store_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_store_misses.walk_pending",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x20,
+ .event_name = "dtlb_store_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x01,
+ .event_name = "load_hit_pre.sw_pf",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_pending",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x01,
+ .event_name = "l1d.replacement",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x01,
+ .event_name = "tx_mem.abort_conflict",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x02,
+ .event_name = "tx_mem.abort_capacity",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x04,
+ .event_name = "tx_mem.abort_hle_store_to_elided_lock",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x08,
+ .event_name = "tx_mem.abort_hle_elision_buffer_not_empty",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x10,
+ .event_name = "tx_mem.abort_hle_elision_buffer_mismatch",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x20,
+ .event_name = "tx_mem.abort_hle_elision_buffer_unsupported_alignment",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x40,
+ .event_name = "tx_mem.hle_elision_buffer_full",
+ },
+ {
+ .event_code = {0x59},
+ .umask = 0x01,
+ .event_name = "partial_rat_stalls.scoreboard",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x01,
+ .event_name = "tx_exec.misc1",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x02,
+ .event_name = "tx_exec.misc2",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x04,
+ .event_name = "tx_exec.misc3",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x08,
+ .event_name = "tx_exec.misc4",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x10,
+ .event_name = "tx_exec.misc5",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_cycles",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_end",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.all_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.cycles_with_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x10,
+ .event_name = "offcore_requests_outstanding.l3_miss_demand_data_rd",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x20,
+ .event_name = "idq.ms_mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_switches",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_uops",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache_16b.ifdata_stall",
+ },
+ {
+ .event_code = {0x83},
+ .umask = 0x01,
+ .event_name = "icache_64b.iftag_hit",
+ },
+ {
+ .event_code = {0x83},
+ .umask = 0x02,
+ .event_name = "icache_64b.iftag_miss",
+ },
+ {
+ .event_code = {0x83},
+ .umask = 0x04,
+ .event_name = "icache_64b.iftag_stall",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x01,
+ .event_name = "itlb_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x02,
+ .event_name = "itlb_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x04,
+ .event_name = "itlb_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x08,
+ .event_name = "itlb_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x0E,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_pending",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_active",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x20,
+ .event_name = "itlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x01,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_0_uops_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_2_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_3_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_fe_was_ok",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_dispatched_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_dispatched_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_dispatched_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_dispatched_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_7",
+ },
+ {
+ .event_code = {0xa2},
+ .umask = 0x01,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x08,
+ .event_name = "resource_stalls.sb",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.stalls_total",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x08,
+ .event_name = "cycle_activity.cycles_l1d_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x0C,
+ .event_name = "cycle_activity.stalls_l1d_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x10,
+ .event_name = "cycle_activity.cycles_mem_any",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x14,
+ .event_name = "cycle_activity.stalls_mem_any",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x01,
+ .event_name = "exe_activity.exe_bound_0_ports",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x02,
+ .event_name = "exe_activity.1_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x04,
+ .event_name = "exe_activity.2_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x08,
+ .event_name = "exe_activity.3_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x10,
+ .event_name = "exe_activity.4_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x40,
+ .event_name = "exe_activity.bound_on_stores",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_active",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_4_uops",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x02,
+ .event_name = "dsb2mite_switches.penalty_cycles",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x01,
+ .event_name = "itlb.itlb_flush",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x01,
+ .event_name = "offcore_requests.demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x02,
+ .event_name = "offcore_requests.demand_code_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x04,
+ .event_name = "offcore_requests.demand_rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x08,
+ .event_name = "offcore_requests.all_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x10,
+ .event_name = "offcore_requests.l3_miss_demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x80,
+ .event_name = "offcore_requests.all_requests",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.thread",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_1_uop_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_2_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_3_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_4_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_1",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_2",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_3",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_4",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_none",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x10,
+ .event_name = "uops_executed.x87",
+ },
+ {
+ .event_code = {0xB2},
+ .umask = 0x01,
+ .event_name = "offcore_requests_buffer.sq_full",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x01,
+ .event_name = "tlb_flush.dtlb_thread",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x20,
+ .event_name = "tlb_flush.stlb_any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.prec_dist",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.total_cycles_ps",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.count",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x01,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x04,
+ .event_name = "br_inst_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x08,
+ .event_name = "br_inst_retired.near_return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x10,
+ .event_name = "br_inst_retired.not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x20,
+ .event_name = "br_inst_retired.near_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x40,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x01,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x02,
+ .event_name = "br_misp_retired.near_call",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x04,
+ .event_name = "br_misp_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x20,
+ .event_name = "br_misp_retired.near_taken",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x01,
+ .event_name = "fp_arith_inst_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x02,
+ .event_name = "fp_arith_inst_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x04,
+ .event_name = "fp_arith_inst_retired.128b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x08,
+ .event_name = "fp_arith_inst_retired.128b_packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "fp_arith_inst_retired.256b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x20,
+ .event_name = "fp_arith_inst_retired.256b_packed_single",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x01,
+ .event_name = "hle_retired.start",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x02,
+ .event_name = "hle_retired.commit",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x04,
+ .event_name = "hle_retired.aborted",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x08,
+ .event_name = "hle_retired.aborted_mem",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x10,
+ .event_name = "hle_retired.aborted_timer",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x20,
+ .event_name = "hle_retired.aborted_unfriendly",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x40,
+ .event_name = "hle_retired.aborted_memtype",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x80,
+ .event_name = "hle_retired.aborted_events",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x01,
+ .event_name = "rtm_retired.start",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x02,
+ .event_name = "rtm_retired.commit",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x04,
+ .event_name = "rtm_retired.aborted",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x08,
+ .event_name = "rtm_retired.aborted_mem",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x10,
+ .event_name = "rtm_retired.aborted_timer",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x20,
+ .event_name = "rtm_retired.aborted_unfriendly",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x40,
+ .event_name = "rtm_retired.aborted_memtype",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x80,
+ .event_name = "rtm_retired.aborted_events",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1E,
+ .event_name = "fp_assist.any",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x01,
+ .event_name = "hw_interrupts.received",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x20,
+ .event_name = "rob_misc_events.lbr_inserts",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x40,
+ .event_name = "rob_misc_events.pause_inst",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x11,
+ .event_name = "mem_inst_retired.stlb_miss_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x12,
+ .event_name = "mem_inst_retired.stlb_miss_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x21,
+ .event_name = "mem_inst_retired.lock_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x41,
+ .event_name = "mem_inst_retired.split_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x42,
+ .event_name = "mem_inst_retired.split_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x81,
+ .event_name = "mem_inst_retired.all_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x82,
+ .event_name = "mem_inst_retired.all_stores",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x01,
+ .event_name = "mem_load_retired.l1_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x02,
+ .event_name = "mem_load_retired.l2_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x04,
+ .event_name = "mem_load_retired.l3_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x08,
+ .event_name = "mem_load_retired.l1_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x10,
+ .event_name = "mem_load_retired.l2_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x20,
+ .event_name = "mem_load_retired.l3_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x40,
+ .event_name = "mem_load_retired.fb_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x01,
+ .event_name = "mem_load_l3_hit_retired.xsnp_miss",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x02,
+ .event_name = "mem_load_l3_hit_retired.xsnp_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x04,
+ .event_name = "mem_load_l3_hit_retired.xsnp_hitm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x08,
+ .event_name = "mem_load_l3_hit_retired.xsnp_none",
+ },
+ {
+ .event_code = {0xD4},
+ .umask = 0x04,
+ .event_name = "mem_load_misc_retired.uc",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x01,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_trans.l2_wb",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x1F,
+ .event_name = "l2_lines_in.all",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x01,
+ .event_name = "l2_lines_out.silent",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x02,
+ .event_name = "l2_lines_out.non_silent",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x04,
+ .event_name = "l2_lines_out.useless_pref",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x04,
+ .event_name = "l2_lines_out.useless_hwpf",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x55, 0x00, 1},
+ {0x55, 0x01, 1},
+ {0x55, 0x02, 1},
+ {0x55, 0x03, 1},
+ {0x55, 0x04, 1},
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread_any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "ld_blocks.store_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "ld_blocks.no_sr",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x01,
+ .event_name = "ld_blocks_partial.address_alias",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x01,
+ .event_name = "dtlb_load_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x02,
+ .event_name = "dtlb_load_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x04,
+ .event_name = "dtlb_load_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x08,
+ .event_name = "dtlb_load_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x0E,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.walk_pending",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x01,
+ .event_name = "int_misc.recovery_cycles",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x01,
+ .event_name = "int_misc.recovery_cycles_any",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x80,
+ .event_name = "int_misc.clear_resteer_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x20,
+ .event_name = "uops_issued.slow_lea",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x01,
+ .event_name = "arith.divider_active",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x21,
+ .event_name = "l2_rqsts.demand_data_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x22,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x24,
+ .event_name = "l2_rqsts.code_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x27,
+ .event_name = "l2_rqsts.all_demand_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x38,
+ .event_name = "l2_rqsts.pf_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3F,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc1,
+ .event_name = "l2_rqsts.demand_data_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc2,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xc4,
+ .event_name = "l2_rqsts.code_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xd8,
+ .event_name = "l2_rqsts.pf_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE1,
+ .event_name = "l2_rqsts.all_demand_data_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE2,
+ .event_name = "l2_rqsts.all_rfo",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xE4,
+ .event_name = "l2_rqsts.all_code_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xe7,
+ .event_name = "l2_rqsts.all_demand_references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xF8,
+ .event_name = "l2_rqsts.all_pf",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x07,
+ .event_name = "core_power.lvl0_turbo_license",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x18,
+ .event_name = "core_power.lvl1_turbo_license",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x20,
+ .event_name = "core_power.lvl2_turbo_license",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x40,
+ .event_name = "core_power.throttle",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x01,
+ .event_name = "sw_prefetch_access.nta",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x02,
+ .event_name = "sw_prefetch_access.t0",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x04,
+ .event_name = "sw_prefetch_access.t1_t2",
+ },
+ {
+ .event_code = {0x32},
+ .umask = 0x08,
+ .event_name = "sw_prefetch_access.prefetchw",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.ring0_trans",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_unhalted.ref_xclk_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x02,
+ .event_name = "cpu_clk_thread_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x02,
+ .event_name = "l1d_pend_miss.fb_full",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x01,
+ .event_name = "dtlb_store_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x02,
+ .event_name = "dtlb_store_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x04,
+ .event_name = "dtlb_store_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x08,
+ .event_name = "dtlb_store_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x0E,
+ .event_name = "dtlb_store_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_store_misses.walk_pending",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x20,
+ .event_name = "dtlb_store_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x01,
+ .event_name = "load_hit_pre.sw_pf",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_pending",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x01,
+ .event_name = "l1d.replacement",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x01,
+ .event_name = "tx_mem.abort_conflict",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x02,
+ .event_name = "tx_mem.abort_capacity",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x04,
+ .event_name = "tx_mem.abort_hle_store_to_elided_lock",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x08,
+ .event_name = "tx_mem.abort_hle_elision_buffer_not_empty",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x10,
+ .event_name = "tx_mem.abort_hle_elision_buffer_mismatch",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x20,
+ .event_name = "tx_mem.abort_hle_elision_buffer_unsupported_alignment",
+ },
+ {
+ .event_code = {0x54},
+ .umask = 0x40,
+ .event_name = "tx_mem.hle_elision_buffer_full",
+ },
+ {
+ .event_code = {0x59},
+ .umask = 0x01,
+ .event_name = "partial_rat_stalls.scoreboard",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x01,
+ .event_name = "tx_exec.misc1",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x02,
+ .event_name = "tx_exec.misc2",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x04,
+ .event_name = "tx_exec.misc3",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x08,
+ .event_name = "tx_exec.misc4",
+ },
+ {
+ .event_code = {0x5d},
+ .umask = 0x10,
+ .event_name = "tx_exec.misc5",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_end",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_cycles",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x02,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_code_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.cycles_with_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.all_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x10,
+ .event_name = "offcore_requests_outstanding.l3_miss_demand_data_rd",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x20,
+ .event_name = "idq.ms_mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_switches",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x04,
+ .event_name = "icache_16b.ifdata_stall",
+ },
+ {
+ .event_code = {0x83},
+ .umask = 0x01,
+ .event_name = "icache_64b.iftag_hit",
+ },
+ {
+ .event_code = {0x83},
+ .umask = 0x02,
+ .event_name = "icache_64b.iftag_miss",
+ },
+ {
+ .event_code = {0x83},
+ .umask = 0x04,
+ .event_name = "icache_64b.iftag_stall",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x01,
+ .event_name = "itlb_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x02,
+ .event_name = "itlb_misses.walk_completed_4k",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x04,
+ .event_name = "itlb_misses.walk_completed_2m_4m",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x08,
+ .event_name = "itlb_misses.walk_completed_1g",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x0E,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_pending",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.walk_active",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x20,
+ .event_name = "itlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x01,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_fe_was_ok",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_3_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_2_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_0_uops_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x04,
+ .event_name = "uops_dispatched_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x08,
+ .event_name = "uops_dispatched_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x10,
+ .event_name = "uops_dispatched_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x20,
+ .event_name = "uops_dispatched_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_6",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_7",
+ },
+ {
+ .event_code = {0xa2},
+ .umask = 0x01,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x08,
+ .event_name = "resource_stalls.sb",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.stalls_total",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x08,
+ .event_name = "cycle_activity.cycles_l1d_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x0C,
+ .event_name = "cycle_activity.stalls_l1d_miss",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x10,
+ .event_name = "cycle_activity.cycles_mem_any",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x14,
+ .event_name = "cycle_activity.stalls_mem_any",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x01,
+ .event_name = "exe_activity.exe_bound_0_ports",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x02,
+ .event_name = "exe_activity.1_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x04,
+ .event_name = "exe_activity.2_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x08,
+ .event_name = "exe_activity.3_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x10,
+ .event_name = "exe_activity.4_ports_util",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x40,
+ .event_name = "exe_activity.bound_on_stores",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_4_uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_active",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x02,
+ .event_name = "dsb2mite_switches.penalty_cycles",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x01,
+ .event_name = "itlb.itlb_flush",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x01,
+ .event_name = "offcore_requests.demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x02,
+ .event_name = "offcore_requests.demand_code_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x04,
+ .event_name = "offcore_requests.demand_rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x08,
+ .event_name = "offcore_requests.all_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x10,
+ .event_name = "offcore_requests.l3_miss_demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x80,
+ .event_name = "offcore_requests.all_requests",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_4_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_3_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_2_uops_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.cycles_ge_1_uop_exec",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_executed.thread",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_none",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_4",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_3",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_2",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_executed.core_cycles_ge_1",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x10,
+ .event_name = "uops_executed.x87",
+ },
+ {
+ .event_code = {0xB2},
+ .umask = 0x01,
+ .event_name = "offcore_requests_buffer.sq_full",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x01,
+ .event_name = "tlb_flush.dtlb_thread",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x20,
+ .event_name = "tlb_flush.stlb_any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.prec_dist",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.total_cycles_ps",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.count",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x01,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x04,
+ .event_name = "br_inst_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x08,
+ .event_name = "br_inst_retired.near_return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x10,
+ .event_name = "br_inst_retired.not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x20,
+ .event_name = "br_inst_retired.near_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x40,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x01,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x02,
+ .event_name = "br_misp_retired.near_call",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x04,
+ .event_name = "br_misp_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x20,
+ .event_name = "br_misp_retired.near_taken",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x01,
+ .event_name = "fp_arith_inst_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x02,
+ .event_name = "fp_arith_inst_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x04,
+ .event_name = "fp_arith_inst_retired.128b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x08,
+ .event_name = "fp_arith_inst_retired.128b_packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "fp_arith_inst_retired.256b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x20,
+ .event_name = "fp_arith_inst_retired.256b_packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x40,
+ .event_name = "fp_arith_inst_retired.512b_packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x80,
+ .event_name = "fp_arith_inst_retired.512b_packed_single",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x01,
+ .event_name = "hle_retired.start",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x02,
+ .event_name = "hle_retired.commit",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x04,
+ .event_name = "hle_retired.aborted",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x08,
+ .event_name = "hle_retired.aborted_mem",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x10,
+ .event_name = "hle_retired.aborted_timer",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x20,
+ .event_name = "hle_retired.aborted_unfriendly",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x40,
+ .event_name = "hle_retired.aborted_memtype",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x80,
+ .event_name = "hle_retired.aborted_events",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x01,
+ .event_name = "rtm_retired.start",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x02,
+ .event_name = "rtm_retired.commit",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x04,
+ .event_name = "rtm_retired.aborted",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x08,
+ .event_name = "rtm_retired.aborted_mem",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x10,
+ .event_name = "rtm_retired.aborted_timer",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x20,
+ .event_name = "rtm_retired.aborted_unfriendly",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x40,
+ .event_name = "rtm_retired.aborted_memtype",
+ },
+ {
+ .event_code = {0xC9},
+ .umask = 0x80,
+ .event_name = "rtm_retired.aborted_events",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1E,
+ .event_name = "fp_assist.any",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x01,
+ .event_name = "hw_interrupts.received",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x20,
+ .event_name = "rob_misc_events.lbr_inserts",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x40,
+ .event_name = "rob_misc_events.pause_inst",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x11,
+ .event_name = "mem_inst_retired.stlb_miss_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x12,
+ .event_name = "mem_inst_retired.stlb_miss_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x21,
+ .event_name = "mem_inst_retired.lock_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x41,
+ .event_name = "mem_inst_retired.split_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x42,
+ .event_name = "mem_inst_retired.split_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x81,
+ .event_name = "mem_inst_retired.all_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x82,
+ .event_name = "mem_inst_retired.all_stores",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x01,
+ .event_name = "mem_load_retired.l1_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x02,
+ .event_name = "mem_load_retired.l2_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x04,
+ .event_name = "mem_load_retired.l3_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x08,
+ .event_name = "mem_load_retired.l1_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x10,
+ .event_name = "mem_load_retired.l2_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x20,
+ .event_name = "mem_load_retired.l3_miss",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x40,
+ .event_name = "mem_load_retired.fb_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x01,
+ .event_name = "mem_load_l3_hit_retired.xsnp_miss",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x02,
+ .event_name = "mem_load_l3_hit_retired.xsnp_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x04,
+ .event_name = "mem_load_l3_hit_retired.xsnp_hitm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x08,
+ .event_name = "mem_load_l3_hit_retired.xsnp_none",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x01,
+ .event_name = "mem_load_l3_miss_retired.local_dram",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x02,
+ .event_name = "mem_load_l3_miss_retired.remote_dram",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x04,
+ .event_name = "mem_load_l3_miss_retired.remote_hitm",
+ },
+ {
+ .event_code = {0xD3},
+ .umask = 0x08,
+ .event_name = "mem_load_l3_miss_retired.remote_fwd",
+ },
+ {
+ .event_code = {0xD4},
+ .umask = 0x04,
+ .event_name = "mem_load_misc_retired.uc",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x01,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x01,
+ .event_name = "core_snoop_response.rsp_ihiti",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x02,
+ .event_name = "core_snoop_response.rsp_ihitfse",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x04,
+ .event_name = "core_snoop_response.rsp_shitfse",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x08,
+ .event_name = "core_snoop_response.rsp_sfwdm",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x10,
+ .event_name = "core_snoop_response.rsp_ifwdm",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x20,
+ .event_name = "core_snoop_response.rsp_ifwdfe",
+ },
+ {
+ .event_code = {0xEF},
+ .umask = 0x40,
+ .event_name = "core_snoop_response.rsp_sfwdfe",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_trans.l2_wb",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x1F,
+ .event_name = "l2_lines_in.all",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x01,
+ .event_name = "l2_lines_out.silent",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x02,
+ .event_name = "l2_lines_out.non_silent",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x04,
+ .event_name = "l2_lines_out.useless_pref",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x04,
+ .event_name = "l2_lines_out.useless_hwpf",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_code = {0xFE},
+ .umask = 0x02,
+ .event_name = "idi_misc.wb_upgrade",
+ },
+ {
+ .event_code = {0xFE},
+ .umask = 0x04,
+ .event_name = "idi_misc.wb_downgrade",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.demand_data_rd.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.demand_rfo.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.demand_code_rd.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.pf_l2_data_rd.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.pf_l2_rfo.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.pf_l3_data_rd.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.pf_l3_rfo.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.pf_l1d_and_sw.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.all_pf_data_rd.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.all_pf_rfo.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.all_data_rd.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_code = {0xB7, 0xBB},
+ .umask = 0x01,
+ .event_name = "offcore_response.all_rfo.l3_hit.snoop_hit_with_fwd",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x37, 0x00, 0},
+ {0x4C, 0x00, 0},
+ {0x4D, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x7E,
+ .event_name = "br_inst_retired.jcc",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0xFE,
+ .event_name = "br_inst_retired.taken_jcc",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0xF9,
+ .event_name = "br_inst_retired.call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0xFD,
+ .event_name = "br_inst_retired.rel_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0xFB,
+ .event_name = "br_inst_retired.ind_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0xF7,
+ .event_name = "br_inst_retired.return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0xEB,
+ .event_name = "br_inst_retired.non_return_ind",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0xBF,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x7E,
+ .event_name = "br_misp_retired.jcc",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0xFE,
+ .event_name = "br_misp_retired.taken_jcc",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0xFB,
+ .event_name = "br_misp_retired.ind_call",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0xF7,
+ .event_name = "br_misp_retired.return",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0xEB,
+ .event_name = "br_misp_retired.non_return_ind",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.ms",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x10,
+ .event_name = "uops_retired.all",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x01,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.fp_assist",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x08,
+ .event_name = "machine_clears.all",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x01,
+ .event_name = "no_alloc_cycles.rob_full",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x04,
+ .event_name = "no_alloc_cycles.mispredicts",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x20,
+ .event_name = "no_alloc_cycles.rat_stall",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x50,
+ .event_name = "no_alloc_cycles.not_delivered",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x3F,
+ .event_name = "no_alloc_cycles.all",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x01,
+ .event_name = "rs_full_stall.mec",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x1F,
+ .event_name = "rs_full_stall.all",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xCD},
+ .umask = 0x01,
+ .event_name = "cycles_div_busy.all",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.core",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.core_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_unhalted.ref",
+ },
+ {
+ .event_code = {0x30},
+ .umask = 0x00,
+ .event_name = "l2_reject_xq.all",
+ },
+ {
+ .event_code = {0x31},
+ .umask = 0x00,
+ .event_name = "core_reject_l2q.all",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x03,
+ .event_name = "icache.accesses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x01,
+ .event_name = "icache.hit",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x02,
+ .event_name = "icache.misses",
+ },
+ {
+ .event_code = {0x86},
+ .umask = 0x02,
+ .event_name = "fetch_stall.itlb_fill_pending_cycles",
+ },
+ {
+ .event_code = {0x86},
+ .umask = 0x04,
+ .event_name = "fetch_stall.icache_fill_pending_cycles",
+ },
+ {
+ .event_code = {0x86},
+ .umask = 0x3F,
+ .event_name = "fetch_stall.all",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x01,
+ .event_name = "baclears.all",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x08,
+ .event_name = "baclears.return",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x10,
+ .event_name = "baclears.cond",
+ },
+ {
+ .event_code = {0xE7},
+ .umask = 0x01,
+ .event_name = "ms_decoded.ms_entry",
+ },
+ {
+ .event_code = {0xE9},
+ .umask = 0x01,
+ .event_name = "decode_restriction.predecode_wrong",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x01,
+ .event_name = "rehabq.ld_block_st_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "rehabq.ld_block_std_notready",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x04,
+ .event_name = "rehabq.st_splits",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "rehabq.ld_splits",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x10,
+ .event_name = "rehabq.lock",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x20,
+ .event_name = "rehabq.sta_full",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x40,
+ .event_name = "rehabq.any_ld",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x80,
+ .event_name = "rehabq.any_st",
+ },
+ {
+ .event_code = {0x04},
+ .umask = 0x01,
+ .event_name = "mem_uops_retired.l1_miss_loads",
+ },
+ {
+ .event_code = {0x04},
+ .umask = 0x02,
+ .event_name = "mem_uops_retired.l2_hit_loads",
+ },
+ {
+ .event_code = {0x04},
+ .umask = 0x04,
+ .event_name = "mem_uops_retired.l2_miss_loads",
+ },
+ {
+ .event_code = {0x04},
+ .umask = 0x08,
+ .event_name = "mem_uops_retired.dtlb_miss_loads",
+ },
+ {
+ .event_code = {0x04},
+ .umask = 0x10,
+ .event_name = "mem_uops_retired.utlb_miss",
+ },
+ {
+ .event_code = {0x04},
+ .umask = 0x20,
+ .event_name = "mem_uops_retired.hitm",
+ },
+ {
+ .event_code = {0x04},
+ .umask = 0x40,
+ .event_name = "mem_uops_retired.all_loads",
+ },
+ {
+ .event_code = {0x04},
+ .umask = 0x80,
+ .event_name = "mem_uops_retired.all_stores",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x01,
+ .event_name = "page_walks.d_side_walks",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x01,
+ .event_name = "page_walks.d_side_cycles",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x02,
+ .event_name = "page_walks.i_side_walks",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x02,
+ .event_name = "page_walks.i_side_cycles",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x03,
+ .event_name = "page_walks.walks",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x03,
+ .event_name = "page_walks.cycles",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x80,
+ .event_name = "br_inst_retired.all_taken_branches",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x2A, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x00},
+ .umask = 0x03,
+ .event_name = "cpu_clk_unhalted.ref_tsc",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x01,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x00},
+ .umask = 0x02,
+ .event_name = "cpu_clk_unhalted.thread_any",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x01,
+ .event_name = "ld_blocks.data_unknown",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x02,
+ .event_name = "ld_blocks.store_forward",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x08,
+ .event_name = "ld_blocks.no_sr",
+ },
+ {
+ .event_code = {0x03},
+ .umask = 0x10,
+ .event_name = "ld_blocks.all_block",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x01,
+ .event_name = "misalign_mem_ref.loads",
+ },
+ {
+ .event_code = {0x05},
+ .umask = 0x02,
+ .event_name = "misalign_mem_ref.stores",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x01,
+ .event_name = "ld_blocks_partial.address_alias",
+ },
+ {
+ .event_code = {0x07},
+ .umask = 0x08,
+ .event_name = "ld_blocks_partial.all_sta_block",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x01,
+ .event_name = "dtlb_load_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x02,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x04,
+ .event_name = "dtlb_load_misses.walk_duration",
+ },
+ {
+ .event_code = {0x08},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_stalls_count",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x03,
+ .event_name = "int_misc.recovery_cycles_any",
+ },
+ {
+ .event_code = {0x0D},
+ .umask = 0x40,
+ .event_name = "int_misc.rat_stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0x0E},
+ .umask = 0x01,
+ .event_name = "uops_issued.core_stall_cycles",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x01,
+ .event_name = "fp_comp_ops_exe.x87",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x10,
+ .event_name = "fp_comp_ops_exe.sse_packed_double",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x20,
+ .event_name = "fp_comp_ops_exe.sse_scalar_single",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x40,
+ .event_name = "fp_comp_ops_exe.sse_packed_single",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x80,
+ .event_name = "fp_comp_ops_exe.sse_scalar_double",
+ },
+ {
+ .event_code = {0x11},
+ .umask = 0x01,
+ .event_name = "simd_fp_256.packed_single",
+ },
+ {
+ .event_code = {0x11},
+ .umask = 0x02,
+ .event_name = "simd_fp_256.packed_double",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x01,
+ .event_name = "arith.fpu_div_active",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x01,
+ .event_name = "arith.fpu_div",
+ },
+ {
+ .event_code = {0x17},
+ .umask = 0x01,
+ .event_name = "insts_written_to_iq.insts",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x01,
+ .event_name = "l2_rqsts.demand_data_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x03,
+ .event_name = "l2_rqsts.all_demand_data_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x04,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x08,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x0C,
+ .event_name = "l2_rqsts.all_rfo",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x10,
+ .event_name = "l2_rqsts.code_rd_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x20,
+ .event_name = "l2_rqsts.code_rd_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.all_code_rd",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x40,
+ .event_name = "l2_rqsts.pf_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x80,
+ .event_name = "l2_rqsts.pf_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC0,
+ .event_name = "l2_rqsts.all_pf",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x01,
+ .event_name = "l2_store_lock_rqsts.miss",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x04,
+ .event_name = "l2_store_lock_rqsts.hit_e",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x08,
+ .event_name = "l2_store_lock_rqsts.hit_m",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x0F,
+ .event_name = "l2_store_lock_rqsts.all",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x01,
+ .event_name = "l2_l1d_wb_rqsts.miss",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x02,
+ .event_name = "l2_l1d_wb_rqsts.hit_s",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x04,
+ .event_name = "l2_l1d_wb_rqsts.hit_e",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x08,
+ .event_name = "l2_l1d_wb_rqsts.hit_m",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x0F,
+ .event_name = "l2_l1d_wb_rqsts.all",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x00,
+ .event_name = "cpu_clk_unhalted.thread_p_any",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x01,
+ .event_name = "cpu_clk_thread_unhalted.ref_xclk",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x02,
+ .event_name = "cpu_clk_thread_unhalted.one_thread_active",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending",
+ },
+ {
+ .event_code = {0x48},
+ .umask = 0x01,
+ .event_name = "l1d_pend_miss.pending_cycles",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x01,
+ .event_name = "dtlb_store_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x02,
+ .event_name = "dtlb_store_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x04,
+ .event_name = "dtlb_store_misses.walk_duration",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_store_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x01,
+ .event_name = "load_hit_pre.sw_pf",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x02,
+ .event_name = "load_hit_pre.hw_pf",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x02,
+ .event_name = "hw_pre_req.dl1_miss",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_cycles",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x01,
+ .event_name = "l1d.replacement",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x02,
+ .event_name = "l1d.allocated_in_m",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x04,
+ .event_name = "l1d.eviction",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x08,
+ .event_name = "l1d.all_m_replacement",
+ },
+ {
+ .event_code = {0x59},
+ .umask = 0x20,
+ .event_name = "partial_rat_stalls.flags_merge_uop",
+ },
+ {
+ .event_code = {0x59},
+ .umask = 0x20,
+ .event_name = "partial_rat_stalls.flags_merge_uop_cycles",
+ },
+ {
+ .event_code = {0x59},
+ .umask = 0x40,
+ .event_name = "partial_rat_stalls.slow_lea_window",
+ },
+ {
+ .event_code = {0x59},
+ .umask = 0x80,
+ .event_name = "partial_rat_stalls.mul_single_uop",
+ },
+ {
+ .event_code = {0x5B},
+ .umask = 0x0C,
+ .event_name = "resource_stalls2.all_fl_empty",
+ },
+ {
+ .event_code = {0x5B},
+ .umask = 0x0F,
+ .event_name = "resource_stalls2.all_prf_control",
+ },
+ {
+ .event_code = {0x5B},
+ .umask = 0x40,
+ .event_name = "resource_stalls2.bob_full",
+ },
+ {
+ .event_code = {0x5B},
+ .umask = 0x4F,
+ .event_name = "resource_stalls2.ooo_rsrc",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x01,
+ .event_name = "cpl_cycles.ring0_trans",
+ },
+ {
+ .event_code = {0x5C},
+ .umask = 0x02,
+ .event_name = "cpl_cycles.ring123",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_cycles",
+ },
+ {
+ .event_code = {0x5E},
+ .umask = 0x01,
+ .event_name = "rs_events.empty_end",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x01,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x04,
+ .event_name = "offcore_requests_outstanding.cycles_with_demand_rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.all_data_rd",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x08,
+ .event_name = "offcore_requests_outstanding.cycles_with_data_rd",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x01,
+ .event_name = "lock_cycles.split_lock_uc_lock_duration",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x02,
+ .event_name = "lock_cycles.cache_lock_duration",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x02,
+ .event_name = "idq.empty",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x04,
+ .event_name = "idq.mite_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x08,
+ .event_name = "idq.dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x10,
+ .event_name = "idq.ms_dsb_occur",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x18,
+ .event_name = "idq.all_dsb_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x20,
+ .event_name = "idq.ms_mite_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_4_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x24,
+ .event_name = "idq.all_mite_cycles_any_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_uops",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_cycles",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x30,
+ .event_name = "idq.ms_switches",
+ },
+ {
+ .event_code = {0x79},
+ .umask = 0x3c,
+ .event_name = "idq.mite_all_uops",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x01,
+ .event_name = "icache.hit",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x02,
+ .event_name = "icache.misses",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x01,
+ .event_name = "itlb_misses.miss_causes_a_walk",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x02,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x04,
+ .event_name = "itlb_misses.walk_duration",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x10,
+ .event_name = "itlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x01,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x04,
+ .event_name = "ild_stall.iq_full",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x41,
+ .event_name = "br_inst_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x81,
+ .event_name = "br_inst_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x82,
+ .event_name = "br_inst_exec.taken_direct_jump",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x84,
+ .event_name = "br_inst_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x88,
+ .event_name = "br_inst_exec.taken_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x90,
+ .event_name = "br_inst_exec.taken_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xA0,
+ .event_name = "br_inst_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC1,
+ .event_name = "br_inst_exec.all_conditional",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC2,
+ .event_name = "br_inst_exec.all_direct_jmp",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC4,
+ .event_name = "br_inst_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xC8,
+ .event_name = "br_inst_exec.all_indirect_near_return",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xD0,
+ .event_name = "br_inst_exec.all_direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0xFF,
+ .event_name = "br_inst_exec.all_branches",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x41,
+ .event_name = "br_misp_exec.nontaken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x81,
+ .event_name = "br_misp_exec.taken_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x84,
+ .event_name = "br_misp_exec.taken_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x88,
+ .event_name = "br_misp_exec.taken_return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x90,
+ .event_name = "br_misp_exec.taken_direct_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xA0,
+ .event_name = "br_misp_exec.taken_indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC1,
+ .event_name = "br_misp_exec.all_conditional",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xC4,
+ .event_name = "br_misp_exec.all_indirect_jump_non_call_ret",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xD0,
+ .event_name = "br_misp_exec.all_direct_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0xFF,
+ .event_name = "br_misp_exec.all_branches",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_0_uops_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_2_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_le_3_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_ge_1_uop_deliv.core",
+ },
+ {
+ .event_code = {0x9C},
+ .umask = 0x01,
+ .event_name = "idq_uops_not_delivered.cycles_fe_was_ok",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched_port.port_0_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched_port.port_1_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x0C,
+ .event_name = "uops_dispatched_port.port_2",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x0C,
+ .event_name = "uops_dispatched_port.port_2_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x30,
+ .event_name = "uops_dispatched_port.port_3",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x30,
+ .event_name = "uops_dispatched_port.port_3_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_4",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x40,
+ .event_name = "uops_dispatched_port.port_4_core",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_5",
+ },
+ {
+ .event_code = {0xA1},
+ .umask = 0x80,
+ .event_name = "uops_dispatched_port.port_5_core",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x01,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x02,
+ .event_name = "resource_stalls.lb",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x04,
+ .event_name = "resource_stalls.rs",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x08,
+ .event_name = "resource_stalls.sb",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x0A,
+ .event_name = "resource_stalls.lb_sb",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x0E,
+ .event_name = "resource_stalls.mem_rs",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0xF0,
+ .event_name = "resource_stalls.ooo_rsrc",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x01,
+ .event_name = "cycle_activity.cycles_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x02,
+ .event_name = "cycle_activity.cycles_l1d_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x04,
+ .event_name = "cycle_activity.cycles_no_dispatch",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x05,
+ .event_name = "cycle_activity.stalls_l2_pending",
+ },
+ {
+ .event_code = {0xA3},
+ .umask = 0x06,
+ .event_name = "cycle_activity.stalls_l1d_pending",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.uops",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_active",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x01,
+ .event_name = "lsd.cycles_4_uops",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x01,
+ .event_name = "dsb2mite_switches.count",
+ },
+ {
+ .event_code = {0xAB},
+ .umask = 0x02,
+ .event_name = "dsb2mite_switches.penalty_cycles",
+ },
+ {
+ .event_code = {0xAC},
+ .umask = 0x02,
+ .event_name = "dsb_fill.other_cancel",
+ },
+ {
+ .event_code = {0xAC},
+ .umask = 0x08,
+ .event_name = "dsb_fill.exceed_dsb_lines",
+ },
+ {
+ .event_code = {0xAC},
+ .umask = 0x0A,
+ .event_name = "dsb_fill.all_cancel",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x01,
+ .event_name = "itlb.itlb_flush",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x01,
+ .event_name = "offcore_requests.demand_data_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x02,
+ .event_name = "offcore_requests.demand_code_rd",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x04,
+ .event_name = "offcore_requests.demand_rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x08,
+ .event_name = "offcore_requests.all_data_rd",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x01,
+ .event_name = "uops_dispatched.thread",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x02,
+ .event_name = "uops_dispatched.core",
+ },
+ {
+ .event_code = {0xB2},
+ .umask = 0x01,
+ .event_name = "offcore_requests_buffer.sq_full",
+ },
+ {
+ .event_code = {0xB6},
+ .umask = 0x01,
+ .event_name = "agu_bypass_cancel.count",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x01,
+ .event_name = "tlb_flush.dtlb_thread",
+ },
+ {
+ .event_code = {0xBD},
+ .umask = 0x20,
+ .event_name = "tlb_flush.stlb_any",
+ },
+ {
+ .event_code = {0xBE},
+ .umask = 0x01,
+ .event_name = "page_walks.llc_miss",
+ },
+ {
+ .event_code = {0xBF},
+ .umask = 0x05,
+ .event_name = "l1d_blocks.bank_conflict_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x00,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x01,
+ .event_name = "inst_retired.prec_dist",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x02,
+ .event_name = "other_assists.itlb_miss_retired",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x08,
+ .event_name = "other_assists.avx_store",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x10,
+ .event_name = "other_assists.avx_to_sse",
+ },
+ {
+ .event_code = {0xC1},
+ .umask = 0x20,
+ .event_name = "other_assists.sse_to_avx",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.all",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x01,
+ .event_name = "uops_retired.core_stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x02,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xc3},
+ .umask = 0x01,
+ .event_name = "machine_clears.count",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x02,
+ .event_name = "machine_clears.memory_ordering",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x04,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x20,
+ .event_name = "machine_clears.maskmov",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x00,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x01,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x02,
+ .event_name = "br_inst_retired.near_call_r3",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x04,
+ .event_name = "br_inst_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x08,
+ .event_name = "br_inst_retired.near_return",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x10,
+ .event_name = "br_inst_retired.not_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x20,
+ .event_name = "br_inst_retired.near_taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x40,
+ .event_name = "br_inst_retired.far_branch",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x00,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x01,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x02,
+ .event_name = "br_misp_retired.near_call",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x04,
+ .event_name = "br_misp_retired.all_branches_pebs",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x10,
+ .event_name = "br_misp_retired.not_taken",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x20,
+ .event_name = "br_misp_retired.taken",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x02,
+ .event_name = "fp_assist.x87_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x04,
+ .event_name = "fp_assist.x87_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x08,
+ .event_name = "fp_assist.simd_output",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x10,
+ .event_name = "fp_assist.simd_input",
+ },
+ {
+ .event_code = {0xCA},
+ .umask = 0x1E,
+ .event_name = "fp_assist.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x20,
+ .event_name = "rob_misc_events.lbr_inserts",
+ },
+ {
+ .event_code = {0xCD},
+ .umask = 0x02,
+ .event_name = "mem_trans_retired.precise_store",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x11,
+ .event_name = "mem_uops_retired.stlb_miss_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x12,
+ .event_name = "mem_uops_retired.stlb_miss_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x21,
+ .event_name = "mem_uops_retired.lock_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x41,
+ .event_name = "mem_uops_retired.split_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x42,
+ .event_name = "mem_uops_retired.split_stores",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x81,
+ .event_name = "mem_uops_retired.all_loads",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x82,
+ .event_name = "mem_uops_retired.all_stores",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_retired.l1_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_retired.l2_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_retired.llc_hit",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x40,
+ .event_name = "mem_load_uops_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x01,
+ .event_name = "mem_load_uops_llc_hit_retired.xsnp_miss",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_llc_hit_retired.xsnp_hit",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x04,
+ .event_name = "mem_load_uops_llc_hit_retired.xsnp_hitm",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x08,
+ .event_name = "mem_load_uops_llc_hit_retired.xsnp_none",
+ },
+ {
+ .event_code = {0xD4},
+ .umask = 0x02,
+ .event_name = "mem_load_uops_misc_retired.llc_miss",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x1F,
+ .event_name = "baclears.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x01,
+ .event_name = "l2_trans.demand_data_rd",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x02,
+ .event_name = "l2_trans.rfo",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x04,
+ .event_name = "l2_trans.code_rd",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x08,
+ .event_name = "l2_trans.all_pf",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x10,
+ .event_name = "l2_trans.l1d_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x20,
+ .event_name = "l2_trans.l2_fill",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_trans.l2_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x80,
+ .event_name = "l2_trans.all_requests",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x01,
+ .event_name = "l2_lines_in.i",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x02,
+ .event_name = "l2_lines_in.s",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x04,
+ .event_name = "l2_lines_in.e",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x07,
+ .event_name = "l2_lines_in.all",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x01,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x02,
+ .event_name = "l2_lines_out.demand_dirty",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x04,
+ .event_name = "l2_lines_out.pf_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x08,
+ .event_name = "l2_lines_out.pf_dirty",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x0A,
+ .event_name = "l2_lines_out.dirty_all",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x2C, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "arith.cycles_div_busy",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "arith.div",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x2,
+ .event_name = "arith.mul",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x2,
+ .event_name = "baclear.bad_target",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x1,
+ .event_name = "baclear.clear",
+ },
+ {
+ .event_code = {0xA7},
+ .umask = 0x1,
+ .event_name = "baclear_force_iq",
+ },
+ {
+ .event_code = {0xE8},
+ .umask = 0x1,
+ .event_name = "bpu_clears.early",
+ },
+ {
+ .event_code = {0xE8},
+ .umask = 0x2,
+ .event_name = "bpu_clears.late",
+ },
+ {
+ .event_code = {0xE5},
+ .umask = 0x1,
+ .event_name = "bpu_missed_call_ret",
+ },
+ {
+ .event_code = {0xE0},
+ .umask = 0x1,
+ .event_name = "br_inst_decoded",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x7F,
+ .event_name = "br_inst_exec.any",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x1,
+ .event_name = "br_inst_exec.cond",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x2,
+ .event_name = "br_inst_exec.direct",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x10,
+ .event_name = "br_inst_exec.direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x20,
+ .event_name = "br_inst_exec.indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x4,
+ .event_name = "br_inst_exec.indirect_non_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x30,
+ .event_name = "br_inst_exec.near_calls",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x7,
+ .event_name = "br_inst_exec.non_calls",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x8,
+ .event_name = "br_inst_exec.return_near",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x40,
+ .event_name = "br_inst_exec.taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x4,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x1,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x2,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x7F,
+ .event_name = "br_misp_exec.any",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x1,
+ .event_name = "br_misp_exec.cond",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x2,
+ .event_name = "br_misp_exec.direct",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x10,
+ .event_name = "br_misp_exec.direct_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x20,
+ .event_name = "br_misp_exec.indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x4,
+ .event_name = "br_misp_exec.indirect_non_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x30,
+ .event_name = "br_misp_exec.near_calls",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x7,
+ .event_name = "br_misp_exec.non_calls",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x8,
+ .event_name = "br_misp_exec.return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x40,
+ .event_name = "br_misp_exec.taken",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x4,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x1,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x2,
+ .event_name = "br_misp_retired.near_call",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x2,
+ .event_name = "cache_lock_cycles.l1d",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x1,
+ .event_name = "cache_lock_cycles.l1d_l2",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.ref",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x1,
+ .event_name = "cpu_clk_unhalted.ref_p",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.total_cycles",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x1,
+ .event_name = "dtlb_load_misses.any",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x80,
+ .event_name = "dtlb_load_misses.large_walk_completed",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.pde_miss",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x2,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x4,
+ .event_name = "dtlb_load_misses.walk_cycles",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x1,
+ .event_name = "dtlb_misses.any",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x80,
+ .event_name = "dtlb_misses.large_walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x20,
+ .event_name = "dtlb_misses.pde_miss",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x2,
+ .event_name = "dtlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x4,
+ .event_name = "dtlb_misses.walk_cycles",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_cycles",
+ },
+ {
+ .event_code = {0xD5},
+ .umask = 0x1,
+ .event_name = "es_reg_renames",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x1,
+ .event_name = "fp_assist.all",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x4,
+ .event_name = "fp_assist.input",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x2,
+ .event_name = "fp_assist.output",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x2,
+ .event_name = "fp_comp_ops_exe.mmx",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x80,
+ .event_name = "fp_comp_ops_exe.sse_double_precision",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x4,
+ .event_name = "fp_comp_ops_exe.sse_fp",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x10,
+ .event_name = "fp_comp_ops_exe.sse_fp_packed",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x20,
+ .event_name = "fp_comp_ops_exe.sse_fp_scalar",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x40,
+ .event_name = "fp_comp_ops_exe.sse_single_precision",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x8,
+ .event_name = "fp_comp_ops_exe.sse2_integer",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x1,
+ .event_name = "fp_comp_ops_exe.x87",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x3,
+ .event_name = "fp_mmx_trans.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x1,
+ .event_name = "fp_mmx_trans.to_fp",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x2,
+ .event_name = "fp_mmx_trans.to_mmx",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0xF,
+ .event_name = "ild_stall.any",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x4,
+ .event_name = "ild_stall.iq_full",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x1,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x2,
+ .event_name = "ild_stall.mru",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x8,
+ .event_name = "ild_stall.regen",
+ },
+ {
+ .event_code = {0x18},
+ .umask = 0x1,
+ .event_name = "inst_decoded.dec0",
+ },
+ {
+ .event_code = {0x1E},
+ .umask = 0x1,
+ .event_name = "inst_queue_write_cycles",
+ },
+ {
+ .event_code = {0x17},
+ .umask = 0x1,
+ .event_name = "inst_queue_writes",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x4,
+ .event_name = "inst_retired.mmx",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x2,
+ .event_name = "inst_retired.x87",
+ },
+ {
+ .event_code = {0x6C},
+ .umask = 0x1,
+ .event_name = "io_transactions",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x1,
+ .event_name = "itlb_flush",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x20,
+ .event_name = "itlb_miss_retired",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x1,
+ .event_name = "itlb_misses.any",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x80,
+ .event_name = "itlb_misses.large_walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x2,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x4,
+ .event_name = "itlb_misses.walk_cycles",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x4,
+ .event_name = "l1d.m_evict",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x2,
+ .event_name = "l1d.m_repl",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x8,
+ .event_name = "l1d.m_snoop_evict",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x1,
+ .event_name = "l1d.repl",
+ },
+ {
+ .event_code = {0x52},
+ .umask = 0x1,
+ .event_name = "l1d_cache_prefetch_lock_fb_hit",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x2,
+ .event_name = "l1d_prefetch.miss",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x1,
+ .event_name = "l1d_prefetch.requests",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x4,
+ .event_name = "l1d_prefetch.triggers",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x4,
+ .event_name = "l1d_wb_l2.e_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x1,
+ .event_name = "l1d_wb_l2.i_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x8,
+ .event_name = "l1d_wb_l2.m_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0xF,
+ .event_name = "l1d_wb_l2.mesi",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x2,
+ .event_name = "l1d_wb_l2.s_state",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x4,
+ .event_name = "l1i.cycles_stalled",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x1,
+ .event_name = "l1i.hits",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x2,
+ .event_name = "l1i.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x3,
+ .event_name = "l1i.reads",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xFF,
+ .event_name = "l2_data_rqsts.any",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x4,
+ .event_name = "l2_data_rqsts.demand.e_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x1,
+ .event_name = "l2_data_rqsts.demand.i_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x8,
+ .event_name = "l2_data_rqsts.demand.m_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xF,
+ .event_name = "l2_data_rqsts.demand.mesi",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x2,
+ .event_name = "l2_data_rqsts.demand.s_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x40,
+ .event_name = "l2_data_rqsts.prefetch.e_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x10,
+ .event_name = "l2_data_rqsts.prefetch.i_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x80,
+ .event_name = "l2_data_rqsts.prefetch.m_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xF0,
+ .event_name = "l2_data_rqsts.prefetch.mesi",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x20,
+ .event_name = "l2_data_rqsts.prefetch.s_state",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x7,
+ .event_name = "l2_lines_in.any",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x4,
+ .event_name = "l2_lines_in.e_state",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x2,
+ .event_name = "l2_lines_in.s_state",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0xF,
+ .event_name = "l2_lines_out.any",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x1,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x2,
+ .event_name = "l2_lines_out.demand_dirty",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x4,
+ .event_name = "l2_lines_out.prefetch_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x8,
+ .event_name = "l2_lines_out.prefetch_dirty",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x10,
+ .event_name = "l2_rqsts.ifetch_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x20,
+ .event_name = "l2_rqsts.ifetch_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.ifetches",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x1,
+ .event_name = "l2_rqsts.ld_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x2,
+ .event_name = "l2_rqsts.ld_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3,
+ .event_name = "l2_rqsts.loads",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xAA,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x40,
+ .event_name = "l2_rqsts.prefetch_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x80,
+ .event_name = "l2_rqsts.prefetch_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC0,
+ .event_name = "l2_rqsts.prefetches",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x4,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x8,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC,
+ .event_name = "l2_rqsts.rfos",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x80,
+ .event_name = "l2_transactions.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x20,
+ .event_name = "l2_transactions.fill",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x4,
+ .event_name = "l2_transactions.ifetch",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x10,
+ .event_name = "l2_transactions.l1d_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x1,
+ .event_name = "l2_transactions.load",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x8,
+ .event_name = "l2_transactions.prefetch",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x2,
+ .event_name = "l2_transactions.rfo",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_transactions.wb",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x40,
+ .event_name = "l2_write.lock.e_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xE0,
+ .event_name = "l2_write.lock.hit",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x10,
+ .event_name = "l2_write.lock.i_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x80,
+ .event_name = "l2_write.lock.m_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xF0,
+ .event_name = "l2_write.lock.mesi",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x20,
+ .event_name = "l2_write.lock.s_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xE,
+ .event_name = "l2_write.rfo.hit",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x1,
+ .event_name = "l2_write.rfo.i_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x8,
+ .event_name = "l2_write.rfo.m_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xF,
+ .event_name = "l2_write.rfo.mesi",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x2,
+ .event_name = "l2_write.rfo.s_state",
+ },
+ {
+ .event_code = {0x82},
+ .umask = 0x1,
+ .event_name = "large_itlb.hit",
+ },
+ {
+ .event_code = {0x3},
+ .umask = 0x2,
+ .event_name = "load_block.overlap_store",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x7,
+ .event_name = "load_dispatch.any",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x4,
+ .event_name = "load_dispatch.mob",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x1,
+ .event_name = "load_dispatch.rs",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x2,
+ .event_name = "load_dispatch.rs_delayed",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x1,
+ .event_name = "load_hit_pre",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x1,
+ .event_name = "lsd.active",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x1,
+ .event_name = "lsd.inactive",
+ },
+ {
+ .event_code = {0x20},
+ .umask = 0x1,
+ .event_name = "lsd_overflow",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x1,
+ .event_name = "machine_clears.cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x2,
+ .event_name = "machine_clears.mem_order",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x4,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x1,
+ .event_name = "macro_insts.decoded",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x1,
+ .event_name = "macro_insts.fusions_decoded",
+ },
+ {
+ .event_code = {0xB},
+ .umask = 0x1,
+ .event_name = "mem_inst_retired.loads",
+ },
+ {
+ .event_code = {0xB},
+ .umask = 0x2,
+ .event_name = "mem_inst_retired.stores",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x80,
+ .event_name = "mem_load_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x40,
+ .event_name = "mem_load_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x1,
+ .event_name = "mem_load_retired.l1d_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x2,
+ .event_name = "mem_load_retired.l2_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x10,
+ .event_name = "mem_load_retired.llc_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x4,
+ .event_name = "mem_load_retired.llc_unshared_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x8,
+ .event_name = "mem_load_retired.other_core_l2_hit_hitm",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x1,
+ .event_name = "mem_store_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x2,
+ .event_name = "misalign_mem_ref.store",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x80,
+ .event_name = "offcore_requests.any",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x8,
+ .event_name = "offcore_requests.any.read",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x10,
+ .event_name = "offcore_requests.any.rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x2,
+ .event_name = "offcore_requests.demand.read_code",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x1,
+ .event_name = "offcore_requests.demand.read_data",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x4,
+ .event_name = "offcore_requests.demand.rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x40,
+ .event_name = "offcore_requests.l1d_writeback",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x8,
+ .event_name = "offcore_requests_outstanding.any.read",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x8,
+ .event_name = "offcore_requests_outstanding.any.read_not_empty",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x2,
+ .event_name = "offcore_requests_outstanding.demand.read_code",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x2,
+ .event_name = "offcore_requests_outstanding.demand.read_code_not_empty",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x1,
+ .event_name = "offcore_requests_outstanding.demand.read_data",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x1,
+ .event_name = "offcore_requests_outstanding.demand.read_data_not_empty",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x4,
+ .event_name = "offcore_requests_outstanding.demand.rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x4,
+ .event_name = "offcore_requests_outstanding.demand.rfo_not_empty",
+ },
+ {
+ .event_code = {0xB2},
+ .umask = 0x1,
+ .event_name = "offcore_requests_sq_full",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x1,
+ .event_name = "partial_address_alias",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0xF,
+ .event_name = "rat_stalls.any",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x1,
+ .event_name = "rat_stalls.flags",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x2,
+ .event_name = "rat_stalls.registers",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x4,
+ .event_name = "rat_stalls.rob_read_port",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x8,
+ .event_name = "rat_stalls.scoreboard",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x1,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x20,
+ .event_name = "resource_stalls.fpcw",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x2,
+ .event_name = "resource_stalls.load",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x40,
+ .event_name = "resource_stalls.mxcsr",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x80,
+ .event_name = "resource_stalls.other",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob_full",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x4,
+ .event_name = "resource_stalls.rs_full",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x8,
+ .event_name = "resource_stalls.store",
+ },
+ {
+ .event_code = {0x4},
+ .umask = 0x7,
+ .event_name = "sb_drain.any",
+ },
+ {
+ .event_code = {0xD4},
+ .umask = 0x1,
+ .event_name = "seg_rename_stalls",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x4,
+ .event_name = "simd_int_128.pack",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x20,
+ .event_name = "simd_int_128.packed_arith",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x10,
+ .event_name = "simd_int_128.packed_logical",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x1,
+ .event_name = "simd_int_128.packed_mpy",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x2,
+ .event_name = "simd_int_128.packed_shift",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x40,
+ .event_name = "simd_int_128.shuffle_move",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x8,
+ .event_name = "simd_int_128.unpack",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x4,
+ .event_name = "simd_int_64.pack",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x20,
+ .event_name = "simd_int_64.packed_arith",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x10,
+ .event_name = "simd_int_64.packed_logical",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x1,
+ .event_name = "simd_int_64.packed_mpy",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x2,
+ .event_name = "simd_int_64.packed_shift",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x40,
+ .event_name = "simd_int_64.shuffle_move",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x8,
+ .event_name = "simd_int_64.unpack",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x1,
+ .event_name = "snoop_response.hit",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x2,
+ .event_name = "snoop_response.hite",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x4,
+ .event_name = "snoop_response.hitm",
+ },
+ {
+ .event_code = {0xB4},
+ .umask = 0x4,
+ .event_name = "snoopq_requests.code",
+ },
+ {
+ .event_code = {0xB4},
+ .umask = 0x1,
+ .event_name = "snoopq_requests.data",
+ },
+ {
+ .event_code = {0xB4},
+ .umask = 0x2,
+ .event_name = "snoopq_requests.invalidate",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x4,
+ .event_name = "snoopq_requests_outstanding.code",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x4,
+ .event_name = "snoopq_requests_outstanding.code_not_empty",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x1,
+ .event_name = "snoopq_requests_outstanding.data",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x1,
+ .event_name = "snoopq_requests_outstanding.data_not_empty",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x2,
+ .event_name = "snoopq_requests_outstanding.invalidate",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x2,
+ .event_name = "snoopq_requests_outstanding.invalidate_not_empty",
+ },
+ {
+ .event_code = {0xF6},
+ .umask = 0x1,
+ .event_name = "sq_full_stall_cycles",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x4,
+ .event_name = "sq_misc.lru_hints",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x4,
+ .event_name = "ssex_uops_retired.packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x1,
+ .event_name = "ssex_uops_retired.packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x8,
+ .event_name = "ssex_uops_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x2,
+ .event_name = "ssex_uops_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "ssex_uops_retired.vector_integer",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x4,
+ .event_name = "store_blocks.at_ret",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x8,
+ .event_name = "store_blocks.l1d_block",
+ },
+ {
+ .event_code = {0x19},
+ .umask = 0x1,
+ .event_name = "two_uop_insts_decoded",
+ },
+ {
+ .event_code = {0xDB},
+ .umask = 0x1,
+ .event_name = "uop_unfusion",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x4,
+ .event_name = "uops_decoded.esp_folding",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x8,
+ .event_name = "uops_decoded.esp_sync",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x2,
+ .event_name = "uops_decoded.ms_cycles_active",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x1,
+ .event_name = "uops_decoded.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_active_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_active_cycles_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_stall_count",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_stall_count_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_stall_cycles_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1,
+ .event_name = "uops_executed.port0",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x40,
+ .event_name = "uops_executed.port015",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x40,
+ .event_name = "uops_executed.port015_stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x2,
+ .event_name = "uops_executed.port1",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x4,
+ .event_name = "uops_executed.port2_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x80,
+ .event_name = "uops_executed.port234_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x8,
+ .event_name = "uops_executed.port3_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x10,
+ .event_name = "uops_executed.port4_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x20,
+ .event_name = "uops_executed.port5",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.core_stall_cycles",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.cycles_all_threads",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x2,
+ .event_name = "uops_issued.fused",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.active_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.any",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x4,
+ .event_name = "uops_retired.macro_fused",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x2,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.total_cycles_ps",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x25, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "arith.cycles_div_busy",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "arith.div",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x2,
+ .event_name = "arith.mul",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x2,
+ .event_name = "baclear.bad_target",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x1,
+ .event_name = "baclear.clear",
+ },
+ {
+ .event_code = {0xA7},
+ .umask = 0x1,
+ .event_name = "baclear_force_iq",
+ },
+ {
+ .event_code = {0xE8},
+ .umask = 0x1,
+ .event_name = "bpu_clears.early",
+ },
+ {
+ .event_code = {0xE8},
+ .umask = 0x2,
+ .event_name = "bpu_clears.late",
+ },
+ {
+ .event_code = {0xE5},
+ .umask = 0x1,
+ .event_name = "bpu_missed_call_ret",
+ },
+ {
+ .event_code = {0xE0},
+ .umask = 0x1,
+ .event_name = "br_inst_decoded",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x7F,
+ .event_name = "br_inst_exec.any",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x1,
+ .event_name = "br_inst_exec.cond",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x2,
+ .event_name = "br_inst_exec.direct",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x10,
+ .event_name = "br_inst_exec.direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x20,
+ .event_name = "br_inst_exec.indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x4,
+ .event_name = "br_inst_exec.indirect_non_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x30,
+ .event_name = "br_inst_exec.near_calls",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x7,
+ .event_name = "br_inst_exec.non_calls",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x8,
+ .event_name = "br_inst_exec.return_near",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x40,
+ .event_name = "br_inst_exec.taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x4,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x1,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x2,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x7F,
+ .event_name = "br_misp_exec.any",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x1,
+ .event_name = "br_misp_exec.cond",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x2,
+ .event_name = "br_misp_exec.direct",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x10,
+ .event_name = "br_misp_exec.direct_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x20,
+ .event_name = "br_misp_exec.indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x4,
+ .event_name = "br_misp_exec.indirect_non_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x30,
+ .event_name = "br_misp_exec.near_calls",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x7,
+ .event_name = "br_misp_exec.non_calls",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x8,
+ .event_name = "br_misp_exec.return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x40,
+ .event_name = "br_misp_exec.taken",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x4,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x1,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x2,
+ .event_name = "br_misp_retired.near_call",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x2,
+ .event_name = "cache_lock_cycles.l1d",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x1,
+ .event_name = "cache_lock_cycles.l1d_l2",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.ref",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x1,
+ .event_name = "cpu_clk_unhalted.ref_p",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.total_cycles",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x1,
+ .event_name = "dtlb_load_misses.any",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.pde_miss",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x2,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x4,
+ .event_name = "dtlb_load_misses.walk_cycles",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x1,
+ .event_name = "dtlb_misses.any",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x80,
+ .event_name = "dtlb_misses.large_walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x2,
+ .event_name = "dtlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x4,
+ .event_name = "dtlb_misses.walk_cycles",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_cycles",
+ },
+ {
+ .event_code = {0xD5},
+ .umask = 0x1,
+ .event_name = "es_reg_renames",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x1,
+ .event_name = "fp_assist.all",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x4,
+ .event_name = "fp_assist.input",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x2,
+ .event_name = "fp_assist.output",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x2,
+ .event_name = "fp_comp_ops_exe.mmx",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x80,
+ .event_name = "fp_comp_ops_exe.sse_double_precision",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x4,
+ .event_name = "fp_comp_ops_exe.sse_fp",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x10,
+ .event_name = "fp_comp_ops_exe.sse_fp_packed",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x20,
+ .event_name = "fp_comp_ops_exe.sse_fp_scalar",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x40,
+ .event_name = "fp_comp_ops_exe.sse_single_precision",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x8,
+ .event_name = "fp_comp_ops_exe.sse2_integer",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x1,
+ .event_name = "fp_comp_ops_exe.x87",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x3,
+ .event_name = "fp_mmx_trans.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x1,
+ .event_name = "fp_mmx_trans.to_fp",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x2,
+ .event_name = "fp_mmx_trans.to_mmx",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0xF,
+ .event_name = "ild_stall.any",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x4,
+ .event_name = "ild_stall.iq_full",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x1,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x2,
+ .event_name = "ild_stall.mru",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x8,
+ .event_name = "ild_stall.regen",
+ },
+ {
+ .event_code = {0x18},
+ .umask = 0x1,
+ .event_name = "inst_decoded.dec0",
+ },
+ {
+ .event_code = {0x1E},
+ .umask = 0x1,
+ .event_name = "inst_queue_write_cycles",
+ },
+ {
+ .event_code = {0x17},
+ .umask = 0x1,
+ .event_name = "inst_queue_writes",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x4,
+ .event_name = "inst_retired.mmx",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x2,
+ .event_name = "inst_retired.x87",
+ },
+ {
+ .event_code = {0x6C},
+ .umask = 0x1,
+ .event_name = "io_transactions",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x1,
+ .event_name = "itlb_flush",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x20,
+ .event_name = "itlb_miss_retired",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x1,
+ .event_name = "itlb_misses.any",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x2,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x4,
+ .event_name = "itlb_misses.walk_cycles",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x4,
+ .event_name = "l1d.m_evict",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x2,
+ .event_name = "l1d.m_repl",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x8,
+ .event_name = "l1d.m_snoop_evict",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x1,
+ .event_name = "l1d.repl",
+ },
+ {
+ .event_code = {0x52},
+ .umask = 0x1,
+ .event_name = "l1d_cache_prefetch_lock_fb_hit",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x2,
+ .event_name = "l1d_prefetch.miss",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x1,
+ .event_name = "l1d_prefetch.requests",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x4,
+ .event_name = "l1d_prefetch.triggers",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x4,
+ .event_name = "l1d_wb_l2.e_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x1,
+ .event_name = "l1d_wb_l2.i_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x8,
+ .event_name = "l1d_wb_l2.m_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0xF,
+ .event_name = "l1d_wb_l2.mesi",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x2,
+ .event_name = "l1d_wb_l2.s_state",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x4,
+ .event_name = "l1i.cycles_stalled",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x1,
+ .event_name = "l1i.hits",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x2,
+ .event_name = "l1i.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x3,
+ .event_name = "l1i.reads",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xFF,
+ .event_name = "l2_data_rqsts.any",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x4,
+ .event_name = "l2_data_rqsts.demand.e_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x1,
+ .event_name = "l2_data_rqsts.demand.i_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x8,
+ .event_name = "l2_data_rqsts.demand.m_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xF,
+ .event_name = "l2_data_rqsts.demand.mesi",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x2,
+ .event_name = "l2_data_rqsts.demand.s_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x40,
+ .event_name = "l2_data_rqsts.prefetch.e_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x10,
+ .event_name = "l2_data_rqsts.prefetch.i_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x80,
+ .event_name = "l2_data_rqsts.prefetch.m_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xF0,
+ .event_name = "l2_data_rqsts.prefetch.mesi",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x20,
+ .event_name = "l2_data_rqsts.prefetch.s_state",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x7,
+ .event_name = "l2_lines_in.any",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x4,
+ .event_name = "l2_lines_in.e_state",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x2,
+ .event_name = "l2_lines_in.s_state",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0xF,
+ .event_name = "l2_lines_out.any",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x1,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x2,
+ .event_name = "l2_lines_out.demand_dirty",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x4,
+ .event_name = "l2_lines_out.prefetch_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x8,
+ .event_name = "l2_lines_out.prefetch_dirty",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x10,
+ .event_name = "l2_rqsts.ifetch_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x20,
+ .event_name = "l2_rqsts.ifetch_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.ifetches",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x1,
+ .event_name = "l2_rqsts.ld_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x2,
+ .event_name = "l2_rqsts.ld_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3,
+ .event_name = "l2_rqsts.loads",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xAA,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x40,
+ .event_name = "l2_rqsts.prefetch_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x80,
+ .event_name = "l2_rqsts.prefetch_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC0,
+ .event_name = "l2_rqsts.prefetches",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x4,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x8,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC,
+ .event_name = "l2_rqsts.rfos",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x80,
+ .event_name = "l2_transactions.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x20,
+ .event_name = "l2_transactions.fill",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x4,
+ .event_name = "l2_transactions.ifetch",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x10,
+ .event_name = "l2_transactions.l1d_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x1,
+ .event_name = "l2_transactions.load",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x8,
+ .event_name = "l2_transactions.prefetch",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x2,
+ .event_name = "l2_transactions.rfo",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_transactions.wb",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x40,
+ .event_name = "l2_write.lock.e_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xE0,
+ .event_name = "l2_write.lock.hit",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x10,
+ .event_name = "l2_write.lock.i_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x80,
+ .event_name = "l2_write.lock.m_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xF0,
+ .event_name = "l2_write.lock.mesi",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x20,
+ .event_name = "l2_write.lock.s_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xE,
+ .event_name = "l2_write.rfo.hit",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x1,
+ .event_name = "l2_write.rfo.i_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x8,
+ .event_name = "l2_write.rfo.m_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xF,
+ .event_name = "l2_write.rfo.mesi",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x2,
+ .event_name = "l2_write.rfo.s_state",
+ },
+ {
+ .event_code = {0x82},
+ .umask = 0x1,
+ .event_name = "large_itlb.hit",
+ },
+ {
+ .event_code = {0x3},
+ .umask = 0x2,
+ .event_name = "load_block.overlap_store",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x7,
+ .event_name = "load_dispatch.any",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x4,
+ .event_name = "load_dispatch.mob",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x1,
+ .event_name = "load_dispatch.rs",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x2,
+ .event_name = "load_dispatch.rs_delayed",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x1,
+ .event_name = "load_hit_pre",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x1,
+ .event_name = "lsd.active",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x1,
+ .event_name = "lsd.inactive",
+ },
+ {
+ .event_code = {0x20},
+ .umask = 0x1,
+ .event_name = "lsd_overflow",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x1,
+ .event_name = "machine_clears.cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x2,
+ .event_name = "machine_clears.mem_order",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x4,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x1,
+ .event_name = "macro_insts.decoded",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x1,
+ .event_name = "macro_insts.fusions_decoded",
+ },
+ {
+ .event_code = {0xB},
+ .umask = 0x1,
+ .event_name = "mem_inst_retired.loads",
+ },
+ {
+ .event_code = {0xB},
+ .umask = 0x2,
+ .event_name = "mem_inst_retired.stores",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x80,
+ .event_name = "mem_load_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x40,
+ .event_name = "mem_load_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x1,
+ .event_name = "mem_load_retired.l1d_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x2,
+ .event_name = "mem_load_retired.l2_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x10,
+ .event_name = "mem_load_retired.llc_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x4,
+ .event_name = "mem_load_retired.llc_unshared_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x8,
+ .event_name = "mem_load_retired.other_core_l2_hit_hitm",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x1,
+ .event_name = "mem_store_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x10,
+ .event_name = "mem_uncore_retired.local_dram",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x2,
+ .event_name = "mem_uncore_retired.other_core_l2_hitm",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x8,
+ .event_name = "mem_uncore_retired.remote_cache_local_home_hit",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x20,
+ .event_name = "mem_uncore_retired.remote_dram",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x80,
+ .event_name = "mem_uncore_retired.uncacheable",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x80,
+ .event_name = "offcore_requests.any",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x8,
+ .event_name = "offcore_requests.any.read",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x10,
+ .event_name = "offcore_requests.any.rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x2,
+ .event_name = "offcore_requests.demand.read_code",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x1,
+ .event_name = "offcore_requests.demand.read_data",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x4,
+ .event_name = "offcore_requests.demand.rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x40,
+ .event_name = "offcore_requests.l1d_writeback",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x20,
+ .event_name = "offcore_requests.uncached_mem",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x8,
+ .event_name = "offcore_requests_outstanding.any.read",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x8,
+ .event_name = "offcore_requests_outstanding.any.read_not_empty",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x2,
+ .event_name = "offcore_requests_outstanding.demand.read_code",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x2,
+ .event_name = "offcore_requests_outstanding.demand.read_code_not_empty",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x1,
+ .event_name = "offcore_requests_outstanding.demand.read_data",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x1,
+ .event_name = "offcore_requests_outstanding.demand.read_data_not_empty",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x4,
+ .event_name = "offcore_requests_outstanding.demand.rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x4,
+ .event_name = "offcore_requests_outstanding.demand.rfo_not_empty",
+ },
+ {
+ .event_code = {0xB2},
+ .umask = 0x1,
+ .event_name = "offcore_requests_sq_full",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x1,
+ .event_name = "partial_address_alias",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0xF,
+ .event_name = "rat_stalls.any",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x1,
+ .event_name = "rat_stalls.flags",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x2,
+ .event_name = "rat_stalls.registers",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x4,
+ .event_name = "rat_stalls.rob_read_port",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x8,
+ .event_name = "rat_stalls.scoreboard",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x1,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x20,
+ .event_name = "resource_stalls.fpcw",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x2,
+ .event_name = "resource_stalls.load",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x40,
+ .event_name = "resource_stalls.mxcsr",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x80,
+ .event_name = "resource_stalls.other",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob_full",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x4,
+ .event_name = "resource_stalls.rs_full",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x8,
+ .event_name = "resource_stalls.store",
+ },
+ {
+ .event_code = {0x4},
+ .umask = 0x7,
+ .event_name = "sb_drain.any",
+ },
+ {
+ .event_code = {0xD4},
+ .umask = 0x1,
+ .event_name = "seg_rename_stalls",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x4,
+ .event_name = "simd_int_128.pack",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x20,
+ .event_name = "simd_int_128.packed_arith",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x10,
+ .event_name = "simd_int_128.packed_logical",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x1,
+ .event_name = "simd_int_128.packed_mpy",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x2,
+ .event_name = "simd_int_128.packed_shift",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x40,
+ .event_name = "simd_int_128.shuffle_move",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x8,
+ .event_name = "simd_int_128.unpack",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x4,
+ .event_name = "simd_int_64.pack",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x20,
+ .event_name = "simd_int_64.packed_arith",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x10,
+ .event_name = "simd_int_64.packed_logical",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x1,
+ .event_name = "simd_int_64.packed_mpy",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x2,
+ .event_name = "simd_int_64.packed_shift",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x40,
+ .event_name = "simd_int_64.shuffle_move",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x8,
+ .event_name = "simd_int_64.unpack",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x1,
+ .event_name = "snoop_response.hit",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x2,
+ .event_name = "snoop_response.hite",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x4,
+ .event_name = "snoop_response.hitm",
+ },
+ {
+ .event_code = {0xB4},
+ .umask = 0x4,
+ .event_name = "snoopq_requests.code",
+ },
+ {
+ .event_code = {0xB4},
+ .umask = 0x1,
+ .event_name = "snoopq_requests.data",
+ },
+ {
+ .event_code = {0xB4},
+ .umask = 0x2,
+ .event_name = "snoopq_requests.invalidate",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x4,
+ .event_name = "snoopq_requests_outstanding.code",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x4,
+ .event_name = "snoopq_requests_outstanding.code_not_empty",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x1,
+ .event_name = "snoopq_requests_outstanding.data",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x1,
+ .event_name = "snoopq_requests_outstanding.data_not_empty",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x2,
+ .event_name = "snoopq_requests_outstanding.invalidate",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x2,
+ .event_name = "snoopq_requests_outstanding.invalidate_not_empty",
+ },
+ {
+ .event_code = {0xF6},
+ .umask = 0x1,
+ .event_name = "sq_full_stall_cycles",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x4,
+ .event_name = "sq_misc.lru_hints",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x4,
+ .event_name = "ssex_uops_retired.packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x1,
+ .event_name = "ssex_uops_retired.packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x8,
+ .event_name = "ssex_uops_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x2,
+ .event_name = "ssex_uops_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "ssex_uops_retired.vector_integer",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x4,
+ .event_name = "store_blocks.at_ret",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x8,
+ .event_name = "store_blocks.l1d_block",
+ },
+ {
+ .event_code = {0x19},
+ .umask = 0x1,
+ .event_name = "two_uop_insts_decoded",
+ },
+ {
+ .event_code = {0xDB},
+ .umask = 0x1,
+ .event_name = "uop_unfusion",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x4,
+ .event_name = "uops_decoded.esp_folding",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x8,
+ .event_name = "uops_decoded.esp_sync",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x2,
+ .event_name = "uops_decoded.ms_cycles_active",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x1,
+ .event_name = "uops_decoded.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_active_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_active_cycles_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_stall_count",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_stall_count_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_stall_cycles_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1,
+ .event_name = "uops_executed.port0",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x40,
+ .event_name = "uops_executed.port015",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x40,
+ .event_name = "uops_executed.port015_stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x2,
+ .event_name = "uops_executed.port1",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x4,
+ .event_name = "uops_executed.port2_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x80,
+ .event_name = "uops_executed.port234_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x8,
+ .event_name = "uops_executed.port3_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x10,
+ .event_name = "uops_executed.port4_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x20,
+ .event_name = "uops_executed.port5",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.core_stall_cycles",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.cycles_all_threads",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x2,
+ .event_name = "uops_issued.fused",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.active_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.any",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x4,
+ .event_name = "uops_retired.macro_fused",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x2,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.total_cycles_ps",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
--- /dev/null
+
+#include <perfmon/perfmon_intel.h>
+
+static perfmon_intel_pmc_cpu_model_t cpu_model_table[] = {
+ {0x2F, 0x00, 0},
+
+};
+
+static perfmon_intel_pmc_event_t event_table[] = {
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "arith.cycles_div_busy",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x1,
+ .event_name = "arith.div",
+ },
+ {
+ .event_code = {0x14},
+ .umask = 0x2,
+ .event_name = "arith.mul",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x2,
+ .event_name = "baclear.bad_target",
+ },
+ {
+ .event_code = {0xE6},
+ .umask = 0x1,
+ .event_name = "baclear.clear",
+ },
+ {
+ .event_code = {0xA7},
+ .umask = 0x1,
+ .event_name = "baclear_force_iq",
+ },
+ {
+ .event_code = {0xE8},
+ .umask = 0x1,
+ .event_name = "bpu_clears.early",
+ },
+ {
+ .event_code = {0xE8},
+ .umask = 0x2,
+ .event_name = "bpu_clears.late",
+ },
+ {
+ .event_code = {0xE5},
+ .umask = 0x1,
+ .event_name = "bpu_missed_call_ret",
+ },
+ {
+ .event_code = {0xE0},
+ .umask = 0x1,
+ .event_name = "br_inst_decoded",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x7F,
+ .event_name = "br_inst_exec.any",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x1,
+ .event_name = "br_inst_exec.cond",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x2,
+ .event_name = "br_inst_exec.direct",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x10,
+ .event_name = "br_inst_exec.direct_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x20,
+ .event_name = "br_inst_exec.indirect_near_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x4,
+ .event_name = "br_inst_exec.indirect_non_call",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x30,
+ .event_name = "br_inst_exec.near_calls",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x7,
+ .event_name = "br_inst_exec.non_calls",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x8,
+ .event_name = "br_inst_exec.return_near",
+ },
+ {
+ .event_code = {0x88},
+ .umask = 0x40,
+ .event_name = "br_inst_exec.taken",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x4,
+ .event_name = "br_inst_retired.all_branches",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x1,
+ .event_name = "br_inst_retired.conditional",
+ },
+ {
+ .event_code = {0xC4},
+ .umask = 0x2,
+ .event_name = "br_inst_retired.near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x7F,
+ .event_name = "br_misp_exec.any",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x1,
+ .event_name = "br_misp_exec.cond",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x2,
+ .event_name = "br_misp_exec.direct",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x10,
+ .event_name = "br_misp_exec.direct_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x20,
+ .event_name = "br_misp_exec.indirect_near_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x4,
+ .event_name = "br_misp_exec.indirect_non_call",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x30,
+ .event_name = "br_misp_exec.near_calls",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x7,
+ .event_name = "br_misp_exec.non_calls",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x8,
+ .event_name = "br_misp_exec.return_near",
+ },
+ {
+ .event_code = {0x89},
+ .umask = 0x40,
+ .event_name = "br_misp_exec.taken",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x4,
+ .event_name = "br_misp_retired.all_branches",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x1,
+ .event_name = "br_misp_retired.conditional",
+ },
+ {
+ .event_code = {0xC5},
+ .umask = 0x2,
+ .event_name = "br_misp_retired.near_call",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x2,
+ .event_name = "cache_lock_cycles.l1d",
+ },
+ {
+ .event_code = {0x63},
+ .umask = 0x1,
+ .event_name = "cache_lock_cycles.l1d_l2",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.ref",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x1,
+ .event_name = "cpu_clk_unhalted.ref_p",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.total_cycles",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x1,
+ .event_name = "dtlb_load_misses.any",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x80,
+ .event_name = "dtlb_load_misses.large_walk_completed",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x20,
+ .event_name = "dtlb_load_misses.pde_miss",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x10,
+ .event_name = "dtlb_load_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x2,
+ .event_name = "dtlb_load_misses.walk_completed",
+ },
+ {
+ .event_code = {0x8},
+ .umask = 0x4,
+ .event_name = "dtlb_load_misses.walk_cycles",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x1,
+ .event_name = "dtlb_misses.any",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x80,
+ .event_name = "dtlb_misses.large_walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x20,
+ .event_name = "dtlb_misses.pde_miss",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x10,
+ .event_name = "dtlb_misses.stlb_hit",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x2,
+ .event_name = "dtlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x49},
+ .umask = 0x4,
+ .event_name = "dtlb_misses.walk_cycles",
+ },
+ {
+ .event_code = {0x4F},
+ .umask = 0x10,
+ .event_name = "ept.walk_cycles",
+ },
+ {
+ .event_code = {0xD5},
+ .umask = 0x1,
+ .event_name = "es_reg_renames",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x1,
+ .event_name = "fp_assist.all",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x4,
+ .event_name = "fp_assist.input",
+ },
+ {
+ .event_code = {0xF7},
+ .umask = 0x2,
+ .event_name = "fp_assist.output",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x2,
+ .event_name = "fp_comp_ops_exe.mmx",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x80,
+ .event_name = "fp_comp_ops_exe.sse_double_precision",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x4,
+ .event_name = "fp_comp_ops_exe.sse_fp",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x10,
+ .event_name = "fp_comp_ops_exe.sse_fp_packed",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x20,
+ .event_name = "fp_comp_ops_exe.sse_fp_scalar",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x40,
+ .event_name = "fp_comp_ops_exe.sse_single_precision",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x8,
+ .event_name = "fp_comp_ops_exe.sse2_integer",
+ },
+ {
+ .event_code = {0x10},
+ .umask = 0x1,
+ .event_name = "fp_comp_ops_exe.x87",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x3,
+ .event_name = "fp_mmx_trans.any",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x1,
+ .event_name = "fp_mmx_trans.to_fp",
+ },
+ {
+ .event_code = {0xCC},
+ .umask = 0x2,
+ .event_name = "fp_mmx_trans.to_mmx",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0xF,
+ .event_name = "ild_stall.any",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x4,
+ .event_name = "ild_stall.iq_full",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x1,
+ .event_name = "ild_stall.lcp",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x2,
+ .event_name = "ild_stall.mru",
+ },
+ {
+ .event_code = {0x87},
+ .umask = 0x8,
+ .event_name = "ild_stall.regen",
+ },
+ {
+ .event_code = {0x18},
+ .umask = 0x1,
+ .event_name = "inst_decoded.dec0",
+ },
+ {
+ .event_code = {0x1E},
+ .umask = 0x1,
+ .event_name = "inst_queue_write_cycles",
+ },
+ {
+ .event_code = {0x17},
+ .umask = 0x1,
+ .event_name = "inst_queue_writes",
+ },
+ {
+ .event_code = {0x0},
+ .umask = 0x0,
+ .event_name = "inst_retired.any",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.any_p",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x4,
+ .event_name = "inst_retired.mmx",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x2,
+ .event_name = "inst_retired.x87",
+ },
+ {
+ .event_code = {0x6C},
+ .umask = 0x1,
+ .event_name = "io_transactions",
+ },
+ {
+ .event_code = {0xAE},
+ .umask = 0x1,
+ .event_name = "itlb_flush",
+ },
+ {
+ .event_code = {0xC8},
+ .umask = 0x20,
+ .event_name = "itlb_miss_retired",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x1,
+ .event_name = "itlb_misses.any",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x80,
+ .event_name = "itlb_misses.large_walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x2,
+ .event_name = "itlb_misses.walk_completed",
+ },
+ {
+ .event_code = {0x85},
+ .umask = 0x4,
+ .event_name = "itlb_misses.walk_cycles",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x4,
+ .event_name = "l1d.m_evict",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x2,
+ .event_name = "l1d.m_repl",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x8,
+ .event_name = "l1d.m_snoop_evict",
+ },
+ {
+ .event_code = {0x51},
+ .umask = 0x1,
+ .event_name = "l1d.repl",
+ },
+ {
+ .event_code = {0x52},
+ .umask = 0x1,
+ .event_name = "l1d_cache_prefetch_lock_fb_hit",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x2,
+ .event_name = "l1d_prefetch.miss",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x1,
+ .event_name = "l1d_prefetch.requests",
+ },
+ {
+ .event_code = {0x4E},
+ .umask = 0x4,
+ .event_name = "l1d_prefetch.triggers",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x4,
+ .event_name = "l1d_wb_l2.e_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x1,
+ .event_name = "l1d_wb_l2.i_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x8,
+ .event_name = "l1d_wb_l2.m_state",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0xF,
+ .event_name = "l1d_wb_l2.mesi",
+ },
+ {
+ .event_code = {0x28},
+ .umask = 0x2,
+ .event_name = "l1d_wb_l2.s_state",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x4,
+ .event_name = "l1i.cycles_stalled",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x1,
+ .event_name = "l1i.hits",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x2,
+ .event_name = "l1i.misses",
+ },
+ {
+ .event_code = {0x80},
+ .umask = 0x3,
+ .event_name = "l1i.reads",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xFF,
+ .event_name = "l2_data_rqsts.any",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x4,
+ .event_name = "l2_data_rqsts.demand.e_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x1,
+ .event_name = "l2_data_rqsts.demand.i_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x8,
+ .event_name = "l2_data_rqsts.demand.m_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xF,
+ .event_name = "l2_data_rqsts.demand.mesi",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x2,
+ .event_name = "l2_data_rqsts.demand.s_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x40,
+ .event_name = "l2_data_rqsts.prefetch.e_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x10,
+ .event_name = "l2_data_rqsts.prefetch.i_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x80,
+ .event_name = "l2_data_rqsts.prefetch.m_state",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0xF0,
+ .event_name = "l2_data_rqsts.prefetch.mesi",
+ },
+ {
+ .event_code = {0x26},
+ .umask = 0x20,
+ .event_name = "l2_data_rqsts.prefetch.s_state",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x7,
+ .event_name = "l2_lines_in.any",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x4,
+ .event_name = "l2_lines_in.e_state",
+ },
+ {
+ .event_code = {0xF1},
+ .umask = 0x2,
+ .event_name = "l2_lines_in.s_state",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0xF,
+ .event_name = "l2_lines_out.any",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x1,
+ .event_name = "l2_lines_out.demand_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x2,
+ .event_name = "l2_lines_out.demand_dirty",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x4,
+ .event_name = "l2_lines_out.prefetch_clean",
+ },
+ {
+ .event_code = {0xF2},
+ .umask = 0x8,
+ .event_name = "l2_lines_out.prefetch_dirty",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x10,
+ .event_name = "l2_rqsts.ifetch_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x20,
+ .event_name = "l2_rqsts.ifetch_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x30,
+ .event_name = "l2_rqsts.ifetches",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x1,
+ .event_name = "l2_rqsts.ld_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x2,
+ .event_name = "l2_rqsts.ld_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x3,
+ .event_name = "l2_rqsts.loads",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xAA,
+ .event_name = "l2_rqsts.miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x40,
+ .event_name = "l2_rqsts.prefetch_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x80,
+ .event_name = "l2_rqsts.prefetch_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC0,
+ .event_name = "l2_rqsts.prefetches",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xFF,
+ .event_name = "l2_rqsts.references",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x4,
+ .event_name = "l2_rqsts.rfo_hit",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0x8,
+ .event_name = "l2_rqsts.rfo_miss",
+ },
+ {
+ .event_code = {0x24},
+ .umask = 0xC,
+ .event_name = "l2_rqsts.rfos",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x80,
+ .event_name = "l2_transactions.any",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x20,
+ .event_name = "l2_transactions.fill",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x4,
+ .event_name = "l2_transactions.ifetch",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x10,
+ .event_name = "l2_transactions.l1d_wb",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x1,
+ .event_name = "l2_transactions.load",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x8,
+ .event_name = "l2_transactions.prefetch",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x2,
+ .event_name = "l2_transactions.rfo",
+ },
+ {
+ .event_code = {0xF0},
+ .umask = 0x40,
+ .event_name = "l2_transactions.wb",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x40,
+ .event_name = "l2_write.lock.e_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xE0,
+ .event_name = "l2_write.lock.hit",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x10,
+ .event_name = "l2_write.lock.i_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x80,
+ .event_name = "l2_write.lock.m_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xF0,
+ .event_name = "l2_write.lock.mesi",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x20,
+ .event_name = "l2_write.lock.s_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xE,
+ .event_name = "l2_write.rfo.hit",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x1,
+ .event_name = "l2_write.rfo.i_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x8,
+ .event_name = "l2_write.rfo.m_state",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0xF,
+ .event_name = "l2_write.rfo.mesi",
+ },
+ {
+ .event_code = {0x27},
+ .umask = 0x2,
+ .event_name = "l2_write.rfo.s_state",
+ },
+ {
+ .event_code = {0x82},
+ .umask = 0x1,
+ .event_name = "large_itlb.hit",
+ },
+ {
+ .event_code = {0x3},
+ .umask = 0x2,
+ .event_name = "load_block.overlap_store",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x7,
+ .event_name = "load_dispatch.any",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x4,
+ .event_name = "load_dispatch.mob",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x1,
+ .event_name = "load_dispatch.rs",
+ },
+ {
+ .event_code = {0x13},
+ .umask = 0x2,
+ .event_name = "load_dispatch.rs_delayed",
+ },
+ {
+ .event_code = {0x4C},
+ .umask = 0x1,
+ .event_name = "load_hit_pre",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x41,
+ .event_name = "longest_lat_cache.miss",
+ },
+ {
+ .event_code = {0x2E},
+ .umask = 0x4F,
+ .event_name = "longest_lat_cache.reference",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x1,
+ .event_name = "lsd.active",
+ },
+ {
+ .event_code = {0xA8},
+ .umask = 0x1,
+ .event_name = "lsd.inactive",
+ },
+ {
+ .event_code = {0x20},
+ .umask = 0x1,
+ .event_name = "lsd_overflow",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x1,
+ .event_name = "machine_clears.cycles",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x2,
+ .event_name = "machine_clears.mem_order",
+ },
+ {
+ .event_code = {0xC3},
+ .umask = 0x4,
+ .event_name = "machine_clears.smc",
+ },
+ {
+ .event_code = {0xD0},
+ .umask = 0x1,
+ .event_name = "macro_insts.decoded",
+ },
+ {
+ .event_code = {0xA6},
+ .umask = 0x1,
+ .event_name = "macro_insts.fusions_decoded",
+ },
+ {
+ .event_code = {0xB},
+ .umask = 0x1,
+ .event_name = "mem_inst_retired.loads",
+ },
+ {
+ .event_code = {0xB},
+ .umask = 0x2,
+ .event_name = "mem_inst_retired.stores",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x80,
+ .event_name = "mem_load_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x40,
+ .event_name = "mem_load_retired.hit_lfb",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x1,
+ .event_name = "mem_load_retired.l1d_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x2,
+ .event_name = "mem_load_retired.l2_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x10,
+ .event_name = "mem_load_retired.llc_miss",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x4,
+ .event_name = "mem_load_retired.llc_unshared_hit",
+ },
+ {
+ .event_code = {0xCB},
+ .umask = 0x8,
+ .event_name = "mem_load_retired.other_core_l2_hit_hitm",
+ },
+ {
+ .event_code = {0xC},
+ .umask = 0x1,
+ .event_name = "mem_store_retired.dtlb_miss",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x2,
+ .event_name = "mem_uncore_retired.local_hitm",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x8,
+ .event_name = "mem_uncore_retired.local_dram_and_remote_cache_hit",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x20,
+ .event_name = "mem_uncore_retired.remote_dram",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x80,
+ .event_name = "mem_uncore_retired.uncacheable",
+ },
+ {
+ .event_code = {0xF},
+ .umask = 0x4,
+ .event_name = "mem_uncore_retired.remote_hitm",
+ },
+ {
+ .event_code = {0x5},
+ .umask = 0x2,
+ .event_name = "misalign_mem_ref.store",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x80,
+ .event_name = "offcore_requests.any",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x8,
+ .event_name = "offcore_requests.any.read",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x10,
+ .event_name = "offcore_requests.any.rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x2,
+ .event_name = "offcore_requests.demand.read_code",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x1,
+ .event_name = "offcore_requests.demand.read_data",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x4,
+ .event_name = "offcore_requests.demand.rfo",
+ },
+ {
+ .event_code = {0xB0},
+ .umask = 0x40,
+ .event_name = "offcore_requests.l1d_writeback",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x8,
+ .event_name = "offcore_requests_outstanding.any.read",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x8,
+ .event_name = "offcore_requests_outstanding.any.read_not_empty",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x2,
+ .event_name = "offcore_requests_outstanding.demand.read_code",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x2,
+ .event_name = "offcore_requests_outstanding.demand.read_code_not_empty",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x1,
+ .event_name = "offcore_requests_outstanding.demand.read_data",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x1,
+ .event_name = "offcore_requests_outstanding.demand.read_data_not_empty",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x4,
+ .event_name = "offcore_requests_outstanding.demand.rfo",
+ },
+ {
+ .event_code = {0x60},
+ .umask = 0x4,
+ .event_name = "offcore_requests_outstanding.demand.rfo_not_empty",
+ },
+ {
+ .event_code = {0xB2},
+ .umask = 0x1,
+ .event_name = "offcore_requests_sq_full",
+ },
+ {
+ .event_code = {0x7},
+ .umask = 0x1,
+ .event_name = "partial_address_alias",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0xF,
+ .event_name = "rat_stalls.any",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x1,
+ .event_name = "rat_stalls.flags",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x2,
+ .event_name = "rat_stalls.registers",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x4,
+ .event_name = "rat_stalls.rob_read_port",
+ },
+ {
+ .event_code = {0xD2},
+ .umask = 0x8,
+ .event_name = "rat_stalls.scoreboard",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x1,
+ .event_name = "resource_stalls.any",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x20,
+ .event_name = "resource_stalls.fpcw",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x2,
+ .event_name = "resource_stalls.load",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x40,
+ .event_name = "resource_stalls.mxcsr",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x80,
+ .event_name = "resource_stalls.other",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x10,
+ .event_name = "resource_stalls.rob_full",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x4,
+ .event_name = "resource_stalls.rs_full",
+ },
+ {
+ .event_code = {0xA2},
+ .umask = 0x8,
+ .event_name = "resource_stalls.store",
+ },
+ {
+ .event_code = {0x4},
+ .umask = 0x7,
+ .event_name = "sb_drain.any",
+ },
+ {
+ .event_code = {0xD4},
+ .umask = 0x1,
+ .event_name = "seg_rename_stalls",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x4,
+ .event_name = "simd_int_128.pack",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x20,
+ .event_name = "simd_int_128.packed_arith",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x10,
+ .event_name = "simd_int_128.packed_logical",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x1,
+ .event_name = "simd_int_128.packed_mpy",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x2,
+ .event_name = "simd_int_128.packed_shift",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x40,
+ .event_name = "simd_int_128.shuffle_move",
+ },
+ {
+ .event_code = {0x12},
+ .umask = 0x8,
+ .event_name = "simd_int_128.unpack",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x4,
+ .event_name = "simd_int_64.pack",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x20,
+ .event_name = "simd_int_64.packed_arith",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x10,
+ .event_name = "simd_int_64.packed_logical",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x1,
+ .event_name = "simd_int_64.packed_mpy",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x2,
+ .event_name = "simd_int_64.packed_shift",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x40,
+ .event_name = "simd_int_64.shuffle_move",
+ },
+ {
+ .event_code = {0xFD},
+ .umask = 0x8,
+ .event_name = "simd_int_64.unpack",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x1,
+ .event_name = "snoop_response.hit",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x2,
+ .event_name = "snoop_response.hite",
+ },
+ {
+ .event_code = {0xB8},
+ .umask = 0x4,
+ .event_name = "snoop_response.hitm",
+ },
+ {
+ .event_code = {0xB4},
+ .umask = 0x4,
+ .event_name = "snoopq_requests.code",
+ },
+ {
+ .event_code = {0xB4},
+ .umask = 0x1,
+ .event_name = "snoopq_requests.data",
+ },
+ {
+ .event_code = {0xB4},
+ .umask = 0x2,
+ .event_name = "snoopq_requests.invalidate",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x4,
+ .event_name = "snoopq_requests_outstanding.code",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x4,
+ .event_name = "snoopq_requests_outstanding.code_not_empty",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x1,
+ .event_name = "snoopq_requests_outstanding.data",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x1,
+ .event_name = "snoopq_requests_outstanding.data_not_empty",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x2,
+ .event_name = "snoopq_requests_outstanding.invalidate",
+ },
+ {
+ .event_code = {0xB3},
+ .umask = 0x2,
+ .event_name = "snoopq_requests_outstanding.invalidate_not_empty",
+ },
+ {
+ .event_code = {0xF6},
+ .umask = 0x1,
+ .event_name = "sq_full_stall_cycles",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x4,
+ .event_name = "sq_misc.lru_hints",
+ },
+ {
+ .event_code = {0xF4},
+ .umask = 0x10,
+ .event_name = "sq_misc.split_lock",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x4,
+ .event_name = "ssex_uops_retired.packed_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x1,
+ .event_name = "ssex_uops_retired.packed_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x8,
+ .event_name = "ssex_uops_retired.scalar_double",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x2,
+ .event_name = "ssex_uops_retired.scalar_single",
+ },
+ {
+ .event_code = {0xC7},
+ .umask = 0x10,
+ .event_name = "ssex_uops_retired.vector_integer",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x4,
+ .event_name = "store_blocks.at_ret",
+ },
+ {
+ .event_code = {0x6},
+ .umask = 0x8,
+ .event_name = "store_blocks.l1d_block",
+ },
+ {
+ .event_code = {0x3C},
+ .umask = 0x0,
+ .event_name = "cpu_clk_unhalted.thread_p",
+ },
+ {
+ .event_code = {0x19},
+ .umask = 0x1,
+ .event_name = "two_uop_insts_decoded",
+ },
+ {
+ .event_code = {0xDB},
+ .umask = 0x1,
+ .event_name = "uop_unfusion",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x4,
+ .event_name = "uops_decoded.esp_folding",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x8,
+ .event_name = "uops_decoded.esp_sync",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x2,
+ .event_name = "uops_decoded.ms_cycles_active",
+ },
+ {
+ .event_code = {0xD1},
+ .umask = 0x1,
+ .event_name = "uops_decoded.stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_active_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_active_cycles_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_stall_count",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_stall_count_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x3F,
+ .event_name = "uops_executed.core_stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1F,
+ .event_name = "uops_executed.core_stall_cycles_no_port5",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x1,
+ .event_name = "uops_executed.port0",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x40,
+ .event_name = "uops_executed.port015",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x40,
+ .event_name = "uops_executed.port015_stall_cycles",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x2,
+ .event_name = "uops_executed.port1",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x4,
+ .event_name = "uops_executed.port2_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x80,
+ .event_name = "uops_executed.port234_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x8,
+ .event_name = "uops_executed.port3_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x10,
+ .event_name = "uops_executed.port4_core",
+ },
+ {
+ .event_code = {0xB1},
+ .umask = 0x20,
+ .event_name = "uops_executed.port5",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.any",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.core_stall_cycles",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.cycles_all_threads",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x2,
+ .event_name = "uops_issued.fused",
+ },
+ {
+ .event_code = {0xE},
+ .umask = 0x1,
+ .event_name = "uops_issued.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.active_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.any",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x4,
+ .event_name = "uops_retired.macro_fused",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x2,
+ .event_name = "uops_retired.retire_slots",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.stall_cycles",
+ },
+ {
+ .event_code = {0xC2},
+ .umask = 0x1,
+ .event_name = "uops_retired.total_cycles",
+ },
+ {
+ .event_code = {0xC0},
+ .umask = 0x1,
+ .event_name = "inst_retired.total_cycles_ps",
+ },
+ {
+ .event_name = 0,
+ },
+};
+
+PERFMON_REGISTER_INTEL_PMC (cpu_model_table, event_table);
+
Code Review / vpp.git / commitdiff