vppinfra: SFENCE requires SSE2 to be enabled

Change-Id: I0469bb91107cf0acced3cd19820db8d3712701c0
Type: fix
Fixes: eaabe07
Signed-off-by: Damjan Marion <damarion@cisco.com>

diff --git a/src/vppinfra/clib.h b/src/vppinfra/clib.h
index dab7eeb..d145824 100644 (file)
--- a/src/vppinfra/clib.h
+++ b/src/vppinfra/clib.h
@@ -181,7 +181,7 @@
 /* Full memory barrier (read and write). */
 #define CLIB_MEMORY_BARRIER() __sync_synchronize ()
 
-#if __x86_64__
+#if __SSE__
 #define CLIB_MEMORY_STORE_BARRIER() __builtin_ia32_sfence ()
 #else
 #define CLIB_MEMORY_STORE_BARRIER() __sync_synchronize ()