This change only affects Aarch64 where previously we were using 128
bytes.
Change-Id: I52a3f2f3ff8c06abe8ae3933bc0d7a2a7749dd8a
Signed-off-by: Damjan Marion <damarion@cisco.com>
*/
#ifndef CLIB_LOG2_CACHE_LINE_BYTES
-#if defined(__x86_64__) || defined(__ARM_ARCH_7A__) || defined(__i386__)
-#define CLIB_LOG2_CACHE_LINE_BYTES 6
-#endif
-
-#ifdef __aarch64__
-#define CLIB_LOG2_CACHE_LINE_BYTES 7
-#endif
-
-/* Default cache line size of 32 bytes. */
+/* Default cache line size of 64 bytes. */
#ifndef CLIB_LOG2_CACHE_LINE_BYTES
-#define CLIB_LOG2_CACHE_LINE_BYTES 5
+#define CLIB_LOG2_CACHE_LINE_BYTES 6
#endif
#endif /* CLIB_LOG2_CACHE_LINE_BYTES defined */