ip4-input: fix prefetch data issue for tunnel decap cases

There are two reasons to modify the existing code ip4_input_inline.

1. For many tunnel decap cases, inner ip header or its part is possible
in the second cacheline, not first cacheline only after the field "data",
and this will cause data cache miss once the second cacheline is needed
to access. e.g vxlan-gpe.
2. For most of cases, "data" is the starting address of ethernet
header, not IP header. The existing code causes misunderstanding
from code readability perspective.

Change-Id: I43e119b899dbde95803bccbac54259729fd2cddf
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
Signed-off-by: Yuwei Zhang <yuwei1.zhang@intel.com>

diff --git a/src/vnet/ip/ip4_input.c b/src/vnet/ip/ip4_input.c
index 5a2ae17..1928a66 100644 (file)
--- a/src/vnet/ip/ip4_input.c
+++ b/src/vnet/ip/ip4_input.c
@@ -163,10 +163,14 @@ ip4_input_inline (vlib_main_t * vm,
          vlib_prefetch_buffer_header (b[10], LOAD);
          vlib_prefetch_buffer_header (b[11], LOAD);
 
-         CLIB_PREFETCH (b[4]->data, sizeof (ip4_header_t), LOAD);
-         CLIB_PREFETCH (b[5]->data, sizeof (ip4_header_t), LOAD);
-         CLIB_PREFETCH (b[6]->data, sizeof (ip4_header_t), LOAD);
-         CLIB_PREFETCH (b[7]->data, sizeof (ip4_header_t), LOAD);
+         CLIB_PREFETCH (vlib_buffer_get_current (b[4]),
+                        sizeof (ip4_header_t), LOAD);
+         CLIB_PREFETCH (vlib_buffer_get_current (b[5]),
+                        sizeof (ip4_header_t), LOAD);
+         CLIB_PREFETCH (vlib_buffer_get_current (b[6]),
+                        sizeof (ip4_header_t), LOAD);
+         CLIB_PREFETCH (vlib_buffer_get_current (b[7]),
+                        sizeof (ip4_header_t), LOAD);
        }
 
       vnet_buffer (b[0])->ip.adj_index[VLIB_RX] = ~0;