drivers/net/bnx2x/bnx2x.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015-2018 Cavium Inc.
  10  * All rights reserved.
  11  * www.cavium.com
  12  */
  13
  14 #define BNX2X_DRIVER_VERSION "1.78.18"
  15
  16 #include "bnx2x.h"
  17 #include "bnx2x_vfpf.h"
  18 #include "ecore_sp.h"
  19 #include "ecore_init.h"
  20 #include "ecore_init_ops.h"
  21
  22 #include "rte_version.h"
  23
  24 #include <sys/types.h>
  25 #include <sys/stat.h>
  26 #include <fcntl.h>
  27 #include <zlib.h>
  28
  29 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  30 #define BNX2X_PMD_VERSION_MAJOR 1
  31 #define BNX2X_PMD_VERSION_MINOR 0
  32 #define BNX2X_PMD_VERSION_REVISION 6
  33 #define BNX2X_PMD_VERSION_PATCH 1
  34
  35 static inline const char *
  36 bnx2x_pmd_version(void)
  37 {
  38         static char version[32];
  39
  40         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  41                         BNX2X_PMD_VER_PREFIX,
  42                         BNX2X_DRIVER_VERSION,
  43                         BNX2X_PMD_VERSION_MAJOR,
  44                         BNX2X_PMD_VERSION_MINOR,
  45                         BNX2X_PMD_VERSION_REVISION,
  46                         BNX2X_PMD_VERSION_PATCH);
  47
  48         return version;
  49 }
  50
  51 static z_stream zlib_stream;
  52
  53 #define EVL_VLID_MASK 0x0FFF
  54
  55 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  56 #define BNX2X_DEF_SB_IDX     0x0002
  57
  58 /*
  59  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  60  * function HW initialization.
  61  */
  62 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  63 #define FLR_WAIT_INTERVAL 50    /* usecs */
  64 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  65
  66 struct pbf_pN_buf_regs {
  67         int pN;
  68         uint32_t init_crd;
  69         uint32_t crd;
  70         uint32_t crd_freed;
  71 };
  72
  73 struct pbf_pN_cmd_regs {
  74         int pN;
  75         uint32_t lines_occup;
  76         uint32_t lines_freed;
  77 };
  78
  79 /* resources needed for unloading a previously loaded device */
  80
  81 #define BNX2X_PREV_WAIT_NEEDED 1
  82 rte_spinlock_t bnx2x_prev_mtx;
  83 struct bnx2x_prev_list_node {
  84         LIST_ENTRY(bnx2x_prev_list_node) node;
  85         uint8_t bus;
  86         uint8_t slot;
  87         uint8_t path;
  88         uint8_t aer;
  89         uint8_t undi;
  90 };
  91
  92 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  93         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  94
  95 static int load_count[2][3] = { { 0 } };
  96         /* per-path: 0-common, 1-port0, 2-port1 */
  97
  98 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
  99                                 uint8_t cmng_type);
 100 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 101 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 102                               uint8_t port);
 103 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 104 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 105 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 106 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 107 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 108                                      uint8_t print);
 109 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 110 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 111 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 112 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 113                                  struct bnx2x_fastpath *fp,
 114                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 115 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
 116 static void bnx2x_link_report(struct bnx2x_softc *sc);
 117 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 118 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 119 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 120 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 121 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 122 static __rte_noinline
 123 int bnx2x_nic_load(struct bnx2x_softc *sc);
 124
 125 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 126 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 127 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 128                          uint8_t storm, uint16_t index, uint8_t op,
 129                          uint8_t update);
 130
 131 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 132 {
 133         int res;
 134
 135         mb();
 136         res = ((*addr) & (1UL << nr)) != 0;
 137         mb();
 138         return res;
 139 }
 140
 141 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 142 {
 143         __sync_fetch_and_or(addr, (1UL << nr));
 144 }
 145
 146 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 147 {
 148         __sync_fetch_and_and(addr, ~(1UL << nr));
 149 }
 150
 151 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 152 {
 153         unsigned long mask = (1UL << nr);
 154         return __sync_fetch_and_and(addr, ~mask) & mask;
 155 }
 156
 157 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 158 {
 159         return __sync_val_compare_and_swap(addr, old, new);
 160 }
 161
 162 int
 163 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 164               const char *msg, uint32_t align)
 165 {
 166         char mz_name[RTE_MEMZONE_NAMESIZE];
 167         const struct rte_memzone *z;
 168
 169         dma->sc = sc;
 170         if (IS_PF(sc))
 171                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 172                         rte_get_timer_cycles());
 173         else
 174                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 175                         rte_get_timer_cycles());
 176
 177         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 178         z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
 179                                         SOCKET_ID_ANY,
 180                                         RTE_MEMZONE_IOVA_CONTIG, align);
 181         if (z == NULL) {
 182                 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
 183                 return -ENOMEM;
 184         }
 185         dma->paddr = (uint64_t) z->iova;
 186         dma->vaddr = z->addr;
 187
 188         PMD_DRV_LOG(DEBUG, sc,
 189                     "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 190
 191         return 0;
 192 }
 193
 194 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 195 {
 196         uint32_t lock_status;
 197         uint32_t resource_bit = (1 << resource);
 198         int func = SC_FUNC(sc);
 199         uint32_t hw_lock_control_reg;
 200         int cnt;
 201
 202         if (resource)
 203                 PMD_INIT_FUNC_TRACE(sc);
 204
 205         /* validate the resource is within range */
 206         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 207                 PMD_DRV_LOG(NOTICE, sc,
 208                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 209                             resource);
 210                 return -1;
 211         }
 212
 213         if (func <= 5) {
 214                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 215         } else {
 216                 hw_lock_control_reg =
 217                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 218         }
 219
 220         /* validate the resource is not already taken */
 221         lock_status = REG_RD(sc, hw_lock_control_reg);
 222         if (lock_status & resource_bit) {
 223                 PMD_DRV_LOG(NOTICE, sc,
 224                             "resource in use (status 0x%x bit 0x%x)",
 225                             lock_status, resource_bit);
 226                 return -1;
 227         }
 228
 229         /* try every 5ms for 5 seconds */
 230         for (cnt = 0; cnt < 1000; cnt++) {
 231                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 232                 lock_status = REG_RD(sc, hw_lock_control_reg);
 233                 if (lock_status & resource_bit) {
 234                         return 0;
 235                 }
 236                 DELAY(5000);
 237         }
 238
 239         PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
 240                     resource, resource_bit);
 241         return -1;
 242 }
 243
 244 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 245 {
 246         uint32_t lock_status;
 247         uint32_t resource_bit = (1 << resource);
 248         int func = SC_FUNC(sc);
 249         uint32_t hw_lock_control_reg;
 250
 251         if (resource)
 252                 PMD_INIT_FUNC_TRACE(sc);
 253
 254         /* validate the resource is within range */
 255         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 256                 PMD_DRV_LOG(NOTICE, sc,
 257                             "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
 258                             " resource_bit 0x%x", resource, resource_bit);
 259                 return -1;
 260         }
 261
 262         if (func <= 5) {
 263                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 264         } else {
 265                 hw_lock_control_reg =
 266                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 267         }
 268
 269         /* validate the resource is currently taken */
 270         lock_status = REG_RD(sc, hw_lock_control_reg);
 271         if (!(lock_status & resource_bit)) {
 272                 PMD_DRV_LOG(NOTICE, sc,
 273                             "resource not in use (status 0x%x bit 0x%x)",
 274                             lock_status, resource_bit);
 275                 return -1;
 276         }
 277
 278         REG_WR(sc, hw_lock_control_reg, resource_bit);
 279         return 0;
 280 }
 281
 282 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
 283 {
 284         BNX2X_PHY_LOCK(sc);
 285         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 286 }
 287
 288 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
 289 {
 290         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 291         BNX2X_PHY_UNLOCK(sc);
 292 }
 293
 294 /* copy command into DMAE command memory and set DMAE command Go */
 295 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 296 {
 297         uint32_t cmd_offset;
 298         uint32_t i;
 299
 300         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 301         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 302                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 303         }
 304
 305         REG_WR(sc, dmae_reg_go_c[idx], 1);
 306 }
 307
 308 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 309 {
 310         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 311                           DMAE_COMMAND_C_TYPE_ENABLE);
 312 }
 313
 314 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 315 {
 316         return opcode & ~DMAE_COMMAND_SRC_RESET;
 317 }
 318
 319 uint32_t
 320 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 321                 uint8_t with_comp, uint8_t comp_type)
 322 {
 323         uint32_t opcode = 0;
 324
 325         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 326                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 327
 328         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 329
 330         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 331
 332         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 333                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 334
 335         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 336
 337 #ifdef __BIG_ENDIAN
 338         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 339 #else
 340         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 341 #endif
 342
 343         if (with_comp) {
 344                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 345         }
 346
 347         return opcode;
 348 }
 349
 350 static void
 351 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 352                         uint8_t src_type, uint8_t dst_type)
 353 {
 354         memset(dmae, 0, sizeof(struct dmae_command));
 355
 356         /* set the opcode */
 357         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 358                                        TRUE, DMAE_COMP_PCI);
 359
 360         /* fill in the completion parameters */
 361         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 362         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 363         dmae->comp_val = DMAE_COMP_VAL;
 364 }
 365
 366 /* issue a DMAE command over the init channel and wait for completion */
 367 static int
 368 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 369 {
 370         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 371         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 372
 373         /* reset completion */
 374         *wb_comp = 0;
 375
 376         /* post the command on the channel used for initializations */
 377         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 378
 379         /* wait for completion */
 380         DELAY(500);
 381
 382         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 383                 if (!timeout ||
 384                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 385                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 386                         PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
 387                         return DMAE_TIMEOUT;
 388                 }
 389
 390                 timeout--;
 391                 DELAY(50);
 392         }
 393
 394         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 395                 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
 396                 return DMAE_PCI_ERROR;
 397         }
 398
 399         return 0;
 400 }
 401
 402 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 403 {
 404         struct dmae_command dmae;
 405         uint32_t *data;
 406         uint32_t i;
 407         int rc;
 408
 409         if (!sc->dmae_ready) {
 410                 data = BNX2X_SP(sc, wb_data[0]);
 411
 412                 for (i = 0; i < len32; i++) {
 413                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 414                 }
 415
 416                 return;
 417         }
 418
 419         /* set opcode and fixed command fields */
 420         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 421
 422         /* fill in addresses and len */
 423         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 424         dmae.src_addr_hi = 0;
 425         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 426         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 427         dmae.len = len32;
 428
 429         /* issue the command and wait for completion */
 430         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 431                 rte_panic("DMAE failed (%d)", rc);
 432         };
 433 }
 434
 435 void
 436 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 437                uint32_t len32)
 438 {
 439         struct dmae_command dmae;
 440         int rc;
 441
 442         if (!sc->dmae_ready) {
 443                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 444                 return;
 445         }
 446
 447         /* set opcode and fixed command fields */
 448         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 449
 450         /* fill in addresses and len */
 451         dmae.src_addr_lo = U64_LO(dma_addr);
 452         dmae.src_addr_hi = U64_HI(dma_addr);
 453         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 454         dmae.dst_addr_hi = 0;
 455         dmae.len = len32;
 456
 457         /* issue the command and wait for completion */
 458         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 459                 rte_panic("DMAE failed (%d)", rc);
 460         }
 461 }
 462
 463 static void
 464 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 465                         uint32_t addr, uint32_t len)
 466 {
 467         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 468         uint32_t offset = 0;
 469
 470         while (len > dmae_wr_max) {
 471                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 472                                (addr + offset), /* dst GRC address */
 473                                dmae_wr_max);
 474                 offset += (dmae_wr_max * 4);
 475                 len -= dmae_wr_max;
 476         }
 477
 478         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 479                        (addr + offset), /* dst GRC address */
 480                        len);
 481 }
 482
 483 void
 484 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 485                        uint32_t cid)
 486 {
 487         /* ustorm cxt validation */
 488         cxt->ustorm_ag_context.cdu_usage =
 489             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 490                                    CDU_REGION_NUMBER_UCM_AG,
 491                                    ETH_CONNECTION_TYPE);
 492         /* xcontext validation */
 493         cxt->xstorm_ag_context.cdu_reserved =
 494             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 495                                    CDU_REGION_NUMBER_XCM_AG,
 496                                    ETH_CONNECTION_TYPE);
 497 }
 498
 499 static void
 500 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 501                             uint8_t sb_index, uint8_t ticks)
 502 {
 503         uint32_t addr =
 504             (BAR_CSTRORM_INTMEM +
 505              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 506
 507         REG_WR8(sc, addr, ticks);
 508 }
 509
 510 static void
 511 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 512                             uint8_t sb_index, uint8_t disable)
 513 {
 514         uint32_t enable_flag =
 515             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 516         uint32_t addr =
 517             (BAR_CSTRORM_INTMEM +
 518              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 519         uint8_t flags;
 520
 521         /* clear and set */
 522         flags = REG_RD8(sc, addr);
 523         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 524         flags |= enable_flag;
 525         REG_WR8(sc, addr, flags);
 526 }
 527
 528 void
 529 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 530                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 531 {
 532         uint8_t ticks = (usec / 4);
 533
 534         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 535
 536         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 537         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 538 }
 539
 540 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 541 {
 542         return REG_RD(sc, reg_addr);
 543 }
 544
 545 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 546 {
 547         REG_WR(sc, reg_addr, val);
 548 }
 549
 550 void
 551 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 552                    __rte_unused const elink_log_id_t elink_log_id, ...)
 553 {
 554         PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
 555 }
 556
 557 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 558 {
 559         uint32_t spio_reg;
 560
 561         /* Only 2 SPIOs are configurable */
 562         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 563                 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
 564                 return -1;
 565         }
 566
 567         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 568
 569         /* read SPIO and mask except the float bits */
 570         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 571
 572         switch (mode) {
 573         case MISC_SPIO_OUTPUT_LOW:
 574                 /* clear FLOAT and set CLR */
 575                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 576                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 577                 break;
 578
 579         case MISC_SPIO_OUTPUT_HIGH:
 580                 /* clear FLOAT and set SET */
 581                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 582                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 583                 break;
 584
 585         case MISC_SPIO_INPUT_HI_Z:
 586                 /* set FLOAT */
 587                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 588                 break;
 589
 590         default:
 591                 break;
 592         }
 593
 594         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 595         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 596
 597         return 0;
 598 }
 599
 600 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 601 {
 602         /* The GPIO should be swapped if swap register is set and active */
 603         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 604                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 605         int gpio_shift = gpio_num;
 606         if (gpio_port)
 607                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 608
 609         uint32_t gpio_mask = (1 << gpio_shift);
 610         uint32_t gpio_reg;
 611
 612         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 613                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 614                 return -1;
 615         }
 616
 617         /* read GPIO value */
 618         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 619
 620         /* get the requested pin value */
 621         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 622 }
 623
 624 static int
 625 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 626 {
 627         /* The GPIO should be swapped if swap register is set and active */
 628         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 629                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 630         int gpio_shift = gpio_num;
 631         if (gpio_port)
 632                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 633
 634         uint32_t gpio_mask = (1 << gpio_shift);
 635         uint32_t gpio_reg;
 636
 637         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 638                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 639                 return -1;
 640         }
 641
 642         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 643
 644         /* read GPIO and mask except the float bits */
 645         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 646
 647         switch (mode) {
 648         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 649                 /* clear FLOAT and set CLR */
 650                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 651                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 652                 break;
 653
 654         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 655                 /* clear FLOAT and set SET */
 656                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 657                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 658                 break;
 659
 660         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 661                 /* set FLOAT */
 662                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 663                 break;
 664
 665         default:
 666                 break;
 667         }
 668
 669         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 670         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 671
 672         return 0;
 673 }
 674
 675 static int
 676 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 677 {
 678         uint32_t gpio_reg;
 679
 680         /* any port swapping should be handled by caller */
 681
 682         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 683
 684         /* read GPIO and mask except the float bits */
 685         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 686         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 687         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 688         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 689
 690         switch (mode) {
 691         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 692                 /* set CLR */
 693                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 694                 break;
 695
 696         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 697                 /* set SET */
 698                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 699                 break;
 700
 701         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 702                 /* set FLOAT */
 703                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 704                 break;
 705
 706         default:
 707                 PMD_DRV_LOG(NOTICE, sc,
 708                             "Invalid GPIO mode assignment %d", mode);
 709                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 710                 return -1;
 711         }
 712
 713         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 714         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 715
 716         return 0;
 717 }
 718
 719 static int
 720 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 721                    uint8_t port)
 722 {
 723         /* The GPIO should be swapped if swap register is set and active */
 724         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 725                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 726         int gpio_shift = gpio_num;
 727         if (gpio_port)
 728                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 729
 730         uint32_t gpio_mask = (1 << gpio_shift);
 731         uint32_t gpio_reg;
 732
 733         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 734                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 735                 return -1;
 736         }
 737
 738         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 739
 740         /* read GPIO int */
 741         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 742
 743         switch (mode) {
 744         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 745                 /* clear SET and set CLR */
 746                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 747                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 748                 break;
 749
 750         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 751                 /* clear CLR and set SET */
 752                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 753                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 754                 break;
 755
 756         default:
 757                 break;
 758         }
 759
 760         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 761         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 762
 763         return 0;
 764 }
 765
 766 uint32_t
 767 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 768 {
 769         return bnx2x_gpio_read(sc, gpio_num, port);
 770 }
 771
 772 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 773                             uint8_t port)
 774 {
 775         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 776 }
 777
 778 uint8_t
 779 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 780                          uint8_t mode /* 0=low 1=high */ )
 781 {
 782         return bnx2x_gpio_mult_write(sc, pins, mode);
 783 }
 784
 785 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 786                                 uint8_t port)
 787 {
 788         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 789 }
 790
 791 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 792 {
 793         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 794                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 795 }
 796
 797 /* send the MCP a request, block until there is a reply */
 798 uint32_t
 799 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 800 {
 801         int mb_idx = SC_FW_MB_IDX(sc);
 802         uint32_t seq;
 803         uint32_t rc = 0;
 804         uint32_t cnt = 1;
 805         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 806
 807         seq = ++sc->fw_seq;
 808         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 809         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 810
 811         PMD_DRV_LOG(DEBUG, sc,
 812                     "wrote command 0x%08x to FW MB param 0x%08x",
 813                     (command | seq), param);
 814
 815         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 816         do {
 817                 DELAY(delay * 1000);
 818                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 819         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 820
 821         /* is this a reply to our command? */
 822         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 823                 rc &= FW_MSG_CODE_MASK;
 824         } else {
 825                 /* Ruh-roh! */
 826                 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
 827                 rc = 0;
 828         }
 829
 830         return rc;
 831 }
 832
 833 static uint32_t
 834 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 835 {
 836         return elink_cb_fw_command(sc, command, param);
 837 }
 838
 839 static void
 840 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 841                            rte_iova_t mapping)
 842 {
 843         REG_WR(sc, addr, U64_LO(mapping));
 844         REG_WR(sc, (addr + 4), U64_HI(mapping));
 845 }
 846
 847 static void
 848 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 849                       uint16_t abs_fid)
 850 {
 851         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 852                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 853         __storm_memset_dma_mapping(sc, addr, mapping);
 854 }
 855
 856 static void
 857 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 858 {
 859         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 860                 pf_id);
 861         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 862                 pf_id);
 863         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 864                 pf_id);
 865         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 866                 pf_id);
 867 }
 868
 869 static void
 870 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 871 {
 872         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 873                 enable);
 874         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 875                 enable);
 876         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 877                 enable);
 878         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 879                 enable);
 880 }
 881
 882 static void
 883 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 884                      uint16_t pfid)
 885 {
 886         uint32_t addr;
 887         size_t size;
 888
 889         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 890         size = sizeof(struct event_ring_data);
 891         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 892 }
 893
 894 static void
 895 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 896 {
 897         uint32_t addr = (BAR_CSTRORM_INTMEM +
 898                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 899         REG_WR16(sc, addr, eq_prod);
 900 }
 901
 902 /*
 903  * Post a slowpath command.
 904  *
 905  * A slowpath command is used to propagate a configuration change through
 906  * the controller in a controlled manner, allowing each STORM processor and
 907  * other H/W blocks to phase in the change.  The commands sent on the
 908  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 909  * completion of the ramrod will occur in different ways.  Here's a
 910  * breakdown of ramrods and how they complete:
 911  *
 912  * RAMROD_CMD_ID_ETH_PORT_SETUP
 913  *   Used to setup the leading connection on a port.  Completes on the
 914  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 915  *
 916  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 917  *   Used to setup an additional connection on a port.  Completes on the
 918  *   RCQ of the multi-queue/RSS connection being initialized.
 919  *
 920  * RAMROD_CMD_ID_ETH_STAT_QUERY
 921  *   Used to force the storm processors to update the statistics database
 922  *   in host memory.  This ramrod is send on the leading connection CID and
 923  *   completes as an index increment of the CSTORM on the default status
 924  *   block.
 925  *
 926  * RAMROD_CMD_ID_ETH_UPDATE
 927  *   Used to update the state of the leading connection, usually to udpate
 928  *   the RSS indirection table.  Completes on the RCQ of the leading
 929  *   connection. (Not currently used under FreeBSD until OS support becomes
 930  *   available.)
 931  *
 932  * RAMROD_CMD_ID_ETH_HALT
 933  *   Used when tearing down a connection prior to driver unload.  Completes
 934  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 935  *   use this on the leading connection.
 936  *
 937  * RAMROD_CMD_ID_ETH_SET_MAC
 938  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 939  *   the RCQ of the leading connection.
 940  *
 941  * RAMROD_CMD_ID_ETH_CFC_DEL
 942  *   Used when tearing down a conneciton prior to driver unload.  Completes
 943  *   on the RCQ of the leading connection (since the current connection
 944  *   has been completely removed from controller memory).
 945  *
 946  * RAMROD_CMD_ID_ETH_PORT_DEL
 947  *   Used to tear down the leading connection prior to driver unload,
 948  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 949  *   default status block.
 950  *
 951  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 952  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 953  *   RSS connection that is being offloaded.  (Not currently used under
 954  *   FreeBSD.)
 955  *
 956  * There can only be one command pending per function.
 957  *
 958  * Returns:
 959  *   0 = Success, !0 = Failure.
 960  */
 961
 962 /* must be called under the spq lock */
 963 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 964 {
 965         struct eth_spe *next_spe = sc->spq_prod_bd;
 966
 967         if (sc->spq_prod_bd == sc->spq_last_bd) {
 968                 /* wrap back to the first eth_spq */
 969                 sc->spq_prod_bd = sc->spq;
 970                 sc->spq_prod_idx = 0;
 971         } else {
 972                 sc->spq_prod_bd++;
 973                 sc->spq_prod_idx++;
 974         }
 975
 976         return next_spe;
 977 }
 978
 979 /* must be called under the spq lock */
 980 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 981 {
 982         int func = SC_FUNC(sc);
 983
 984         /*
 985          * Make sure that BD data is updated before writing the producer.
 986          * BD data is written to the memory, the producer is read from the
 987          * memory, thus we need a full memory barrier to ensure the ordering.
 988          */
 989         mb();
 990
 991         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 992                  sc->spq_prod_idx);
 993
 994         mb();
 995 }
 996
 997 /**
 998  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 999  *
1000  * @cmd:      command to check
1001  * @cmd_type: command type
1002  */
1003 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1004 {
1005         if ((cmd_type == NONE_CONNECTION_TYPE) ||
1006             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1007             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1008             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1009             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1010             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1011             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1012                 return TRUE;
1013         } else {
1014                 return FALSE;
1015         }
1016 }
1017
1018 /**
1019  * bnx2x_sp_post - place a single command on an SP ring
1020  *
1021  * @sc:         driver handle
1022  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1023  * @cid:        SW CID the command is related to
1024  * @data_hi:    command private data address (high 32 bits)
1025  * @data_lo:    command private data address (low 32 bits)
1026  * @cmd_type:   command type (e.g. NONE, ETH)
1027  *
1028  * SP data is handled as if it's always an address pair, thus data fields are
1029  * not swapped to little endian in upper functions. Instead this function swaps
1030  * data as if it's two uint32 fields.
1031  */
1032 int
1033 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1034             uint32_t data_lo, int cmd_type)
1035 {
1036         struct eth_spe *spe;
1037         uint16_t type;
1038         int common;
1039
1040         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1041
1042         if (common) {
1043                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1044                         PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1045                         return -1;
1046                 }
1047         } else {
1048                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1049                         PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1050                         return -1;
1051                 }
1052         }
1053
1054         spe = bnx2x_sp_get_next(sc);
1055
1056         /* CID needs port number to be encoded int it */
1057         spe->hdr.conn_and_cmd_data =
1058             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1059
1060         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1061
1062         /* TBD: Check if it works for VFs */
1063         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1064                  SPE_HDR_FUNCTION_ID);
1065
1066         spe->hdr.type = htole16(type);
1067
1068         spe->data.update_data_addr.hi = htole32(data_hi);
1069         spe->data.update_data_addr.lo = htole32(data_lo);
1070
1071         /*
1072          * It's ok if the actual decrement is issued towards the memory
1073          * somewhere between the lock and unlock. Thus no more explict
1074          * memory barrier is needed.
1075          */
1076         if (common) {
1077                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1078         } else {
1079                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1080         }
1081
1082         PMD_DRV_LOG(DEBUG, sc,
1083                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1084                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1085                     sc->spq_prod_idx,
1086                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1087                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1088                                 (uint8_t *) sc->spq_prod_bd -
1089                                 (uint8_t *) sc->spq), command, common,
1090                     HW_CID(sc, cid), data_hi, data_lo, type,
1091                     atomic_load_acq_long(&sc->cq_spq_left),
1092                     atomic_load_acq_long(&sc->eq_spq_left));
1093
1094         bnx2x_sp_prod_update(sc);
1095
1096         return 0;
1097 }
1098
1099 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1100 {
1101         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1102                  sc->fw_drv_pulse_wr_seq);
1103 }
1104
1105 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1106 {
1107         uint16_t hw_cons;
1108         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1109
1110         if (unlikely(!txq)) {
1111                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1112                 return 0;
1113         }
1114
1115         mb();                   /* status block fields can change */
1116         hw_cons = le16toh(*fp->tx_cons_sb);
1117         return hw_cons != txq->tx_pkt_head;
1118 }
1119
1120 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1121 {
1122         /* expand this for multi-cos if ever supported */
1123         return bnx2x_tx_queue_has_work(fp);
1124 }
1125
1126 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1127 {
1128         uint16_t rx_cq_cons_sb;
1129         struct bnx2x_rx_queue *rxq;
1130         rxq = fp->sc->rx_queues[fp->index];
1131         if (unlikely(!rxq)) {
1132                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1133                 return 0;
1134         }
1135
1136         mb();                   /* status block fields can change */
1137         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1138         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1139                      MAX_RCQ_ENTRIES(rxq)))
1140                 rx_cq_cons_sb++;
1141         return rxq->rx_cq_head != rx_cq_cons_sb;
1142 }
1143
1144 static void
1145 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1146              union eth_rx_cqe *rr_cqe)
1147 {
1148         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1149         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1150         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1151         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1152
1153         PMD_DRV_LOG(DEBUG, sc,
1154                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1155                     fp->index, cid, command, sc->state,
1156                     rr_cqe->ramrod_cqe.ramrod_type);
1157
1158         switch (command) {
1159         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1160                 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1161                 drv_cmd = ECORE_Q_CMD_UPDATE;
1162                 break;
1163
1164         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1165                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1166                 drv_cmd = ECORE_Q_CMD_SETUP;
1167                 break;
1168
1169         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1170                 PMD_DRV_LOG(DEBUG, sc,
1171                             "got MULTI[%d] tx-only setup ramrod", cid);
1172                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1173                 break;
1174
1175         case (RAMROD_CMD_ID_ETH_HALT):
1176                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1177                 drv_cmd = ECORE_Q_CMD_HALT;
1178                 break;
1179
1180         case (RAMROD_CMD_ID_ETH_TERMINATE):
1181                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1182                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1183                 break;
1184
1185         case (RAMROD_CMD_ID_ETH_EMPTY):
1186                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1187                 drv_cmd = ECORE_Q_CMD_EMPTY;
1188                 break;
1189
1190         default:
1191                 PMD_DRV_LOG(DEBUG, sc,
1192                             "ERROR: unexpected MC reply (%d)"
1193                             "on fp[%d]", command, fp->index);
1194                 return;
1195         }
1196
1197         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1198             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1199                 /*
1200                  * q_obj->complete_cmd() failure means that this was
1201                  * an unexpected completion.
1202                  *
1203                  * In this case we don't want to increase the sc->spq_left
1204                  * because apparently we haven't sent this command the first
1205                  * place.
1206                  */
1207                 // rte_panic("Unexpected SP completion");
1208                 return;
1209         }
1210
1211         atomic_add_acq_long(&sc->cq_spq_left, 1);
1212
1213         PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1214                     atomic_load_acq_long(&sc->cq_spq_left));
1215 }
1216
1217 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1218 {
1219         struct bnx2x_rx_queue *rxq;
1220         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1221         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1222
1223         rxq = sc->rx_queues[fp->index];
1224         if (!rxq) {
1225                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1226                 return 0;
1227         }
1228
1229         /* CQ "next element" is of the size of the regular element */
1230         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1231         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1232                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1233                 hw_cq_cons++;
1234         }
1235
1236         bd_cons = rxq->rx_bd_head;
1237         bd_prod = rxq->rx_bd_tail;
1238         bd_prod_fw = bd_prod;
1239         sw_cq_cons = rxq->rx_cq_head;
1240         sw_cq_prod = rxq->rx_cq_tail;
1241
1242         /*
1243          * Memory barrier necessary as speculative reads of the rx
1244          * buffer can be ahead of the index in the status block
1245          */
1246         rmb();
1247
1248         while (sw_cq_cons != hw_cq_cons) {
1249                 union eth_rx_cqe *cqe;
1250                 struct eth_fast_path_rx_cqe *cqe_fp;
1251                 uint8_t cqe_fp_flags;
1252                 enum eth_rx_cqe_type cqe_fp_type;
1253
1254                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1255                 bd_prod = RX_BD(bd_prod, rxq);
1256                 bd_cons = RX_BD(bd_cons, rxq);
1257
1258                 cqe = &rxq->cq_ring[comp_ring_cons];
1259                 cqe_fp = &cqe->fast_path_cqe;
1260                 cqe_fp_flags = cqe_fp->type_error_flags;
1261                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1262
1263                 /* is this a slowpath msg? */
1264                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1265                         bnx2x_sp_event(sc, fp, cqe);
1266                         goto next_cqe;
1267                 }
1268
1269                 /* is this an error packet? */
1270                 if (unlikely(cqe_fp_flags &
1271                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1272                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1273                                    cqe_fp_flags, sw_cq_cons);
1274                         goto next_rx;
1275                 }
1276
1277                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1278
1279 next_rx:
1280                 bd_cons = NEXT_RX_BD(bd_cons);
1281                 bd_prod = NEXT_RX_BD(bd_prod);
1282                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1283
1284 next_cqe:
1285                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1286                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1287
1288         }                       /* while work to do */
1289
1290         rxq->rx_bd_head = bd_cons;
1291         rxq->rx_bd_tail = bd_prod_fw;
1292         rxq->rx_cq_head = sw_cq_cons;
1293         rxq->rx_cq_tail = sw_cq_prod;
1294
1295         /* Update producers */
1296         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1297
1298         return sw_cq_cons != hw_cq_cons;
1299 }
1300
1301 static uint16_t
1302 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1303                 uint16_t pkt_idx, uint16_t bd_idx)
1304 {
1305         struct eth_tx_start_bd *tx_start_bd =
1306             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1307         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1308         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1309
1310         if (likely(tx_mbuf != NULL)) {
1311                 rte_pktmbuf_free_seg(tx_mbuf);
1312         } else {
1313                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1314                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1315         }
1316
1317         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1318         txq->nb_tx_avail += nbd;
1319
1320         while (nbd--)
1321                 bd_idx = NEXT_TX_BD(bd_idx);
1322
1323         return bd_idx;
1324 }
1325
1326 /* processes transmit completions */
1327 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1328 {
1329         uint16_t bd_cons, hw_cons, sw_cons;
1330         __rte_unused uint16_t tx_bd_avail;
1331
1332         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1333
1334         if (unlikely(!txq)) {
1335                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1336                 return 0;
1337         }
1338
1339         bd_cons = txq->tx_bd_head;
1340         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1341         sw_cons = txq->tx_pkt_head;
1342
1343         while (sw_cons != hw_cons) {
1344                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1345                 sw_cons++;
1346         }
1347
1348         txq->tx_pkt_head = sw_cons;
1349         txq->tx_bd_head = bd_cons;
1350
1351         tx_bd_avail = txq->nb_tx_avail;
1352
1353         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1354                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1355                    fp->index, tx_bd_avail, hw_cons,
1356                    txq->tx_pkt_head, txq->tx_pkt_tail,
1357                    txq->tx_bd_head, txq->tx_bd_tail);
1358         return TRUE;
1359 }
1360
1361 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1362 {
1363         struct bnx2x_fastpath *fp;
1364         int i, count;
1365
1366         /* wait until all TX fastpath tasks have completed */
1367         for (i = 0; i < sc->num_queues; i++) {
1368                 fp = &sc->fp[i];
1369
1370                 count = 1000;
1371
1372                 while (bnx2x_has_tx_work(fp)) {
1373                         bnx2x_txeof(sc, fp);
1374
1375                         if (count == 0) {
1376                                 PMD_TX_LOG(ERR,
1377                                            "Timeout waiting for fp[%d] "
1378                                            "transmits to complete!", i);
1379                                 rte_panic("tx drain failure");
1380                                 return;
1381                         }
1382
1383                         count--;
1384                         DELAY(1000);
1385                         rmb();
1386                 }
1387         }
1388
1389         return;
1390 }
1391
1392 static int
1393 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1394                  int mac_type, uint8_t wait_for_comp)
1395 {
1396         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1397         int rc;
1398
1399         /* wait for completion of requested */
1400         if (wait_for_comp) {
1401                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1402         }
1403
1404         /* Set the mac type of addresses we want to clear */
1405         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1406
1407         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1408         if (rc < 0)
1409                 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1410
1411         return rc;
1412 }
1413
1414 static int
1415 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1416                         unsigned long *rx_accept_flags,
1417                         unsigned long *tx_accept_flags)
1418 {
1419         /* Clear the flags first */
1420         *rx_accept_flags = 0;
1421         *tx_accept_flags = 0;
1422
1423         switch (rx_mode) {
1424         case BNX2X_RX_MODE_NONE:
1425                 /*
1426                  * 'drop all' supersedes any accept flags that may have been
1427                  * passed to the function.
1428                  */
1429                 break;
1430
1431         case BNX2X_RX_MODE_NORMAL:
1432                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1433                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1434                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1435
1436                 /* internal switching mode */
1437                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1438                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1439                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1440
1441                 break;
1442
1443         case BNX2X_RX_MODE_ALLMULTI:
1444                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1445                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1446                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1447
1448                 /* internal switching mode */
1449                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1450                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1451                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1452
1453                 break;
1454
1455         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1456         case BNX2X_RX_MODE_PROMISC:
1457                 /*
1458                  * According to deffinition of SI mode, iface in promisc mode
1459                  * should receive matched and unmatched (in resolution of port)
1460                  * unicast packets.
1461                  */
1462                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1463                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1464                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1465                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1466
1467                 /* internal switching mode */
1468                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1469                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1470
1471                 if (IS_MF_SI(sc)) {
1472                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1473                 } else {
1474                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1475                 }
1476
1477                 break;
1478
1479         default:
1480                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1481                 return -1;
1482         }
1483
1484         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1485         if (rx_mode != BNX2X_RX_MODE_NONE) {
1486                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1487                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1488         }
1489
1490         return 0;
1491 }
1492
1493 static int
1494 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1495                   unsigned long rx_mode_flags,
1496                   unsigned long rx_accept_flags,
1497                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1498 {
1499         struct ecore_rx_mode_ramrod_params ramrod_param;
1500         int rc;
1501
1502         memset(&ramrod_param, 0, sizeof(ramrod_param));
1503
1504         /* Prepare ramrod parameters */
1505         ramrod_param.cid = 0;
1506         ramrod_param.cl_id = cl_id;
1507         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1508         ramrod_param.func_id = SC_FUNC(sc);
1509
1510         ramrod_param.pstate = &sc->sp_state;
1511         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1512
1513         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1514         ramrod_param.rdata_mapping =
1515             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1516             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1517
1518         ramrod_param.ramrod_flags = ramrod_flags;
1519         ramrod_param.rx_mode_flags = rx_mode_flags;
1520
1521         ramrod_param.rx_accept_flags = rx_accept_flags;
1522         ramrod_param.tx_accept_flags = tx_accept_flags;
1523
1524         rc = ecore_config_rx_mode(sc, &ramrod_param);
1525         if (rc < 0) {
1526                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1527                 return rc;
1528         }
1529
1530         return 0;
1531 }
1532
1533 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1534 {
1535         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1536         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1537         int rc;
1538
1539         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1540                                    &tx_accept_flags);
1541         if (rc) {
1542                 return rc;
1543         }
1544
1545         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1546         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1547         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1548
1549         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1550                                  rx_accept_flags, tx_accept_flags,
1551                                  ramrod_flags);
1552 }
1553
1554 /* returns the "mcp load_code" according to global load_count array */
1555 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1556 {
1557         int path = SC_PATH(sc);
1558         int port = SC_PORT(sc);
1559
1560         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1561                     path, load_count[path][0], load_count[path][1],
1562                     load_count[path][2]);
1563
1564         load_count[path][0]++;
1565         load_count[path][1 + port]++;
1566         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1567                     path, load_count[path][0], load_count[path][1],
1568                     load_count[path][2]);
1569         if (load_count[path][0] == 1)
1570                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1571         else if (load_count[path][1 + port] == 1)
1572                 return FW_MSG_CODE_DRV_LOAD_PORT;
1573         else
1574                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1575 }
1576
1577 /* returns the "mcp load_code" according to global load_count array */
1578 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1579 {
1580         int port = SC_PORT(sc);
1581         int path = SC_PATH(sc);
1582
1583         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1584                     path, load_count[path][0], load_count[path][1],
1585                     load_count[path][2]);
1586         load_count[path][0]--;
1587         load_count[path][1 + port]--;
1588         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1589                     path, load_count[path][0], load_count[path][1],
1590                     load_count[path][2]);
1591         if (load_count[path][0] == 0) {
1592                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1593         } else if (load_count[path][1 + port] == 0) {
1594                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1595         } else {
1596                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1597         }
1598 }
1599
1600 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1601 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1602 {
1603         uint32_t reset_code = 0;
1604
1605         /* Select the UNLOAD request mode */
1606         if (unload_mode == UNLOAD_NORMAL) {
1607                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1608         } else {
1609                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1610         }
1611
1612         /* Send the request to the MCP */
1613         if (!BNX2X_NOMCP(sc)) {
1614                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1615         } else {
1616                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1617         }
1618
1619         return reset_code;
1620 }
1621
1622 /* send UNLOAD_DONE command to the MCP */
1623 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1624 {
1625         uint32_t reset_param =
1626             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1627
1628         /* Report UNLOAD_DONE to MCP */
1629         if (!BNX2X_NOMCP(sc)) {
1630                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1631         }
1632 }
1633
1634 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1635 {
1636         int tout = 50;
1637
1638         if (!sc->port.pmf) {
1639                 return 0;
1640         }
1641
1642         /*
1643          * (assumption: No Attention from MCP at this stage)
1644          * PMF probably in the middle of TX disable/enable transaction
1645          * 1. Sync IRS for default SB
1646          * 2. Sync SP queue - this guarantees us that attention handling started
1647          * 3. Wait, that TX disable/enable transaction completes
1648          *
1649          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1650          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1651          * received completion for the transaction the state is TX_STOPPED.
1652          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1653          * transaction.
1654          */
1655
1656         while (ecore_func_get_state(sc, &sc->func_obj) !=
1657                ECORE_F_STATE_STARTED && tout--) {
1658                 DELAY(20000);
1659         }
1660
1661         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1662                 /*
1663                  * Failed to complete the transaction in a "good way"
1664                  * Force both transactions with CLR bit.
1665                  */
1666                 struct ecore_func_state_params func_params = { NULL };
1667
1668                 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1669                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1670
1671                 func_params.f_obj = &sc->func_obj;
1672                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1673
1674                 /* STARTED-->TX_STOPPED */
1675                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1676                 ecore_func_state_change(sc, &func_params);
1677
1678                 /* TX_STOPPED-->STARTED */
1679                 func_params.cmd = ECORE_F_CMD_TX_START;
1680                 return ecore_func_state_change(sc, &func_params);
1681         }
1682
1683         return 0;
1684 }
1685
1686 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1687 {
1688         struct bnx2x_fastpath *fp = &sc->fp[index];
1689         struct ecore_queue_state_params q_params = { NULL };
1690         int rc;
1691
1692         PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1693
1694         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1695         /* We want to wait for completion in this context */
1696         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1697
1698         /* Stop the primary connection: */
1699
1700         /* ...halt the connection */
1701         q_params.cmd = ECORE_Q_CMD_HALT;
1702         rc = ecore_queue_state_change(sc, &q_params);
1703         if (rc) {
1704                 return rc;
1705         }
1706
1707         /* ...terminate the connection */
1708         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1709         memset(&q_params.params.terminate, 0,
1710                sizeof(q_params.params.terminate));
1711         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1712         rc = ecore_queue_state_change(sc, &q_params);
1713         if (rc) {
1714                 return rc;
1715         }
1716
1717         /* ...delete cfc entry */
1718         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1719         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1720         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1721         return ecore_queue_state_change(sc, &q_params);
1722 }
1723
1724 /* wait for the outstanding SP commands */
1725 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1726 {
1727         unsigned long tmp;
1728         int tout = 5000;        /* wait for 5 secs tops */
1729
1730         while (tout--) {
1731                 mb();
1732                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1733                         return TRUE;
1734                 }
1735
1736                 DELAY(1000);
1737         }
1738
1739         mb();
1740
1741         tmp = atomic_load_acq_long(&sc->sp_state);
1742         if (tmp & mask) {
1743                 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1744                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1745                 return FALSE;
1746         }
1747
1748         return FALSE;
1749 }
1750
1751 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1752 {
1753         struct ecore_func_state_params func_params = { NULL };
1754         int rc;
1755
1756         /* prepare parameters for function state transitions */
1757         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1758         func_params.f_obj = &sc->func_obj;
1759         func_params.cmd = ECORE_F_CMD_STOP;
1760
1761         /*
1762          * Try to stop the function the 'good way'. If it fails (in case
1763          * of a parity error during bnx2x_chip_cleanup()) and we are
1764          * not in a debug mode, perform a state transaction in order to
1765          * enable further HW_RESET transaction.
1766          */
1767         rc = ecore_func_state_change(sc, &func_params);
1768         if (rc) {
1769                 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1770                             "Running a dry transaction");
1771                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1772                 return ecore_func_state_change(sc, &func_params);
1773         }
1774
1775         return 0;
1776 }
1777
1778 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1779 {
1780         struct ecore_func_state_params func_params = { NULL };
1781
1782         /* Prepare parameters for function state transitions */
1783         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1784
1785         func_params.f_obj = &sc->func_obj;
1786         func_params.cmd = ECORE_F_CMD_HW_RESET;
1787
1788         func_params.params.hw_init.load_phase = load_code;
1789
1790         return ecore_func_state_change(sc, &func_params);
1791 }
1792
1793 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1794 {
1795         if (disable_hw) {
1796                 /* prevent the HW from sending interrupts */
1797                 bnx2x_int_disable(sc);
1798         }
1799 }
1800
1801 static void
1802 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1803 {
1804         int port = SC_PORT(sc);
1805         struct ecore_mcast_ramrod_params rparam = { NULL };
1806         uint32_t reset_code;
1807         int i, rc = 0;
1808
1809         bnx2x_drain_tx_queues(sc);
1810
1811         /* give HW time to discard old tx messages */
1812         DELAY(1000);
1813
1814         /* Clean all ETH MACs */
1815         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1816                               FALSE);
1817         if (rc < 0) {
1818                 PMD_DRV_LOG(NOTICE, sc,
1819                             "Failed to delete all ETH MACs (%d)", rc);
1820         }
1821
1822         /* Clean up UC list  */
1823         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1824                               TRUE);
1825         if (rc < 0) {
1826                 PMD_DRV_LOG(NOTICE, sc,
1827                             "Failed to delete UC MACs list (%d)", rc);
1828         }
1829
1830         /* Disable LLH */
1831         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1832
1833         /* Set "drop all" to stop Rx */
1834
1835         /*
1836          * We need to take the if_maddr_lock() here in order to prevent
1837          * a race between the completion code and this code.
1838          */
1839
1840         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1841                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1842         } else {
1843                 bnx2x_set_storm_rx_mode(sc);
1844         }
1845
1846         /* Clean up multicast configuration */
1847         rparam.mcast_obj = &sc->mcast_obj;
1848         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1849         if (rc < 0) {
1850                 PMD_DRV_LOG(NOTICE, sc,
1851                             "Failed to send DEL MCAST command (%d)", rc);
1852         }
1853
1854         /*
1855          * Send the UNLOAD_REQUEST to the MCP. This will return if
1856          * this function should perform FUNCTION, PORT, or COMMON HW
1857          * reset.
1858          */
1859         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1860
1861         /*
1862          * (assumption: No Attention from MCP at this stage)
1863          * PMF probably in the middle of TX disable/enable transaction
1864          */
1865         rc = bnx2x_func_wait_started(sc);
1866         if (rc) {
1867                 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1868         }
1869
1870         /*
1871          * Close multi and leading connections
1872          * Completions for ramrods are collected in a synchronous way
1873          */
1874         for (i = 0; i < sc->num_queues; i++) {
1875                 if (bnx2x_stop_queue(sc, i)) {
1876                         goto unload_error;
1877                 }
1878         }
1879
1880         /*
1881          * If SP settings didn't get completed so far - something
1882          * very wrong has happen.
1883          */
1884         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1885                 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1886         }
1887
1888 unload_error:
1889
1890         rc = bnx2x_func_stop(sc);
1891         if (rc) {
1892                 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1893         }
1894
1895         /* disable HW interrupts */
1896         bnx2x_int_disable_sync(sc, TRUE);
1897
1898         /* Reset the chip */
1899         rc = bnx2x_reset_hw(sc, reset_code);
1900         if (rc) {
1901                 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1902         }
1903
1904         /* Report UNLOAD_DONE to MCP */
1905         bnx2x_send_unload_done(sc, keep_link);
1906 }
1907
1908 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1909 {
1910         uint32_t val;
1911
1912         PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1913
1914         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1915         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1916                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1917         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1918 }
1919
1920 /*
1921  * Cleans the object that have internal lists without sending
1922  * ramrods. Should be run when interrutps are disabled.
1923  */
1924 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1925 {
1926         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1927         struct ecore_mcast_ramrod_params rparam = { NULL };
1928         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1929         int rc;
1930
1931         /* Cleanup MACs' object first... */
1932
1933         /* Wait for completion of requested */
1934         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1935         /* Perform a dry cleanup */
1936         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1937
1938         /* Clean ETH primary MAC */
1939         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1940         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1941                                  &ramrod_flags);
1942         if (rc != 0) {
1943                 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1944         }
1945
1946         /* Cleanup UC list */
1947         vlan_mac_flags = 0;
1948         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1949         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1950         if (rc != 0) {
1951                 PMD_DRV_LOG(NOTICE, sc,
1952                             "Failed to clean UC list MACs (%d)", rc);
1953         }
1954
1955         /* Now clean mcast object... */
1956
1957         rparam.mcast_obj = &sc->mcast_obj;
1958         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1959
1960         /* Add a DEL command... */
1961         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1962         if (rc < 0) {
1963                 PMD_DRV_LOG(NOTICE, sc,
1964                             "Failed to send DEL MCAST command (%d)", rc);
1965         }
1966
1967         /* now wait until all pending commands are cleared */
1968
1969         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1970         while (rc != 0) {
1971                 if (rc < 0) {
1972                         PMD_DRV_LOG(NOTICE, sc,
1973                                     "Failed to clean MCAST object (%d)", rc);
1974                         return;
1975                 }
1976
1977                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1978         }
1979 }
1980
1981 /* stop the controller */
1982 __rte_noinline
1983 int
1984 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1985 {
1986         uint8_t global = FALSE;
1987         uint32_t val;
1988
1989         PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
1990
1991         /* mark driver as unloaded in shmem2 */
1992         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1993                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1994                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1995                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1996         }
1997
1998         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1999             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2000                 /*
2001                  * We can get here if the driver has been unloaded
2002                  * during parity error recovery and is either waiting for a
2003                  * leader to complete or for other functions to unload and
2004                  * then ifconfig down has been issued. In this case we want to
2005                  * unload and let other functions to complete a recovery
2006                  * process.
2007                  */
2008                 sc->recovery_state = BNX2X_RECOVERY_DONE;
2009                 sc->is_leader = 0;
2010                 bnx2x_release_leader_lock(sc);
2011                 mb();
2012
2013                 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2014                 return -1;
2015         }
2016
2017         /*
2018          * Nothing to do during unload if previous bnx2x_nic_load()
2019          * did not completed successfully - all resourses are released.
2020          */
2021         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2022                 return 0;
2023         }
2024
2025         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2026         mb();
2027
2028         sc->rx_mode = BNX2X_RX_MODE_NONE;
2029         bnx2x_set_rx_mode(sc);
2030         mb();
2031
2032         if (IS_PF(sc)) {
2033                 /* set ALWAYS_ALIVE bit in shmem */
2034                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2035
2036                 bnx2x_drv_pulse(sc);
2037
2038                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2039                 bnx2x_save_statistics(sc);
2040         }
2041
2042         /* wait till consumers catch up with producers in all queues */
2043         bnx2x_drain_tx_queues(sc);
2044
2045         /* if VF indicate to PF this function is going down (PF will delete sp
2046          * elements and clear initializations
2047          */
2048         if (IS_VF(sc)) {
2049                 bnx2x_vf_unload(sc);
2050         } else if (unload_mode != UNLOAD_RECOVERY) {
2051                 /* if this is a normal/close unload need to clean up chip */
2052                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2053         } else {
2054                 /* Send the UNLOAD_REQUEST to the MCP */
2055                 bnx2x_send_unload_req(sc, unload_mode);
2056
2057                 /*
2058                  * Prevent transactions to host from the functions on the
2059                  * engine that doesn't reset global blocks in case of global
2060                  * attention once gloabl blocks are reset and gates are opened
2061                  * (the engine which leader will perform the recovery
2062                  * last).
2063                  */
2064                 if (!CHIP_IS_E1x(sc)) {
2065                         bnx2x_pf_disable(sc);
2066                 }
2067
2068                 /* disable HW interrupts */
2069                 bnx2x_int_disable_sync(sc, TRUE);
2070
2071                 /* Report UNLOAD_DONE to MCP */
2072                 bnx2x_send_unload_done(sc, FALSE);
2073         }
2074
2075         /*
2076          * At this stage no more interrupts will arrive so we may safely clean
2077          * the queue'able objects here in case they failed to get cleaned so far.
2078          */
2079         if (IS_PF(sc)) {
2080                 bnx2x_squeeze_objects(sc);
2081         }
2082
2083         /* There should be no more pending SP commands at this stage */
2084         sc->sp_state = 0;
2085
2086         sc->port.pmf = 0;
2087
2088         if (IS_PF(sc)) {
2089                 bnx2x_free_mem(sc);
2090         }
2091
2092         bnx2x_free_fw_stats_mem(sc);
2093
2094         sc->state = BNX2X_STATE_CLOSED;
2095
2096         /*
2097          * Check if there are pending parity attentions. If there are - set
2098          * RECOVERY_IN_PROGRESS.
2099          */
2100         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2101                 bnx2x_set_reset_in_progress(sc);
2102
2103                 /* Set RESET_IS_GLOBAL if needed */
2104                 if (global) {
2105                         bnx2x_set_reset_global(sc);
2106                 }
2107         }
2108
2109         /*
2110          * The last driver must disable a "close the gate" if there is no
2111          * parity attention or "process kill" pending.
2112          */
2113         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2114             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2115                 bnx2x_disable_close_the_gate(sc);
2116         }
2117
2118         PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2119
2120         return 0;
2121 }
2122
2123 /*
2124  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2125  * visible to the controller.
2126  *
2127  * If an mbuf is submitted to this routine and cannot be given to the
2128  * controller (e.g. it has too many fragments) then the function may free
2129  * the mbuf and return to the caller.
2130  *
2131  * Returns:
2132  *     int: Number of TX BDs used for the mbuf
2133  *
2134  *   Note the side effect that an mbuf may be freed if it causes a problem.
2135  */
2136 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2137 {
2138         struct eth_tx_start_bd *tx_start_bd;
2139         uint16_t bd_prod, pkt_prod;
2140         struct bnx2x_softc *sc;
2141         uint32_t nbds = 0;
2142
2143         sc = txq->sc;
2144         bd_prod = txq->tx_bd_tail;
2145         pkt_prod = txq->tx_pkt_tail;
2146
2147         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2148
2149         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2150
2151         tx_start_bd->addr =
2152             rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2153         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2154         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2155         tx_start_bd->general_data =
2156             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2157
2158         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2159
2160         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2161                 tx_start_bd->vlan_or_ethertype =
2162                     rte_cpu_to_le_16(m0->vlan_tci);
2163                 tx_start_bd->bd_flags.as_bitfield |=
2164                     (X_ETH_OUTBAND_VLAN <<
2165                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2166         } else {
2167                 if (IS_PF(sc))
2168                         tx_start_bd->vlan_or_ethertype =
2169                             rte_cpu_to_le_16(pkt_prod);
2170                 else {
2171                         struct ether_hdr *eh =
2172                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2173
2174                         tx_start_bd->vlan_or_ethertype =
2175                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2176                 }
2177         }
2178
2179         bd_prod = NEXT_TX_BD(bd_prod);
2180         if (IS_VF(sc)) {
2181                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2182                 const struct ether_hdr *eh =
2183                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2184                 uint8_t mac_type = UNICAST_ADDRESS;
2185
2186                 tx_parse_bd =
2187                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2188                 if (is_multicast_ether_addr(&eh->d_addr)) {
2189                         if (is_broadcast_ether_addr(&eh->d_addr))
2190                                 mac_type = BROADCAST_ADDRESS;
2191                         else
2192                                 mac_type = MULTICAST_ADDRESS;
2193                 }
2194                 tx_parse_bd->parsing_data =
2195                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2196
2197                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2198                            &eh->d_addr.addr_bytes[0], 2);
2199                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2200                            &eh->d_addr.addr_bytes[2], 2);
2201                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2202                            &eh->d_addr.addr_bytes[4], 2);
2203                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2204                            &eh->s_addr.addr_bytes[0], 2);
2205                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2206                            &eh->s_addr.addr_bytes[2], 2);
2207                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2208                            &eh->s_addr.addr_bytes[4], 2);
2209
2210                 tx_parse_bd->data.mac_addr.dst_hi =
2211                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2212                 tx_parse_bd->data.mac_addr.dst_mid =
2213                     rte_cpu_to_be_16(tx_parse_bd->data.
2214                                      mac_addr.dst_mid);
2215                 tx_parse_bd->data.mac_addr.dst_lo =
2216                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2217                 tx_parse_bd->data.mac_addr.src_hi =
2218                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2219                 tx_parse_bd->data.mac_addr.src_mid =
2220                     rte_cpu_to_be_16(tx_parse_bd->data.
2221                                      mac_addr.src_mid);
2222                 tx_parse_bd->data.mac_addr.src_lo =
2223                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2224
2225                 PMD_TX_LOG(DEBUG,
2226                            "PBD dst %x %x %x src %x %x %x p_data %x",
2227                            tx_parse_bd->data.mac_addr.dst_hi,
2228                            tx_parse_bd->data.mac_addr.dst_mid,
2229                            tx_parse_bd->data.mac_addr.dst_lo,
2230                            tx_parse_bd->data.mac_addr.src_hi,
2231                            tx_parse_bd->data.mac_addr.src_mid,
2232                            tx_parse_bd->data.mac_addr.src_lo,
2233                            tx_parse_bd->parsing_data);
2234         }
2235
2236         PMD_TX_LOG(DEBUG,
2237                    "start bd: nbytes %d flags %x vlan %x",
2238                    tx_start_bd->nbytes,
2239                    tx_start_bd->bd_flags.as_bitfield,
2240                    tx_start_bd->vlan_or_ethertype);
2241
2242         bd_prod = NEXT_TX_BD(bd_prod);
2243         pkt_prod++;
2244
2245         if (TX_IDX(bd_prod) < 2)
2246                 nbds++;
2247
2248         txq->nb_tx_avail -= 2;
2249         txq->tx_bd_tail = bd_prod;
2250         txq->tx_pkt_tail = pkt_prod;
2251
2252         return nbds + 2;
2253 }
2254
2255 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2256 {
2257         return L2_ILT_LINES(sc);
2258 }
2259
2260 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2261 {
2262         struct ilt_client_info *ilt_client;
2263         struct ecore_ilt *ilt = sc->ilt;
2264         uint16_t line = 0;
2265
2266         PMD_INIT_FUNC_TRACE(sc);
2267
2268         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2269
2270         /* CDU */
2271         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2272         ilt_client->client_num = ILT_CLIENT_CDU;
2273         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2274         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2275         ilt_client->start = line;
2276         line += bnx2x_cid_ilt_lines(sc);
2277
2278         if (CNIC_SUPPORT(sc)) {
2279                 line += CNIC_ILT_LINES;
2280         }
2281
2282         ilt_client->end = (line - 1);
2283
2284         /* QM */
2285         if (QM_INIT(sc->qm_cid_count)) {
2286                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2287                 ilt_client->client_num = ILT_CLIENT_QM;
2288                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2289                 ilt_client->flags = 0;
2290                 ilt_client->start = line;
2291
2292                 /* 4 bytes for each cid */
2293                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2294                                      QM_ILT_PAGE_SZ);
2295
2296                 ilt_client->end = (line - 1);
2297         }
2298
2299         if (CNIC_SUPPORT(sc)) {
2300                 /* SRC */
2301                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2302                 ilt_client->client_num = ILT_CLIENT_SRC;
2303                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2304                 ilt_client->flags = 0;
2305                 ilt_client->start = line;
2306                 line += SRC_ILT_LINES;
2307                 ilt_client->end = (line - 1);
2308
2309                 /* TM */
2310                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2311                 ilt_client->client_num = ILT_CLIENT_TM;
2312                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2313                 ilt_client->flags = 0;
2314                 ilt_client->start = line;
2315                 line += TM_ILT_LINES;
2316                 ilt_client->end = (line - 1);
2317         }
2318
2319         assert((line <= ILT_MAX_LINES));
2320 }
2321
2322 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2323 {
2324         int i;
2325
2326         for (i = 0; i < sc->num_queues; i++) {
2327                 /* get the Rx buffer size for RX frames */
2328                 sc->fp[i].rx_buf_size =
2329                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2330         }
2331 }
2332
2333 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2334 {
2335
2336         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2337
2338         return sc->ilt == NULL;
2339 }
2340
2341 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2342 {
2343         sc->ilt->lines = rte_calloc("",
2344                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2345                                     RTE_CACHE_LINE_SIZE);
2346         return sc->ilt->lines == NULL;
2347 }
2348
2349 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2350 {
2351         rte_free(sc->ilt);
2352         sc->ilt = NULL;
2353 }
2354
2355 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2356 {
2357         if (sc->ilt->lines != NULL) {
2358                 rte_free(sc->ilt->lines);
2359                 sc->ilt->lines = NULL;
2360         }
2361 }
2362
2363 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2364 {
2365         uint32_t i;
2366
2367         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2368                 sc->context[i].vcxt = NULL;
2369                 sc->context[i].size = 0;
2370         }
2371
2372         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2373
2374         bnx2x_free_ilt_lines_mem(sc);
2375 }
2376
2377 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2378 {
2379         int context_size;
2380         int allocated;
2381         int i;
2382         char cdu_name[RTE_MEMZONE_NAMESIZE];
2383
2384         /*
2385          * Allocate memory for CDU context:
2386          * This memory is allocated separately and not in the generic ILT
2387          * functions because CDU differs in few aspects:
2388          * 1. There can be multiple entities allocating memory for context -
2389          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2390          * its own ILT lines.
2391          * 2. Since CDU page-size is not a single 4KB page (which is the case
2392          * for the other ILT clients), to be efficient we want to support
2393          * allocation of sub-page-size in the last entry.
2394          * 3. Context pointers are used by the driver to pass to FW / update
2395          * the context (for the other ILT clients the pointers are used just to
2396          * free the memory during unload).
2397          */
2398         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2399         for (i = 0, allocated = 0; allocated < context_size; i++) {
2400                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2401                                           (context_size - allocated));
2402
2403                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2404                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2405                                   &sc->context[i].vcxt_dma,
2406                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2407                         bnx2x_free_mem(sc);
2408                         return -1;
2409                 }
2410
2411                 sc->context[i].vcxt =
2412                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2413
2414                 allocated += sc->context[i].size;
2415         }
2416
2417         bnx2x_alloc_ilt_lines_mem(sc);
2418
2419         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2420                 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2421                 bnx2x_free_mem(sc);
2422                 return -1;
2423         }
2424
2425         return 0;
2426 }
2427
2428 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2429 {
2430         sc->fw_stats_num = 0;
2431
2432         sc->fw_stats_req_size = 0;
2433         sc->fw_stats_req = NULL;
2434         sc->fw_stats_req_mapping = 0;
2435
2436         sc->fw_stats_data_size = 0;
2437         sc->fw_stats_data = NULL;
2438         sc->fw_stats_data_mapping = 0;
2439 }
2440
2441 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2442 {
2443         uint8_t num_queue_stats;
2444         int num_groups, vf_headroom = 0;
2445
2446         /* number of queues for statistics is number of eth queues */
2447         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2448
2449         /*
2450          * Total number of FW statistics requests =
2451          *   1 for port stats + 1 for PF stats + num of queues
2452          */
2453         sc->fw_stats_num = (2 + num_queue_stats);
2454
2455         /*
2456          * Request is built from stats_query_header and an array of
2457          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2458          * rules. The real number or requests is configured in the
2459          * stats_query_header.
2460          */
2461         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2462         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2463                 num_groups++;
2464
2465         sc->fw_stats_req_size =
2466             (sizeof(struct stats_query_header) +
2467              (num_groups * sizeof(struct stats_query_cmd_group)));
2468
2469         /*
2470          * Data for statistics requests + stats_counter.
2471          * stats_counter holds per-STORM counters that are incremented when
2472          * STORM has finished with the current request. Memory for FCoE
2473          * offloaded statistics are counted anyway, even if they will not be sent.
2474          * VF stats are not accounted for here as the data of VF stats is stored
2475          * in memory allocated by the VF, not here.
2476          */
2477         sc->fw_stats_data_size =
2478             (sizeof(struct stats_counter) +
2479              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2480              /* sizeof(struct fcoe_statistics_params) + */
2481              (sizeof(struct per_queue_stats) * num_queue_stats));
2482
2483         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2484                           &sc->fw_stats_dma, "fw_stats",
2485                           RTE_CACHE_LINE_SIZE) != 0) {
2486                 bnx2x_free_fw_stats_mem(sc);
2487                 return -1;
2488         }
2489
2490         /* set up the shortcuts */
2491
2492         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2493         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2494
2495         sc->fw_stats_data =
2496             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2497                                          sc->fw_stats_req_size);
2498         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2499                                      sc->fw_stats_req_size);
2500
2501         return 0;
2502 }
2503
2504 /*
2505  * Bits map:
2506  * 0-7  - Engine0 load counter.
2507  * 8-15 - Engine1 load counter.
2508  * 16   - Engine0 RESET_IN_PROGRESS bit.
2509  * 17   - Engine1 RESET_IN_PROGRESS bit.
2510  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2511  *        function on the engine
2512  * 19   - Engine1 ONE_IS_LOADED.
2513  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2514  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2515  *        for just the one belonging to its engine).
2516  */
2517 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2518 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2519 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2520 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2521 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2522 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2523 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2524 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2525
2526 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2527 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2528 {
2529         uint32_t val;
2530         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2531         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2532         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2533         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2534 }
2535
2536 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2537 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2538 {
2539         uint32_t val;
2540         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2541         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2542         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2543         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2544 }
2545
2546 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2547 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2548 {
2549         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2550 }
2551
2552 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2553 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2554 {
2555         uint32_t val;
2556         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2557             BNX2X_PATH0_RST_IN_PROG_BIT;
2558
2559         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2560
2561         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2562         /* Clear the bit */
2563         val &= ~bit;
2564         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2565
2566         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2567 }
2568
2569 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2570 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2571 {
2572         uint32_t val;
2573         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2574             BNX2X_PATH0_RST_IN_PROG_BIT;
2575
2576         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2577
2578         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2579         /* Set the bit */
2580         val |= bit;
2581         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2582
2583         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2584 }
2585
2586 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2587 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2588 {
2589         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2590         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2591             BNX2X_PATH0_RST_IN_PROG_BIT;
2592
2593         /* return false if bit is set */
2594         return (val & bit) ? FALSE : TRUE;
2595 }
2596
2597 /* get the load status for an engine, should be run under rtnl lock */
2598 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2599 {
2600         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2601             BNX2X_PATH0_LOAD_CNT_MASK;
2602         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2603             BNX2X_PATH0_LOAD_CNT_SHIFT;
2604         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2605
2606         val = ((val & mask) >> shift);
2607
2608         return val != 0;
2609 }
2610
2611 /* set pf load mark */
2612 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2613 {
2614         uint32_t val;
2615         uint32_t val1;
2616         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2617             BNX2X_PATH0_LOAD_CNT_MASK;
2618         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2619             BNX2X_PATH0_LOAD_CNT_SHIFT;
2620
2621         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2622
2623         PMD_INIT_FUNC_TRACE(sc);
2624
2625         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2626
2627         /* get the current counter value */
2628         val1 = ((val & mask) >> shift);
2629
2630         /* set bit of this PF */
2631         val1 |= (1 << SC_ABS_FUNC(sc));
2632
2633         /* clear the old value */
2634         val &= ~mask;
2635
2636         /* set the new one */
2637         val |= ((val1 << shift) & mask);
2638
2639         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2640
2641         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2642 }
2643
2644 /* clear pf load mark */
2645 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2646 {
2647         uint32_t val1, val;
2648         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2649             BNX2X_PATH0_LOAD_CNT_MASK;
2650         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2651             BNX2X_PATH0_LOAD_CNT_SHIFT;
2652
2653         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2654         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2655
2656         /* get the current counter value */
2657         val1 = (val & mask) >> shift;
2658
2659         /* clear bit of that PF */
2660         val1 &= ~(1 << SC_ABS_FUNC(sc));
2661
2662         /* clear the old value */
2663         val &= ~mask;
2664
2665         /* set the new one */
2666         val |= ((val1 << shift) & mask);
2667
2668         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2669         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2670         return val1 != 0;
2671 }
2672
2673 /* send load requrest to mcp and analyze response */
2674 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2675 {
2676         PMD_INIT_FUNC_TRACE(sc);
2677
2678         /* init fw_seq */
2679         sc->fw_seq =
2680             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2681              DRV_MSG_SEQ_NUMBER_MASK);
2682
2683         PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2684
2685 #ifdef BNX2X_PULSE
2686         /* get the current FW pulse sequence */
2687         sc->fw_drv_pulse_wr_seq =
2688             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2689              DRV_PULSE_SEQ_MASK);
2690 #else
2691         /* set ALWAYS_ALIVE bit in shmem */
2692         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2693         bnx2x_drv_pulse(sc);
2694 #endif
2695
2696         /* load request */
2697         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2698                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2699
2700         /* if the MCP fails to respond we must abort */
2701         if (!(*load_code)) {
2702                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2703                 return -1;
2704         }
2705
2706         /* if MCP refused then must abort */
2707         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2708                 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2709                 return -1;
2710         }
2711
2712         return 0;
2713 }
2714
2715 /*
2716  * Check whether another PF has already loaded FW to chip. In virtualized
2717  * environments a pf from anoth VM may have already initialized the device
2718  * including loading FW.
2719  */
2720 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2721 {
2722         uint32_t my_fw, loaded_fw;
2723
2724         /* is another pf loaded on this engine? */
2725         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2726             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2727                 /* build my FW version dword */
2728                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2729                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2730                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2731                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2732
2733                 /* read loaded FW from chip */
2734                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2735                 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2736                             loaded_fw, my_fw);
2737
2738                 /* abort nic load if version mismatch */
2739                 if (my_fw != loaded_fw) {
2740                         PMD_DRV_LOG(NOTICE, sc,
2741                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2742                                     loaded_fw, my_fw);
2743                         return -1;
2744                 }
2745         }
2746
2747         return 0;
2748 }
2749
2750 /* mark PMF if applicable */
2751 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2752 {
2753         uint32_t ncsi_oem_data_addr;
2754
2755         PMD_INIT_FUNC_TRACE(sc);
2756
2757         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2758             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2759             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2760                 /*
2761                  * Barrier here for ordering between the writing to sc->port.pmf here
2762                  * and reading it from the periodic task.
2763                  */
2764                 sc->port.pmf = 1;
2765                 mb();
2766         } else {
2767                 sc->port.pmf = 0;
2768         }
2769
2770         PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2771
2772         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2773                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2774                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2775                         if (ncsi_oem_data_addr) {
2776                                 REG_WR(sc,
2777                                        (ncsi_oem_data_addr +
2778                                         offsetof(struct glob_ncsi_oem_data,
2779                                                  driver_version)), 0);
2780                         }
2781                 }
2782         }
2783 }
2784
2785 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2786 {
2787         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2788         int abs_func;
2789         int vn;
2790
2791         if (BNX2X_NOMCP(sc)) {
2792                 return;         /* what should be the default bvalue in this case */
2793         }
2794
2795         /*
2796          * The formula for computing the absolute function number is...
2797          * For 2 port configuration (4 functions per port):
2798          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2799          * For 4 port configuration (2 functions per port):
2800          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2801          */
2802         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2803                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2804                 if (abs_func >= E1H_FUNC_MAX) {
2805                         break;
2806                 }
2807                 sc->devinfo.mf_info.mf_config[vn] =
2808                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2809         }
2810
2811         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2812             FUNC_MF_CFG_FUNC_DISABLED) {
2813                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2814                 sc->flags |= BNX2X_MF_FUNC_DIS;
2815         } else {
2816                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2817                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2818         }
2819 }
2820
2821 /* acquire split MCP access lock register */
2822 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2823 {
2824         uint32_t j, val;
2825
2826         for (j = 0; j < 1000; j++) {
2827                 val = (1UL << 31);
2828                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2829                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2830                 if (val & (1L << 31))
2831                         break;
2832
2833                 DELAY(5000);
2834         }
2835
2836         if (!(val & (1L << 31))) {
2837                 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2838                 return -1;
2839         }
2840
2841         return 0;
2842 }
2843
2844 /* release split MCP access lock register */
2845 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2846 {
2847         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2848 }
2849
2850 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2851 {
2852         int port = SC_PORT(sc);
2853         uint32_t ext_phy_config;
2854
2855         /* mark the failure */
2856         ext_phy_config =
2857             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2858
2859         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2860         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2861         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2862                  ext_phy_config);
2863
2864         /* log the failure */
2865         PMD_DRV_LOG(INFO, sc,
2866                     "Fan Failure has caused the driver to shutdown "
2867                     "the card to prevent permanent damage. "
2868                     "Please contact OEM Support for assistance");
2869
2870         rte_panic("Schedule task to handle fan failure");
2871 }
2872
2873 /* this function is called upon a link interrupt */
2874 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2875 {
2876         uint32_t pause_enabled = 0;
2877         struct host_port_stats *pstats;
2878         int cmng_fns;
2879
2880         /* Make sure that we are synced with the current statistics */
2881         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2882
2883         elink_link_update(&sc->link_params, &sc->link_vars);
2884
2885         if (sc->link_vars.link_up) {
2886
2887                 /* dropless flow control */
2888                 if (sc->dropless_fc) {
2889                         pause_enabled = 0;
2890
2891                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2892                                 pause_enabled = 1;
2893                         }
2894
2895                         REG_WR(sc,
2896                                (BAR_USTRORM_INTMEM +
2897                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2898                                pause_enabled);
2899                 }
2900
2901                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2902                         pstats = BNX2X_SP(sc, port_stats);
2903                         /* reset old mac stats */
2904                         memset(&(pstats->mac_stx[0]), 0,
2905                                sizeof(struct mac_stx));
2906                 }
2907
2908                 if (sc->state == BNX2X_STATE_OPEN) {
2909                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2910                 }
2911         }
2912
2913         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2914                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2915
2916                 if (cmng_fns != CMNG_FNS_NONE) {
2917                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2918                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2919                 }
2920         }
2921
2922         bnx2x_link_report_locked(sc);
2923
2924         if (IS_MF(sc)) {
2925                 bnx2x_link_sync_notify(sc);
2926         }
2927 }
2928
2929 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2930 {
2931         int port = SC_PORT(sc);
2932         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2933             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2934         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2935             NIG_REG_MASK_INTERRUPT_PORT0;
2936         uint32_t aeu_mask;
2937         uint32_t nig_mask = 0;
2938         uint32_t reg_addr;
2939         uint32_t igu_acked;
2940         uint32_t cnt;
2941
2942         if (sc->attn_state & asserted) {
2943                 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2944         }
2945
2946         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2947
2948         aeu_mask = REG_RD(sc, aeu_addr);
2949
2950         aeu_mask &= ~(asserted & 0x3ff);
2951
2952         REG_WR(sc, aeu_addr, aeu_mask);
2953
2954         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2955
2956         sc->attn_state |= asserted;
2957
2958         if (asserted & ATTN_HARD_WIRED_MASK) {
2959                 if (asserted & ATTN_NIG_FOR_FUNC) {
2960
2961                         bnx2x_acquire_phy_lock(sc);
2962                         /* save nig interrupt mask */
2963                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2964
2965                         /* If nig_mask is not set, no need to call the update function */
2966                         if (nig_mask) {
2967                                 REG_WR(sc, nig_int_mask_addr, 0);
2968
2969                                 bnx2x_link_attn(sc);
2970                         }
2971
2972                         /* handle unicore attn? */
2973                 }
2974
2975                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2976                         PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
2977                 }
2978
2979                 if (asserted & GPIO_2_FUNC) {
2980                         PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
2981                 }
2982
2983                 if (asserted & GPIO_3_FUNC) {
2984                         PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
2985                 }
2986
2987                 if (asserted & GPIO_4_FUNC) {
2988                         PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
2989                 }
2990
2991                 if (port == 0) {
2992                         if (asserted & ATTN_GENERAL_ATTN_1) {
2993                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
2994                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2995                         }
2996                         if (asserted & ATTN_GENERAL_ATTN_2) {
2997                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
2998                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2999                         }
3000                         if (asserted & ATTN_GENERAL_ATTN_3) {
3001                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3002                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3003                         }
3004                 } else {
3005                         if (asserted & ATTN_GENERAL_ATTN_4) {
3006                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3007                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3008                         }
3009                         if (asserted & ATTN_GENERAL_ATTN_5) {
3010                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3011                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3012                         }
3013                         if (asserted & ATTN_GENERAL_ATTN_6) {
3014                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3015                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3016                         }
3017                 }
3018         }
3019         /* hardwired */
3020         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3021                 reg_addr =
3022                     (HC_REG_COMMAND_REG + port * 32 +
3023                      COMMAND_REG_ATTN_BITS_SET);
3024         } else {
3025                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3026         }
3027
3028         PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3029                     asserted,
3030                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3031                     reg_addr);
3032         REG_WR(sc, reg_addr, asserted);
3033
3034         /* now set back the mask */
3035         if (asserted & ATTN_NIG_FOR_FUNC) {
3036                 /*
3037                  * Verify that IGU ack through BAR was written before restoring
3038                  * NIG mask. This loop should exit after 2-3 iterations max.
3039                  */
3040                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3041                         cnt = 0;
3042
3043                         do {
3044                                 igu_acked =
3045                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3046                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3047                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3048
3049                         if (!igu_acked) {
3050                                 PMD_DRV_LOG(ERR, sc,
3051                                             "Failed to verify IGU ack on time");
3052                         }
3053
3054                         mb();
3055                 }
3056
3057                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3058
3059                 bnx2x_release_phy_lock(sc);
3060         }
3061 }
3062
3063 static void
3064 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3065                      __rte_unused const char *blk)
3066 {
3067         PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3068 }
3069
3070 static int
3071 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3072                               uint8_t print)
3073 {
3074         uint32_t cur_bit = 0;
3075         int i = 0;
3076
3077         for (i = 0; sig; i++) {
3078                 cur_bit = ((uint32_t) 0x1 << i);
3079                 if (sig & cur_bit) {
3080                         switch (cur_bit) {
3081                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3082                                 if (print)
3083                                         bnx2x_print_next_block(sc, par_num++,
3084                                                              "BRB");
3085                                 break;
3086                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3087                                 if (print)
3088                                         bnx2x_print_next_block(sc, par_num++,
3089                                                              "PARSER");
3090                                 break;
3091                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3092                                 if (print)
3093                                         bnx2x_print_next_block(sc, par_num++,
3094                                                              "TSDM");
3095                                 break;
3096                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3097                                 if (print)
3098                                         bnx2x_print_next_block(sc, par_num++,
3099                                                              "SEARCHER");
3100                                 break;
3101                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3102                                 if (print)
3103                                         bnx2x_print_next_block(sc, par_num++,
3104                                                              "TCM");
3105                                 break;
3106                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3107                                 if (print)
3108                                         bnx2x_print_next_block(sc, par_num++,
3109                                                              "TSEMI");
3110                                 break;
3111                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3112                                 if (print)
3113                                         bnx2x_print_next_block(sc, par_num++,
3114                                                              "XPB");
3115                                 break;
3116                         }
3117
3118                         /* Clear the bit */
3119                         sig &= ~cur_bit;
3120                 }
3121         }
3122
3123         return par_num;
3124 }
3125
3126 static int
3127 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3128                               uint8_t * global, uint8_t print)
3129 {
3130         int i = 0;
3131         uint32_t cur_bit = 0;
3132         for (i = 0; sig; i++) {
3133                 cur_bit = ((uint32_t) 0x1 << i);
3134                 if (sig & cur_bit) {
3135                         switch (cur_bit) {
3136                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3137                                 if (print)
3138                                         bnx2x_print_next_block(sc, par_num++,
3139                                                              "PBF");
3140                                 break;
3141                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3142                                 if (print)
3143                                         bnx2x_print_next_block(sc, par_num++,
3144                                                              "QM");
3145                                 break;
3146                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3147                                 if (print)
3148                                         bnx2x_print_next_block(sc, par_num++,
3149                                                              "TM");
3150                                 break;
3151                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3152                                 if (print)
3153                                         bnx2x_print_next_block(sc, par_num++,
3154                                                              "XSDM");
3155                                 break;
3156                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3157                                 if (print)
3158                                         bnx2x_print_next_block(sc, par_num++,
3159                                                              "XCM");
3160                                 break;
3161                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3162                                 if (print)
3163                                         bnx2x_print_next_block(sc, par_num++,
3164                                                              "XSEMI");
3165                                 break;
3166                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3167                                 if (print)
3168                                         bnx2x_print_next_block(sc, par_num++,
3169                                                              "DOORBELLQ");
3170                                 break;
3171                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3172                                 if (print)
3173                                         bnx2x_print_next_block(sc, par_num++,
3174                                                              "NIG");
3175                                 break;
3176                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3177                                 if (print)
3178                                         bnx2x_print_next_block(sc, par_num++,
3179                                                              "VAUX PCI CORE");
3180                                 *global = TRUE;
3181                                 break;
3182                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3183                                 if (print)
3184                                         bnx2x_print_next_block(sc, par_num++,
3185                                                              "DEBUG");
3186                                 break;
3187                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3188                                 if (print)
3189                                         bnx2x_print_next_block(sc, par_num++,
3190                                                              "USDM");
3191                                 break;
3192                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3193                                 if (print)
3194                                         bnx2x_print_next_block(sc, par_num++,
3195                                                              "UCM");
3196                                 break;
3197                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3198                                 if (print)
3199                                         bnx2x_print_next_block(sc, par_num++,
3200                                                              "USEMI");
3201                                 break;
3202                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3203                                 if (print)
3204                                         bnx2x_print_next_block(sc, par_num++,
3205                                                              "UPB");
3206                                 break;
3207                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3208                                 if (print)
3209                                         bnx2x_print_next_block(sc, par_num++,
3210                                                              "CSDM");
3211                                 break;
3212                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3213                                 if (print)
3214                                         bnx2x_print_next_block(sc, par_num++,
3215                                                              "CCM");
3216                                 break;
3217                         }
3218
3219                         /* Clear the bit */
3220                         sig &= ~cur_bit;
3221                 }
3222         }
3223
3224         return par_num;
3225 }
3226
3227 static int
3228 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3229                               uint8_t print)
3230 {
3231         uint32_t cur_bit = 0;
3232         int i = 0;
3233
3234         for (i = 0; sig; i++) {
3235                 cur_bit = ((uint32_t) 0x1 << i);
3236                 if (sig & cur_bit) {
3237                         switch (cur_bit) {
3238                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3239                                 if (print)
3240                                         bnx2x_print_next_block(sc, par_num++,
3241                                                              "CSEMI");
3242                                 break;
3243                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3244                                 if (print)
3245                                         bnx2x_print_next_block(sc, par_num++,
3246                                                              "PXP");
3247                                 break;
3248                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3249                                 if (print)
3250                                         bnx2x_print_next_block(sc, par_num++,
3251                                                              "PXPPCICLOCKCLIENT");
3252                                 break;
3253                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3254                                 if (print)
3255                                         bnx2x_print_next_block(sc, par_num++,
3256                                                              "CFC");
3257                                 break;
3258                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3259                                 if (print)
3260                                         bnx2x_print_next_block(sc, par_num++,
3261                                                              "CDU");
3262                                 break;
3263                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3264                                 if (print)
3265                                         bnx2x_print_next_block(sc, par_num++,
3266                                                              "DMAE");
3267                                 break;
3268                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3269                                 if (print)
3270                                         bnx2x_print_next_block(sc, par_num++,
3271                                                              "IGU");
3272                                 break;
3273                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3274                                 if (print)
3275                                         bnx2x_print_next_block(sc, par_num++,
3276                                                              "MISC");
3277                                 break;
3278                         }
3279
3280                         /* Clear the bit */
3281                         sig &= ~cur_bit;
3282                 }
3283         }
3284
3285         return par_num;
3286 }
3287
3288 static int
3289 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3290                               uint8_t * global, uint8_t print)
3291 {
3292         uint32_t cur_bit = 0;
3293         int i = 0;
3294
3295         for (i = 0; sig; i++) {
3296                 cur_bit = ((uint32_t) 0x1 << i);
3297                 if (sig & cur_bit) {
3298                         switch (cur_bit) {
3299                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3300                                 if (print)
3301                                         bnx2x_print_next_block(sc, par_num++,
3302                                                              "MCP ROM");
3303                                 *global = TRUE;
3304                                 break;
3305                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3306                                 if (print)
3307                                         bnx2x_print_next_block(sc, par_num++,
3308                                                              "MCP UMP RX");
3309                                 *global = TRUE;
3310                                 break;
3311                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3312                                 if (print)
3313                                         bnx2x_print_next_block(sc, par_num++,
3314                                                              "MCP UMP TX");
3315                                 *global = TRUE;
3316                                 break;
3317                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3318                                 if (print)
3319                                         bnx2x_print_next_block(sc, par_num++,
3320                                                              "MCP SCPAD");
3321                                 *global = TRUE;
3322                                 break;
3323                         }
3324
3325                         /* Clear the bit */
3326                         sig &= ~cur_bit;
3327                 }
3328         }
3329
3330         return par_num;
3331 }
3332
3333 static int
3334 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3335                               uint8_t print)
3336 {
3337         uint32_t cur_bit = 0;
3338         int i = 0;
3339
3340         for (i = 0; sig; i++) {
3341                 cur_bit = ((uint32_t) 0x1 << i);
3342                 if (sig & cur_bit) {
3343                         switch (cur_bit) {
3344                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3345                                 if (print)
3346                                         bnx2x_print_next_block(sc, par_num++,
3347                                                              "PGLUE_B");
3348                                 break;
3349                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3350                                 if (print)
3351                                         bnx2x_print_next_block(sc, par_num++,
3352                                                              "ATC");
3353                                 break;
3354                         }
3355
3356                         /* Clear the bit */
3357                         sig &= ~cur_bit;
3358                 }
3359         }
3360
3361         return par_num;
3362 }
3363
3364 static uint8_t
3365 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3366                 uint32_t * sig)
3367 {
3368         int par_num = 0;
3369
3370         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3371             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3372             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3373             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3374             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3375                 PMD_DRV_LOG(ERR, sc,
3376                             "Parity error: HW block parity attention:"
3377                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3378                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3379                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3380                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3381                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3382                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3383
3384                 if (print)
3385                         PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3386
3387                 par_num =
3388                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3389                                                   HW_PRTY_ASSERT_SET_0,
3390                                                   par_num, print);
3391                 par_num =
3392                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3393                                                   HW_PRTY_ASSERT_SET_1,
3394                                                   par_num, global, print);
3395                 par_num =
3396                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3397                                                   HW_PRTY_ASSERT_SET_2,
3398                                                   par_num, print);
3399                 par_num =
3400                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3401                                                   HW_PRTY_ASSERT_SET_3,
3402                                                   par_num, global, print);
3403                 par_num =
3404                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3405                                                   HW_PRTY_ASSERT_SET_4,
3406                                                   par_num, print);
3407
3408                 if (print)
3409                         PMD_DRV_LOG(INFO, sc, "");
3410
3411                 return TRUE;
3412         }
3413
3414         return FALSE;
3415 }
3416
3417 static uint8_t
3418 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3419 {
3420         struct attn_route attn = { {0} };
3421         int port = SC_PORT(sc);
3422
3423         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3424         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3425         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3426         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3427
3428         if (!CHIP_IS_E1x(sc))
3429                 attn.sig[4] =
3430                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3431
3432         return bnx2x_parity_attn(sc, global, print, attn.sig);
3433 }
3434
3435 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3436 {
3437         uint32_t val;
3438
3439         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3440                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3441                 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3442                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3443                         PMD_DRV_LOG(INFO, sc,
3444                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3445                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3446                         PMD_DRV_LOG(INFO, sc,
3447                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3448                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3449                         PMD_DRV_LOG(INFO, sc,
3450                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3451                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3452                         PMD_DRV_LOG(INFO, sc,
3453                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3454                 if (val &
3455                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3456                         PMD_DRV_LOG(INFO, sc,
3457                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3458                 if (val &
3459                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3460                         PMD_DRV_LOG(INFO, sc,
3461                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3462                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3463                         PMD_DRV_LOG(INFO, sc,
3464                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3465                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3466                         PMD_DRV_LOG(INFO, sc,
3467                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3468                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3469                         PMD_DRV_LOG(INFO, sc,
3470                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3471         }
3472
3473         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3474                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3475                 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3476                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3477                         PMD_DRV_LOG(INFO, sc,
3478                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3479                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3480                         PMD_DRV_LOG(INFO, sc,
3481                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3482                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3483                         PMD_DRV_LOG(INFO, sc,
3484                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3485                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3486                         PMD_DRV_LOG(INFO, sc,
3487                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3488                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3489                         PMD_DRV_LOG(INFO, sc,
3490                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3491                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3492                         PMD_DRV_LOG(INFO, sc,
3493                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3494         }
3495
3496         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3497                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3498                 PMD_DRV_LOG(INFO, sc,
3499                             "ERROR: FATAL parity attention set4 0x%08x",
3500                             (uint32_t) (attn &
3501                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3502                                          |
3503                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3504         }
3505 }
3506
3507 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3508 {
3509         int port = SC_PORT(sc);
3510
3511         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3512 }
3513
3514 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3515 {
3516         int port = SC_PORT(sc);
3517
3518         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3519 }
3520
3521 /*
3522  * called due to MCP event (on pmf):
3523  *   reread new bandwidth configuration
3524  *   configure FW
3525  *   notify others function about the change
3526  */
3527 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3528 {
3529         if (sc->link_vars.link_up) {
3530                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3531                 bnx2x_link_sync_notify(sc);
3532         }
3533
3534         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3535 }
3536
3537 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3538 {
3539         bnx2x_config_mf_bw(sc);
3540         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3541 }
3542
3543 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3544 {
3545         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3546 }
3547
3548 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3549
3550 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3551 {
3552         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3553
3554         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3555                 ETH_STAT_INFO_VERSION_LEN);
3556
3557         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3558                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3559                                               ether_stat->mac_local + MAC_PAD,
3560                                               MAC_PAD, ETH_ALEN);
3561
3562         ether_stat->mtu_size = sc->mtu;
3563
3564         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3565         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3566
3567         ether_stat->txq_size = sc->tx_ring_size;
3568         ether_stat->rxq_size = sc->rx_ring_size;
3569 }
3570
3571 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3572 {
3573         enum drv_info_opcode op_code;
3574         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3575
3576         /* if drv_info version supported by MFW doesn't match - send NACK */
3577         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3578                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3579                 return;
3580         }
3581
3582         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3583                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3584
3585         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3586
3587         switch (op_code) {
3588         case ETH_STATS_OPCODE:
3589                 bnx2x_drv_info_ether_stat(sc);
3590                 break;
3591         case FCOE_STATS_OPCODE:
3592         case ISCSI_STATS_OPCODE:
3593         default:
3594                 /* if op code isn't supported - send NACK */
3595                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3596                 return;
3597         }
3598
3599         /*
3600          * If we got drv_info attn from MFW then these fields are defined in
3601          * shmem2 for sure
3602          */
3603         SHMEM2_WR(sc, drv_info_host_addr_lo,
3604                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3605         SHMEM2_WR(sc, drv_info_host_addr_hi,
3606                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3607
3608         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3609 }
3610
3611 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3612 {
3613         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3614 /*
3615  * This is the only place besides the function initialization
3616  * where the sc->flags can change so it is done without any
3617  * locks
3618  */
3619                 if (sc->devinfo.
3620                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3621                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3622                         sc->flags |= BNX2X_MF_FUNC_DIS;
3623                         bnx2x_e1h_disable(sc);
3624                 } else {
3625                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3626                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3627                         bnx2x_e1h_enable(sc);
3628                 }
3629                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3630         }
3631
3632         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3633                 bnx2x_config_mf_bw(sc);
3634                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3635         }
3636
3637         /* Report results to MCP */
3638         if (dcc_event)
3639                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3640         else
3641                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3642 }
3643
3644 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3645 {
3646         int port = SC_PORT(sc);
3647         uint32_t val;
3648
3649         sc->port.pmf = 1;
3650
3651         /*
3652          * We need the mb() to ensure the ordering between the writing to
3653          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3654          */
3655         mb();
3656
3657         /* enable nig attention */
3658         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3659         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3660                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3661                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3662         } else if (!CHIP_IS_E1x(sc)) {
3663                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3664                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3665         }
3666
3667         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3668 }
3669
3670 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3671 {
3672         char last_idx;
3673         int i, rc = 0;
3674         __rte_unused uint32_t row0, row1, row2, row3;
3675
3676         /* XSTORM */
3677         last_idx =
3678             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3679         if (last_idx)
3680                 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3681
3682         /* print the asserts */
3683         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3684
3685                 row0 =
3686                     REG_RD(sc,
3687                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3688                 row1 =
3689                     REG_RD(sc,
3690                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3691                            4);
3692                 row2 =
3693                     REG_RD(sc,
3694                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3695                            8);
3696                 row3 =
3697                     REG_RD(sc,
3698                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3699                            12);
3700
3701                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3702                         PMD_DRV_LOG(ERR, sc,
3703                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3704                                     i, row3, row2, row1, row0);
3705                         rc++;
3706                 } else {
3707                         break;
3708                 }
3709         }
3710
3711         /* TSTORM */
3712         last_idx =
3713             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3714         if (last_idx) {
3715                 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3716         }
3717
3718         /* print the asserts */
3719         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3720
3721                 row0 =
3722                     REG_RD(sc,
3723                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3724                 row1 =
3725                     REG_RD(sc,
3726                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3727                            4);
3728                 row2 =
3729                     REG_RD(sc,
3730                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3731                            8);
3732                 row3 =
3733                     REG_RD(sc,
3734                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3735                            12);
3736
3737                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3738                         PMD_DRV_LOG(ERR, sc,
3739                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3740                                     i, row3, row2, row1, row0);
3741                         rc++;
3742                 } else {
3743                         break;
3744                 }
3745         }
3746
3747         /* CSTORM */
3748         last_idx =
3749             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3750         if (last_idx) {
3751                 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3752         }
3753
3754         /* print the asserts */
3755         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3756
3757                 row0 =
3758                     REG_RD(sc,
3759                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3760                 row1 =
3761                     REG_RD(sc,
3762                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3763                            4);
3764                 row2 =
3765                     REG_RD(sc,
3766                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3767                            8);
3768                 row3 =
3769                     REG_RD(sc,
3770                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3771                            12);
3772
3773                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3774                         PMD_DRV_LOG(ERR, sc,
3775                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3776                                     i, row3, row2, row1, row0);
3777                         rc++;
3778                 } else {
3779                         break;
3780                 }
3781         }
3782
3783         /* USTORM */
3784         last_idx =
3785             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3786         if (last_idx) {
3787                 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3788         }
3789
3790         /* print the asserts */
3791         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3792
3793                 row0 =
3794                     REG_RD(sc,
3795                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3796                 row1 =
3797                     REG_RD(sc,
3798                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3799                            4);
3800                 row2 =
3801                     REG_RD(sc,
3802                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3803                            8);
3804                 row3 =
3805                     REG_RD(sc,
3806                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3807                            12);
3808
3809                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3810                         PMD_DRV_LOG(ERR, sc,
3811                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3812                                     i, row3, row2, row1, row0);
3813                         rc++;
3814                 } else {
3815                         break;
3816                 }
3817         }
3818
3819         return rc;
3820 }
3821
3822 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3823 {
3824         int func = SC_FUNC(sc);
3825         uint32_t val;
3826
3827         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3828
3829                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3830
3831                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3832                         bnx2x_read_mf_cfg(sc);
3833                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3834                             MFCFG_RD(sc,
3835                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3836                         val =
3837                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3838
3839                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3840                                 bnx2x_dcc_event(sc,
3841                                               (val &
3842                                                DRV_STATUS_DCC_EVENT_MASK));
3843
3844                         if (val & DRV_STATUS_SET_MF_BW)
3845                                 bnx2x_set_mf_bw(sc);
3846
3847                         if (val & DRV_STATUS_DRV_INFO_REQ)
3848                                 bnx2x_handle_drv_info_req(sc);
3849
3850                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3851                                 bnx2x_pmf_update(sc);
3852
3853                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3854                                 bnx2x_handle_eee_event(sc);
3855
3856                         if (sc->link_vars.periodic_flags &
3857                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3858                                 /* sync with link */
3859                                 bnx2x_acquire_phy_lock(sc);
3860                                 sc->link_vars.periodic_flags &=
3861                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3862                                 bnx2x_release_phy_lock(sc);
3863                                 if (IS_MF(sc)) {
3864                                         bnx2x_link_sync_notify(sc);
3865                                 }
3866                                 bnx2x_link_report(sc);
3867                         }
3868
3869                         /*
3870                          * Always call it here: bnx2x_link_report() will
3871                          * prevent the link indication duplication.
3872                          */
3873                         bnx2x_link_status_update(sc);
3874
3875                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3876
3877                         PMD_DRV_LOG(ERR, sc, "MC assert!");
3878                         bnx2x_mc_assert(sc);
3879                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3880                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3881                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3882                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3883                         rte_panic("MC assert!");
3884
3885                 } else if (attn & BNX2X_MCP_ASSERT) {
3886
3887                         PMD_DRV_LOG(ERR, sc, "MCP assert!");
3888                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3889
3890                 } else {
3891                         PMD_DRV_LOG(ERR, sc,
3892                                     "Unknown HW assert! (attn 0x%08x)", attn);
3893                 }
3894         }
3895
3896         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3897                 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3898                 if (attn & BNX2X_GRC_TIMEOUT) {
3899                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3900                         PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3901                 }
3902                 if (attn & BNX2X_GRC_RSV) {
3903                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3904                         PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3905                 }
3906                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3907         }
3908 }
3909
3910 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3911 {
3912         int port = SC_PORT(sc);
3913         int reg_offset;
3914         uint32_t val0, mask0, val1, mask1;
3915         uint32_t val;
3916
3917         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3918                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3919                 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3920 /* CFC error attention */
3921                 if (val & 0x2) {
3922                         PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3923                 }
3924         }
3925
3926         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3927                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3928                 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3929 /* RQ_USDMDP_FIFO_OVERFLOW */
3930                 if (val & 0x18000) {
3931                         PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3932                 }
3933
3934                 if (!CHIP_IS_E1x(sc)) {
3935                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3936                         PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3937                 }
3938         }
3939 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3940 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3941
3942         if (attn & AEU_PXP2_HW_INT_BIT) {
3943 /*  CQ47854 workaround do not panic on
3944  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3945  */
3946                 if (!CHIP_IS_E1x(sc)) {
3947                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3948                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3949                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3950                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3951                         /*
3952                          * If the only PXP2_EOP_ERROR_BIT is set in
3953                          * STS0 and STS1 - clear it
3954                          *
3955                          * probably we lose additional attentions between
3956                          * STS0 and STS_CLR0, in this case user will not
3957                          * be notified about them
3958                          */
3959                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3960                             !(val1 & mask1))
3961                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3962
3963                         /* print the register, since no one can restore it */
3964                         PMD_DRV_LOG(ERR, sc,
3965                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3966
3967                         /*
3968                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3969                          * then notify
3970                          */
3971                         if (val0 & PXP2_EOP_ERROR_BIT) {
3972                                 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
3973
3974                                 /*
3975                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3976                                  * set then clear attention from PXP2 block without panic
3977                                  */
3978                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3979                                     ((val1 & mask1) == 0))
3980                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3981                         }
3982                 }
3983         }
3984
3985         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3986                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3987                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3988
3989                 val = REG_RD(sc, reg_offset);
3990                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3991                 REG_WR(sc, reg_offset, val);
3992
3993                 PMD_DRV_LOG(ERR, sc,
3994                             "FATAL HW block attention set2 0x%x",
3995                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3996                 rte_panic("HW block attention set2");
3997         }
3998 }
3999
4000 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4001 {
4002         int port = SC_PORT(sc);
4003         int reg_offset;
4004         uint32_t val;
4005
4006         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4007                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4008                 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4009 /* DORQ discard attention */
4010                 if (val & 0x2) {
4011                         PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4012                 }
4013         }
4014
4015         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4016                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4017                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4018
4019                 val = REG_RD(sc, reg_offset);
4020                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4021                 REG_WR(sc, reg_offset, val);
4022
4023                 PMD_DRV_LOG(ERR, sc,
4024                             "FATAL HW block attention set1 0x%08x",
4025                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4026                 rte_panic("HW block attention set1");
4027         }
4028 }
4029
4030 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4031 {
4032         int port = SC_PORT(sc);
4033         int reg_offset;
4034         uint32_t val;
4035
4036         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4037             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4038
4039         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4040                 val = REG_RD(sc, reg_offset);
4041                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4042                 REG_WR(sc, reg_offset, val);
4043
4044                 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4045
4046 /* Fan failure attention */
4047                 elink_hw_reset_phy(&sc->link_params);
4048                 bnx2x_fan_failure(sc);
4049         }
4050
4051         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4052                 bnx2x_acquire_phy_lock(sc);
4053                 elink_handle_module_detect_int(&sc->link_params);
4054                 bnx2x_release_phy_lock(sc);
4055         }
4056
4057         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4058                 val = REG_RD(sc, reg_offset);
4059                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4060                 REG_WR(sc, reg_offset, val);
4061
4062                 rte_panic("FATAL HW block attention set0 0x%lx",
4063                           (attn & HW_INTERRUT_ASSERT_SET_0));
4064         }
4065 }
4066
4067 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4068 {
4069         struct attn_route attn;
4070         struct attn_route *group_mask;
4071         int port = SC_PORT(sc);
4072         int index;
4073         uint32_t reg_addr;
4074         uint32_t val;
4075         uint32_t aeu_mask;
4076         uint8_t global = FALSE;
4077
4078         /*
4079          * Need to take HW lock because MCP or other port might also
4080          * try to handle this event.
4081          */
4082         bnx2x_acquire_alr(sc);
4083
4084         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4085                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4086
4087 /* disable HW interrupts */
4088                 bnx2x_int_disable(sc);
4089                 bnx2x_release_alr(sc);
4090                 return;
4091         }
4092
4093         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4094         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4095         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4096         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4097         if (!CHIP_IS_E1x(sc)) {
4098                 attn.sig[4] =
4099                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4100         } else {
4101                 attn.sig[4] = 0;
4102         }
4103
4104         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4105                 if (deasserted & (1 << index)) {
4106                         group_mask = &sc->attn_group[index];
4107
4108                         bnx2x_attn_int_deasserted4(sc,
4109                                                  attn.
4110                                                  sig[4] & group_mask->sig[4]);
4111                         bnx2x_attn_int_deasserted3(sc,
4112                                                  attn.
4113                                                  sig[3] & group_mask->sig[3]);
4114                         bnx2x_attn_int_deasserted1(sc,
4115                                                  attn.
4116                                                  sig[1] & group_mask->sig[1]);
4117                         bnx2x_attn_int_deasserted2(sc,
4118                                                  attn.
4119                                                  sig[2] & group_mask->sig[2]);
4120                         bnx2x_attn_int_deasserted0(sc,
4121                                                  attn.
4122                                                  sig[0] & group_mask->sig[0]);
4123                 }
4124         }
4125
4126         bnx2x_release_alr(sc);
4127
4128         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4129                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4130                             COMMAND_REG_ATTN_BITS_CLR);
4131         } else {
4132                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4133         }
4134
4135         val = ~deasserted;
4136         PMD_DRV_LOG(DEBUG, sc,
4137                     "about to mask 0x%08x at %s addr 0x%08x", val,
4138                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4139                     reg_addr);
4140         REG_WR(sc, reg_addr, val);
4141
4142         if (~sc->attn_state & deasserted) {
4143                 PMD_DRV_LOG(ERR, sc, "IGU error");
4144         }
4145
4146         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4147             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4148
4149         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4150
4151         aeu_mask = REG_RD(sc, reg_addr);
4152
4153         aeu_mask |= (deasserted & 0x3ff);
4154
4155         REG_WR(sc, reg_addr, aeu_mask);
4156         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4157
4158         sc->attn_state &= ~deasserted;
4159 }
4160
4161 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4162 {
4163         /* read local copy of bits */
4164         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4165         uint32_t attn_ack =
4166             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4167         uint32_t attn_state = sc->attn_state;
4168
4169         /* look for changed bits */
4170         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4171         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4172
4173         PMD_DRV_LOG(DEBUG, sc,
4174                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4175                     attn_bits, attn_ack, asserted, deasserted);
4176
4177         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4178                 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4179         }
4180
4181         /* handle bits that were raised */
4182         if (asserted) {
4183                 bnx2x_attn_int_asserted(sc, asserted);
4184         }
4185
4186         if (deasserted) {
4187                 bnx2x_attn_int_deasserted(sc, deasserted);
4188         }
4189 }
4190
4191 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4192 {
4193         struct host_sp_status_block *def_sb = sc->def_sb;
4194         uint16_t rc = 0;
4195
4196         mb();                   /* status block is written to by the chip */
4197
4198         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4199                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4200                 rc |= BNX2X_DEF_SB_ATT_IDX;
4201         }
4202
4203         if (sc->def_idx != def_sb->sp_sb.running_index) {
4204                 sc->def_idx = def_sb->sp_sb.running_index;
4205                 rc |= BNX2X_DEF_SB_IDX;
4206         }
4207
4208         mb();
4209
4210         return rc;
4211 }
4212
4213 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4214                                                           uint32_t cid)
4215 {
4216         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4217 }
4218
4219 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4220 {
4221         struct ecore_mcast_ramrod_params rparam;
4222         int rc;
4223
4224         memset(&rparam, 0, sizeof(rparam));
4225
4226         rparam.mcast_obj = &sc->mcast_obj;
4227
4228         /* clear pending state for the last command */
4229         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4230
4231         /* if there are pending mcast commands - send them */
4232         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4233                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4234                 if (rc < 0) {
4235                         PMD_DRV_LOG(INFO, sc,
4236                                     "Failed to send pending mcast commands (%d)",
4237                                     rc);
4238                 }
4239         }
4240 }
4241
4242 static void
4243 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4244 {
4245         unsigned long ramrod_flags = 0;
4246         int rc = 0;
4247         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4248         struct ecore_vlan_mac_obj *vlan_mac_obj;
4249
4250         /* always push next commands out, don't wait here */
4251         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4252
4253         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4254         case ECORE_FILTER_MAC_PENDING:
4255                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4256                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4257                 break;
4258
4259         case ECORE_FILTER_MCAST_PENDING:
4260                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4261                 bnx2x_handle_mcast_eqe(sc);
4262                 return;
4263
4264         default:
4265                 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4266                             elem->message.data.eth_event.echo);
4267                 return;
4268         }
4269
4270         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4271
4272         if (rc < 0) {
4273                 PMD_DRV_LOG(NOTICE, sc,
4274                             "Failed to schedule new commands (%d)", rc);
4275         } else if (rc > 0) {
4276                 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4277         }
4278 }
4279
4280 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4281 {
4282         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4283
4284         /* send rx_mode command again if was requested */
4285         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4286                 bnx2x_set_storm_rx_mode(sc);
4287         }
4288 }
4289
4290 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4291 {
4292         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4293         wmb();                  /* keep prod updates ordered */
4294 }
4295
4296 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4297 {
4298         uint16_t hw_cons, sw_cons, sw_prod;
4299         union event_ring_elem *elem;
4300         uint8_t echo;
4301         uint32_t cid;
4302         uint8_t opcode;
4303         int spqe_cnt = 0;
4304         struct ecore_queue_sp_obj *q_obj;
4305         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4306         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4307
4308         hw_cons = le16toh(*sc->eq_cons_sb);
4309
4310         /*
4311          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4312          * when we get to the next-page we need to adjust so the loop
4313          * condition below will be met. The next element is the size of a
4314          * regular element and hence incrementing by 1
4315          */
4316         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4317                 hw_cons++;
4318         }
4319
4320         /*
4321          * This function may never run in parallel with itself for a
4322          * specific sc and no need for a read memory barrier here.
4323          */
4324         sw_cons = sc->eq_cons;
4325         sw_prod = sc->eq_prod;
4326
4327         for (;
4328              sw_cons != hw_cons;
4329              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4330
4331                 elem = &sc->eq[EQ_DESC(sw_cons)];
4332
4333 /* elem CID originates from FW, actually LE */
4334                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4335                 opcode = elem->message.opcode;
4336
4337 /* handle eq element */
4338                 switch (opcode) {
4339                 case EVENT_RING_OPCODE_STAT_QUERY:
4340                         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4341                                     sc->stats_comp++);
4342                         /* nothing to do with stats comp */
4343                         goto next_spqe;
4344
4345                 case EVENT_RING_OPCODE_CFC_DEL:
4346                         /* handle according to cid range */
4347                         /* we may want to verify here that the sc state is HALTING */
4348                         PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4349                                     cid);
4350                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4351                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4352                                 break;
4353                         }
4354                         goto next_spqe;
4355
4356                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4357                         PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4358                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4359                                 break;
4360                         }
4361                         goto next_spqe;
4362
4363                 case EVENT_RING_OPCODE_START_TRAFFIC:
4364                         PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4365                         if (f_obj->complete_cmd
4366                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4367                                 break;
4368                         }
4369                         goto next_spqe;
4370
4371                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4372                         echo = elem->message.data.function_update_event.echo;
4373                         if (echo == SWITCH_UPDATE) {
4374                                 PMD_DRV_LOG(DEBUG, sc,
4375                                             "got FUNC_SWITCH_UPDATE ramrod");
4376                                 if (f_obj->complete_cmd(sc, f_obj,
4377                                                         ECORE_F_CMD_SWITCH_UPDATE))
4378                                 {
4379                                         break;
4380                                 }
4381                         } else {
4382                                 PMD_DRV_LOG(DEBUG, sc,
4383                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4384                                 f_obj->complete_cmd(sc, f_obj,
4385                                                     ECORE_F_CMD_AFEX_UPDATE);
4386                         }
4387                         goto next_spqe;
4388
4389                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4390                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4391                         if (q_obj->complete_cmd(sc, q_obj,
4392                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4393                                 break;
4394                         }
4395                         goto next_spqe;
4396
4397                 case EVENT_RING_OPCODE_FUNCTION_START:
4398                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4399                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4400                                 break;
4401                         }
4402                         goto next_spqe;
4403
4404                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4405                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4406                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4407                                 break;
4408                         }
4409                         goto next_spqe;
4410                 }
4411
4412                 switch (opcode | sc->state) {
4413                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4414                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4415                         cid =
4416                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4417                         PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4418                                     cid);
4419                         rss_raw->clear_pending(rss_raw);
4420                         break;
4421
4422                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4423                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4424                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4425                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4426                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4427                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4428                         PMD_DRV_LOG(DEBUG, sc,
4429                                     "got (un)set mac ramrod");
4430                         bnx2x_handle_classification_eqe(sc, elem);
4431                         break;
4432
4433                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4434                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4435                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4436                         PMD_DRV_LOG(DEBUG, sc,
4437                                     "got mcast ramrod");
4438                         bnx2x_handle_mcast_eqe(sc);
4439                         break;
4440
4441                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4442                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4443                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4444                         PMD_DRV_LOG(DEBUG, sc,
4445                                     "got rx_mode ramrod");
4446                         bnx2x_handle_rx_mode_eqe(sc);
4447                         break;
4448
4449                 default:
4450                         /* unknown event log error and continue */
4451                         PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4452                                     elem->message.opcode, sc->state);
4453                 }
4454
4455 next_spqe:
4456                 spqe_cnt++;
4457         }                       /* for */
4458
4459         mb();
4460         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4461
4462         sc->eq_cons = sw_cons;
4463         sc->eq_prod = sw_prod;
4464
4465         /* make sure that above mem writes were issued towards the memory */
4466         wmb();
4467
4468         /* update producer */
4469         bnx2x_update_eq_prod(sc, sc->eq_prod);
4470 }
4471
4472 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4473 {
4474         uint16_t status;
4475         int rc = 0;
4476
4477         PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4478
4479         /* what work needs to be performed? */
4480         status = bnx2x_update_dsb_idx(sc);
4481
4482         PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4483
4484         /* HW attentions */
4485         if (status & BNX2X_DEF_SB_ATT_IDX) {
4486                 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4487                 bnx2x_attn_int(sc);
4488                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4489                 rc = 1;
4490         }
4491
4492         /* SP events: STAT_QUERY and others */
4493         if (status & BNX2X_DEF_SB_IDX) {
4494 /* handle EQ completions */
4495                 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4496                 bnx2x_eq_int(sc);
4497                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4498                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4499                 status &= ~BNX2X_DEF_SB_IDX;
4500         }
4501
4502         /* if status is non zero then something went wrong */
4503         if (unlikely(status)) {
4504                 PMD_DRV_LOG(INFO, sc,
4505                             "Got an unknown SP interrupt! (0x%04x)", status);
4506         }
4507
4508         /* ack status block only if something was actually handled */
4509         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4510                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4511
4512         return rc;
4513 }
4514
4515 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4516 {
4517         struct bnx2x_softc *sc = fp->sc;
4518         uint8_t more_rx = FALSE;
4519
4520         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4521                                "---> FP TASK QUEUE (%d) <--", fp->index);
4522
4523         /* update the fastpath index */
4524         bnx2x_update_fp_sb_idx(fp);
4525
4526         if (scan_fp) {
4527                 if (bnx2x_has_rx_work(fp)) {
4528                         more_rx = bnx2x_rxeof(sc, fp);
4529                 }
4530
4531                 if (more_rx) {
4532                         /* still more work to do */
4533                         bnx2x_handle_fp_tq(fp, scan_fp);
4534                         return;
4535                 }
4536         }
4537
4538         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4539                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4540 }
4541
4542 /*
4543  * Legacy interrupt entry point.
4544  *
4545  * Verifies that the controller generated the interrupt and
4546  * then calls a separate routine to handle the various
4547  * interrupt causes: link, RX, and TX.
4548  */
4549 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4550 {
4551         struct bnx2x_fastpath *fp;
4552         uint32_t status, mask;
4553         int i, rc = 0;
4554
4555         /*
4556          * 0 for ustorm, 1 for cstorm
4557          * the bits returned from ack_int() are 0-15
4558          * bit 0 = attention status block
4559          * bit 1 = fast path status block
4560          * a mask of 0x2 or more = tx/rx event
4561          * a mask of 1 = slow path event
4562          */
4563
4564         status = bnx2x_ack_int(sc);
4565
4566         /* the interrupt is not for us */
4567         if (unlikely(status == 0)) {
4568                 return 0;
4569         }
4570
4571         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4572         //bnx2x_dump_status_block(sc);
4573
4574         FOR_EACH_ETH_QUEUE(sc, i) {
4575                 fp = &sc->fp[i];
4576                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4577                 if (status & mask) {
4578                 /* acknowledge and disable further fastpath interrupts */
4579                         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4580                                      0, IGU_INT_DISABLE, 0);
4581                         bnx2x_handle_fp_tq(fp, scan_fp);
4582                         status &= ~mask;
4583                 }
4584         }
4585
4586         if (unlikely(status & 0x1)) {
4587                 /* acknowledge and disable further slowpath interrupts */
4588                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4589                              0, IGU_INT_DISABLE, 0);
4590                 rc = bnx2x_handle_sp_tq(sc);
4591                 status &= ~0x1;
4592         }
4593
4594         if (unlikely(status)) {
4595                 PMD_DRV_LOG(WARNING, sc,
4596                             "Unexpected fastpath status (0x%08x)!", status);
4597         }
4598
4599         return rc;
4600 }
4601
4602 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4603 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4604 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4605 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4606 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4607 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4608 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4609 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4610 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4611
4612 static struct
4613 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4614         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4615         .init_hw_cmn = bnx2x_init_hw_common,
4616         .init_hw_port = bnx2x_init_hw_port,
4617         .init_hw_func = bnx2x_init_hw_func,
4618
4619         .reset_hw_cmn = bnx2x_reset_common,
4620         .reset_hw_port = bnx2x_reset_port,
4621         .reset_hw_func = bnx2x_reset_func,
4622
4623         .init_fw = bnx2x_init_firmware,
4624         .release_fw = bnx2x_release_firmware,
4625 };
4626
4627 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4628 {
4629         sc->dmae_ready = 0;
4630
4631         PMD_INIT_FUNC_TRACE(sc);
4632
4633         ecore_init_func_obj(sc,
4634                             &sc->func_obj,
4635                             BNX2X_SP(sc, func_rdata),
4636                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4637                             BNX2X_SP(sc, func_afex_rdata),
4638                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4639                             &bnx2x_func_sp_drv);
4640 }
4641
4642 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4643 {
4644         struct ecore_func_state_params func_params = { NULL };
4645         int rc;
4646
4647         PMD_INIT_FUNC_TRACE(sc);
4648
4649         /* prepare the parameters for function state transitions */
4650         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4651
4652         func_params.f_obj = &sc->func_obj;
4653         func_params.cmd = ECORE_F_CMD_HW_INIT;
4654
4655         func_params.params.hw_init.load_phase = load_code;
4656
4657         /*
4658          * Via a plethora of function pointers, we will eventually reach
4659          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4660          */
4661         rc = ecore_func_state_change(sc, &func_params);
4662
4663         return rc;
4664 }
4665
4666 static void
4667 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4668 {
4669         uint32_t i;
4670
4671         if (!(len % 4) && !(addr % 4)) {
4672                 for (i = 0; i < len; i += 4) {
4673                         REG_WR(sc, (addr + i), fill);
4674                 }
4675         } else {
4676                 for (i = 0; i < len; i++) {
4677                         REG_WR8(sc, (addr + i), fill);
4678                 }
4679         }
4680 }
4681
4682 /* writes FP SP data to FW - data_size in dwords */
4683 static void
4684 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4685                   uint32_t data_size)
4686 {
4687         uint32_t index;
4688
4689         for (index = 0; index < data_size; index++) {
4690                 REG_WR(sc,
4691                        (BAR_CSTRORM_INTMEM +
4692                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4693                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4694         }
4695 }
4696
4697 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4698 {
4699         struct hc_status_block_data_e2 sb_data_e2;
4700         struct hc_status_block_data_e1x sb_data_e1x;
4701         uint32_t *sb_data_p;
4702         uint32_t data_size = 0;
4703
4704         if (!CHIP_IS_E1x(sc)) {
4705                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4706                 sb_data_e2.common.state = SB_DISABLED;
4707                 sb_data_e2.common.p_func.vf_valid = FALSE;
4708                 sb_data_p = (uint32_t *) & sb_data_e2;
4709                 data_size = (sizeof(struct hc_status_block_data_e2) /
4710                              sizeof(uint32_t));
4711         } else {
4712                 memset(&sb_data_e1x, 0,
4713                        sizeof(struct hc_status_block_data_e1x));
4714                 sb_data_e1x.common.state = SB_DISABLED;
4715                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4716                 sb_data_p = (uint32_t *) & sb_data_e1x;
4717                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4718                              sizeof(uint32_t));
4719         }
4720
4721         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4722
4723         bnx2x_fill(sc,
4724                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4725                  CSTORM_STATUS_BLOCK_SIZE);
4726         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4727                  0, CSTORM_SYNC_BLOCK_SIZE);
4728 }
4729
4730 static void
4731 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4732                   struct hc_sp_status_block_data *sp_sb_data)
4733 {
4734         uint32_t i;
4735
4736         for (i = 0;
4737              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4738              i++) {
4739                 REG_WR(sc,
4740                        (BAR_CSTRORM_INTMEM +
4741                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4742                         (i * sizeof(uint32_t))),
4743                        *((uint32_t *) sp_sb_data + i));
4744         }
4745 }
4746
4747 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4748 {
4749         struct hc_sp_status_block_data sp_sb_data;
4750
4751         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4752
4753         sp_sb_data.state = SB_DISABLED;
4754         sp_sb_data.p_func.vf_valid = FALSE;
4755
4756         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4757
4758         bnx2x_fill(sc,
4759                  (BAR_CSTRORM_INTMEM +
4760                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4761                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4762         bnx2x_fill(sc,
4763                  (BAR_CSTRORM_INTMEM +
4764                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4765                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4766 }
4767
4768 static void
4769 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4770                              int igu_seg_id)
4771 {
4772         hc_sm->igu_sb_id = igu_sb_id;
4773         hc_sm->igu_seg_id = igu_seg_id;
4774         hc_sm->timer_value = 0xFF;
4775         hc_sm->time_to_expire = 0xFFFFFFFF;
4776 }
4777
4778 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4779 {
4780         /* zero out state machine indices */
4781
4782         /* rx indices */
4783         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4784
4785         /* tx indices */
4786         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4787         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4788         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4789         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4790
4791         /* map indices */
4792
4793         /* rx indices */
4794         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4795             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4796
4797         /* tx indices */
4798         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4799             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4800         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4801             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4802         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4803             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4804         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4805             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4806 }
4807
4808 static void
4809 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4810             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4811 {
4812         struct hc_status_block_data_e2 sb_data_e2;
4813         struct hc_status_block_data_e1x sb_data_e1x;
4814         struct hc_status_block_sm *hc_sm_p;
4815         uint32_t *sb_data_p;
4816         int igu_seg_id;
4817         int data_size;
4818
4819         if (CHIP_INT_MODE_IS_BC(sc)) {
4820                 igu_seg_id = HC_SEG_ACCESS_NORM;
4821         } else {
4822                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4823         }
4824
4825         bnx2x_zero_fp_sb(sc, fw_sb_id);
4826
4827         if (!CHIP_IS_E1x(sc)) {
4828                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4829                 sb_data_e2.common.state = SB_ENABLED;
4830                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4831                 sb_data_e2.common.p_func.vf_id = vfid;
4832                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4833                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4834                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4835                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4836                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4837                 hc_sm_p = sb_data_e2.common.state_machine;
4838                 sb_data_p = (uint32_t *) & sb_data_e2;
4839                 data_size = (sizeof(struct hc_status_block_data_e2) /
4840                              sizeof(uint32_t));
4841                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4842         } else {
4843                 memset(&sb_data_e1x, 0,
4844                        sizeof(struct hc_status_block_data_e1x));
4845                 sb_data_e1x.common.state = SB_ENABLED;
4846                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4847                 sb_data_e1x.common.p_func.vf_id = 0xff;
4848                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4849                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4850                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4851                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4852                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4853                 hc_sm_p = sb_data_e1x.common.state_machine;
4854                 sb_data_p = (uint32_t *) & sb_data_e1x;
4855                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4856                              sizeof(uint32_t));
4857                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4858         }
4859
4860         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4861         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4862
4863         /* write indices to HW - PCI guarantees endianity of regpairs */
4864         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4865 }
4866
4867 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4868 {
4869         if (CHIP_IS_E1x(fp->sc)) {
4870                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4871         } else {
4872                 return fp->cl_id;
4873         }
4874 }
4875
4876 static uint32_t
4877 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4878 {
4879         uint32_t offset = BAR_USTRORM_INTMEM;
4880
4881         if (IS_VF(sc)) {
4882                 return PXP_VF_ADDR_USDM_QUEUES_START +
4883                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4884                          sizeof(struct ustorm_queue_zone_data));
4885         } else if (!CHIP_IS_E1x(sc)) {
4886                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4887         } else {
4888                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4889         }
4890
4891         return offset;
4892 }
4893
4894 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4895 {
4896         struct bnx2x_fastpath *fp = &sc->fp[idx];
4897         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4898         unsigned long q_type = 0;
4899         int cos;
4900
4901         fp->sc = sc;
4902         fp->index = idx;
4903
4904         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4905         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4906
4907         if (CHIP_IS_E1x(sc))
4908                 fp->cl_id = SC_L_ID(sc) + idx;
4909         else
4910 /* want client ID same as IGU SB ID for non-E1 */
4911                 fp->cl_id = fp->igu_sb_id;
4912         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4913
4914         /* setup sb indices */
4915         if (!CHIP_IS_E1x(sc)) {
4916                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4917                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4918         } else {
4919                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4920                 fp->sb_running_index =
4921                     fp->status_block.e1x_sb->sb.running_index;
4922         }
4923
4924         /* init shortcut */
4925         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4926
4927         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4928
4929         for (cos = 0; cos < sc->max_cos; cos++) {
4930                 cids[cos] = idx;
4931         }
4932         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4933
4934         /* nothing more for a VF to do */
4935         if (IS_VF(sc)) {
4936                 return;
4937         }
4938
4939         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4940                     fp->fw_sb_id, fp->igu_sb_id);
4941
4942         bnx2x_update_fp_sb_idx(fp);
4943
4944         /* Configure Queue State object */
4945         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4946         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4947
4948         ecore_init_queue_obj(sc,
4949                              &sc->sp_objs[idx].q_obj,
4950                              fp->cl_id,
4951                              cids,
4952                              sc->max_cos,
4953                              SC_FUNC(sc),
4954                              BNX2X_SP(sc, q_rdata),
4955                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4956                              q_type);
4957
4958         /* configure classification DBs */
4959         ecore_init_mac_obj(sc,
4960                            &sc->sp_objs[idx].mac_obj,
4961                            fp->cl_id,
4962                            idx,
4963                            SC_FUNC(sc),
4964                            BNX2X_SP(sc, mac_rdata),
4965                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4966                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4967                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4968 }
4969
4970 static void
4971 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4972                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4973 {
4974         union ustorm_eth_rx_producers rx_prods;
4975         uint32_t i;
4976
4977         /* update producers */
4978         rx_prods.prod.bd_prod = rx_bd_prod;
4979         rx_prods.prod.cqe_prod = rx_cq_prod;
4980         rx_prods.prod.reserved = 0;
4981
4982         /*
4983          * Make sure that the BD and SGE data is updated before updating the
4984          * producers since FW might read the BD/SGE right after the producer
4985          * is updated.
4986          * This is only applicable for weak-ordered memory model archs such
4987          * as IA-64. The following barrier is also mandatory since FW will
4988          * assumes BDs must have buffers.
4989          */
4990         wmb();
4991
4992         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4993                 REG_WR(sc,
4994                        (fp->ustorm_rx_prods_offset + (i * 4)),
4995                        rx_prods.raw_data[i]);
4996         }
4997
4998         wmb();                  /* keep prod updates ordered */
4999 }
5000
5001 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5002 {
5003         struct bnx2x_fastpath *fp;
5004         int i;
5005         struct bnx2x_rx_queue *rxq;
5006
5007         for (i = 0; i < sc->num_queues; i++) {
5008                 fp = &sc->fp[i];
5009                 rxq = sc->rx_queues[fp->index];
5010                 if (!rxq) {
5011                         PMD_RX_LOG(ERR, "RX queue is NULL");
5012                         return;
5013                 }
5014
5015                 rxq->rx_bd_head = 0;
5016                 rxq->rx_bd_tail = rxq->nb_rx_desc;
5017                 rxq->rx_cq_head = 0;
5018                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5019                 *fp->rx_cq_cons_sb = 0;
5020
5021                 /*
5022                  * Activate the BD ring...
5023                  * Warning, this will generate an interrupt (to the TSTORM)
5024                  * so this can only be done after the chip is initialized
5025                  */
5026                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5027
5028                 if (i != 0) {
5029                         continue;
5030                 }
5031         }
5032 }
5033
5034 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5035 {
5036         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5037
5038         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5039         fp->tx_db.data.zero_fill1 = 0;
5040         fp->tx_db.data.prod = 0;
5041
5042         if (!txq) {
5043                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5044                 return;
5045         }
5046
5047         txq->tx_pkt_tail = 0;
5048         txq->tx_pkt_head = 0;
5049         txq->tx_bd_tail = 0;
5050         txq->tx_bd_head = 0;
5051 }
5052
5053 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5054 {
5055         int i;
5056
5057         for (i = 0; i < sc->num_queues; i++) {
5058                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5059         }
5060 }
5061
5062 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5063 {
5064         struct host_sp_status_block *def_sb = sc->def_sb;
5065         rte_iova_t mapping = sc->def_sb_dma.paddr;
5066         int igu_sp_sb_index;
5067         int igu_seg_id;
5068         int port = SC_PORT(sc);
5069         int func = SC_FUNC(sc);
5070         int reg_offset, reg_offset_en5;
5071         uint64_t section;
5072         int index, sindex;
5073         struct hc_sp_status_block_data sp_sb_data;
5074
5075         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5076
5077         if (CHIP_INT_MODE_IS_BC(sc)) {
5078                 igu_sp_sb_index = DEF_SB_IGU_ID;
5079                 igu_seg_id = HC_SEG_ACCESS_DEF;
5080         } else {
5081                 igu_sp_sb_index = sc->igu_dsb_id;
5082                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5083         }
5084
5085         /* attentions */
5086         section = ((uint64_t) mapping +
5087                    offsetof(struct host_sp_status_block, atten_status_block));
5088         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5089         sc->attn_state = 0;
5090
5091         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5092             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5093
5094         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5095             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5096
5097         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5098 /* take care of sig[0]..sig[4] */
5099                 for (sindex = 0; sindex < 4; sindex++) {
5100                         sc->attn_group[index].sig[sindex] =
5101                             REG_RD(sc,
5102                                    (reg_offset + (sindex * 0x4) +
5103                                     (0x10 * index)));
5104                 }
5105
5106                 if (!CHIP_IS_E1x(sc)) {
5107                         /*
5108                          * enable5 is separate from the rest of the registers,
5109                          * and the address skip is 4 and not 16 between the
5110                          * different groups
5111                          */
5112                         sc->attn_group[index].sig[4] =
5113                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5114                 } else {
5115                         sc->attn_group[index].sig[4] = 0;
5116                 }
5117         }
5118
5119         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5120                 reg_offset =
5121                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5122                 REG_WR(sc, reg_offset, U64_LO(section));
5123                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5124         } else if (!CHIP_IS_E1x(sc)) {
5125                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5126                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5127         }
5128
5129         section = ((uint64_t) mapping +
5130                    offsetof(struct host_sp_status_block, sp_sb));
5131
5132         bnx2x_zero_sp_sb(sc);
5133
5134         /* PCI guarantees endianity of regpair */
5135         sp_sb_data.state = SB_ENABLED;
5136         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5137         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5138         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5139         sp_sb_data.igu_seg_id = igu_seg_id;
5140         sp_sb_data.p_func.pf_id = func;
5141         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5142         sp_sb_data.p_func.vf_id = 0xff;
5143
5144         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5145
5146         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5147 }
5148
5149 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5150 {
5151         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5152         sc->spq_prod_idx = 0;
5153         sc->dsb_sp_prod =
5154             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5155         sc->spq_prod_bd = sc->spq;
5156         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5157 }
5158
5159 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5160 {
5161         union event_ring_elem *elem;
5162         int i;
5163
5164         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5165                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5166
5167                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5168                                                          BNX2X_PAGE_SIZE *
5169                                                          (i % NUM_EQ_PAGES)));
5170                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5171                                                          BNX2X_PAGE_SIZE *
5172                                                          (i % NUM_EQ_PAGES)));
5173         }
5174
5175         sc->eq_cons = 0;
5176         sc->eq_prod = NUM_EQ_DESC;
5177         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5178
5179         atomic_store_rel_long(&sc->eq_spq_left,
5180                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5181                                    NUM_EQ_DESC) - 1));
5182 }
5183
5184 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5185 {
5186         int i;
5187
5188         if (IS_MF_SI(sc)) {
5189 /*
5190  * In switch independent mode, the TSTORM needs to accept
5191  * packets that failed classification, since approximate match
5192  * mac addresses aren't written to NIG LLH.
5193  */
5194                 REG_WR8(sc,
5195                         (BAR_TSTRORM_INTMEM +
5196                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5197         } else
5198                 REG_WR8(sc,
5199                         (BAR_TSTRORM_INTMEM +
5200                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5201
5202         /*
5203          * Zero this manually as its initialization is currently missing
5204          * in the initTool.
5205          */
5206         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5207                 REG_WR(sc,
5208                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5209                        0);
5210         }
5211
5212         if (!CHIP_IS_E1x(sc)) {
5213                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5214                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5215                         HC_IGU_NBC_MODE);
5216         }
5217 }
5218
5219 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5220 {
5221         switch (load_code) {
5222         case FW_MSG_CODE_DRV_LOAD_COMMON:
5223         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5224                 bnx2x_init_internal_common(sc);
5225                 /* no break */
5226
5227         case FW_MSG_CODE_DRV_LOAD_PORT:
5228                 /* nothing to do */
5229                 /* no break */
5230
5231         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5232                 /* internal memory per function is initialized inside bnx2x_pf_init */
5233                 break;
5234
5235         default:
5236                 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5237                             load_code);
5238                 break;
5239         }
5240 }
5241
5242 static void
5243 storm_memset_func_cfg(struct bnx2x_softc *sc,
5244                       struct tstorm_eth_function_common_config *tcfg,
5245                       uint16_t abs_fid)
5246 {
5247         uint32_t addr;
5248         size_t size;
5249
5250         addr = (BAR_TSTRORM_INTMEM +
5251                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5252         size = sizeof(struct tstorm_eth_function_common_config);
5253         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5254 }
5255
5256 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5257 {
5258         struct tstorm_eth_function_common_config tcfg = { 0 };
5259
5260         if (CHIP_IS_E1x(sc)) {
5261                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5262         }
5263
5264         /* Enable the function in the FW */
5265         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5266         storm_memset_func_en(sc, p->func_id, 1);
5267
5268         /* spq */
5269         if (p->func_flgs & FUNC_FLG_SPQ) {
5270                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5271                 REG_WR(sc,
5272                        (XSEM_REG_FAST_MEMORY +
5273                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5274         }
5275 }
5276
5277 /*
5278  * Calculates the sum of vn_min_rates.
5279  * It's needed for further normalizing of the min_rates.
5280  * Returns:
5281  *   sum of vn_min_rates.
5282  *     or
5283  *   0 - if all the min_rates are 0.
5284  * In the later case fainess algorithm should be deactivated.
5285  * If all min rates are not zero then those that are zeroes will be set to 1.
5286  */
5287 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5288 {
5289         uint32_t vn_cfg;
5290         uint32_t vn_min_rate;
5291         int all_zero = 1;
5292         int vn;
5293
5294         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5295                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5296                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5297                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5298
5299                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5300                         /* skip hidden VNs */
5301                         vn_min_rate = 0;
5302                 } else if (!vn_min_rate) {
5303                         /* If min rate is zero - set it to 100 */
5304                         vn_min_rate = DEF_MIN_RATE;
5305                 } else {
5306                         all_zero = 0;
5307                 }
5308
5309                 input->vnic_min_rate[vn] = vn_min_rate;
5310         }
5311
5312         /* if ETS or all min rates are zeros - disable fairness */
5313         if (all_zero) {
5314                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5315         } else {
5316                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5317         }
5318 }
5319
5320 static uint16_t
5321 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5322 {
5323         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5324                             FUNC_MF_CFG_MAX_BW_SHIFT);
5325
5326         if (!max_cfg) {
5327                 PMD_DRV_LOG(DEBUG, sc,
5328                             "Max BW configured to 0 - using 100 instead");
5329                 max_cfg = 100;
5330         }
5331
5332         return max_cfg;
5333 }
5334
5335 static void
5336 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5337 {
5338         uint16_t vn_max_rate;
5339         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5340         uint32_t max_cfg;
5341
5342         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5343                 vn_max_rate = 0;
5344         } else {
5345                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5346
5347                 if (IS_MF_SI(sc)) {
5348                         /* max_cfg in percents of linkspeed */
5349                         vn_max_rate =
5350                             ((sc->link_vars.line_speed * max_cfg) / 100);
5351                 } else {        /* SD modes */
5352                         /* max_cfg is absolute in 100Mb units */
5353                         vn_max_rate = (max_cfg * 100);
5354                 }
5355         }
5356
5357         input->vnic_max_rate[vn] = vn_max_rate;
5358 }
5359
5360 static void
5361 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5362 {
5363         struct cmng_init_input input;
5364         int vn;
5365
5366         memset(&input, 0, sizeof(struct cmng_init_input));
5367
5368         input.port_rate = sc->link_vars.line_speed;
5369
5370         if (cmng_type == CMNG_FNS_MINMAX) {
5371 /* read mf conf from shmem */
5372                 if (read_cfg) {
5373                         bnx2x_read_mf_cfg(sc);
5374                 }
5375
5376 /* get VN min rate and enable fairness if not 0 */
5377                 bnx2x_calc_vn_min(sc, &input);
5378
5379 /* get VN max rate */
5380                 if (sc->port.pmf) {
5381                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5382                                 bnx2x_calc_vn_max(sc, vn, &input);
5383                         }
5384                 }
5385
5386 /* always enable rate shaping and fairness */
5387                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5388
5389                 ecore_init_cmng(&input, &sc->cmng);
5390                 return;
5391         }
5392 }
5393
5394 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5395 {
5396         if (CHIP_REV_IS_SLOW(sc)) {
5397                 return CMNG_FNS_NONE;
5398         }
5399
5400         if (IS_MF(sc)) {
5401                 return CMNG_FNS_MINMAX;
5402         }
5403
5404         return CMNG_FNS_NONE;
5405 }
5406
5407 static void
5408 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5409 {
5410         int vn;
5411         int func;
5412         uint32_t addr;
5413         size_t size;
5414
5415         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5416         size = sizeof(struct cmng_struct_per_port);
5417         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5418
5419         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5420                 func = func_by_vn(sc, vn);
5421
5422                 addr = (BAR_XSTRORM_INTMEM +
5423                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5424                 size = sizeof(struct rate_shaping_vars_per_vn);
5425                 ecore_storm_memset_struct(sc, addr, size,
5426                                           (uint32_t *) & cmng->
5427                                           vnic.vnic_max_rate[vn]);
5428
5429                 addr = (BAR_XSTRORM_INTMEM +
5430                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5431                 size = sizeof(struct fairness_vars_per_vn);
5432                 ecore_storm_memset_struct(sc, addr, size,
5433                                           (uint32_t *) & cmng->
5434                                           vnic.vnic_min_rate[vn]);
5435         }
5436 }
5437
5438 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5439 {
5440         struct bnx2x_func_init_params func_init;
5441         struct event_ring_data eq_data;
5442         uint16_t flags;
5443
5444         memset(&eq_data, 0, sizeof(struct event_ring_data));
5445         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5446
5447         if (!CHIP_IS_E1x(sc)) {
5448 /* reset IGU PF statistics: MSIX + ATTN */
5449 /* PF */
5450                 REG_WR(sc,
5451                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5452                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5453                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5454                          4)), 0);
5455 /* ATTN */
5456                 REG_WR(sc,
5457                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5458                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5459                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5460                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5461                          4)), 0);
5462         }
5463
5464         /* function setup flags */
5465         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5466
5467         func_init.func_flgs = flags;
5468         func_init.pf_id = SC_FUNC(sc);
5469         func_init.func_id = SC_FUNC(sc);
5470         func_init.spq_map = sc->spq_dma.paddr;
5471         func_init.spq_prod = sc->spq_prod_idx;
5472
5473         bnx2x_func_init(sc, &func_init);
5474
5475         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5476
5477         /*
5478          * Congestion management values depend on the link rate.
5479          * There is no active link so initial link rate is set to 10Gbps.
5480          * When the link comes up the congestion management values are
5481          * re-calculated according to the actual link rate.
5482          */
5483         sc->link_vars.line_speed = SPEED_10000;
5484         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5485
5486         /* Only the PMF sets the HW */
5487         if (sc->port.pmf) {
5488                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5489         }
5490
5491         /* init Event Queue - PCI bus guarantees correct endainity */
5492         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5493         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5494         eq_data.producer = sc->eq_prod;
5495         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5496         eq_data.sb_id = DEF_SB_ID;
5497         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5498 }
5499
5500 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5501 {
5502         int port = SC_PORT(sc);
5503         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5504         uint32_t val = REG_RD(sc, addr);
5505         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5506             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5507         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5508         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5509
5510         if (msix) {
5511                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5512                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5513                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5514                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5515                 if (single_msix) {
5516                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5517                 }
5518         } else if (msi) {
5519                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5520                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5521                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5522                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5523         } else {
5524                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5525                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5526                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5527                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5528
5529                 REG_WR(sc, addr, val);
5530
5531                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5532         }
5533
5534         REG_WR(sc, addr, val);
5535
5536         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5537         mb();
5538
5539         /* init leading/trailing edge */
5540         if (IS_MF(sc)) {
5541                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5542                 if (sc->port.pmf) {
5543                         /* enable nig and gpio3 attention */
5544                         val |= 0x1100;
5545                 }
5546         } else {
5547                 val = 0xffff;
5548         }
5549
5550         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5551         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5552
5553         /* make sure that interrupts are indeed enabled from here on */
5554         mb();
5555 }
5556
5557 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5558 {
5559         uint32_t val;
5560         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5561             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5562         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5563         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5564
5565         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5566
5567         if (msix) {
5568                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5569                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5570                 if (single_msix) {
5571                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5572                 }
5573         } else if (msi) {
5574                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5575                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5576                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5577         } else {
5578                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5579                 val |= (IGU_PF_CONF_INT_LINE_EN |
5580                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5581         }
5582
5583         /* clean previous status - need to configure igu prior to ack */
5584         if ((!msix) || single_msix) {
5585                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5586                 bnx2x_ack_int(sc);
5587         }
5588
5589         val |= IGU_PF_CONF_FUNC_EN;
5590
5591         PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5592                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5593
5594         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5595
5596         mb();
5597
5598         /* init leading/trailing edge */
5599         if (IS_MF(sc)) {
5600                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5601                 if (sc->port.pmf) {
5602                         /* enable nig and gpio3 attention */
5603                         val |= 0x1100;
5604                 }
5605         } else {
5606                 val = 0xffff;
5607         }
5608
5609         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5610         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5611
5612         /* make sure that interrupts are indeed enabled from here on */
5613         mb();
5614 }
5615
5616 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5617 {
5618         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5619                 bnx2x_hc_int_enable(sc);
5620         } else {
5621                 bnx2x_igu_int_enable(sc);
5622         }
5623 }
5624
5625 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5626 {
5627         int port = SC_PORT(sc);
5628         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5629         uint32_t val = REG_RD(sc, addr);
5630
5631         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5632                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5633                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5634         /* flush all outstanding writes */
5635         mb();
5636
5637         REG_WR(sc, addr, val);
5638         if (REG_RD(sc, addr) != val) {
5639                 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5640         }
5641 }
5642
5643 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5644 {
5645         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5646
5647         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5648                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5649
5650         PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5651
5652         /* flush all outstanding writes */
5653         mb();
5654
5655         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5656         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5657                 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5658         }
5659 }
5660
5661 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5662 {
5663         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5664                 bnx2x_hc_int_disable(sc);
5665         } else {
5666                 bnx2x_igu_int_disable(sc);
5667         }
5668 }
5669
5670 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5671 {
5672         int i;
5673
5674         PMD_INIT_FUNC_TRACE(sc);
5675
5676         for (i = 0; i < sc->num_queues; i++) {
5677                 bnx2x_init_eth_fp(sc, i);
5678         }
5679
5680         rmb();                  /* ensure status block indices were read */
5681
5682         bnx2x_init_rx_rings(sc);
5683         bnx2x_init_tx_rings(sc);
5684
5685         if (IS_VF(sc)) {
5686                 bnx2x_memset_stats(sc);
5687                 return;
5688         }
5689
5690         /* initialize MOD_ABS interrupts */
5691         elink_init_mod_abs_int(sc, &sc->link_vars,
5692                                sc->devinfo.chip_id,
5693                                sc->devinfo.shmem_base,
5694                                sc->devinfo.shmem2_base, SC_PORT(sc));
5695
5696         bnx2x_init_def_sb(sc);
5697         bnx2x_update_dsb_idx(sc);
5698         bnx2x_init_sp_ring(sc);
5699         bnx2x_init_eq_ring(sc);
5700         bnx2x_init_internal(sc, load_code);
5701         bnx2x_pf_init(sc);
5702         bnx2x_stats_init(sc);
5703
5704         /* flush all before enabling interrupts */
5705         mb();
5706
5707         bnx2x_int_enable(sc);
5708
5709         /* check for SPIO5 */
5710         bnx2x_attn_int_deasserted0(sc,
5711                                  REG_RD(sc,
5712                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5713                                          SC_PORT(sc) * 4)) &
5714                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5715 }
5716
5717 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5718 {
5719         /* mcast rules must be added to tx if tx switching is enabled */
5720         ecore_obj_type o_type;
5721         if (sc->flags & BNX2X_TX_SWITCHING)
5722                 o_type = ECORE_OBJ_TYPE_RX_TX;
5723         else
5724                 o_type = ECORE_OBJ_TYPE_RX;
5725
5726         /* RX_MODE controlling object */
5727         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5728
5729         /* multicast configuration controlling object */
5730         ecore_init_mcast_obj(sc,
5731                              &sc->mcast_obj,
5732                              sc->fp[0].cl_id,
5733                              sc->fp[0].index,
5734                              SC_FUNC(sc),
5735                              SC_FUNC(sc),
5736                              BNX2X_SP(sc, mcast_rdata),
5737                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5738                              ECORE_FILTER_MCAST_PENDING,
5739                              &sc->sp_state, o_type);
5740
5741         /* Setup CAM credit pools */
5742         ecore_init_mac_credit_pool(sc,
5743                                    &sc->macs_pool,
5744                                    SC_FUNC(sc),
5745                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5746                                    VNICS_PER_PATH(sc));
5747
5748         ecore_init_vlan_credit_pool(sc,
5749                                     &sc->vlans_pool,
5750                                     SC_ABS_FUNC(sc) >> 1,
5751                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5752                                     VNICS_PER_PATH(sc));
5753
5754         /* RSS configuration object */
5755         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5756                                   sc->fp[0].cl_id,
5757                                   sc->fp[0].index,
5758                                   SC_FUNC(sc),
5759                                   SC_FUNC(sc),
5760                                   BNX2X_SP(sc, rss_rdata),
5761                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5762                                   ECORE_FILTER_RSS_CONF_PENDING,
5763                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5764 }
5765
5766 /*
5767  * Initialize the function. This must be called before sending CLIENT_SETUP
5768  * for the first client.
5769  */
5770 static int bnx2x_func_start(struct bnx2x_softc *sc)
5771 {
5772         struct ecore_func_state_params func_params = { NULL };
5773         struct ecore_func_start_params *start_params =
5774             &func_params.params.start;
5775
5776         /* Prepare parameters for function state transitions */
5777         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5778
5779         func_params.f_obj = &sc->func_obj;
5780         func_params.cmd = ECORE_F_CMD_START;
5781
5782         /* Function parameters */
5783         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5784         start_params->sd_vlan_tag = OVLAN(sc);
5785
5786         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5787                 start_params->network_cos_mode = STATIC_COS;
5788         } else {                /* CHIP_IS_E1X */
5789                 start_params->network_cos_mode = FW_WRR;
5790         }
5791
5792         start_params->gre_tunnel_mode = 0;
5793         start_params->gre_tunnel_rss = 0;
5794
5795         return ecore_func_state_change(sc, &func_params);
5796 }
5797
5798 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5799 {
5800         uint16_t pmcsr;
5801
5802         /* If there is no power capability, silently succeed */
5803         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5804                 PMD_DRV_LOG(WARNING, sc, "No power capability");
5805                 return 0;
5806         }
5807
5808         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5809                  2);
5810
5811         switch (state) {
5812         case PCI_PM_D0:
5813                 pci_write_word(sc,
5814                                (sc->devinfo.pcie_pm_cap_reg +
5815                                 PCIR_POWER_STATUS),
5816                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5817
5818                 if (pmcsr & PCIM_PSTAT_DMASK) {
5819                         /* delay required during transition out of D3hot */
5820                         DELAY(20000);
5821                 }
5822
5823                 break;
5824
5825         case PCI_PM_D3hot:
5826                 /* don't shut down the power for emulation and FPGA */
5827                 if (CHIP_REV_IS_SLOW(sc)) {
5828                         return 0;
5829                 }
5830
5831                 pmcsr &= ~PCIM_PSTAT_DMASK;
5832                 pmcsr |= PCIM_PSTAT_D3;
5833
5834                 if (sc->wol) {
5835                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5836                 }
5837
5838                 pci_write_long(sc,
5839                                (sc->devinfo.pcie_pm_cap_reg +
5840                                 PCIR_POWER_STATUS), pmcsr);
5841
5842                 /*
5843                  * No more memory access after this point until device is brought back
5844                  * to D0 state.
5845                  */
5846                 break;
5847
5848         default:
5849                 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5850                             state);
5851                 return -1;
5852         }
5853
5854         return 0;
5855 }
5856
5857 /* return true if succeeded to acquire the lock */
5858 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5859 {
5860         uint32_t lock_status;
5861         uint32_t resource_bit = (1 << resource);
5862         int func = SC_FUNC(sc);
5863         uint32_t hw_lock_control_reg;
5864
5865         /* Validating that the resource is within range */
5866         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5867                 PMD_DRV_LOG(INFO, sc,
5868                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5869                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5870                 return FALSE;
5871         }
5872
5873         if (func <= 5) {
5874                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5875         } else {
5876                 hw_lock_control_reg =
5877                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5878         }
5879
5880         /* try to acquire the lock */
5881         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5882         lock_status = REG_RD(sc, hw_lock_control_reg);
5883         if (lock_status & resource_bit) {
5884                 return TRUE;
5885         }
5886
5887         PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5888
5889         return FALSE;
5890 }
5891
5892 /*
5893  * Get the recovery leader resource id according to the engine this function
5894  * belongs to. Currently only only 2 engines is supported.
5895  */
5896 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5897 {
5898         if (SC_PATH(sc)) {
5899                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5900         } else {
5901                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5902         }
5903 }
5904
5905 /* try to acquire a leader lock for current engine */
5906 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5907 {
5908         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5909 }
5910
5911 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5912 {
5913         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5914 }
5915
5916 /* close gates #2, #3 and #4 */
5917 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5918 {
5919         uint32_t val;
5920
5921         /* gates #2 and #4a are closed/opened */
5922         /* #4 */
5923         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5924         /* #2 */
5925         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5926
5927         /* #3 */
5928         if (CHIP_IS_E1x(sc)) {
5929 /* prevent interrupts from HC on both ports */
5930                 val = REG_RD(sc, HC_REG_CONFIG_1);
5931                 if (close)
5932                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5933                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5934                 else
5935                         REG_WR(sc, HC_REG_CONFIG_1,
5936                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5937
5938                 val = REG_RD(sc, HC_REG_CONFIG_0);
5939                 if (close)
5940                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5941                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5942                 else
5943                         REG_WR(sc, HC_REG_CONFIG_0,
5944                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5945
5946         } else {
5947 /* Prevent incoming interrupts in IGU */
5948                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5949
5950                 if (close)
5951                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5952                                (val & ~(uint32_t)
5953                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5954                 else
5955                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5956                                (val |
5957                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5958         }
5959
5960         wmb();
5961 }
5962
5963 /* poll for pending writes bit, it should get cleared in no more than 1s */
5964 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5965 {
5966         uint32_t cnt = 1000;
5967         uint32_t pend_bits = 0;
5968
5969         do {
5970                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5971
5972                 if (pend_bits == 0) {
5973                         break;
5974                 }
5975
5976                 DELAY(1000);
5977         } while (cnt-- > 0);
5978
5979         if (cnt <= 0) {
5980                 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
5981                             pend_bits);
5982                 return -1;
5983         }
5984
5985         return 0;
5986 }
5987
5988 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5989
5990 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5991 {
5992         /* Do some magic... */
5993         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5994         *magic_val = val & SHARED_MF_CLP_MAGIC;
5995         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5996 }
5997
5998 /* restore the value of the 'magic' bit */
5999 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6000 {
6001         /* Restore the 'magic' bit value... */
6002         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6003         MFCFG_WR(sc, shared_mf_config.clp_mb,
6004                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6005 }
6006
6007 /* prepare for MCP reset, takes care of CLP configurations */
6008 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6009 {
6010         uint32_t shmem;
6011         uint32_t validity_offset;
6012
6013         /* set `magic' bit in order to save MF config */
6014         bnx2x_clp_reset_prep(sc, magic_val);
6015
6016         /* get shmem offset */
6017         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6018         validity_offset =
6019             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6020
6021         /* Clear validity map flags */
6022         if (shmem > 0) {
6023                 REG_WR(sc, shmem + validity_offset, 0);
6024         }
6025 }
6026
6027 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6028 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6029
6030 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6031 {
6032         /* special handling for emulation and FPGA (10 times longer) */
6033         if (CHIP_REV_IS_SLOW(sc)) {
6034                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6035         } else {
6036                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6037         }
6038 }
6039
6040 /* initialize shmem_base and waits for validity signature to appear */
6041 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6042 {
6043         int cnt = 0;
6044         uint32_t val = 0;
6045
6046         do {
6047                 sc->devinfo.shmem_base =
6048                     sc->link_params.shmem_base =
6049                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6050
6051                 if (sc->devinfo.shmem_base) {
6052                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6053                         if (val & SHR_MEM_VALIDITY_MB)
6054                                 return 0;
6055                 }
6056
6057                 bnx2x_mcp_wait_one(sc);
6058
6059         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6060
6061         PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6062
6063         return -1;
6064 }
6065
6066 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6067 {
6068         int rc = bnx2x_init_shmem(sc);
6069
6070         /* Restore the `magic' bit value */
6071         bnx2x_clp_reset_done(sc, magic_val);
6072
6073         return rc;
6074 }
6075
6076 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6077 {
6078         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6079         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6080         wmb();
6081 }
6082
6083 /*
6084  * Reset the whole chip except for:
6085  *      - PCIE core
6086  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6087  *      - IGU
6088  *      - MISC (including AEU)
6089  *      - GRC
6090  *      - RBCN, RBCP
6091  */
6092 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6093 {
6094         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6095         uint32_t global_bits2, stay_reset2;
6096
6097         /*
6098          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6099          * (per chip) blocks.
6100          */
6101         global_bits2 =
6102             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6103             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6104
6105         /*
6106          * Don't reset the following blocks.
6107          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6108          *            reset, as in 4 port device they might still be owned
6109          *            by the MCP (there is only one leader per path).
6110          */
6111         not_reset_mask1 =
6112             MISC_REGISTERS_RESET_REG_1_RST_HC |
6113             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6114             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6115
6116         not_reset_mask2 =
6117             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6118             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6119             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6120             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6121             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6122             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6123             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6124             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6125             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6126             MISC_REGISTERS_RESET_REG_2_PGLC |
6127             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6128             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6129             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6130             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6131             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6132
6133         /*
6134          * Keep the following blocks in reset:
6135          *  - all xxMACs are handled by the elink code.
6136          */
6137         stay_reset2 =
6138             MISC_REGISTERS_RESET_REG_2_XMAC |
6139             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6140
6141         /* Full reset masks according to the chip */
6142         reset_mask1 = 0xffffffff;
6143
6144         if (CHIP_IS_E1H(sc))
6145                 reset_mask2 = 0x1ffff;
6146         else if (CHIP_IS_E2(sc))
6147                 reset_mask2 = 0xfffff;
6148         else                    /* CHIP_IS_E3 */
6149                 reset_mask2 = 0x3ffffff;
6150
6151         /* Don't reset global blocks unless we need to */
6152         if (!global)
6153                 reset_mask2 &= ~global_bits2;
6154
6155         /*
6156          * In case of attention in the QM, we need to reset PXP
6157          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6158          * because otherwise QM reset would release 'close the gates' shortly
6159          * before resetting the PXP, then the PSWRQ would send a write
6160          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6161          * read the payload data from PSWWR, but PSWWR would not
6162          * respond. The write queue in PGLUE would stuck, dmae commands
6163          * would not return. Therefore it's important to reset the second
6164          * reset register (containing the
6165          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6166          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6167          * bit).
6168          */
6169         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6170                reset_mask2 & (~not_reset_mask2));
6171
6172         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6173                reset_mask1 & (~not_reset_mask1));
6174
6175         mb();
6176         wmb();
6177
6178         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6179                reset_mask2 & (~stay_reset2));
6180
6181         mb();
6182         wmb();
6183
6184         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6185         wmb();
6186 }
6187
6188 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6189 {
6190         int cnt = 1000;
6191         uint32_t val = 0;
6192         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6193         uint32_t tags_63_32 = 0;
6194
6195         /* Empty the Tetris buffer, wait for 1s */
6196         do {
6197                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6198                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6199                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6200                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6201                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6202                 if (CHIP_IS_E3(sc)) {
6203                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6204                 }
6205
6206                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6207                     ((port_is_idle_0 & 0x1) == 0x1) &&
6208                     ((port_is_idle_1 & 0x1) == 0x1) &&
6209                     (pgl_exp_rom2 == 0xffffffff) &&
6210                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6211                         break;
6212                 DELAY(1000);
6213         } while (cnt-- > 0);
6214
6215         if (cnt <= 0) {
6216                 PMD_DRV_LOG(NOTICE, sc,
6217                             "ERROR: Tetris buffer didn't get empty or there "
6218                             "are still outstanding read requests after 1s! "
6219                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6220                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6221                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6222                             pgl_exp_rom2);
6223                 return -1;
6224         }
6225
6226         mb();
6227
6228         /* Close gates #2, #3 and #4 */
6229         bnx2x_set_234_gates(sc, TRUE);
6230
6231         /* Poll for IGU VQs for 57712 and newer chips */
6232         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6233                 return -1;
6234         }
6235
6236         /* clear "unprepared" bit */
6237         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6238         mb();
6239
6240         /* Make sure all is written to the chip before the reset */
6241         wmb();
6242
6243         /*
6244          * Wait for 1ms to empty GLUE and PCI-E core queues,
6245          * PSWHST, GRC and PSWRD Tetris buffer.
6246          */
6247         DELAY(1000);
6248
6249         /* Prepare to chip reset: */
6250         /* MCP */
6251         if (global) {
6252                 bnx2x_reset_mcp_prep(sc, &val);
6253         }
6254
6255         /* PXP */
6256         bnx2x_pxp_prep(sc);
6257         mb();
6258
6259         /* reset the chip */
6260         bnx2x_process_kill_chip_reset(sc, global);
6261         mb();
6262
6263         /* Recover after reset: */
6264         /* MCP */
6265         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6266                 return -1;
6267         }
6268
6269         /* Open the gates #2, #3 and #4 */
6270         bnx2x_set_234_gates(sc, FALSE);
6271
6272         return 0;
6273 }
6274
6275 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6276 {
6277         int rc = 0;
6278         uint8_t global = bnx2x_reset_is_global(sc);
6279         uint32_t load_code;
6280
6281         /*
6282          * If not going to reset MCP, load "fake" driver to reset HW while
6283          * driver is owner of the HW.
6284          */
6285         if (!global && !BNX2X_NOMCP(sc)) {
6286                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6287                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6288                 if (!load_code) {
6289                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6290                         rc = -1;
6291                         goto exit_leader_reset;
6292                 }
6293
6294                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6295                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6296                         PMD_DRV_LOG(NOTICE, sc,
6297                                     "MCP unexpected response, aborting");
6298                         rc = -1;
6299                         goto exit_leader_reset2;
6300                 }
6301
6302                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6303                 if (!load_code) {
6304                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6305                         rc = -1;
6306                         goto exit_leader_reset2;
6307                 }
6308         }
6309
6310         /* try to recover after the failure */
6311         if (bnx2x_process_kill(sc, global)) {
6312                 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6313                             SC_PATH(sc));
6314                 rc = -1;
6315                 goto exit_leader_reset2;
6316         }
6317
6318         /*
6319          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6320          * state.
6321          */
6322         bnx2x_set_reset_done(sc);
6323         if (global) {
6324                 bnx2x_clear_reset_global(sc);
6325         }
6326
6327 exit_leader_reset2:
6328
6329         /* unload "fake driver" if it was loaded */
6330         if (!global &&!BNX2X_NOMCP(sc)) {
6331                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6332                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6333         }
6334
6335 exit_leader_reset:
6336
6337         sc->is_leader = 0;
6338         bnx2x_release_leader_lock(sc);
6339
6340         mb();
6341         return rc;
6342 }
6343
6344 /*
6345  * prepare INIT transition, parameters configured:
6346  *   - HC configuration
6347  *   - Queue's CDU context
6348  */
6349 static void
6350 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6351                    struct ecore_queue_init_params *init_params)
6352 {
6353         uint8_t cos;
6354         int cxt_index, cxt_offset;
6355
6356         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6357         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6358
6359         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6360         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6361
6362         /* HC rate */
6363         init_params->rx.hc_rate =
6364             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6365         init_params->tx.hc_rate =
6366             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6367
6368         /* FW SB ID */
6369         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6370
6371         /* CQ index among the SB indices */
6372         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6373         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6374
6375         /* set maximum number of COSs supported by this queue */
6376         init_params->max_cos = sc->max_cos;
6377
6378         /* set the context pointers queue object */
6379         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6380                 cxt_index = fp->index / ILT_PAGE_CIDS;
6381                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6382                 init_params->cxts[cos] =
6383                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6384         }
6385 }
6386
6387 /* set flags that are common for the Tx-only and not normal connections */
6388 static unsigned long
6389 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6390 {
6391         unsigned long flags = 0;
6392
6393         /* PF driver will always initialize the Queue to an ACTIVE state */
6394         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6395
6396         /*
6397          * tx only connections collect statistics (on the same index as the
6398          * parent connection). The statistics are zeroed when the parent
6399          * connection is initialized.
6400          */
6401
6402         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6403         if (zero_stats) {
6404                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6405         }
6406
6407         /*
6408          * tx only connections can support tx-switching, though their
6409          * CoS-ness doesn't survive the loopback
6410          */
6411         if (sc->flags & BNX2X_TX_SWITCHING) {
6412                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6413         }
6414
6415         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6416
6417         return flags;
6418 }
6419
6420 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6421 {
6422         unsigned long flags = 0;
6423
6424         if (IS_MF_SD(sc)) {
6425                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6426         }
6427
6428         if (leading) {
6429                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6430                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6431         }
6432
6433         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6434
6435         /* merge with common flags */
6436         return flags | bnx2x_get_common_flags(sc, TRUE);
6437 }
6438
6439 static void
6440 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6441                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6442 {
6443         gen_init->stat_id = bnx2x_stats_id(fp);
6444         gen_init->spcl_id = fp->cl_id;
6445         gen_init->mtu = sc->mtu;
6446         gen_init->cos = cos;
6447 }
6448
6449 static void
6450 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6451                  struct rxq_pause_params *pause,
6452                  struct ecore_rxq_setup_params *rxq_init)
6453 {
6454         struct bnx2x_rx_queue *rxq;
6455
6456         rxq = sc->rx_queues[fp->index];
6457         if (!rxq) {
6458                 PMD_RX_LOG(ERR, "RX queue is NULL");
6459                 return;
6460         }
6461         /* pause */
6462         pause->bd_th_lo = BD_TH_LO(sc);
6463         pause->bd_th_hi = BD_TH_HI(sc);
6464
6465         pause->rcq_th_lo = RCQ_TH_LO(sc);
6466         pause->rcq_th_hi = RCQ_TH_HI(sc);
6467
6468         /* validate rings have enough entries to cross high thresholds */
6469         if (sc->dropless_fc &&
6470             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6471                 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6472         }
6473
6474         if (sc->dropless_fc &&
6475             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6476                 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6477         }
6478
6479         pause->pri_map = 1;
6480
6481         /* rxq setup */
6482         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6483         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6484         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6485                                               BNX2X_PAGE_SIZE);
6486
6487         /*
6488          * This should be a maximum number of data bytes that may be
6489          * placed on the BD (not including paddings).
6490          */
6491         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6492
6493         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6494         rxq_init->rss_engine_id = SC_FUNC(sc);
6495         rxq_init->mcast_engine_id = SC_FUNC(sc);
6496
6497         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6498         rxq_init->fw_sb_id = fp->fw_sb_id;
6499
6500         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6501
6502         /*
6503          * configure silent vlan removal
6504          * if multi function mode is afex, then mask default vlan
6505          */
6506         if (IS_MF_AFEX(sc)) {
6507                 rxq_init->silent_removal_value =
6508                     sc->devinfo.mf_info.afex_def_vlan_tag;
6509                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6510         }
6511 }
6512
6513 static void
6514 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6515                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6516 {
6517         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6518
6519         if (!txq) {
6520                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6521                 return;
6522         }
6523         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6524         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6525         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6526         txq_init->fw_sb_id = fp->fw_sb_id;
6527
6528         /*
6529          * set the TSS leading client id for TX classfication to the
6530          * leading RSS client id
6531          */
6532         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6533 }
6534
6535 /*
6536  * This function performs 2 steps in a queue state machine:
6537  *   1) RESET->INIT
6538  *   2) INIT->SETUP
6539  */
6540 static int
6541 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6542 {
6543         struct ecore_queue_state_params q_params = { NULL };
6544         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6545         int rc;
6546
6547         PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6548
6549         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6550
6551         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6552
6553         /* we want to wait for completion in this context */
6554         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6555
6556         /* prepare the INIT parameters */
6557         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6558
6559         /* Set the command */
6560         q_params.cmd = ECORE_Q_CMD_INIT;
6561
6562         /* Change the state to INIT */
6563         rc = ecore_queue_state_change(sc, &q_params);
6564         if (rc) {
6565                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6566                 return rc;
6567         }
6568
6569         PMD_DRV_LOG(DEBUG, sc, "init complete");
6570
6571         /* now move the Queue to the SETUP state */
6572         memset(setup_params, 0, sizeof(*setup_params));
6573
6574         /* set Queue flags */
6575         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6576
6577         /* set general SETUP parameters */
6578         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6579                               FIRST_TX_COS_INDEX);
6580
6581         bnx2x_pf_rx_q_prep(sc, fp,
6582                          &setup_params->pause_params,
6583                          &setup_params->rxq_params);
6584
6585         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6586
6587         /* Set the command */
6588         q_params.cmd = ECORE_Q_CMD_SETUP;
6589
6590         /* change the state to SETUP */
6591         rc = ecore_queue_state_change(sc, &q_params);
6592         if (rc) {
6593                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6594                 return rc;
6595         }
6596
6597         return rc;
6598 }
6599
6600 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6601 {
6602         if (IS_PF(sc))
6603                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6604         else                    /* VF */
6605                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6606 }
6607
6608 static int
6609 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6610                   uint8_t config_hash)
6611 {
6612         struct ecore_config_rss_params params = { NULL };
6613         uint32_t i;
6614
6615         /*
6616          * Although RSS is meaningless when there is a single HW queue we
6617          * still need it enabled in order to have HW Rx hash generated.
6618          */
6619
6620         params.rss_obj = rss_obj;
6621
6622         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6623
6624         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6625
6626         /* RSS configuration */
6627         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6628         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6629         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6630         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6631         if (rss_obj->udp_rss_v4) {
6632                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6633         }
6634         if (rss_obj->udp_rss_v6) {
6635                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6636         }
6637
6638         /* Hash bits */
6639         params.rss_result_mask = MULTI_MASK;
6640
6641         rte_memcpy(params.ind_table, rss_obj->ind_table,
6642                          sizeof(params.ind_table));
6643
6644         if (config_hash) {
6645 /* RSS keys */
6646                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6647                         params.rss_key[i] = (uint32_t) rte_rand();
6648                 }
6649
6650                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6651         }
6652
6653         if (IS_PF(sc))
6654                 return ecore_config_rss(sc, &params);
6655         else
6656                 return bnx2x_vf_config_rss(sc, &params);
6657 }
6658
6659 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6660 {
6661         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6662 }
6663
6664 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6665 {
6666         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6667         uint32_t i;
6668
6669         /*
6670          * Prepare the initial contents of the indirection table if
6671          * RSS is enabled
6672          */
6673         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6674                 sc->rss_conf_obj.ind_table[i] =
6675                     (sc->fp->cl_id + (i % num_eth_queues));
6676         }
6677
6678         if (sc->udp_rss) {
6679                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6680         }
6681
6682         /*
6683          * For 57711 SEARCHER configuration (rss_keys) is
6684          * per-port, so if explicit configuration is needed, do it only
6685          * for a PMF.
6686          *
6687          * For 57712 and newer it's a per-function configuration.
6688          */
6689         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6690 }
6691
6692 static int
6693 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6694                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6695                 unsigned long *ramrod_flags)
6696 {
6697         struct ecore_vlan_mac_ramrod_params ramrod_param;
6698         int rc;
6699
6700         memset(&ramrod_param, 0, sizeof(ramrod_param));
6701
6702         /* fill in general parameters */
6703         ramrod_param.vlan_mac_obj = obj;
6704         ramrod_param.ramrod_flags = *ramrod_flags;
6705
6706         /* fill a user request section if needed */
6707         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6708                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6709                                  ETH_ALEN);
6710
6711                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6712
6713 /* Set the command: ADD or DEL */
6714                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6715                     ECORE_VLAN_MAC_DEL;
6716         }
6717
6718         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6719
6720         if (rc == ECORE_EXISTS) {
6721                 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6722 /* do not treat adding same MAC as error */
6723                 rc = 0;
6724         } else if (rc < 0) {
6725                 PMD_DRV_LOG(ERR, sc,
6726                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6727         }
6728
6729         return rc;
6730 }
6731
6732 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6733 {
6734         unsigned long ramrod_flags = 0;
6735
6736         PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6737
6738         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6739
6740         /* Eth MAC is set on RSS leading client (fp[0]) */
6741         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6742                                &sc->sp_objs->mac_obj,
6743                                set, ECORE_ETH_MAC, &ramrod_flags);
6744 }
6745
6746 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6747 {
6748         uint32_t sel_phy_idx = 0;
6749
6750         if (sc->link_params.num_phys <= 1) {
6751                 return ELINK_INT_PHY;
6752         }
6753
6754         if (sc->link_vars.link_up) {
6755                 sel_phy_idx = ELINK_EXT_PHY1;
6756 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6757                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6758                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6759                      ELINK_SUPPORTED_FIBRE))
6760                         sel_phy_idx = ELINK_EXT_PHY2;
6761         } else {
6762                 switch (elink_phy_selection(&sc->link_params)) {
6763                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6764                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6765                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6766                         sel_phy_idx = ELINK_EXT_PHY1;
6767                         break;
6768                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6769                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6770                         sel_phy_idx = ELINK_EXT_PHY2;
6771                         break;
6772                 }
6773         }
6774
6775         return sel_phy_idx;
6776 }
6777
6778 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6779 {
6780         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6781
6782         /*
6783          * The selected activated PHY is always after swapping (in case PHY
6784          * swapping is enabled). So when swapping is enabled, we need to reverse
6785          * the configuration
6786          */
6787
6788         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6789                 if (sel_phy_idx == ELINK_EXT_PHY1)
6790                         sel_phy_idx = ELINK_EXT_PHY2;
6791                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6792                         sel_phy_idx = ELINK_EXT_PHY1;
6793         }
6794
6795         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6796 }
6797
6798 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6799 {
6800         /*
6801          * Initialize link parameters structure variables
6802          * It is recommended to turn off RX FC for jumbo frames
6803          * for better performance
6804          */
6805         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6806                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6807         } else {
6808                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6809         }
6810 }
6811
6812 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6813 {
6814         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6815         switch (sc->link_vars.ieee_fc &
6816                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6817         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6818         default:
6819                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6820                                                    ADVERTISED_Pause);
6821                 break;
6822
6823         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6824                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6825                                                   ADVERTISED_Pause);
6826                 break;
6827
6828         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6829                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6830                 break;
6831         }
6832 }
6833
6834 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6835 {
6836         uint16_t line_speed = sc->link_vars.line_speed;
6837         if (IS_MF(sc)) {
6838                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6839                                                       sc->devinfo.
6840                                                       mf_info.mf_config[SC_VN
6841                                                                         (sc)]);
6842
6843 /* calculate the current MAX line speed limit for the MF devices */
6844                 if (IS_MF_SI(sc)) {
6845                         line_speed = (line_speed * maxCfg) / 100;
6846                 } else {        /* SD mode */
6847                         uint16_t vn_max_rate = maxCfg * 100;
6848
6849                         if (vn_max_rate < line_speed) {
6850                                 line_speed = vn_max_rate;
6851                         }
6852                 }
6853         }
6854
6855         return line_speed;
6856 }
6857
6858 static void
6859 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6860 {
6861         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6862
6863         memset(data, 0, sizeof(*data));
6864
6865         /* fill the report data with the effective line speed */
6866         data->line_speed = line_speed;
6867
6868         /* Link is down */
6869         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6870                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6871                             &data->link_report_flags);
6872         }
6873
6874         /* Full DUPLEX */
6875         if (sc->link_vars.duplex == DUPLEX_FULL) {
6876                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6877                             &data->link_report_flags);
6878         }
6879
6880         /* Rx Flow Control is ON */
6881         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6882                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6883         }
6884
6885         /* Tx Flow Control is ON */
6886         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6887                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6888         }
6889 }
6890
6891 /* report link status to OS, should be called under phy_lock */
6892 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6893 {
6894         struct bnx2x_link_report_data cur_data;
6895
6896         /* reread mf_cfg */
6897         if (IS_PF(sc)) {
6898                 bnx2x_read_mf_cfg(sc);
6899         }
6900
6901         /* Read the current link report info */
6902         bnx2x_fill_report_data(sc, &cur_data);
6903
6904         /* Don't report link down or exactly the same link status twice */
6905         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6906             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6907                           &sc->last_reported_link.link_report_flags) &&
6908              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6909                           &cur_data.link_report_flags))) {
6910                 return;
6911         }
6912
6913         PMD_DRV_LOG(INFO, sc, "Change in link status : cur_data = %lx, last_reported_link = %lx\n",
6914                     cur_data.link_report_flags,
6915                     sc->last_reported_link.link_report_flags);
6916
6917         sc->link_cnt++;
6918
6919         PMD_DRV_LOG(INFO, sc, "link status change count = %x\n", sc->link_cnt);
6920         /* report new link params and remember the state for the next time */
6921         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6922
6923         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6924                          &cur_data.link_report_flags)) {
6925                 PMD_DRV_LOG(INFO, sc, "NIC Link is Down");
6926         } else {
6927                 __rte_unused const char *duplex;
6928                 __rte_unused const char *flow;
6929
6930                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6931                                            &cur_data.link_report_flags)) {
6932                         duplex = "full";
6933                 } else {
6934                         duplex = "half";
6935                 }
6936
6937 /*
6938  * Handle the FC at the end so that only these flags would be
6939  * possibly set. This way we may easily check if there is no FC
6940  * enabled.
6941  */
6942                 if (cur_data.link_report_flags) {
6943                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6944                                          &cur_data.link_report_flags) &&
6945                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6946                                          &cur_data.link_report_flags)) {
6947                                 flow = "ON - receive & transmit";
6948                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6949                                                 &cur_data.link_report_flags) &&
6950                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6951                                                  &cur_data.link_report_flags)) {
6952                                 flow = "ON - receive";
6953                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6954                                                  &cur_data.link_report_flags) &&
6955                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6956                                                 &cur_data.link_report_flags)) {
6957                                 flow = "ON - transmit";
6958                         } else {
6959                                 flow = "none";  /* possible? */
6960                         }
6961                 } else {
6962                         flow = "none";
6963                 }
6964
6965                 PMD_DRV_LOG(INFO, sc,
6966                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6967                             cur_data.line_speed, duplex, flow);
6968         }
6969 }
6970
6971 static void
6972 bnx2x_link_report(struct bnx2x_softc *sc)
6973 {
6974         bnx2x_acquire_phy_lock(sc);
6975         bnx2x_link_report_locked(sc);
6976         bnx2x_release_phy_lock(sc);
6977 }
6978
6979 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6980 {
6981         if (sc->state != BNX2X_STATE_OPEN) {
6982                 return;
6983         }
6984
6985         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6986                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6987         } else {
6988                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6989                                           ELINK_SUPPORTED_10baseT_Full |
6990                                           ELINK_SUPPORTED_100baseT_Half |
6991                                           ELINK_SUPPORTED_100baseT_Full |
6992                                           ELINK_SUPPORTED_1000baseT_Full |
6993                                           ELINK_SUPPORTED_2500baseX_Full |
6994                                           ELINK_SUPPORTED_10000baseT_Full |
6995                                           ELINK_SUPPORTED_TP |
6996                                           ELINK_SUPPORTED_FIBRE |
6997                                           ELINK_SUPPORTED_Autoneg |
6998                                           ELINK_SUPPORTED_Pause |
6999                                           ELINK_SUPPORTED_Asym_Pause);
7000                 sc->port.advertising[0] = sc->port.supported[0];
7001
7002                 sc->link_params.sc = sc;
7003                 sc->link_params.port = SC_PORT(sc);
7004                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7005                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7006                 sc->link_params.req_line_speed[0] = SPEED_10000;
7007                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7008                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7009
7010                 if (CHIP_REV_IS_FPGA(sc)) {
7011                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7012                         sc->link_vars.line_speed = ELINK_SPEED_1000;
7013                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7014                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7015                 } else {
7016                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7017                         sc->link_vars.line_speed = ELINK_SPEED_10000;
7018                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7019                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7020                 }
7021
7022                 sc->link_vars.link_up = 1;
7023
7024                 sc->link_vars.duplex = DUPLEX_FULL;
7025                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7026
7027                 if (IS_PF(sc)) {
7028                         REG_WR(sc,
7029                                NIG_REG_EGRESS_DRAIN0_MODE +
7030                                sc->link_params.port * 4, 0);
7031                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7032                         bnx2x_link_report(sc);
7033                 }
7034         }
7035
7036         if (IS_PF(sc)) {
7037                 if (sc->link_vars.link_up) {
7038                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7039                 } else {
7040                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7041                 }
7042                 bnx2x_link_report(sc);
7043         } else {
7044                 bnx2x_link_report(sc);
7045                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7046         }
7047 }
7048
7049 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7050 {
7051         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7052         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7053         struct elink_params *lp = &sc->link_params;
7054
7055         bnx2x_set_requested_fc(sc);
7056
7057         bnx2x_acquire_phy_lock(sc);
7058
7059         if (load_mode == LOAD_DIAG) {
7060                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7061 /* Prefer doing PHY loopback at 10G speed, if possible */
7062                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7063                         if (lp->speed_cap_mask[cfg_idx] &
7064                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7065                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7066                         } else {
7067                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7068                         }
7069                 }
7070         }
7071
7072         if (load_mode == LOAD_LOOPBACK_EXT) {
7073                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7074         }
7075
7076         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7077
7078         bnx2x_release_phy_lock(sc);
7079
7080         bnx2x_calc_fc_adv(sc);
7081
7082         if (sc->link_vars.link_up) {
7083                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7084                 bnx2x_link_report(sc);
7085         }
7086
7087         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7088         return rc;
7089 }
7090
7091 /* update flags in shmem */
7092 static void
7093 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7094 {
7095         uint32_t drv_flags;
7096
7097         if (SHMEM2_HAS(sc, drv_flags)) {
7098                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7099                 drv_flags = SHMEM2_RD(sc, drv_flags);
7100
7101                 if (set) {
7102                         drv_flags |= flags;
7103                 } else {
7104                         drv_flags &= ~flags;
7105                 }
7106
7107                 SHMEM2_WR(sc, drv_flags, drv_flags);
7108
7109                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7110         }
7111 }
7112
7113 /* periodic timer callout routine, only runs when the interface is up */
7114 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7115 {
7116         if ((sc->state != BNX2X_STATE_OPEN) ||
7117             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7118                 PMD_DRV_LOG(INFO, sc, "periodic callout exit (state=0x%x)",
7119                             sc->state);
7120                 return;
7121         }
7122         if (!CHIP_REV_IS_SLOW(sc)) {
7123 /*
7124  * This barrier is needed to ensure the ordering between the writing
7125  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7126  * the reading here.
7127  */
7128                 mb();
7129                 if (sc->port.pmf) {
7130                         bnx2x_acquire_phy_lock(sc);
7131                         elink_period_func(&sc->link_params, &sc->link_vars);
7132                         bnx2x_release_phy_lock(sc);
7133                 }
7134         }
7135 #ifdef BNX2X_PULSE
7136         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7137                 int mb_idx = SC_FW_MB_IDX(sc);
7138                 uint32_t drv_pulse;
7139                 uint32_t mcp_pulse;
7140
7141                 ++sc->fw_drv_pulse_wr_seq;
7142                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7143
7144                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7145                 bnx2x_drv_pulse(sc);
7146
7147                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7148                              MCP_PULSE_SEQ_MASK);
7149
7150 /*
7151  * The delta between driver pulse and mcp response should
7152  * be 1 (before mcp response) or 0 (after mcp response).
7153  */
7154                 if ((drv_pulse != mcp_pulse) &&
7155                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7156                         /* someone lost a heartbeat... */
7157                         PMD_DRV_LOG(ERR, sc,
7158                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7159                                     drv_pulse, mcp_pulse);
7160                 }
7161         }
7162 #endif
7163 }
7164
7165 /* start the controller */
7166 static __rte_noinline
7167 int bnx2x_nic_load(struct bnx2x_softc *sc)
7168 {
7169         uint32_t val;
7170         uint32_t load_code = 0;
7171         int i, rc = 0;
7172
7173         PMD_INIT_FUNC_TRACE(sc);
7174
7175         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7176
7177         if (IS_PF(sc)) {
7178 /* must be called before memory allocation and HW init */
7179                 bnx2x_ilt_set_info(sc);
7180         }
7181
7182         bnx2x_set_fp_rx_buf_size(sc);
7183
7184         if (IS_PF(sc)) {
7185                 if (bnx2x_alloc_mem(sc) != 0) {
7186                         sc->state = BNX2X_STATE_CLOSED;
7187                         rc = -ENOMEM;
7188                         goto bnx2x_nic_load_error0;
7189                 }
7190         }
7191
7192         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7193                 sc->state = BNX2X_STATE_CLOSED;
7194                 rc = -ENOMEM;
7195                 goto bnx2x_nic_load_error0;
7196         }
7197
7198         if (IS_VF(sc)) {
7199                 rc = bnx2x_vf_init(sc);
7200                 if (rc) {
7201                         sc->state = BNX2X_STATE_ERROR;
7202                         goto bnx2x_nic_load_error0;
7203                 }
7204         }
7205
7206         if (IS_PF(sc)) {
7207 /* set pf load just before approaching the MCP */
7208                 bnx2x_set_pf_load(sc);
7209
7210 /* if MCP exists send load request and analyze response */
7211                 if (!BNX2X_NOMCP(sc)) {
7212                         /* attempt to load pf */
7213                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7214                                 sc->state = BNX2X_STATE_CLOSED;
7215                                 rc = -ENXIO;
7216                                 goto bnx2x_nic_load_error1;
7217                         }
7218
7219                         /* what did the MCP say? */
7220                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7221                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7222                                 sc->state = BNX2X_STATE_CLOSED;
7223                                 rc = -ENXIO;
7224                                 goto bnx2x_nic_load_error2;
7225                         }
7226                 } else {
7227                         PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7228                         load_code = bnx2x_nic_load_no_mcp(sc);
7229                 }
7230
7231 /* mark PMF if applicable */
7232                 bnx2x_nic_load_pmf(sc, load_code);
7233
7234 /* Init Function state controlling object */
7235                 bnx2x_init_func_obj(sc);
7236
7237 /* Initialize HW */
7238                 if (bnx2x_init_hw(sc, load_code) != 0) {
7239                         PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7240                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7241                         sc->state = BNX2X_STATE_CLOSED;
7242                         rc = -ENXIO;
7243                         goto bnx2x_nic_load_error2;
7244                 }
7245         }
7246
7247         bnx2x_nic_init(sc, load_code);
7248
7249         /* Init per-function objects */
7250         if (IS_PF(sc)) {
7251                 bnx2x_init_objs(sc);
7252
7253 /* set AFEX default VLAN tag to an invalid value */
7254                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7255
7256                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7257                 rc = bnx2x_func_start(sc);
7258                 if (rc) {
7259                         PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7260                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7261                         sc->state = BNX2X_STATE_ERROR;
7262                         goto bnx2x_nic_load_error3;
7263                 }
7264
7265 /* send LOAD_DONE command to MCP */
7266                 if (!BNX2X_NOMCP(sc)) {
7267                         load_code =
7268                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7269                         if (!load_code) {
7270                                 PMD_DRV_LOG(NOTICE, sc,
7271                                             "MCP response failure, aborting");
7272                                 sc->state = BNX2X_STATE_ERROR;
7273                                 rc = -ENXIO;
7274                                 goto bnx2x_nic_load_error3;
7275                         }
7276                 }
7277         }
7278
7279         rc = bnx2x_setup_leading(sc);
7280         if (rc) {
7281                 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7282                 sc->state = BNX2X_STATE_ERROR;
7283                 goto bnx2x_nic_load_error3;
7284         }
7285
7286         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7287                 if (IS_PF(sc))
7288                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7289                 else            /* IS_VF(sc) */
7290                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7291
7292                 if (rc) {
7293                         PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7294                         sc->state = BNX2X_STATE_ERROR;
7295                         goto bnx2x_nic_load_error3;
7296                 }
7297         }
7298
7299         rc = bnx2x_init_rss_pf(sc);
7300         if (rc) {
7301                 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7302                 sc->state = BNX2X_STATE_ERROR;
7303                 goto bnx2x_nic_load_error3;
7304         }
7305
7306         /* now when Clients are configured we are ready to work */
7307         sc->state = BNX2X_STATE_OPEN;
7308
7309         /* Configure a ucast MAC */
7310         if (IS_PF(sc)) {
7311                 rc = bnx2x_set_eth_mac(sc, TRUE);
7312         } else {                /* IS_VF(sc) */
7313                 rc = bnx2x_vf_set_mac(sc, TRUE);
7314         }
7315
7316         if (rc) {
7317                 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7318                 sc->state = BNX2X_STATE_ERROR;
7319                 goto bnx2x_nic_load_error3;
7320         }
7321
7322         if (sc->port.pmf) {
7323                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7324                 if (rc) {
7325                         sc->state = BNX2X_STATE_ERROR;
7326                         goto bnx2x_nic_load_error3;
7327                 }
7328         }
7329
7330         sc->link_params.feature_config_flags &=
7331             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7332
7333         /* start the Tx */
7334         switch (LOAD_OPEN) {
7335         case LOAD_NORMAL:
7336         case LOAD_OPEN:
7337                 break;
7338
7339         case LOAD_DIAG:
7340         case LOAD_LOOPBACK_EXT:
7341                 sc->state = BNX2X_STATE_DIAG;
7342                 break;
7343
7344         default:
7345                 break;
7346         }
7347
7348         if (sc->port.pmf) {
7349                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7350         } else {
7351                 bnx2x_link_status_update(sc);
7352         }
7353
7354         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7355 /* mark driver is loaded in shmem2 */
7356                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7357                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7358                           (val |
7359                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7360                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7361         }
7362
7363         /* start fast path */
7364         /* Initialize Rx filter */
7365         bnx2x_set_rx_mode(sc);
7366
7367         /* wait for all pending SP commands to complete */
7368         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7369                 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7370                 bnx2x_periodic_stop(sc);
7371                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7372                 return -ENXIO;
7373         }
7374
7375         PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7376
7377         return 0;
7378
7379 bnx2x_nic_load_error3:
7380
7381         if (IS_PF(sc)) {
7382                 bnx2x_int_disable_sync(sc, 1);
7383
7384 /* clean out queued objects */
7385                 bnx2x_squeeze_objects(sc);
7386         }
7387
7388 bnx2x_nic_load_error2:
7389
7390         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7391                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7392                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7393         }
7394
7395         sc->port.pmf = 0;
7396
7397 bnx2x_nic_load_error1:
7398
7399         /* clear pf_load status, as it was already set */
7400         if (IS_PF(sc)) {
7401                 bnx2x_clear_pf_load(sc);
7402         }
7403
7404 bnx2x_nic_load_error0:
7405
7406         bnx2x_free_fw_stats_mem(sc);
7407         bnx2x_free_mem(sc);
7408
7409         return rc;
7410 }
7411
7412 /*
7413 * Handles controller initialization.
7414 */
7415 int bnx2x_init(struct bnx2x_softc *sc)
7416 {
7417         int other_engine = SC_PATH(sc) ? 0 : 1;
7418         uint8_t other_load_status, load_status;
7419         uint8_t global = FALSE;
7420         int rc;
7421
7422         /* Check if the driver is still running and bail out if it is. */
7423         if (sc->state != BNX2X_STATE_CLOSED) {
7424                 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7425                 rc = 0;
7426                 goto bnx2x_init_done;
7427         }
7428
7429         bnx2x_set_power_state(sc, PCI_PM_D0);
7430
7431         /*
7432          * If parity occurred during the unload, then attentions and/or
7433          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7434          * loaded on the current engine to complete the recovery. Parity recovery
7435          * is only relevant for PF driver.
7436          */
7437         if (IS_PF(sc)) {
7438                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7439                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7440
7441                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7442                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7443                         do {
7444                                 /*
7445                                  * If there are attentions and they are in global blocks, set
7446                                  * the GLOBAL_RESET bit regardless whether it will be this
7447                                  * function that will complete the recovery or not.
7448                                  */
7449                                 if (global) {
7450                                         bnx2x_set_reset_global(sc);
7451                                 }
7452
7453                                 /*
7454                                  * Only the first function on the current engine should try
7455                                  * to recover in open. In case of attentions in global blocks
7456                                  * only the first in the chip should try to recover.
7457                                  */
7458                                 if ((!load_status
7459                                      && (!global ||!other_load_status))
7460                                     && bnx2x_trylock_leader_lock(sc)
7461                                     && !bnx2x_leader_reset(sc)) {
7462                                         PMD_DRV_LOG(INFO, sc,
7463                                                     "Recovered during init");
7464                                         break;
7465                                 }
7466
7467                                 /* recovery has failed... */
7468                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7469
7470                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7471
7472                                 PMD_DRV_LOG(NOTICE, sc,
7473                                             "Recovery flow hasn't properly "
7474                                             "completed yet, try again later. "
7475                                             "If you still see this message after a "
7476                                             "few retries then power cycle is required.");
7477
7478                                 rc = -ENXIO;
7479                                 goto bnx2x_init_done;
7480                         } while (0);
7481                 }
7482         }
7483
7484         sc->recovery_state = BNX2X_RECOVERY_DONE;
7485
7486         rc = bnx2x_nic_load(sc);
7487
7488 bnx2x_init_done:
7489
7490         if (rc) {
7491                 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7492                             "stack notified driver is NOT running!");
7493         }
7494
7495         return rc;
7496 }
7497
7498 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7499 {
7500         uint32_t val = 0;
7501
7502         /*
7503          * Read the ME register to get the function number. The ME register
7504          * holds the relative-function number and absolute-function number. The
7505          * absolute-function number appears only in E2 and above. Before that
7506          * these bits always contained zero, therefore we cannot blindly use them.
7507          */
7508
7509         val = REG_RD(sc, BAR_ME_REGISTER);
7510
7511         sc->pfunc_rel =
7512             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7513         sc->path_id =
7514             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7515             1;
7516
7517         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7518                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7519         } else {
7520                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7521         }
7522
7523         PMD_DRV_LOG(DEBUG, sc,
7524                     "Relative function %d, Absolute function %d, Path %d",
7525                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7526 }
7527
7528 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7529 {
7530         uint32_t shmem2_size;
7531         uint32_t offset;
7532         uint32_t mf_cfg_offset_value;
7533
7534         /* Non 57712 */
7535         offset = (SHMEM_ADDR(sc, func_mb) +
7536                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7537
7538         /* 57712 plus */
7539         if (sc->devinfo.shmem2_base != 0) {
7540                 shmem2_size = SHMEM2_RD(sc, size);
7541                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7542                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7543                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7544                                 offset = mf_cfg_offset_value;
7545                         }
7546                 }
7547         }
7548
7549         return offset;
7550 }
7551
7552 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7553 {
7554         uint32_t ret;
7555         struct bnx2x_pci_cap *caps;
7556
7557         /* ensure PCIe capability is enabled */
7558         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7559         if (NULL != caps) {
7560                 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7561                             "id=0x%04X type=0x%04X addr=0x%08X",
7562                             caps->id, caps->type, caps->addr);
7563                 pci_read(sc, (caps->addr + reg), &ret, 2);
7564                 return ret;
7565         }
7566
7567         PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7568
7569         return 0;
7570 }
7571
7572 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7573 {
7574         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7575                 PCIM_EXP_STA_TRANSACTION_PND;
7576 }
7577
7578 /*
7579 * Walk the PCI capabiites list for the device to find what features are
7580 * supported. These capabilites may be enabled/disabled by firmware so it's
7581 * best to walk the list rather than make assumptions.
7582 */
7583 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7584 {
7585         PMD_INIT_FUNC_TRACE(sc);
7586
7587         struct bnx2x_pci_cap *caps;
7588         uint16_t link_status;
7589         int reg = 0;
7590
7591         /* check if PCI Power Management is enabled */
7592         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7593         if (NULL != caps) {
7594                 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7595                             "id=0x%04X type=0x%04X addr=0x%08X",
7596                             caps->id, caps->type, caps->addr);
7597
7598                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7599                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7600         }
7601
7602         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7603
7604         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7605         sc->devinfo.pcie_link_width =
7606             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7607
7608         PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7609                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7610
7611         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7612
7613         /* check if MSI capability is enabled */
7614         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7615         if (NULL != caps) {
7616                 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7617
7618                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7619                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7620         }
7621
7622         /* check if MSI-X capability is enabled */
7623         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7624         if (NULL != caps) {
7625                 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7626
7627                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7628                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7629         }
7630 }
7631
7632 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7633 {
7634         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7635         uint32_t val;
7636
7637         /* get the outer vlan if we're in switch-dependent mode */
7638
7639         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7640         mf_info->ext_id = (uint16_t) val;
7641
7642         mf_info->multi_vnics_mode = 1;
7643
7644         if (!VALID_OVLAN(mf_info->ext_id)) {
7645                 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7646                 return 1;
7647         }
7648
7649         /* get the capabilities */
7650         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7651             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7652                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7653         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7654                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7655                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7656         } else {
7657                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7658         }
7659
7660         mf_info->vnics_per_port =
7661             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7662
7663         return 0;
7664 }
7665
7666 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7667 {
7668         uint32_t retval = 0;
7669         uint32_t val;
7670
7671         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7672
7673         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7674                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7675                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7676                 }
7677                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7678                         retval |= MF_PROTO_SUPPORT_ISCSI;
7679                 }
7680                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7681                         retval |= MF_PROTO_SUPPORT_FCOE;
7682                 }
7683         }
7684
7685         return retval;
7686 }
7687
7688 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7689 {
7690         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7691         uint32_t val;
7692
7693         /*
7694          * There is no outer vlan if we're in switch-independent mode.
7695          * If the mac is valid then assume multi-function.
7696          */
7697
7698         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7699
7700         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7701
7702         mf_info->mf_protos_supported =
7703             bnx2x_get_shmem_ext_proto_support_flags(sc);
7704
7705         mf_info->vnics_per_port =
7706             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7707
7708         return 0;
7709 }
7710
7711 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7712 {
7713         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7714         uint32_t e1hov_tag;
7715         uint32_t func_config;
7716         uint32_t niv_config;
7717
7718         mf_info->multi_vnics_mode = 1;
7719
7720         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7721         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7722         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7723
7724         mf_info->ext_id =
7725             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7726                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7727
7728         mf_info->default_vlan =
7729             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7730                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7731
7732         mf_info->niv_allowed_priorities =
7733             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7734                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7735
7736         mf_info->niv_default_cos =
7737             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7738                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7739
7740         mf_info->afex_vlan_mode =
7741             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7742              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7743
7744         mf_info->niv_mba_enabled =
7745             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7746              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7747
7748         mf_info->mf_protos_supported =
7749             bnx2x_get_shmem_ext_proto_support_flags(sc);
7750
7751         mf_info->vnics_per_port =
7752             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7753
7754         return 0;
7755 }
7756
7757 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7758 {
7759         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7760         uint32_t mf_cfg1;
7761         uint32_t mf_cfg2;
7762         uint32_t ovlan1;
7763         uint32_t ovlan2;
7764         uint8_t i, j;
7765
7766         /* various MF mode sanity checks... */
7767
7768         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7769                 PMD_DRV_LOG(NOTICE, sc,
7770                             "Enumerated function %d is marked as hidden",
7771                             SC_PORT(sc));
7772                 return 1;
7773         }
7774
7775         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7776                 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7777                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7778                 return 1;
7779         }
7780
7781         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7782 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7783                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7784                         PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7785                                     SC_VN(sc), OVLAN(sc));
7786                         return 1;
7787                 }
7788
7789                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7790                         PMD_DRV_LOG(NOTICE, sc,
7791                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7792                                     mf_info->multi_vnics_mode, OVLAN(sc));
7793                         return 1;
7794                 }
7795
7796 /*
7797  * Verify all functions are either MF or SF mode. If MF, make sure
7798  * sure that all non-hidden functions have a valid ovlan. If SF,
7799  * make sure that all non-hidden functions have an invalid ovlan.
7800  */
7801                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7802                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7803                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7804                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7805                             (((mf_info->multi_vnics_mode)
7806                               && !VALID_OVLAN(ovlan1))
7807                              || ((!mf_info->multi_vnics_mode)
7808                                  && VALID_OVLAN(ovlan1)))) {
7809                                 PMD_DRV_LOG(NOTICE, sc,
7810                                             "mf_mode=SD function %d MF config "
7811                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7812                                             i, mf_info->multi_vnics_mode,
7813                                             ovlan1);
7814                                 return 1;
7815                         }
7816                 }
7817
7818 /* Verify all funcs on the same port each have a different ovlan. */
7819                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7820                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7821                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7822                         /* iterate from the next function on the port to the max func */
7823                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7824                                 mf_cfg2 =
7825                                     MFCFG_RD(sc, func_mf_config[j].config);
7826                                 ovlan2 =
7827                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7828                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7829                                     && VALID_OVLAN(ovlan1)
7830                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7831                                     && VALID_OVLAN(ovlan2)
7832                                     && (ovlan1 == ovlan2)) {
7833                                         PMD_DRV_LOG(NOTICE, sc,
7834                                                     "mf_mode=SD functions %d and %d "
7835                                                     "have the same ovlan (%d)",
7836                                                     i, j, ovlan1);
7837                                         return 1;
7838                                 }
7839                         }
7840                 }
7841         }
7842         /* MULTI_FUNCTION_SD */
7843         return 0;
7844 }
7845
7846 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7847 {
7848         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7849         uint32_t val, mac_upper;
7850         uint8_t i, vnic;
7851
7852         /* initialize mf_info defaults */
7853         mf_info->vnics_per_port = 1;
7854         mf_info->multi_vnics_mode = FALSE;
7855         mf_info->path_has_ovlan = FALSE;
7856         mf_info->mf_mode = SINGLE_FUNCTION;
7857
7858         if (!CHIP_IS_MF_CAP(sc)) {
7859                 return 0;
7860         }
7861
7862         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7863                 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7864                 return 1;
7865         }
7866
7867         /* get the MF mode (switch dependent / independent / single-function) */
7868
7869         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7870
7871         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7872         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7873
7874                 mac_upper =
7875                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7876
7877                 /* check for legal upper mac bytes */
7878                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7879                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7880                 } else {
7881                         PMD_DRV_LOG(NOTICE, sc,
7882                                     "Invalid config for Switch Independent mode");
7883                 }
7884
7885                 break;
7886
7887         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7888         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7889
7890                 /* get outer vlan configuration */
7891                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7892
7893                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7894                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7895                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7896                 } else {
7897                         PMD_DRV_LOG(NOTICE, sc,
7898                                     "Invalid config for Switch Dependent mode");
7899                 }
7900
7901                 break;
7902
7903         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7904
7905                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7906                 return 0;
7907
7908         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7909
7910                 /*
7911                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7912                  * and the MAC address is valid.
7913                  */
7914                 mac_upper =
7915                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7916
7917                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7918                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7919                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7920                 } else {
7921                         PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7922                 }
7923
7924                 break;
7925
7926         default:
7927
7928                 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7929                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7930
7931                 return 1;
7932         }
7933
7934         /* set path mf_mode (which could be different than function mf_mode) */
7935         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7936                 mf_info->path_has_ovlan = TRUE;
7937         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7938 /*
7939  * Decide on path multi vnics mode. If we're not in MF mode and in
7940  * 4-port mode, this is good enough to check vnic-0 of the other port
7941  * on the same path
7942  */
7943                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7944                         uint8_t other_port = !(PORT_ID(sc) & 1);
7945                         uint8_t abs_func_other_port =
7946                             (SC_PATH(sc) + (2 * other_port));
7947
7948                         val =
7949                             MFCFG_RD(sc,
7950                                      func_mf_config
7951                                      [abs_func_other_port].e1hov_tag);
7952
7953                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7954                 }
7955         }
7956
7957         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7958 /* invalid MF config */
7959                 if (SC_VN(sc) >= 1) {
7960                         PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
7961                         return 1;
7962                 }
7963
7964                 return 0;
7965         }
7966
7967         /* get the MF configuration */
7968         mf_info->mf_config[SC_VN(sc)] =
7969             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7970
7971         switch (mf_info->mf_mode) {
7972         case MULTI_FUNCTION_SD:
7973
7974                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7975                 break;
7976
7977         case MULTI_FUNCTION_SI:
7978
7979                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7980                 break;
7981
7982         case MULTI_FUNCTION_AFEX:
7983
7984                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7985                 break;
7986
7987         default:
7988
7989                 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
7990                             mf_info->mf_mode);
7991                 return 1;
7992         }
7993
7994         /* get the congestion management parameters */
7995
7996         vnic = 0;
7997         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7998 /* get min/max bw */
7999                 val = MFCFG_RD(sc, func_mf_config[i].config);
8000                 mf_info->min_bw[vnic] =
8001                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8002                      FUNC_MF_CFG_MIN_BW_SHIFT);
8003                 mf_info->max_bw[vnic] =
8004                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8005                      FUNC_MF_CFG_MAX_BW_SHIFT);
8006                 vnic++;
8007         }
8008
8009         return bnx2x_check_valid_mf_cfg(sc);
8010 }
8011
8012 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8013 {
8014         int port;
8015         uint32_t mac_hi, mac_lo, val;
8016
8017         PMD_INIT_FUNC_TRACE(sc);
8018
8019         port = SC_PORT(sc);
8020         mac_hi = mac_lo = 0;
8021
8022         sc->link_params.sc = sc;
8023         sc->link_params.port = port;
8024
8025         /* get the hardware config info */
8026         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8027         sc->devinfo.hw_config2 =
8028             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8029
8030         sc->link_params.hw_led_mode =
8031             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8032              SHARED_HW_CFG_LED_MODE_SHIFT);
8033
8034         /* get the port feature config */
8035         sc->port.config =
8036             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8037
8038         /* get the link params */
8039         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8040             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8041             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8042         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8043             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8044             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8045
8046         /* get the lane config */
8047         sc->link_params.lane_config =
8048             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8049
8050         /* get the link config */
8051         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8052         sc->port.link_config[ELINK_INT_PHY] = val;
8053         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8054         sc->port.link_config[ELINK_EXT_PHY1] =
8055             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8056
8057         /* get the override preemphasis flag and enable it or turn it off */
8058         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8059         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8060                 sc->link_params.feature_config_flags |=
8061                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8062         } else {
8063                 sc->link_params.feature_config_flags &=
8064                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8065         }
8066
8067         /* get the initial value of the link params */
8068         sc->link_params.multi_phy_config =
8069             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8070
8071         /* get external phy info */
8072         sc->port.ext_phy_config =
8073             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8074
8075         /* get the multifunction configuration */
8076         bnx2x_get_mf_cfg_info(sc);
8077
8078         /* get the mac address */
8079         if (IS_MF(sc)) {
8080                 mac_hi =
8081                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8082                 mac_lo =
8083                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8084         } else {
8085                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8086                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8087         }
8088
8089         if ((mac_lo == 0) && (mac_hi == 0)) {
8090                 *sc->mac_addr_str = 0;
8091                 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8092         } else {
8093                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8094                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8095                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8096                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8097                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8098                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8099                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8100                          "%02x:%02x:%02x:%02x:%02x:%02x",
8101                          sc->link_params.mac_addr[0],
8102                          sc->link_params.mac_addr[1],
8103                          sc->link_params.mac_addr[2],
8104                          sc->link_params.mac_addr[3],
8105                          sc->link_params.mac_addr[4],
8106                          sc->link_params.mac_addr[5]);
8107                 PMD_DRV_LOG(DEBUG, sc,
8108                             "Ethernet address: %s", sc->mac_addr_str);
8109         }
8110
8111         return 0;
8112 }
8113
8114 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8115 {
8116         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8117         switch (sc->link_params.phy[phy_idx].media_type) {
8118         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8119         case ELINK_ETH_PHY_SFP_1G_FIBER:
8120         case ELINK_ETH_PHY_XFP_FIBER:
8121         case ELINK_ETH_PHY_KR:
8122         case ELINK_ETH_PHY_CX4:
8123                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8124                 sc->media = IFM_10G_CX4;
8125                 break;
8126         case ELINK_ETH_PHY_DA_TWINAX:
8127                 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8128                 sc->media = IFM_10G_TWINAX;
8129                 break;
8130         case ELINK_ETH_PHY_BASE_T:
8131                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8132                 sc->media = IFM_10G_T;
8133                 break;
8134         case ELINK_ETH_PHY_NOT_PRESENT:
8135                 PMD_DRV_LOG(INFO, sc, "Media not present.");
8136                 sc->media = 0;
8137                 break;
8138         case ELINK_ETH_PHY_UNSPECIFIED:
8139         default:
8140                 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8141                 sc->media = 0;
8142                 break;
8143         }
8144 }
8145
8146 #define GET_FIELD(value, fname)                     \
8147 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8148 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8149 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8150
8151 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8152 {
8153         int pfid = SC_FUNC(sc);
8154         int igu_sb_id;
8155         uint32_t val;
8156         uint8_t fid, igu_sb_cnt = 0;
8157
8158         sc->igu_base_sb = 0xff;
8159
8160         if (CHIP_INT_MODE_IS_BC(sc)) {
8161                 int vn = SC_VN(sc);
8162                 igu_sb_cnt = sc->igu_sb_cnt;
8163                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8164                                    FP_SB_MAX_E1x);
8165                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8166                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8167                 return 0;
8168         }
8169
8170         /* IGU in normal mode - read CAM */
8171         for (igu_sb_id = 0;
8172              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8173                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8174                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8175                         continue;
8176                 }
8177                 fid = IGU_FID(val);
8178                 if (fid & IGU_FID_ENCODE_IS_PF) {
8179                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8180                                 continue;
8181                         }
8182                         if (IGU_VEC(val) == 0) {
8183                                 /* default status block */
8184                                 sc->igu_dsb_id = igu_sb_id;
8185                         } else {
8186                                 if (sc->igu_base_sb == 0xff) {
8187                                         sc->igu_base_sb = igu_sb_id;
8188                                 }
8189                                 igu_sb_cnt++;
8190                         }
8191                 }
8192         }
8193
8194         /*
8195          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8196          * that number of CAM entries will not be equal to the value advertised in
8197          * PCI. Driver should use the minimal value of both as the actual status
8198          * block count
8199          */
8200         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8201
8202         if (igu_sb_cnt == 0) {
8203                 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8204                 return -1;
8205         }
8206
8207         return 0;
8208 }
8209
8210 /*
8211 * Gather various information from the device config space, the device itself,
8212 * shmem, and the user input.
8213 */
8214 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8215 {
8216         uint32_t val;
8217         int rc;
8218
8219         /* get the chip revision (chip metal comes from pci config space) */
8220         sc->devinfo.chip_id = sc->link_params.chip_id =
8221             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8222              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8223              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8224              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8225
8226         /* force 57811 according to MISC register */
8227         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8228                 if (CHIP_IS_57810(sc)) {
8229                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8230                                                (sc->
8231                                                 devinfo.chip_id & 0x0000ffff));
8232                 } else if (CHIP_IS_57810_MF(sc)) {
8233                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8234                                                (sc->
8235                                                 devinfo.chip_id & 0x0000ffff));
8236                 }
8237                 sc->devinfo.chip_id |= 0x1;
8238         }
8239
8240         PMD_DRV_LOG(DEBUG, sc,
8241                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8242                     sc->devinfo.chip_id,
8243                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8244                     ((sc->devinfo.chip_id >> 12) & 0xf),
8245                     ((sc->devinfo.chip_id >> 4) & 0xff),
8246                     ((sc->devinfo.chip_id >> 0) & 0xf));
8247
8248         val = (REG_RD(sc, 0x2874) & 0x55);
8249         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8250                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8251                 PMD_DRV_LOG(DEBUG, sc, "single port device");
8252         }
8253
8254         /* set the doorbell size */
8255         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8256
8257         /* determine whether the device is in 2 port or 4 port mode */
8258         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8259         if (CHIP_IS_E2E3(sc)) {
8260 /*
8261  * Read port4mode_en_ovwr[0]:
8262  *   If 1, four port mode is in port4mode_en_ovwr[1].
8263  *   If 0, four port mode is in port4mode_en[0].
8264  */
8265                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8266                 if (val & 1) {
8267                         val = ((val >> 1) & 1);
8268                 } else {
8269                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8270                 }
8271
8272                 sc->devinfo.chip_port_mode =
8273                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8274
8275                 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8276         }
8277
8278         /* get the function and path info for the device */
8279         bnx2x_get_function_num(sc);
8280
8281         /* get the shared memory base address */
8282         sc->devinfo.shmem_base =
8283             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8284         sc->devinfo.shmem2_base =
8285             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8286                         MISC_REG_GENERIC_CR_0));
8287
8288         if (!sc->devinfo.shmem_base) {
8289 /* this should ONLY prevent upcoming shmem reads */
8290                 PMD_DRV_LOG(INFO, sc, "MCP not active");
8291                 sc->flags |= BNX2X_NO_MCP_FLAG;
8292                 return 0;
8293         }
8294
8295         /* make sure the shared memory contents are valid */
8296         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8297         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8298             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8299                 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8300                             val);
8301                 return 0;
8302         }
8303
8304         /* get the bootcode version */
8305         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8306         snprintf(sc->devinfo.bc_ver_str,
8307                  sizeof(sc->devinfo.bc_ver_str),
8308                  "%d.%d.%d",
8309                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8310                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8311                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8312         PMD_DRV_LOG(INFO, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8313
8314         /* get the bootcode shmem address */
8315         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8316
8317         /* clean indirect addresses as they're not used */
8318         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8319         if (IS_PF(sc)) {
8320                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8321                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8322                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8323                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8324                 if (CHIP_IS_E1x(sc)) {
8325                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8326                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8327                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8328                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8329                 }
8330         }
8331
8332         /* get the nvram size */
8333         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8334         sc->devinfo.flash_size =
8335             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8336
8337         bnx2x_set_power_state(sc, PCI_PM_D0);
8338         /* get various configuration parameters from shmem */
8339         bnx2x_get_shmem_info(sc);
8340
8341         /* initialize IGU parameters */
8342         if (CHIP_IS_E1x(sc)) {
8343                 sc->devinfo.int_block = INT_BLOCK_HC;
8344                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8345                 sc->igu_base_sb = 0;
8346         } else {
8347                 sc->devinfo.int_block = INT_BLOCK_IGU;
8348
8349 /* do not allow device reset during IGU info preocessing */
8350                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8351
8352                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8353
8354                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8355                         int tout = 5000;
8356
8357                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8358                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8359                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8360
8361                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8362                                 tout--;
8363                                 DELAY(1000);
8364                         }
8365
8366                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8367                                 PMD_DRV_LOG(NOTICE, sc,
8368                                             "FORCING IGU Normal Mode failed!!!");
8369                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8370                                 return -1;
8371                         }
8372                 }
8373
8374                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8375                         PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8376                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8377                 } else {
8378                         PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8379                 }
8380
8381                 rc = bnx2x_get_igu_cam_info(sc);
8382
8383                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8384
8385                 if (rc) {
8386                         return rc;
8387                 }
8388         }
8389
8390         /*
8391          * Get base FW non-default (fast path) status block ID. This value is
8392          * used to initialize the fw_sb_id saved on the fp/queue structure to
8393          * determine the id used by the FW.
8394          */
8395         if (CHIP_IS_E1x(sc)) {
8396                 sc->base_fw_ndsb =
8397                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8398         } else {
8399 /*
8400  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8401  * the same queue are indicated on the same IGU SB). So we prefer
8402  * FW and IGU SBs to be the same value.
8403  */
8404                 sc->base_fw_ndsb = sc->igu_base_sb;
8405         }
8406
8407         elink_phy_probe(&sc->link_params);
8408
8409         return 0;
8410 }
8411
8412 static void
8413 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8414 {
8415         uint32_t cfg_size = 0;
8416         uint32_t idx;
8417         uint8_t port = SC_PORT(sc);
8418
8419         /* aggregation of supported attributes of all external phys */
8420         sc->port.supported[0] = 0;
8421         sc->port.supported[1] = 0;
8422
8423         switch (sc->link_params.num_phys) {
8424         case 1:
8425                 sc->port.supported[0] =
8426                     sc->link_params.phy[ELINK_INT_PHY].supported;
8427                 cfg_size = 1;
8428                 break;
8429         case 2:
8430                 sc->port.supported[0] =
8431                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8432                 cfg_size = 1;
8433                 break;
8434         case 3:
8435                 if (sc->link_params.multi_phy_config &
8436                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8437                         sc->port.supported[1] =
8438                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8439                         sc->port.supported[0] =
8440                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8441                 } else {
8442                         sc->port.supported[0] =
8443                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8444                         sc->port.supported[1] =
8445                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8446                 }
8447                 cfg_size = 2;
8448                 break;
8449         }
8450
8451         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8452                 PMD_DRV_LOG(ERR, sc,
8453                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8454                             SHMEM_RD(sc,
8455                                      dev_info.port_hw_config
8456                                      [port].external_phy_config),
8457                             SHMEM_RD(sc,
8458                                      dev_info.port_hw_config
8459                                      [port].external_phy_config2));
8460                 return;
8461         }
8462
8463         if (CHIP_IS_E3(sc))
8464                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8465         else {
8466                 switch (switch_cfg) {
8467                 case ELINK_SWITCH_CFG_1G:
8468                         sc->port.phy_addr =
8469                             REG_RD(sc,
8470                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8471                         break;
8472                 case ELINK_SWITCH_CFG_10G:
8473                         sc->port.phy_addr =
8474                             REG_RD(sc,
8475                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8476                         break;
8477                 default:
8478                         PMD_DRV_LOG(ERR, sc,
8479                                     "Invalid switch config in"
8480                                     "link_config=0x%08x",
8481                                     sc->port.link_config[0]);
8482                         return;
8483                 }
8484         }
8485
8486         PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8487
8488         /* mask what we support according to speed_cap_mask per configuration */
8489         for (idx = 0; idx < cfg_size; idx++) {
8490                 if (!(sc->link_params.speed_cap_mask[idx] &
8491                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8492                         sc->port.supported[idx] &=
8493                             ~ELINK_SUPPORTED_10baseT_Half;
8494                 }
8495
8496                 if (!(sc->link_params.speed_cap_mask[idx] &
8497                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8498                         sc->port.supported[idx] &=
8499                             ~ELINK_SUPPORTED_10baseT_Full;
8500                 }
8501
8502                 if (!(sc->link_params.speed_cap_mask[idx] &
8503                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8504                         sc->port.supported[idx] &=
8505                             ~ELINK_SUPPORTED_100baseT_Half;
8506                 }
8507
8508                 if (!(sc->link_params.speed_cap_mask[idx] &
8509                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8510                         sc->port.supported[idx] &=
8511                             ~ELINK_SUPPORTED_100baseT_Full;
8512                 }
8513
8514                 if (!(sc->link_params.speed_cap_mask[idx] &
8515                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8516                         sc->port.supported[idx] &=
8517                             ~ELINK_SUPPORTED_1000baseT_Full;
8518                 }
8519
8520                 if (!(sc->link_params.speed_cap_mask[idx] &
8521                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8522                         sc->port.supported[idx] &=
8523                             ~ELINK_SUPPORTED_2500baseX_Full;
8524                 }
8525
8526                 if (!(sc->link_params.speed_cap_mask[idx] &
8527                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8528                         sc->port.supported[idx] &=
8529                             ~ELINK_SUPPORTED_10000baseT_Full;
8530                 }
8531
8532                 if (!(sc->link_params.speed_cap_mask[idx] &
8533                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8534                         sc->port.supported[idx] &=
8535                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8536                 }
8537         }
8538
8539         PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8540                     sc->port.supported[0], sc->port.supported[1]);
8541 }
8542
8543 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8544 {
8545         uint32_t link_config;
8546         uint32_t idx;
8547         uint32_t cfg_size = 0;
8548
8549         sc->port.advertising[0] = 0;
8550         sc->port.advertising[1] = 0;
8551
8552         switch (sc->link_params.num_phys) {
8553         case 1:
8554         case 2:
8555                 cfg_size = 1;
8556                 break;
8557         case 3:
8558                 cfg_size = 2;
8559                 break;
8560         }
8561
8562         for (idx = 0; idx < cfg_size; idx++) {
8563                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8564                 link_config = sc->port.link_config[idx];
8565
8566                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8567                 case PORT_FEATURE_LINK_SPEED_AUTO:
8568                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8569                                 sc->link_params.req_line_speed[idx] =
8570                                     ELINK_SPEED_AUTO_NEG;
8571                                 sc->port.advertising[idx] |=
8572                                     sc->port.supported[idx];
8573                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8574                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8575                                         sc->port.advertising[idx] |=
8576                                             (ELINK_SUPPORTED_100baseT_Half |
8577                                              ELINK_SUPPORTED_100baseT_Full);
8578                         } else {
8579                                 /* force 10G, no AN */
8580                                 sc->link_params.req_line_speed[idx] =
8581                                     ELINK_SPEED_10000;
8582                                 sc->port.advertising[idx] |=
8583                                     (ADVERTISED_10000baseT_Full |
8584                                      ADVERTISED_FIBRE);
8585                                 continue;
8586                         }
8587                         break;
8588
8589                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8590                         if (sc->
8591                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8592                         {
8593                                 sc->link_params.req_line_speed[idx] =
8594                                     ELINK_SPEED_10;
8595                                 sc->port.advertising[idx] |=
8596                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8597                         } else {
8598                                 PMD_DRV_LOG(ERR, sc,
8599                                             "Invalid NVRAM config link_config=0x%08x "
8600                                             "speed_cap_mask=0x%08x",
8601                                             link_config,
8602                                             sc->
8603                                             link_params.speed_cap_mask[idx]);
8604                                 return;
8605                         }
8606                         break;
8607
8608                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8609                         if (sc->
8610                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8611                         {
8612                                 sc->link_params.req_line_speed[idx] =
8613                                     ELINK_SPEED_10;
8614                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8615                                 sc->port.advertising[idx] |=
8616                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8617                         } else {
8618                                 PMD_DRV_LOG(ERR, sc,
8619                                             "Invalid NVRAM config link_config=0x%08x "
8620                                             "speed_cap_mask=0x%08x",
8621                                             link_config,
8622                                             sc->
8623                                             link_params.speed_cap_mask[idx]);
8624                                 return;
8625                         }
8626                         break;
8627
8628                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8629                         if (sc->
8630                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8631                         {
8632                                 sc->link_params.req_line_speed[idx] =
8633                                     ELINK_SPEED_100;
8634                                 sc->port.advertising[idx] |=
8635                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8636                         } else {
8637                                 PMD_DRV_LOG(ERR, sc,
8638                                             "Invalid NVRAM config link_config=0x%08x "
8639                                             "speed_cap_mask=0x%08x",
8640                                             link_config,
8641                                             sc->
8642                                             link_params.speed_cap_mask[idx]);
8643                                 return;
8644                         }
8645                         break;
8646
8647                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8648                         if (sc->
8649                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8650                         {
8651                                 sc->link_params.req_line_speed[idx] =
8652                                     ELINK_SPEED_100;
8653                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8654                                 sc->port.advertising[idx] |=
8655                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8656                         } else {
8657                                 PMD_DRV_LOG(ERR, sc,
8658                                             "Invalid NVRAM config link_config=0x%08x "
8659                                             "speed_cap_mask=0x%08x",
8660                                             link_config,
8661                                             sc->
8662                                             link_params.speed_cap_mask[idx]);
8663                                 return;
8664                         }
8665                         break;
8666
8667                 case PORT_FEATURE_LINK_SPEED_1G:
8668                         if (sc->port.supported[idx] &
8669                             ELINK_SUPPORTED_1000baseT_Full) {
8670                                 sc->link_params.req_line_speed[idx] =
8671                                     ELINK_SPEED_1000;
8672                                 sc->port.advertising[idx] |=
8673                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8674                         } else {
8675                                 PMD_DRV_LOG(ERR, sc,
8676                                             "Invalid NVRAM config link_config=0x%08x "
8677                                             "speed_cap_mask=0x%08x",
8678                                             link_config,
8679                                             sc->
8680                                             link_params.speed_cap_mask[idx]);
8681                                 return;
8682                         }
8683                         break;
8684
8685                 case PORT_FEATURE_LINK_SPEED_2_5G:
8686                         if (sc->port.supported[idx] &
8687                             ELINK_SUPPORTED_2500baseX_Full) {
8688                                 sc->link_params.req_line_speed[idx] =
8689                                     ELINK_SPEED_2500;
8690                                 sc->port.advertising[idx] |=
8691                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8692                         } else {
8693                                 PMD_DRV_LOG(ERR, sc,
8694                                             "Invalid NVRAM config link_config=0x%08x "
8695                                             "speed_cap_mask=0x%08x",
8696                                             link_config,
8697                                             sc->
8698                                             link_params.speed_cap_mask[idx]);
8699                                 return;
8700                         }
8701                         break;
8702
8703                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8704                         if (sc->port.supported[idx] &
8705                             ELINK_SUPPORTED_10000baseT_Full) {
8706                                 sc->link_params.req_line_speed[idx] =
8707                                     ELINK_SPEED_10000;
8708                                 sc->port.advertising[idx] |=
8709                                     (ADVERTISED_10000baseT_Full |
8710                                      ADVERTISED_FIBRE);
8711                         } else {
8712                                 PMD_DRV_LOG(ERR, sc,
8713                                             "Invalid NVRAM config link_config=0x%08x "
8714                                             "speed_cap_mask=0x%08x",
8715                                             link_config,
8716                                             sc->
8717                                             link_params.speed_cap_mask[idx]);
8718                                 return;
8719                         }
8720                         break;
8721
8722                 case PORT_FEATURE_LINK_SPEED_20G:
8723                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8724                         break;
8725
8726                 default:
8727                         PMD_DRV_LOG(ERR, sc,
8728                                     "Invalid NVRAM config link_config=0x%08x "
8729                                     "speed_cap_mask=0x%08x", link_config,
8730                                     sc->link_params.speed_cap_mask[idx]);
8731                         sc->link_params.req_line_speed[idx] =
8732                             ELINK_SPEED_AUTO_NEG;
8733                         sc->port.advertising[idx] = sc->port.supported[idx];
8734                         break;
8735                 }
8736
8737                 sc->link_params.req_flow_ctrl[idx] =
8738                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8739
8740                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8741                         if (!
8742                             (sc->
8743                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8744                                 sc->link_params.req_flow_ctrl[idx] =
8745                                     ELINK_FLOW_CTRL_NONE;
8746                         } else {
8747                                 bnx2x_set_requested_fc(sc);
8748                         }
8749                 }
8750         }
8751 }
8752
8753 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8754 {
8755         uint8_t port = SC_PORT(sc);
8756         uint32_t eee_mode;
8757
8758         PMD_INIT_FUNC_TRACE(sc);
8759
8760         /* shmem data already read in bnx2x_get_shmem_info() */
8761
8762         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8763         bnx2x_link_settings_requested(sc);
8764
8765         /* configure link feature according to nvram value */
8766         eee_mode =
8767             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8768               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8769              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8770         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8771                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8772                                             ELINK_EEE_MODE_ENABLE_LPI |
8773                                             ELINK_EEE_MODE_OUTPUT_TIME);
8774         } else {
8775                 sc->link_params.eee_mode = 0;
8776         }
8777
8778         /* get the media type */
8779         bnx2x_media_detect(sc);
8780 }
8781
8782 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8783 {
8784         uint32_t flags = MODE_ASIC | MODE_PORT2;
8785
8786         if (CHIP_IS_E2(sc)) {
8787                 flags |= MODE_E2;
8788         } else if (CHIP_IS_E3(sc)) {
8789                 flags |= MODE_E3;
8790                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8791                         flags |= MODE_E3_A0;
8792                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8793
8794                         flags |= MODE_E3_B0 | MODE_COS3;
8795                 }
8796         }
8797
8798         if (IS_MF(sc)) {
8799                 flags |= MODE_MF;
8800                 switch (sc->devinfo.mf_info.mf_mode) {
8801                 case MULTI_FUNCTION_SD:
8802                         flags |= MODE_MF_SD;
8803                         break;
8804                 case MULTI_FUNCTION_SI:
8805                         flags |= MODE_MF_SI;
8806                         break;
8807                 case MULTI_FUNCTION_AFEX:
8808                         flags |= MODE_MF_AFEX;
8809                         break;
8810                 }
8811         } else {
8812                 flags |= MODE_SF;
8813         }
8814
8815 #if defined(__LITTLE_ENDIAN)
8816         flags |= MODE_LITTLE_ENDIAN;
8817 #else /* __BIG_ENDIAN */
8818         flags |= MODE_BIG_ENDIAN;
8819 #endif
8820
8821         INIT_MODE_FLAGS(sc) = flags;
8822 }
8823
8824 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8825 {
8826         struct bnx2x_fastpath *fp;
8827         char buf[32];
8828         uint32_t i;
8829
8830         if (IS_PF(sc)) {
8831 /************************/
8832 /* DEFAULT STATUS BLOCK */
8833 /************************/
8834
8835                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8836                                   &sc->def_sb_dma, "def_sb",
8837                                   RTE_CACHE_LINE_SIZE) != 0) {
8838                         return -1;
8839                 }
8840
8841                 sc->def_sb =
8842                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8843 /***************/
8844 /* EVENT QUEUE */
8845 /***************/
8846
8847                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8848                                   &sc->eq_dma, "ev_queue",
8849                                   RTE_CACHE_LINE_SIZE) != 0) {
8850                         sc->def_sb = NULL;
8851                         return -1;
8852                 }
8853
8854                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8855
8856 /*************/
8857 /* SLOW PATH */
8858 /*************/
8859
8860                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8861                                   &sc->sp_dma, "sp",
8862                                   RTE_CACHE_LINE_SIZE) != 0) {
8863                         sc->eq = NULL;
8864                         sc->def_sb = NULL;
8865                         return -1;
8866                 }
8867
8868                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8869
8870 /*******************/
8871 /* SLOW PATH QUEUE */
8872 /*******************/
8873
8874                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8875                                   &sc->spq_dma, "sp_queue",
8876                                   RTE_CACHE_LINE_SIZE) != 0) {
8877                         sc->sp = NULL;
8878                         sc->eq = NULL;
8879                         sc->def_sb = NULL;
8880                         return -1;
8881                 }
8882
8883                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8884
8885 /***************************/
8886 /* FW DECOMPRESSION BUFFER */
8887 /***************************/
8888
8889                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8890                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8891                         sc->spq = NULL;
8892                         sc->sp = NULL;
8893                         sc->eq = NULL;
8894                         sc->def_sb = NULL;
8895                         return -1;
8896                 }
8897
8898                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8899         }
8900
8901         /*************/
8902         /* FASTPATHS */
8903         /*************/
8904
8905         /* allocate DMA memory for each fastpath structure */
8906         for (i = 0; i < sc->num_queues; i++) {
8907                 fp = &sc->fp[i];
8908                 fp->sc = sc;
8909                 fp->index = i;
8910
8911 /*******************/
8912 /* FP STATUS BLOCK */
8913 /*******************/
8914
8915                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8916                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8917                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8918                         PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8919                         return -1;
8920                 } else {
8921                         if (CHIP_IS_E2E3(sc)) {
8922                                 fp->status_block.e2_sb =
8923                                     (struct host_hc_status_block_e2 *)
8924                                     fp->sb_dma.vaddr;
8925                         } else {
8926                                 fp->status_block.e1x_sb =
8927                                     (struct host_hc_status_block_e1x *)
8928                                     fp->sb_dma.vaddr;
8929                         }
8930                 }
8931         }
8932
8933         return 0;
8934 }
8935
8936 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8937 {
8938         struct bnx2x_fastpath *fp;
8939         int i;
8940
8941         for (i = 0; i < sc->num_queues; i++) {
8942                 fp = &sc->fp[i];
8943
8944 /*******************/
8945 /* FP STATUS BLOCK */
8946 /*******************/
8947
8948                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8949         }
8950
8951         /***************************/
8952         /* FW DECOMPRESSION BUFFER */
8953         /***************************/
8954
8955         sc->gz_buf = NULL;
8956
8957         /*******************/
8958         /* SLOW PATH QUEUE */
8959         /*******************/
8960
8961         sc->spq = NULL;
8962
8963         /*************/
8964         /* SLOW PATH */
8965         /*************/
8966
8967         sc->sp = NULL;
8968
8969         /***************/
8970         /* EVENT QUEUE */
8971         /***************/
8972
8973         sc->eq = NULL;
8974
8975         /************************/
8976         /* DEFAULT STATUS BLOCK */
8977         /************************/
8978
8979         sc->def_sb = NULL;
8980
8981 }
8982
8983 /*
8984 * Previous driver DMAE transaction may have occurred when pre-boot stage
8985 * ended and boot began. This would invalidate the addresses of the
8986 * transaction, resulting in was-error bit set in the PCI causing all
8987 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8988 * the interrupt which detected this from the pglueb and the was-done bit
8989 */
8990 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8991 {
8992         uint32_t val;
8993
8994         if (!CHIP_IS_E1x(sc)) {
8995                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8996                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8997                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8998                                1 << SC_FUNC(sc));
8999                 }
9000         }
9001 }
9002
9003 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9004 {
9005         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9006                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9007         if (!rc) {
9008                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9009                 return -1;
9010         }
9011
9012         return 0;
9013 }
9014
9015 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9016 {
9017         struct bnx2x_prev_list_node *tmp;
9018
9019         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9020                 if ((sc->pcie_bus == tmp->bus) &&
9021                     (sc->pcie_device == tmp->slot) &&
9022                     (SC_PATH(sc) == tmp->path)) {
9023                         return tmp;
9024                 }
9025         }
9026
9027         return NULL;
9028 }
9029
9030 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9031 {
9032         struct bnx2x_prev_list_node *tmp;
9033         int rc = FALSE;
9034
9035         rte_spinlock_lock(&bnx2x_prev_mtx);
9036
9037         tmp = bnx2x_prev_path_get_entry(sc);
9038         if (tmp) {
9039                 if (tmp->aer) {
9040                         PMD_DRV_LOG(DEBUG, sc,
9041                                     "Path %d/%d/%d was marked by AER",
9042                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9043                 } else {
9044                         rc = TRUE;
9045                         PMD_DRV_LOG(DEBUG, sc,
9046                                     "Path %d/%d/%d was already cleaned from previous drivers",
9047                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9048                 }
9049         }
9050
9051         rte_spinlock_unlock(&bnx2x_prev_mtx);
9052
9053         return rc;
9054 }
9055
9056 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9057 {
9058         struct bnx2x_prev_list_node *tmp;
9059
9060         rte_spinlock_lock(&bnx2x_prev_mtx);
9061
9062         /* Check whether the entry for this path already exists */
9063         tmp = bnx2x_prev_path_get_entry(sc);
9064         if (tmp) {
9065                 if (!tmp->aer) {
9066                         PMD_DRV_LOG(DEBUG, sc,
9067                                     "Re-marking AER in path %d/%d/%d",
9068                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9069                 } else {
9070                         PMD_DRV_LOG(DEBUG, sc,
9071                                     "Removing AER indication from path %d/%d/%d",
9072                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9073                         tmp->aer = 0;
9074                 }
9075
9076                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9077                 return 0;
9078         }
9079
9080         rte_spinlock_unlock(&bnx2x_prev_mtx);
9081
9082         /* Create an entry for this path and add it */
9083         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9084                          RTE_CACHE_LINE_SIZE);
9085         if (!tmp) {
9086                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9087                 return -1;
9088         }
9089
9090         tmp->bus = sc->pcie_bus;
9091         tmp->slot = sc->pcie_device;
9092         tmp->path = SC_PATH(sc);
9093         tmp->aer = 0;
9094         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9095
9096         rte_spinlock_lock(&bnx2x_prev_mtx);
9097
9098         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9099
9100         rte_spinlock_unlock(&bnx2x_prev_mtx);
9101
9102         return 0;
9103 }
9104
9105 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9106 {
9107         int i;
9108
9109         /* only E2 and onwards support FLR */
9110         if (CHIP_IS_E1x(sc)) {
9111                 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9112                 return -1;
9113         }
9114
9115         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9116         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9117                 PMD_DRV_LOG(WARNING, sc,
9118                             "FLR not supported by BC_VER: 0x%08x",
9119                             sc->devinfo.bc_ver);
9120                 return -1;
9121         }
9122
9123         /* Wait for Transaction Pending bit clean */
9124         for (i = 0; i < 4; i++) {
9125                 if (i) {
9126                         DELAY(((1 << (i - 1)) * 100) * 1000);
9127                 }
9128
9129                 if (!bnx2x_is_pcie_pending(sc)) {
9130                         goto clear;
9131                 }
9132         }
9133
9134         PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9135                     "proceeding with reset anyway");
9136
9137 clear:
9138         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9139
9140         return 0;
9141 }
9142
9143 struct bnx2x_mac_vals {
9144         uint32_t xmac_addr;
9145         uint32_t xmac_val;
9146         uint32_t emac_addr;
9147         uint32_t emac_val;
9148         uint32_t umac_addr;
9149         uint32_t umac_val;
9150         uint32_t bmac_addr;
9151         uint32_t bmac_val[2];
9152 };
9153
9154 static void
9155 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9156 {
9157         uint32_t val, base_addr, offset, mask, reset_reg;
9158         uint8_t mac_stopped = FALSE;
9159         uint8_t port = SC_PORT(sc);
9160         uint32_t wb_data[2];
9161
9162         /* reset addresses as they also mark which values were changed */
9163         vals->bmac_addr = 0;
9164         vals->umac_addr = 0;
9165         vals->xmac_addr = 0;
9166         vals->emac_addr = 0;
9167
9168         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9169
9170         if (!CHIP_IS_E3(sc)) {
9171                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9172                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9173                 if ((mask & reset_reg) && val) {
9174                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9175                             : NIG_REG_INGRESS_BMAC0_MEM;
9176                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9177                             : BIGMAC_REGISTER_BMAC_CONTROL;
9178
9179                         /*
9180                          * use rd/wr since we cannot use dmae. This is safe
9181                          * since MCP won't access the bus due to the request
9182                          * to unload, and no function on the path can be
9183                          * loaded at this time.
9184                          */
9185                         wb_data[0] = REG_RD(sc, base_addr + offset);
9186                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9187                         vals->bmac_addr = base_addr + offset;
9188                         vals->bmac_val[0] = wb_data[0];
9189                         vals->bmac_val[1] = wb_data[1];
9190                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9191                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9192                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9193                 }
9194
9195                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9196                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9197                 REG_WR(sc, vals->emac_addr, 0);
9198                 mac_stopped = TRUE;
9199         } else {
9200                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9201                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9202                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9203                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9204                                val & ~(1 << 1));
9205                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9206                                val | (1 << 1));
9207                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9208                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9209                         REG_WR(sc, vals->xmac_addr, 0);
9210                         mac_stopped = TRUE;
9211                 }
9212
9213                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9214                 if (mask & reset_reg) {
9215                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9216                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9217                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9218                         REG_WR(sc, vals->umac_addr, 0);
9219                         mac_stopped = TRUE;
9220                 }
9221         }
9222
9223         if (mac_stopped) {
9224                 DELAY(20000);
9225         }
9226 }
9227
9228 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9229 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9230 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9231 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9232
9233 static void
9234 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9235 {
9236         uint16_t rcq, bd;
9237         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9238
9239         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9240         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9241
9242         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9243         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9244 }
9245
9246 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9247 {
9248         uint32_t reset_reg, tmp_reg = 0, rc;
9249         uint8_t prev_undi = FALSE;
9250         struct bnx2x_mac_vals mac_vals;
9251         uint32_t timer_count = 1000;
9252         uint32_t prev_brb;
9253
9254         /*
9255          * It is possible a previous function received 'common' answer,
9256          * but hasn't loaded yet, therefore creating a scenario of
9257          * multiple functions receiving 'common' on the same path.
9258          */
9259         memset(&mac_vals, 0, sizeof(mac_vals));
9260
9261         if (bnx2x_prev_is_path_marked(sc)) {
9262                 return bnx2x_prev_mcp_done(sc);
9263         }
9264
9265         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9266
9267         /* Reset should be performed after BRB is emptied */
9268         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9269                 /* Close the MAC Rx to prevent BRB from filling up */
9270                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9271
9272                 /* close LLH filters towards the BRB */
9273                 elink_set_rx_filter(&sc->link_params, 0);
9274
9275                 /*
9276                  * Check if the UNDI driver was previously loaded.
9277                  * UNDI driver initializes CID offset for normal bell to 0x7
9278                  */
9279                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9280                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9281                         if (tmp_reg == 0x7) {
9282                                 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9283                                 prev_undi = TRUE;
9284                                 /* clear the UNDI indication */
9285                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9286                                 /* clear possible idle check errors */
9287                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9288                         }
9289                 }
9290
9291                 /* wait until BRB is empty */
9292                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9293                 while (timer_count) {
9294                         prev_brb = tmp_reg;
9295
9296                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9297                         if (!tmp_reg) {
9298                                 break;
9299                         }
9300
9301                         PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9302
9303                         /* reset timer as long as BRB actually gets emptied */
9304                         if (prev_brb > tmp_reg) {
9305                                 timer_count = 1000;
9306                         } else {
9307                                 timer_count--;
9308                         }
9309
9310                         /* If UNDI resides in memory, manually increment it */
9311                         if (prev_undi) {
9312                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9313                         }
9314
9315                         DELAY(10);
9316                 }
9317
9318                 if (!timer_count) {
9319                         PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9320                 }
9321         }
9322
9323         /* No packets are in the pipeline, path is ready for reset */
9324         bnx2x_reset_common(sc);
9325
9326         if (mac_vals.xmac_addr) {
9327                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9328         }
9329         if (mac_vals.umac_addr) {
9330                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9331         }
9332         if (mac_vals.emac_addr) {
9333                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9334         }
9335         if (mac_vals.bmac_addr) {
9336                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9337                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9338         }
9339
9340         rc = bnx2x_prev_mark_path(sc, prev_undi);
9341         if (rc) {
9342                 bnx2x_prev_mcp_done(sc);
9343                 return rc;
9344         }
9345
9346         return bnx2x_prev_mcp_done(sc);
9347 }
9348
9349 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9350 {
9351         int rc;
9352
9353         /* Test if previous unload process was already finished for this path */
9354         if (bnx2x_prev_is_path_marked(sc)) {
9355                 return bnx2x_prev_mcp_done(sc);
9356         }
9357
9358         /*
9359          * If function has FLR capabilities, and existing FW version matches
9360          * the one required, then FLR will be sufficient to clean any residue
9361          * left by previous driver
9362          */
9363         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9364         if (!rc) {
9365                 /* fw version is good */
9366                 rc = bnx2x_do_flr(sc);
9367         }
9368
9369         if (!rc) {
9370                 /* FLR was performed */
9371                 return 0;
9372         }
9373
9374         PMD_DRV_LOG(INFO, sc, "Could not FLR");
9375
9376         /* Close the MCP request, return failure */
9377         rc = bnx2x_prev_mcp_done(sc);
9378         if (!rc) {
9379                 rc = BNX2X_PREV_WAIT_NEEDED;
9380         }
9381
9382         return rc;
9383 }
9384
9385 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9386 {
9387         int time_counter = 10;
9388         uint32_t fw, hw_lock_reg, hw_lock_val;
9389         uint32_t rc = 0;
9390
9391         /*
9392          * Clear HW from errors which may have resulted from an interrupted
9393          * DMAE transaction.
9394          */
9395         bnx2x_prev_interrupted_dmae(sc);
9396
9397         /* Release previously held locks */
9398         if (SC_FUNC(sc) <= 5)
9399                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9400         else
9401                 hw_lock_reg =
9402                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9403
9404         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9405         if (hw_lock_val) {
9406                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9407                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9408                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9409                 }
9410                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9411         }
9412
9413         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9414                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9415         }
9416
9417         do {
9418                 /* Lock MCP using an unload request */
9419                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9420                 if (!fw) {
9421                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9422                         rc = -1;
9423                         break;
9424                 }
9425
9426                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9427                         rc = bnx2x_prev_unload_common(sc);
9428                         break;
9429                 }
9430
9431                 /* non-common reply from MCP might require looping */
9432                 rc = bnx2x_prev_unload_uncommon(sc);
9433                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9434                         break;
9435                 }
9436
9437                 DELAY(20000);
9438         } while (--time_counter);
9439
9440         if (!time_counter || rc) {
9441                 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9442                 rc = -1;
9443         }
9444
9445         return rc;
9446 }
9447
9448 static void
9449 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9450 {
9451         if (!CHIP_IS_E1x(sc)) {
9452                 sc->dcb_state = dcb_on;
9453                 sc->dcbx_enabled = dcbx_enabled;
9454         } else {
9455                 sc->dcb_state = FALSE;
9456                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9457         }
9458         PMD_DRV_LOG(DEBUG, sc,
9459                     "DCB state [%s:%s]",
9460                     dcb_on ? "ON" : "OFF",
9461                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9462                     (dcbx_enabled ==
9463                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9464                     : (dcbx_enabled ==
9465                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9466                     "on-chip with negotiation" : "invalid");
9467 }
9468
9469 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9470 {
9471         int cid_count = BNX2X_L2_MAX_CID(sc);
9472
9473         if (CNIC_SUPPORT(sc)) {
9474                 cid_count += CNIC_CID_MAX;
9475         }
9476
9477         return roundup(cid_count, QM_CID_ROUND);
9478 }
9479
9480 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9481 {
9482         int pri, cos;
9483
9484         uint32_t pri_map = 0;
9485
9486         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9487                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9488                 if (cos < sc->max_cos) {
9489                         sc->prio_to_cos[pri] = cos;
9490                 } else {
9491                         PMD_DRV_LOG(WARNING, sc,
9492                                     "Invalid COS %d for priority %d "
9493                                     "(max COS is %d), setting to 0", cos, pri,
9494                                     (sc->max_cos - 1));
9495                         sc->prio_to_cos[pri] = 0;
9496                 }
9497         }
9498 }
9499
9500 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9501 {
9502         struct {
9503                 uint8_t id;
9504                 uint8_t next;
9505         } pci_cap;
9506         uint16_t status;
9507         struct bnx2x_pci_cap *cap;
9508
9509         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9510                                          RTE_CACHE_LINE_SIZE);
9511         if (!cap) {
9512                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9513                 return -ENOMEM;
9514         }
9515
9516 #ifndef __FreeBSD__
9517         pci_read(sc, PCI_STATUS, &status, 2);
9518         if (!(status & PCI_STATUS_CAP_LIST)) {
9519 #else
9520         pci_read(sc, PCIR_STATUS, &status, 2);
9521         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9522 #endif
9523                 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9524                 return -1;
9525         }
9526
9527 #ifndef __FreeBSD__
9528         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9529 #else
9530         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9531 #endif
9532         while (pci_cap.next) {
9533                 cap->addr = pci_cap.next & ~3;
9534                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9535                 if (pci_cap.id == 0xff)
9536                         break;
9537                 cap->id = pci_cap.id;
9538                 cap->type = BNX2X_PCI_CAP;
9539                 cap->next = rte_zmalloc("pci_cap",
9540                                         sizeof(struct bnx2x_pci_cap),
9541                                         RTE_CACHE_LINE_SIZE);
9542                 if (!cap->next) {
9543                         PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9544                         return -ENOMEM;
9545                 }
9546                 cap = cap->next;
9547         }
9548
9549         return 0;
9550 }
9551
9552 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9553 {
9554         if (IS_VF(sc)) {
9555                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9556                                         sc->igu_sb_cnt);
9557                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9558                                         sc->igu_sb_cnt);
9559         } else {
9560                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9561                 sc->max_tx_queues = sc->max_rx_queues;
9562         }
9563 }
9564
9565 #define FW_HEADER_LEN 104
9566 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9567 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9568
9569 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9570 {
9571         const char *fwname;
9572         int f;
9573         struct stat st;
9574
9575         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9576                 ? FW_NAME_57711 : FW_NAME_57810;
9577         f = open(fwname, O_RDONLY);
9578         if (f < 0) {
9579                 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9580                 return;
9581         }
9582
9583         if (fstat(f, &st) < 0) {
9584                 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9585                 close(f);
9586                 return;
9587         }
9588
9589         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9590         if (!sc->firmware) {
9591                 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9592                 close(f);
9593                 return;
9594         }
9595
9596         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9597                 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9598                 close(f);
9599                 return;
9600         }
9601         close(f);
9602
9603         sc->fw_len = st.st_size;
9604         if (sc->fw_len < FW_HEADER_LEN) {
9605                 PMD_DRV_LOG(NOTICE, sc,
9606                             "Invalid fw size: %" PRIu64, sc->fw_len);
9607                 return;
9608         }
9609         PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9610 }
9611
9612 static void
9613 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9614 {
9615         uint32_t *src = (uint32_t *) data;
9616         uint32_t i, j, tmp;
9617
9618         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9619                 tmp = rte_be_to_cpu_32(src[j]);
9620                 dst[i].op = (tmp >> 24) & 0xFF;
9621                 dst[i].offset = tmp & 0xFFFFFF;
9622                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9623         }
9624 }
9625
9626 static void
9627 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9628 {
9629         uint16_t *src = (uint16_t *) data;
9630         uint32_t i;
9631
9632         for (i = 0; i < len / 2; ++i)
9633                 dst[i] = rte_be_to_cpu_16(src[i]);
9634 }
9635
9636 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9637 {
9638         uint32_t *src = (uint32_t *) data;
9639         uint32_t i;
9640
9641         for (i = 0; i < len / 4; ++i)
9642                 dst[i] = rte_be_to_cpu_32(src[i]);
9643 }
9644
9645 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9646 {
9647         uint32_t *src = (uint32_t *) data;
9648         uint32_t i, j, tmp;
9649
9650         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9651                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9652                 tmp = rte_be_to_cpu_32(src[j]);
9653                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9654                 dst[i].m2 = tmp & 0xFFFF;
9655                 ++j;
9656                 tmp = rte_be_to_cpu_32(src[j]);
9657                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9658                 dst[i].size = tmp & 0xFFFF;
9659         }
9660 }
9661
9662 /*
9663 * Device attach function.
9664 *
9665 * Allocates device resources, performs secondary chip identification, and
9666 * initializes driver instance variables. This function is called from driver
9667 * load after a successful probe.
9668 *
9669 * Returns:
9670 *   0 = Success, >0 = Failure
9671 */
9672 int bnx2x_attach(struct bnx2x_softc *sc)
9673 {
9674         int rc;
9675
9676         PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9677
9678         rc = bnx2x_pci_get_caps(sc);
9679         if (rc) {
9680                 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9681                 return rc;
9682         }
9683
9684         sc->state = BNX2X_STATE_CLOSED;
9685
9686         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9687
9688         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9689
9690         /* get PCI capabilites */
9691         bnx2x_probe_pci_caps(sc);
9692
9693         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9694                 uint32_t val;
9695                 pci_read(sc,
9696                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9697                          2);
9698                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9699         } else {
9700                 sc->igu_sb_cnt = 1;
9701         }
9702
9703         /* Init RTE stuff */
9704         bnx2x_init_rte(sc);
9705
9706         if (IS_PF(sc)) {
9707                 /* Enable internal target-read (in case we are probed after PF
9708                  * FLR). Must be done prior to any BAR read access. Only for
9709                  * 57712 and up
9710                  */
9711                 if (!CHIP_IS_E1x(sc)) {
9712                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9713                                1);
9714                         DELAY(200000);
9715                 }
9716
9717                 /* get device info and set params */
9718                 if (bnx2x_get_device_info(sc) != 0) {
9719                         PMD_DRV_LOG(NOTICE, sc, "getting device info");
9720                         return -ENXIO;
9721                 }
9722
9723 /* get phy settings from shmem and 'and' against admin settings */
9724                 bnx2x_get_phy_info(sc);
9725         } else {
9726                 /* Left mac of VF unfilled, PF should set it for VF */
9727                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9728         }
9729
9730         sc->wol = 0;
9731
9732         /* set the default MTU (changed via ifconfig) */
9733         sc->mtu = ETHER_MTU;
9734
9735         bnx2x_set_modes_bitmap(sc);
9736
9737         /* need to reset chip if UNDI was active */
9738         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9739 /* init fw_seq */
9740                 sc->fw_seq =
9741                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9742                      DRV_MSG_SEQ_NUMBER_MASK);
9743                 bnx2x_prev_unload(sc);
9744         }
9745
9746         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9747
9748         /* calculate qm_cid_count */
9749         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9750
9751         sc->max_cos = 1;
9752         bnx2x_init_multi_cos(sc);
9753
9754         return 0;
9755 }
9756
9757 static void
9758 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9759                uint16_t index, uint8_t op, uint8_t update)
9760 {
9761         uint32_t igu_addr = sc->igu_base_addr;
9762         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9763         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9764 }
9765
9766 static void
9767 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9768            uint16_t index, uint8_t op, uint8_t update)
9769 {
9770         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9771                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9772         else {
9773                 uint8_t segment;
9774                 if (CHIP_INT_MODE_IS_BC(sc)) {
9775                         segment = storm;
9776                 } else if (igu_sb_id != sc->igu_dsb_id) {
9777                         segment = IGU_SEG_ACCESS_DEF;
9778                 } else if (storm == ATTENTION_ID) {
9779                         segment = IGU_SEG_ACCESS_ATTN;
9780                 } else {
9781                         segment = IGU_SEG_ACCESS_DEF;
9782                 }
9783                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9784         }
9785 }
9786
9787 static void
9788 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9789                      uint8_t is_pf)
9790 {
9791         uint32_t data, ctl, cnt = 100;
9792         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9793         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9794         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9795             (idu_sb_id / 32) * 4;
9796         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9797         uint32_t func_encode = func |
9798             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9799         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9800
9801         /* Not supported in BC mode */
9802         if (CHIP_INT_MODE_IS_BC(sc)) {
9803                 return;
9804         }
9805
9806         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9807                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9808                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9809
9810         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9811                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9812                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9813
9814         REG_WR(sc, igu_addr_data, data);
9815
9816         mb();
9817
9818         PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9819                     ctl, igu_addr_ctl);
9820         REG_WR(sc, igu_addr_ctl, ctl);
9821
9822         mb();
9823
9824         /* wait for clean up to finish */
9825         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9826                 DELAY(20000);
9827         }
9828
9829         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9830                 PMD_DRV_LOG(DEBUG, sc,
9831                             "Unable to finish IGU cleanup: "
9832                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9833                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9834         }
9835 }
9836
9837 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9838 {
9839         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9840 }
9841
9842 /*******************/
9843 /* ECORE CALLBACKS */
9844 /*******************/
9845
9846 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9847 {
9848         uint32_t val = 0x1400;
9849
9850         PMD_INIT_FUNC_TRACE(sc);
9851
9852         /* reset_common */
9853         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9854                0xd3ffff7f);
9855
9856         if (CHIP_IS_E3(sc)) {
9857                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9858                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9859         }
9860
9861         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9862 }
9863
9864 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9865 {
9866         uint32_t shmem_base[2];
9867         uint32_t shmem2_base[2];
9868
9869         /* Avoid common init in case MFW supports LFA */
9870         if (SHMEM2_RD(sc, size) >
9871             (uint32_t) offsetof(struct shmem2_region,
9872                                 lfa_host_addr[SC_PORT(sc)])) {
9873                 return;
9874         }
9875
9876         shmem_base[0] = sc->devinfo.shmem_base;
9877         shmem2_base[0] = sc->devinfo.shmem2_base;
9878
9879         if (!CHIP_IS_E1x(sc)) {
9880                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9881                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9882         }
9883
9884         bnx2x_acquire_phy_lock(sc);
9885         elink_common_init_phy(sc, shmem_base, shmem2_base,
9886                               sc->devinfo.chip_id, 0);
9887         bnx2x_release_phy_lock(sc);
9888 }
9889
9890 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9891 {
9892         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9893
9894         val &= ~IGU_PF_CONF_FUNC_EN;
9895
9896         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9897         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9898         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9899 }
9900
9901 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9902 {
9903         uint16_t devctl;
9904         int r_order, w_order;
9905
9906         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9907
9908         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9909         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9910
9911         ecore_init_pxp_arb(sc, r_order, w_order);
9912 }
9913
9914 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9915 {
9916         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9917         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9918         return base + (SC_ABS_FUNC(sc)) * stride;
9919 }
9920
9921 /*
9922  * Called only on E1H or E2.
9923  * When pretending to be PF, the pretend value is the function number 0..7.
9924  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9925  * combination.
9926  */
9927 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9928 {
9929         uint32_t pretend_reg;
9930
9931         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9932                 return -1;
9933
9934         /* get my own pretend register */
9935         pretend_reg = bnx2x_get_pretend_reg(sc);
9936         REG_WR(sc, pretend_reg, pretend_func_val);
9937         REG_RD(sc, pretend_reg);
9938         return 0;
9939 }
9940
9941 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9942 {
9943         int is_required;
9944         uint32_t val;
9945         int port;
9946
9947         is_required = 0;
9948         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9949                SHARED_HW_CFG_FAN_FAILURE_MASK);
9950
9951         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9952                 is_required = 1;
9953         }
9954         /*
9955          * The fan failure mechanism is usually related to the PHY type since
9956          * the power consumption of the board is affected by the PHY. Currently,
9957          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9958          */
9959         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9960                 for (port = PORT_0; port < PORT_MAX; port++) {
9961                         is_required |= elink_fan_failure_det_req(sc,
9962                                                                  sc->
9963                                                                  devinfo.shmem_base,
9964                                                                  sc->
9965                                                                  devinfo.shmem2_base,
9966                                                                  port);
9967                 }
9968         }
9969
9970         if (is_required == 0) {
9971                 return;
9972         }
9973
9974         /* Fan failure is indicated by SPIO 5 */
9975         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9976
9977         /* set to active low mode */
9978         val = REG_RD(sc, MISC_REG_SPIO_INT);
9979         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9980         REG_WR(sc, MISC_REG_SPIO_INT, val);
9981
9982         /* enable interrupt to signal the IGU */
9983         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9984         val |= MISC_SPIO_SPIO5;
9985         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9986 }
9987
9988 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9989 {
9990         uint32_t val;
9991
9992         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9993         if (!CHIP_IS_E1x(sc)) {
9994                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9995         } else {
9996                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9997         }
9998         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9999         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10000         /*
10001          * mask read length error interrupts in brb for parser
10002          * (parsing unit and 'checksum and crc' unit)
10003          * these errors are legal (PU reads fixed length and CAC can cause
10004          * read length error on truncated packets)
10005          */
10006         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10007         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10008         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10009         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10010         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10011         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10012         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10013         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10014         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10015         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10016         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10017         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10018         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10019         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10020         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10021         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10022         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10023         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10024         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10025
10026         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10027                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10028                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10029         if (!CHIP_IS_E1x(sc)) {
10030                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10031                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10032         }
10033         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10034
10035         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10036         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10037         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10038         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10039
10040         if (!CHIP_IS_E1x(sc)) {
10041 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10042                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10043         }
10044
10045         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10046         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10047         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10048         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10049 }
10050
10051 /**
10052  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10053  *
10054  * @sc:     driver handle
10055  */
10056 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10057 {
10058         uint8_t abs_func_id;
10059         uint32_t val;
10060
10061         PMD_DRV_LOG(DEBUG, sc,
10062                     "starting common init for func %d", SC_ABS_FUNC(sc));
10063
10064         /*
10065          * take the RESET lock to protect undi_unload flow from accessing
10066          * registers while we are resetting the chip
10067          */
10068         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10069
10070         bnx2x_reset_common(sc);
10071
10072         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10073
10074         val = 0xfffc;
10075         if (CHIP_IS_E3(sc)) {
10076                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10077                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10078         }
10079
10080         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10081
10082         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10083
10084         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10085
10086         if (!CHIP_IS_E1x(sc)) {
10087 /*
10088  * 4-port mode or 2-port mode we need to turn off master-enable for
10089  * everyone. After that we turn it back on for self. So, we disregard
10090  * multi-function, and always disable all functions on the given path,
10091  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10092  */
10093                 for (abs_func_id = SC_PATH(sc);
10094                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10095                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10096                                 REG_WR(sc,
10097                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10098                                        1);
10099                                 continue;
10100                         }
10101
10102                         bnx2x_pretend_func(sc, abs_func_id);
10103
10104                         /* clear pf enable */
10105                         bnx2x_pf_disable(sc);
10106
10107                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10108                 }
10109         }
10110
10111         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10112
10113         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10114         bnx2x_init_pxp(sc);
10115
10116 #ifdef __BIG_ENDIAN
10117         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10118         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10119         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10120         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10121         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10122         /* make sure this value is 0 */
10123         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10124
10125         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10126         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10127         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10128         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10129         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10130 #endif
10131
10132         ecore_ilt_init_page_size(sc, INITOP_SET);
10133
10134         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10135                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10136         }
10137
10138         /* let the HW do it's magic... */
10139         DELAY(100000);
10140
10141         /* finish PXP init */
10142
10143         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10144         if (val != 1) {
10145                 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10146                 return -1;
10147         }
10148         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10149         if (val != 1) {
10150                 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10151                 return -1;
10152         }
10153
10154         /*
10155          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10156          * entries with value "0" and valid bit on. This needs to be done by the
10157          * first PF that is loaded in a path (i.e. common phase)
10158          */
10159         if (!CHIP_IS_E1x(sc)) {
10160 /*
10161  * In E2 there is a bug in the timers block that can cause function 6 / 7
10162  * (i.e. vnic3) to start even if it is marked as "scan-off".
10163  * This occurs when a different function (func2,3) is being marked
10164  * as "scan-off". Real-life scenario for example: if a driver is being
10165  * load-unloaded while func6,7 are down. This will cause the timer to access
10166  * the ilt, translate to a logical address and send a request to read/write.
10167  * Since the ilt for the function that is down is not valid, this will cause
10168  * a translation error which is unrecoverable.
10169  * The Workaround is intended to make sure that when this happens nothing
10170  * fatal will occur. The workaround:
10171  *  1.  First PF driver which loads on a path will:
10172  *      a.  After taking the chip out of reset, by using pretend,
10173  *          it will write "0" to the following registers of
10174  *          the other vnics.
10175  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10176  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10177  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10178  *          And for itself it will write '1' to
10179  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10180  *          dmae-operations (writing to pram for example.)
10181  *          note: can be done for only function 6,7 but cleaner this
10182  *            way.
10183  *      b.  Write zero+valid to the entire ILT.
10184  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10185  *          VNIC3 (of that port). The range allocated will be the
10186  *          entire ILT. This is needed to prevent  ILT range error.
10187  *  2.  Any PF driver load flow:
10188  *      a.  ILT update with the physical addresses of the allocated
10189  *          logical pages.
10190  *      b.  Wait 20msec. - note that this timeout is needed to make
10191  *          sure there are no requests in one of the PXP internal
10192  *          queues with "old" ILT addresses.
10193  *      c.  PF enable in the PGLC.
10194  *      d.  Clear the was_error of the PF in the PGLC. (could have
10195  *          occurred while driver was down)
10196  *      e.  PF enable in the CFC (WEAK + STRONG)
10197  *      f.  Timers scan enable
10198  *  3.  PF driver unload flow:
10199  *      a.  Clear the Timers scan_en.
10200  *      b.  Polling for scan_on=0 for that PF.
10201  *      c.  Clear the PF enable bit in the PXP.
10202  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10203  *      e.  Write zero+valid to all ILT entries (The valid bit must
10204  *          stay set)
10205  *      f.  If this is VNIC 3 of a port then also init
10206  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10207  *          to the last enrty in the ILT.
10208  *
10209  *      Notes:
10210  *      Currently the PF error in the PGLC is non recoverable.
10211  *      In the future the there will be a recovery routine for this error.
10212  *      Currently attention is masked.
10213  *      Having an MCP lock on the load/unload process does not guarantee that
10214  *      there is no Timer disable during Func6/7 enable. This is because the
10215  *      Timers scan is currently being cleared by the MCP on FLR.
10216  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10217  *      there is error before clearing it. But the flow above is simpler and
10218  *      more general.
10219  *      All ILT entries are written by zero+valid and not just PF6/7
10220  *      ILT entries since in the future the ILT entries allocation for
10221  *      PF-s might be dynamic.
10222  */
10223                 struct ilt_client_info ilt_cli;
10224                 struct ecore_ilt ilt;
10225
10226                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10227                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10228
10229 /* initialize dummy TM client */
10230                 ilt_cli.start = 0;
10231                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10232                 ilt_cli.client_num = ILT_CLIENT_TM;
10233
10234 /*
10235  * Step 1: set zeroes to all ilt page entries with valid bit on
10236  * Step 2: set the timers first/last ilt entry to point
10237  * to the entire range to prevent ILT range error for 3rd/4th
10238  * vnic (this code assumes existence of the vnic)
10239  *
10240  * both steps performed by call to ecore_ilt_client_init_op()
10241  * with dummy TM client
10242  *
10243  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10244  * and his brother are split registers
10245  */
10246
10247                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10248                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10249                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10250
10251                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10252                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10253                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10254         }
10255
10256         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10257         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10258
10259         if (!CHIP_IS_E1x(sc)) {
10260                 int factor = 0;
10261
10262                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10263                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10264
10265 /* let the HW do it's magic... */
10266                 do {
10267                         DELAY(200000);
10268                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10269                 } while (factor-- && (val != 1));
10270
10271                 if (val != 1) {
10272                         PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10273                         return -1;
10274                 }
10275         }
10276
10277         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10278
10279         /* clean the DMAE memory */
10280         sc->dmae_ready = 1;
10281         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10282
10283         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10284
10285         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10286
10287         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10288
10289         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10290
10291         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10292         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10293         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10294         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10295
10296         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10297
10298         /* QM queues pointers table */
10299         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10300
10301         /* soft reset pulse */
10302         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10303         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10304
10305         if (CNIC_SUPPORT(sc))
10306                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10307
10308         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10309         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10310
10311         if (!CHIP_REV_IS_SLOW(sc)) {
10312 /* enable hw interrupt from doorbell Q */
10313                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10314         }
10315
10316         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10317
10318         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10319         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10320         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10321
10322         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10323                 if (IS_MF_AFEX(sc)) {
10324                         /*
10325                          * configure that AFEX and VLAN headers must be
10326                          * received in AFEX mode
10327                          */
10328                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10329                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10330                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10331                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10332                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10333                 } else {
10334                         /*
10335                          * Bit-map indicating which L2 hdrs may appear
10336                          * after the basic Ethernet header
10337                          */
10338                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10339                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10340                 }
10341         }
10342
10343         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10344         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10345         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10346         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10347
10348         if (!CHIP_IS_E1x(sc)) {
10349 /* reset VFC memories */
10350                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10351                        VFC_MEMORIES_RST_REG_CAM_RST |
10352                        VFC_MEMORIES_RST_REG_RAM_RST);
10353                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10354                        VFC_MEMORIES_RST_REG_CAM_RST |
10355                        VFC_MEMORIES_RST_REG_RAM_RST);
10356
10357                 DELAY(20000);
10358         }
10359
10360         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10361         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10362         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10363         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10364
10365         /* sync semi rtc */
10366         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10367         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10368
10369         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10370         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10371         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10372
10373         if (!CHIP_IS_E1x(sc)) {
10374                 if (IS_MF_AFEX(sc)) {
10375                         /*
10376                          * configure that AFEX and VLAN headers must be
10377                          * sent in AFEX mode
10378                          */
10379                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10380                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10381                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10382                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10383                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10384                 } else {
10385                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10386                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10387                 }
10388         }
10389
10390         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10391
10392         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10393
10394         if (CNIC_SUPPORT(sc)) {
10395                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10396                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10397                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10398                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10399                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10400                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10401                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10402                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10403                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10404                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10405         }
10406         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10407
10408         if (sizeof(union cdu_context) != 1024) {
10409 /* we currently assume that a context is 1024 bytes */
10410                 PMD_DRV_LOG(NOTICE, sc,
10411                             "please adjust the size of cdu_context(%ld)",
10412                             (long)sizeof(union cdu_context));
10413         }
10414
10415         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10416         val = (4 << 24) + (0 << 12) + 1024;
10417         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10418
10419         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10420
10421         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10422         /* enable context validation interrupt from CFC */
10423         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10424
10425         /* set the thresholds to prevent CFC/CDU race */
10426         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10427         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10428
10429         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10430                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10431         }
10432
10433         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10434         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10435
10436         /* Reset PCIE errors for debug */
10437         REG_WR(sc, 0x2814, 0xffffffff);
10438         REG_WR(sc, 0x3820, 0xffffffff);
10439
10440         if (!CHIP_IS_E1x(sc)) {
10441                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10442                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10443                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10444                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10445                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10446                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10447                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10448                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10449                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10450                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10451                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10452         }
10453
10454         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10455
10456         /* in E3 this done in per-port section */
10457         if (!CHIP_IS_E3(sc))
10458                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10459
10460         if (CHIP_IS_E1H(sc)) {
10461 /* not applicable for E2 (and above ...) */
10462                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10463         }
10464
10465         if (CHIP_REV_IS_SLOW(sc)) {
10466                 DELAY(200000);
10467         }
10468
10469         /* finish CFC init */
10470         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10471         if (val != 1) {
10472                 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10473                 return -1;
10474         }
10475         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10476         if (val != 1) {
10477                 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10478                 return -1;
10479         }
10480         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10481         if (val != 1) {
10482                 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10483                 return -1;
10484         }
10485         REG_WR(sc, CFC_REG_DEBUG0, 0);
10486
10487         bnx2x_setup_fan_failure_detection(sc);
10488
10489         /* clear PXP2 attentions */
10490         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10491
10492         bnx2x_enable_blocks_attention(sc);
10493
10494         if (!CHIP_REV_IS_SLOW(sc)) {
10495                 ecore_enable_blocks_parity(sc);
10496         }
10497
10498         if (!BNX2X_NOMCP(sc)) {
10499                 if (CHIP_IS_E1x(sc)) {
10500                         bnx2x_common_init_phy(sc);
10501                 }
10502         }
10503
10504         return 0;
10505 }
10506
10507 /**
10508  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10509  *
10510  * @sc:     driver handle
10511  */
10512 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10513 {
10514         int rc = bnx2x_init_hw_common(sc);
10515
10516         if (rc) {
10517                 return rc;
10518         }
10519
10520         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10521         if (!BNX2X_NOMCP(sc)) {
10522                 bnx2x_common_init_phy(sc);
10523         }
10524
10525         return 0;
10526 }
10527
10528 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10529 {
10530         int port = SC_PORT(sc);
10531         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10532         uint32_t low, high;
10533         uint32_t val;
10534
10535         PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10536
10537         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10538
10539         ecore_init_block(sc, BLOCK_MISC, init_phase);
10540         ecore_init_block(sc, BLOCK_PXP, init_phase);
10541         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10542
10543         /*
10544          * Timers bug workaround: disables the pf_master bit in pglue at
10545          * common phase, we need to enable it here before any dmae access are
10546          * attempted. Therefore we manually added the enable-master to the
10547          * port phase (it also happens in the function phase)
10548          */
10549         if (!CHIP_IS_E1x(sc)) {
10550                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10551         }
10552
10553         ecore_init_block(sc, BLOCK_ATC, init_phase);
10554         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10555         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10556         ecore_init_block(sc, BLOCK_QM, init_phase);
10557
10558         ecore_init_block(sc, BLOCK_TCM, init_phase);
10559         ecore_init_block(sc, BLOCK_UCM, init_phase);
10560         ecore_init_block(sc, BLOCK_CCM, init_phase);
10561         ecore_init_block(sc, BLOCK_XCM, init_phase);
10562
10563         /* QM cid (connection) count */
10564         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10565
10566         if (CNIC_SUPPORT(sc)) {
10567                 ecore_init_block(sc, BLOCK_TM, init_phase);
10568                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10569                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10570         }
10571
10572         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10573
10574         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10575
10576         if (CHIP_IS_E1H(sc)) {
10577                 if (IS_MF(sc)) {
10578                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10579                 } else if (sc->mtu > 4096) {
10580                         if (BNX2X_ONE_PORT(sc)) {
10581                                 low = 160;
10582                         } else {
10583                                 val = sc->mtu;
10584                                 /* (24*1024 + val*4)/256 */
10585                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10586                         }
10587                 } else {
10588                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10589                 }
10590                 high = (low + 56);      /* 14*1024/256 */
10591                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10592                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10593         }
10594
10595         if (CHIP_IS_MODE_4_PORT(sc)) {
10596                 REG_WR(sc, SC_PORT(sc) ?
10597                        BRB1_REG_MAC_GUARANTIED_1 :
10598                        BRB1_REG_MAC_GUARANTIED_0, 40);
10599         }
10600
10601         ecore_init_block(sc, BLOCK_PRS, init_phase);
10602         if (CHIP_IS_E3B0(sc)) {
10603                 if (IS_MF_AFEX(sc)) {
10604                         /* configure headers for AFEX mode */
10605                         if (SC_PORT(sc)) {
10606                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10607                                        0xE);
10608                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10609                                        0x6);
10610                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10611                         } else {
10612                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10613                                        0xE);
10614                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10615                                        0x6);
10616                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10617                         }
10618                 } else {
10619                         /* Ovlan exists only if we are in multi-function +
10620                          * switch-dependent mode, in switch-independent there
10621                          * is no ovlan headers
10622                          */
10623                         REG_WR(sc, SC_PORT(sc) ?
10624                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10625                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10626                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10627                 }
10628         }
10629
10630         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10631         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10632         ecore_init_block(sc, BLOCK_USDM, init_phase);
10633         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10634
10635         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10636         ecore_init_block(sc, BLOCK_USEM, init_phase);
10637         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10638         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10639
10640         ecore_init_block(sc, BLOCK_UPB, init_phase);
10641         ecore_init_block(sc, BLOCK_XPB, init_phase);
10642
10643         ecore_init_block(sc, BLOCK_PBF, init_phase);
10644
10645         if (CHIP_IS_E1x(sc)) {
10646 /* configure PBF to work without PAUSE mtu 9000 */
10647                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10648
10649 /* update threshold */
10650                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10651 /* update init credit */
10652                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10653                        (9040 / 16) + 553 - 22);
10654
10655 /* probe changes */
10656                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10657                 DELAY(50);
10658                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10659         }
10660
10661         if (CNIC_SUPPORT(sc)) {
10662                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10663         }
10664
10665         ecore_init_block(sc, BLOCK_CDU, init_phase);
10666         ecore_init_block(sc, BLOCK_CFC, init_phase);
10667         ecore_init_block(sc, BLOCK_HC, init_phase);
10668         ecore_init_block(sc, BLOCK_IGU, init_phase);
10669         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10670         /* init aeu_mask_attn_func_0/1:
10671          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10672          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10673          *             bits 4-7 are used for "per vn group attention" */
10674         val = IS_MF(sc) ? 0xF7 : 0x7;
10675         val |= 0x10;
10676         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10677
10678         ecore_init_block(sc, BLOCK_NIG, init_phase);
10679
10680         if (!CHIP_IS_E1x(sc)) {
10681 /* Bit-map indicating which L2 hdrs may appear after the
10682  * basic Ethernet header
10683  */
10684                 if (IS_MF_AFEX(sc)) {
10685                         REG_WR(sc, SC_PORT(sc) ?
10686                                NIG_REG_P1_HDRS_AFTER_BASIC :
10687                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10688                 } else {
10689                         REG_WR(sc, SC_PORT(sc) ?
10690                                NIG_REG_P1_HDRS_AFTER_BASIC :
10691                                NIG_REG_P0_HDRS_AFTER_BASIC,
10692                                IS_MF_SD(sc) ? 7 : 6);
10693                 }
10694
10695                 if (CHIP_IS_E3(sc)) {
10696                         REG_WR(sc, SC_PORT(sc) ?
10697                                NIG_REG_LLH1_MF_MODE :
10698                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10699                 }
10700         }
10701         if (!CHIP_IS_E3(sc)) {
10702                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10703         }
10704
10705         /* 0x2 disable mf_ov, 0x1 enable */
10706         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10707                (IS_MF_SD(sc) ? 0x1 : 0x2));
10708
10709         if (!CHIP_IS_E1x(sc)) {
10710                 val = 0;
10711                 switch (sc->devinfo.mf_info.mf_mode) {
10712                 case MULTI_FUNCTION_SD:
10713                         val = 1;
10714                         break;
10715                 case MULTI_FUNCTION_SI:
10716                 case MULTI_FUNCTION_AFEX:
10717                         val = 2;
10718                         break;
10719                 }
10720
10721                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10722                             NIG_REG_LLH0_CLS_TYPE), val);
10723         }
10724         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10725         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10726         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10727
10728         /* If SPIO5 is set to generate interrupts, enable it for this port */
10729         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10730         if (val & MISC_SPIO_SPIO5) {
10731                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10732                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10733                 val = REG_RD(sc, reg_addr);
10734                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10735                 REG_WR(sc, reg_addr, val);
10736         }
10737
10738         return 0;
10739 }
10740
10741 static uint32_t
10742 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10743                        uint32_t expected, uint32_t poll_count)
10744 {
10745         uint32_t cur_cnt = poll_count;
10746         uint32_t val;
10747
10748         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10749                 DELAY(FLR_WAIT_INTERVAL);
10750         }
10751
10752         return val;
10753 }
10754
10755 static int
10756 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10757                               __rte_unused const char *msg, uint32_t poll_cnt)
10758 {
10759         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10760
10761         if (val != 0) {
10762                 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10763                 return -1;
10764         }
10765
10766         return 0;
10767 }
10768
10769 /* Common routines with VF FLR cleanup */
10770 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10771 {
10772         /* adjust polling timeout */
10773         if (CHIP_REV_IS_EMUL(sc)) {
10774                 return FLR_POLL_CNT * 2000;
10775         }
10776
10777         if (CHIP_REV_IS_FPGA(sc)) {
10778                 return FLR_POLL_CNT * 120;
10779         }
10780
10781         return FLR_POLL_CNT;
10782 }
10783
10784 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10785 {
10786         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10787         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10788                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10789                                           "CFC PF usage counter timed out",
10790                                           poll_cnt)) {
10791                 return -1;
10792         }
10793
10794         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10795         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10796                                           DORQ_REG_PF_USAGE_CNT,
10797                                           "DQ PF usage counter timed out",
10798                                           poll_cnt)) {
10799                 return -1;
10800         }
10801
10802         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10803         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10804                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10805                                           "QM PF usage counter timed out",
10806                                           poll_cnt)) {
10807                 return -1;
10808         }
10809
10810         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10811         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10812                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10813                                           "Timers VNIC usage counter timed out",
10814                                           poll_cnt)) {
10815                 return -1;
10816         }
10817
10818         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10819                                           TM_REG_LIN0_NUM_SCANS +
10820                                           4 * SC_PORT(sc),
10821                                           "Timers NUM_SCANS usage counter timed out",
10822                                           poll_cnt)) {
10823                 return -1;
10824         }
10825
10826         /* Wait DMAE PF usage counter to zero */
10827         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10828                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10829                                           "DMAE dommand register timed out",
10830                                           poll_cnt)) {
10831                 return -1;
10832         }
10833
10834         return 0;
10835 }
10836
10837 #define OP_GEN_PARAM(param)                                            \
10838         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10839 #define OP_GEN_TYPE(type)                                           \
10840         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10841 #define OP_GEN_AGG_VECT(index)                                             \
10842         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10843
10844 static int
10845 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10846                      uint32_t poll_cnt)
10847 {
10848         uint32_t op_gen_command = 0;
10849         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10850                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10851         int ret = 0;
10852
10853         if (REG_RD(sc, comp_addr)) {
10854                 PMD_DRV_LOG(NOTICE, sc,
10855                             "Cleanup complete was not 0 before sending");
10856                 return -1;
10857         }
10858
10859         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10860         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10861         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10862         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10863
10864         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10865
10866         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10867                 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10868                 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10869                             (REG_RD(sc, comp_addr)));
10870                 rte_panic("FLR cleanup failed");
10871                 return -1;
10872         }
10873
10874         /* Zero completion for nxt FLR */
10875         REG_WR(sc, comp_addr, 0);
10876
10877         return ret;
10878 }
10879
10880 static void
10881 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10882                        uint32_t poll_count)
10883 {
10884         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10885         uint32_t cur_cnt = poll_count;
10886
10887         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10888         crd = crd_start = REG_RD(sc, regs->crd);
10889         init_crd = REG_RD(sc, regs->init_crd);
10890
10891         while ((crd != init_crd) &&
10892                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10893                 (init_crd - crd_start))) {
10894                 if (cur_cnt--) {
10895                         DELAY(FLR_WAIT_INTERVAL);
10896                         crd = REG_RD(sc, regs->crd);
10897                         crd_freed = REG_RD(sc, regs->crd_freed);
10898                 } else {
10899                         break;
10900                 }
10901         }
10902 }
10903
10904 static void
10905 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10906                        uint32_t poll_count)
10907 {
10908         uint32_t occup, to_free, freed, freed_start;
10909         uint32_t cur_cnt = poll_count;
10910
10911         occup = to_free = REG_RD(sc, regs->lines_occup);
10912         freed = freed_start = REG_RD(sc, regs->lines_freed);
10913
10914         while (occup &&
10915                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10916                 to_free)) {
10917                 if (cur_cnt--) {
10918                         DELAY(FLR_WAIT_INTERVAL);
10919                         occup = REG_RD(sc, regs->lines_occup);
10920                         freed = REG_RD(sc, regs->lines_freed);
10921                 } else {
10922                         break;
10923                 }
10924         }
10925 }
10926
10927 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10928 {
10929         struct pbf_pN_cmd_regs cmd_regs[] = {
10930                 {0, (CHIP_IS_E3B0(sc)) ?
10931                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10932                  (CHIP_IS_E3B0(sc)) ?
10933                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10934                 {1, (CHIP_IS_E3B0(sc)) ?
10935                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10936                  (CHIP_IS_E3B0(sc)) ?
10937                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10938                 {4, (CHIP_IS_E3B0(sc)) ?
10939                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10940                  (CHIP_IS_E3B0(sc)) ?
10941                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10942                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10943         };
10944
10945         struct pbf_pN_buf_regs buf_regs[] = {
10946                 {0, (CHIP_IS_E3B0(sc)) ?
10947                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10948                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10949                  (CHIP_IS_E3B0(sc)) ?
10950                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10951                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10952                 {1, (CHIP_IS_E3B0(sc)) ?
10953                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10954                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10955                  (CHIP_IS_E3B0(sc)) ?
10956                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10957                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10958                 {4, (CHIP_IS_E3B0(sc)) ?
10959                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10960                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10961                  (CHIP_IS_E3B0(sc)) ?
10962                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10963                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10964         };
10965
10966         uint32_t i;
10967
10968         /* Verify the command queues are flushed P0, P1, P4 */
10969         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10970                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10971         }
10972
10973         /* Verify the transmission buffers are flushed P0, P1, P4 */
10974         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10975                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10976         }
10977 }
10978
10979 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10980 {
10981         __rte_unused uint32_t val;
10982
10983         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10984         PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10985
10986         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10987         PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
10988
10989         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10990         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10991
10992         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10993         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10994
10995         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10996         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10997
10998         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10999         PMD_DRV_LOG(DEBUG, sc,
11000                     "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11001
11002         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11003         PMD_DRV_LOG(DEBUG, sc,
11004                     "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11005
11006         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11007         PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11008                     val);
11009 }
11010
11011 /**
11012  *      bnx2x_pf_flr_clnup
11013  *      a. re-enable target read on the PF
11014  *      b. poll cfc per function usgae counter
11015  *      c. poll the qm perfunction usage counter
11016  *      d. poll the tm per function usage counter
11017  *      e. poll the tm per function scan-done indication
11018  *      f. clear the dmae channel associated wit hthe PF
11019  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11020  *      h. call the common flr cleanup code with -1 (pf indication)
11021  */
11022 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11023 {
11024         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11025
11026         /* Re-enable PF target read access */
11027         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11028
11029         /* Poll HW usage counters */
11030         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11031                 return -1;
11032         }
11033
11034         /* Zero the igu 'trailing edge' and 'leading edge' */
11035
11036         /* Send the FW cleanup command */
11037         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11038                 return -1;
11039         }
11040
11041         /* ATC cleanup */
11042
11043         /* Verify TX hw is flushed */
11044         bnx2x_tx_hw_flushed(sc, poll_cnt);
11045
11046         /* Wait 100ms (not adjusted according to platform) */
11047         DELAY(100000);
11048
11049         /* Verify no pending pci transactions */
11050         if (bnx2x_is_pcie_pending(sc)) {
11051                 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11052         }
11053
11054         /* Debug */
11055         bnx2x_hw_enable_status(sc);
11056
11057         /*
11058          * Master enable - Due to WB DMAE writes performed before this
11059          * register is re-initialized as part of the regular function init
11060          */
11061         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11062
11063         return 0;
11064 }
11065
11066 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11067 {
11068         int port = SC_PORT(sc);
11069         int func = SC_FUNC(sc);
11070         int init_phase = PHASE_PF0 + func;
11071         struct ecore_ilt *ilt = sc->ilt;
11072         uint16_t cdu_ilt_start;
11073         uint32_t addr, val;
11074         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11075         int main_mem_width, rc;
11076         uint32_t i;
11077
11078         PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11079
11080         /* FLR cleanup */
11081         if (!CHIP_IS_E1x(sc)) {
11082                 rc = bnx2x_pf_flr_clnup(sc);
11083                 if (rc) {
11084                         PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11085                         return rc;
11086                 }
11087         }
11088
11089         /* set MSI reconfigure capability */
11090         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11091                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11092                 val = REG_RD(sc, addr);
11093                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11094                 REG_WR(sc, addr, val);
11095         }
11096
11097         ecore_init_block(sc, BLOCK_PXP, init_phase);
11098         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11099
11100         ilt = sc->ilt;
11101         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11102
11103         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11104                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11105                 ilt->lines[cdu_ilt_start + i].page_mapping =
11106                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11107                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11108         }
11109         ecore_ilt_init_op(sc, INITOP_SET);
11110
11111         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11112
11113         if (!CHIP_IS_E1x(sc)) {
11114                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11115
11116 /* Turn on a single ISR mode in IGU if driver is going to use
11117  * INT#x or MSI
11118  */
11119                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11120                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11121                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11122                 }
11123
11124 /*
11125  * Timers workaround bug: function init part.
11126  * Need to wait 20msec after initializing ILT,
11127  * needed to make sure there are no requests in
11128  * one of the PXP internal queues with "old" ILT addresses
11129  */
11130                 DELAY(20000);
11131
11132 /*
11133  * Master enable - Due to WB DMAE writes performed before this
11134  * register is re-initialized as part of the regular function
11135  * init
11136  */
11137                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11138 /* Enable the function in IGU */
11139                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11140         }
11141
11142         sc->dmae_ready = 1;
11143
11144         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11145
11146         if (!CHIP_IS_E1x(sc))
11147                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11148
11149         ecore_init_block(sc, BLOCK_ATC, init_phase);
11150         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11151         ecore_init_block(sc, BLOCK_NIG, init_phase);
11152         ecore_init_block(sc, BLOCK_SRC, init_phase);
11153         ecore_init_block(sc, BLOCK_MISC, init_phase);
11154         ecore_init_block(sc, BLOCK_TCM, init_phase);
11155         ecore_init_block(sc, BLOCK_UCM, init_phase);
11156         ecore_init_block(sc, BLOCK_CCM, init_phase);
11157         ecore_init_block(sc, BLOCK_XCM, init_phase);
11158         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11159         ecore_init_block(sc, BLOCK_USEM, init_phase);
11160         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11161         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11162
11163         if (!CHIP_IS_E1x(sc))
11164                 REG_WR(sc, QM_REG_PF_EN, 1);
11165
11166         if (!CHIP_IS_E1x(sc)) {
11167                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11168                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11169                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11170                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11171         }
11172         ecore_init_block(sc, BLOCK_QM, init_phase);
11173
11174         ecore_init_block(sc, BLOCK_TM, init_phase);
11175         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11176
11177         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11178         ecore_init_block(sc, BLOCK_PRS, init_phase);
11179         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11180         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11181         ecore_init_block(sc, BLOCK_USDM, init_phase);
11182         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11183         ecore_init_block(sc, BLOCK_UPB, init_phase);
11184         ecore_init_block(sc, BLOCK_XPB, init_phase);
11185         ecore_init_block(sc, BLOCK_PBF, init_phase);
11186         if (!CHIP_IS_E1x(sc))
11187                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11188
11189         ecore_init_block(sc, BLOCK_CDU, init_phase);
11190
11191         ecore_init_block(sc, BLOCK_CFC, init_phase);
11192
11193         if (!CHIP_IS_E1x(sc))
11194                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11195
11196         if (IS_MF(sc)) {
11197                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11198                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11199         }
11200
11201         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11202
11203         /* HC init per function */
11204         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11205                 if (CHIP_IS_E1H(sc)) {
11206                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11207
11208                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11209                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11210                 }
11211                 ecore_init_block(sc, BLOCK_HC, init_phase);
11212
11213         } else {
11214                 uint32_t num_segs, sb_idx, prod_offset;
11215
11216                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11217
11218                 if (!CHIP_IS_E1x(sc)) {
11219                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11220                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11221                 }
11222
11223                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11224
11225                 if (!CHIP_IS_E1x(sc)) {
11226                         int dsb_idx = 0;
11227         /**
11228          * Producer memory:
11229          * E2 mode: address 0-135 match to the mapping memory;
11230          * 136 - PF0 default prod; 137 - PF1 default prod;
11231          * 138 - PF2 default prod; 139 - PF3 default prod;
11232          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11233          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11234          * 144-147 reserved.
11235          *
11236          * E1.5 mode - In backward compatible mode;
11237          * for non default SB; each even line in the memory
11238          * holds the U producer and each odd line hold
11239          * the C producer. The first 128 producers are for
11240          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11241          * producers are for the DSB for each PF.
11242          * Each PF has five segments: (the order inside each
11243          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11244          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11245          * 144-147 attn prods;
11246          */
11247                         /* non-default-status-blocks */
11248                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11249                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11250                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11251                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11252                                     num_segs;
11253
11254                                 for (i = 0; i < num_segs; i++) {
11255                                         addr = IGU_REG_PROD_CONS_MEMORY +
11256                                             (prod_offset + i) * 4;
11257                                         REG_WR(sc, addr, 0);
11258                                 }
11259                                 /* send consumer update with value 0 */
11260                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11261                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11262                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11263                         }
11264
11265                         /* default-status-blocks */
11266                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11267                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11268
11269                         if (CHIP_IS_MODE_4_PORT(sc))
11270                                 dsb_idx = SC_FUNC(sc);
11271                         else
11272                                 dsb_idx = SC_VN(sc);
11273
11274                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11275                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11276                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11277
11278                         /*
11279                          * igu prods come in chunks of E1HVN_MAX (4) -
11280                          * does not matters what is the current chip mode
11281                          */
11282                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11283                                 addr = IGU_REG_PROD_CONS_MEMORY +
11284                                     (prod_offset + i) * 4;
11285                                 REG_WR(sc, addr, 0);
11286                         }
11287                         /* send consumer update with 0 */
11288                         if (CHIP_INT_MODE_IS_BC(sc)) {
11289                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11290                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11291                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11292                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11293                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11294                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11295                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11296                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11297                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11298                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11299                         } else {
11300                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11301                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11302                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11303                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11304                         }
11305                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11306
11307                         /* !!! these should become driver const once
11308                            rf-tool supports split-68 const */
11309                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11310                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11311                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11312                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11313                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11314                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11315                 }
11316         }
11317
11318         /* Reset PCIE errors for debug */
11319         REG_WR(sc, 0x2114, 0xffffffff);
11320         REG_WR(sc, 0x2120, 0xffffffff);
11321
11322         if (CHIP_IS_E1x(sc)) {
11323                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11324                 main_mem_base = HC_REG_MAIN_MEMORY +
11325                     SC_PORT(sc) * (main_mem_size * 4);
11326                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11327                 main_mem_width = 8;
11328
11329                 val = REG_RD(sc, main_mem_prty_clr);
11330                 if (val) {
11331                         PMD_DRV_LOG(DEBUG, sc,
11332                                     "Parity errors in HC block during function init (0x%x)!",
11333                                     val);
11334                 }
11335
11336 /* Clear "false" parity errors in MSI-X table */
11337                 for (i = main_mem_base;
11338                      i < main_mem_base + main_mem_size * 4;
11339                      i += main_mem_width) {
11340                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11341                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11342                                        i, main_mem_width / 4);
11343                 }
11344 /* Clear HC parity attention */
11345                 REG_RD(sc, main_mem_prty_clr);
11346         }
11347
11348         /* Enable STORMs SP logging */
11349         REG_WR8(sc, BAR_USTRORM_INTMEM +
11350                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11351         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11352                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11353         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11354                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11355         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11356                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11357
11358         elink_phy_probe(&sc->link_params);
11359
11360         return 0;
11361 }
11362
11363 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11364 {
11365         if (!BNX2X_NOMCP(sc)) {
11366                 bnx2x_acquire_phy_lock(sc);
11367                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11368                 bnx2x_release_phy_lock(sc);
11369         } else {
11370                 if (!CHIP_REV_IS_SLOW(sc)) {
11371                         PMD_DRV_LOG(WARNING, sc,
11372                                     "Bootcode is missing - cannot reset link");
11373                 }
11374         }
11375 }
11376
11377 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11378 {
11379         int port = SC_PORT(sc);
11380         uint32_t val;
11381
11382         /* reset physical Link */
11383         bnx2x_link_reset(sc);
11384
11385         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11386
11387         /* Do not rcv packets to BRB */
11388         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11389         /* Do not direct rcv packets that are not for MCP to the BRB */
11390         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11391                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11392
11393         /* Configure AEU */
11394         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11395
11396         DELAY(100000);
11397
11398         /* Check for BRB port occupancy */
11399         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11400         if (val) {
11401                 PMD_DRV_LOG(DEBUG, sc,
11402                             "BRB1 is not empty, %d blocks are occupied", val);
11403         }
11404 }
11405
11406 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11407 {
11408         int reg;
11409         uint32_t wb_write[2];
11410
11411         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11412
11413         wb_write[0] = ONCHIP_ADDR1(addr);
11414         wb_write[1] = ONCHIP_ADDR2(addr);
11415         REG_WR_DMAE(sc, reg, wb_write, 2);
11416 }
11417
11418 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11419 {
11420         uint32_t i, base = FUNC_ILT_BASE(func);
11421         for (i = base; i < base + ILT_PER_FUNC; i++) {
11422                 bnx2x_ilt_wr(sc, i, 0);
11423         }
11424 }
11425
11426 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11427 {
11428         struct bnx2x_fastpath *fp;
11429         int port = SC_PORT(sc);
11430         int func = SC_FUNC(sc);
11431         int i;
11432
11433         /* Disable the function in the FW */
11434         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11435         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11436         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11437         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11438
11439         /* FP SBs */
11440         FOR_EACH_ETH_QUEUE(sc, i) {
11441                 fp = &sc->fp[i];
11442                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11443                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11444                         SB_DISABLED);
11445         }
11446
11447         /* SP SB */
11448         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11449                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11450
11451         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11452                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11453                        0);
11454         }
11455
11456         /* Configure IGU */
11457         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11458                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11459                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11460         } else {
11461                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11462                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11463         }
11464
11465         if (CNIC_LOADED(sc)) {
11466 /* Disable Timer scan */
11467                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11468 /*
11469  * Wait for at least 10ms and up to 2 second for the timers
11470  * scan to complete
11471  */
11472                 for (i = 0; i < 200; i++) {
11473                         DELAY(10000);
11474                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11475                                 break;
11476                 }
11477         }
11478
11479         /* Clear ILT */
11480         bnx2x_clear_func_ilt(sc, func);
11481
11482         /*
11483          * Timers workaround bug for E2: if this is vnic-3,
11484          * we need to set the entire ilt range for this timers.
11485          */
11486         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11487                 struct ilt_client_info ilt_cli;
11488 /* use dummy TM client */
11489                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11490                 ilt_cli.start = 0;
11491                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11492                 ilt_cli.client_num = ILT_CLIENT_TM;
11493
11494                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11495         }
11496
11497         /* this assumes that reset_port() called before reset_func() */
11498         if (!CHIP_IS_E1x(sc)) {
11499                 bnx2x_pf_disable(sc);
11500         }
11501
11502         sc->dmae_ready = 0;
11503 }
11504
11505 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11506 {
11507         rte_free(sc->init_ops);
11508         rte_free(sc->init_ops_offsets);
11509         rte_free(sc->init_data);
11510         rte_free(sc->iro_array);
11511 }
11512
11513 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11514 {
11515         uint32_t len, i;
11516         uint8_t *p = sc->firmware;
11517         uint32_t off[24];
11518
11519         for (i = 0; i < 24; ++i)
11520                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11521
11522         len = off[0];
11523         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11524         if (!sc->init_ops)
11525                 goto alloc_failed;
11526         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11527
11528         len = off[2];
11529         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11530         if (!sc->init_ops_offsets)
11531                 goto alloc_failed;
11532         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11533
11534         len = off[4];
11535         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11536         if (!sc->init_data)
11537                 goto alloc_failed;
11538         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11539
11540         sc->tsem_int_table_data = p + off[7];
11541         sc->tsem_pram_data = p + off[9];
11542         sc->usem_int_table_data = p + off[11];
11543         sc->usem_pram_data = p + off[13];
11544         sc->csem_int_table_data = p + off[15];
11545         sc->csem_pram_data = p + off[17];
11546         sc->xsem_int_table_data = p + off[19];
11547         sc->xsem_pram_data = p + off[21];
11548
11549         len = off[22];
11550         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11551         if (!sc->iro_array)
11552                 goto alloc_failed;
11553         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11554
11555         return 0;
11556
11557 alloc_failed:
11558         bnx2x_release_firmware(sc);
11559         return -1;
11560 }
11561
11562 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11563 {
11564 #define MIN_PREFIX_SIZE (10)
11565
11566         int n = MIN_PREFIX_SIZE;
11567         uint16_t xlen;
11568
11569         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11570             len <= MIN_PREFIX_SIZE) {
11571                 return -1;
11572         }
11573
11574         /* optional extra fields are present */
11575         if (zbuf[3] & 0x4) {
11576                 xlen = zbuf[13];
11577                 xlen <<= 8;
11578                 xlen += zbuf[12];
11579
11580                 n += xlen;
11581         }
11582         /* file name is present */
11583         if (zbuf[3] & 0x8) {
11584                 while ((zbuf[n++] != 0) && (n < len)) ;
11585         }
11586
11587         return n;
11588 }
11589
11590 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11591 {
11592         int ret;
11593         int data_begin = cut_gzip_prefix(zbuf, len);
11594
11595         PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11596
11597         if (data_begin <= 0) {
11598                 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11599                 return -1;
11600         }
11601
11602         memset(&zlib_stream, 0, sizeof(zlib_stream));
11603         zlib_stream.next_in = zbuf + data_begin;
11604         zlib_stream.avail_in = len - data_begin;
11605         zlib_stream.next_out = sc->gz_buf;
11606         zlib_stream.avail_out = FW_BUF_SIZE;
11607
11608         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11609         if (ret != Z_OK) {
11610                 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11611                 return ret;
11612         }
11613
11614         ret = inflate(&zlib_stream, Z_FINISH);
11615         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11616                 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11617                             zlib_stream.msg);
11618         }
11619
11620         sc->gz_outlen = zlib_stream.total_out;
11621         if (sc->gz_outlen & 0x3) {
11622                 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11623                             sc->gz_outlen);
11624         }
11625         sc->gz_outlen >>= 2;
11626
11627         inflateEnd(&zlib_stream);
11628
11629         if (ret == Z_STREAM_END)
11630                 return 0;
11631
11632         return ret;
11633 }
11634
11635 static void
11636 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11637                           uint32_t addr, uint32_t len)
11638 {
11639         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11640 }
11641
11642 void
11643 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11644                           uint32_t * data)
11645 {
11646         uint8_t i;
11647         for (i = 0; i < size / 4; i++) {
11648                 REG_WR(sc, addr + (i * 4), data[i]);
11649         }
11650 }
11651
11652 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11653 {
11654         uint32_t phy_type_idx = ext_phy_type >> 8;
11655         static const char *types[] =
11656             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11657                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11658                 "BNX2X-8727",
11659                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11660         };
11661
11662         if (phy_type_idx < 12)
11663                 return types[phy_type_idx];
11664         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11665                 return types[12];
11666         else
11667                 return types[13];
11668 }
11669
11670 static const char *get_state(uint32_t state)
11671 {
11672         uint32_t state_idx = state >> 12;
11673         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11674                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11675                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11676                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11677                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11678         };
11679
11680         if (state_idx <= 0xF)
11681                 return states[state_idx];
11682         else
11683                 return states[0x10];
11684 }
11685
11686 static const char *get_recovery_state(uint32_t state)
11687 {
11688         static const char *states[] = { "NONE", "DONE", "INIT",
11689                 "WAIT", "FAILED", "NIC_LOADING"
11690         };
11691         return states[state];
11692 }
11693
11694 static const char *get_rx_mode(uint32_t mode)
11695 {
11696         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11697                 "PROMISC", "MAX_MULTICAST", "ERROR"
11698         };
11699
11700         if (mode < 0x4)
11701                 return modes[mode];
11702         else if (BNX2X_MAX_MULTICAST == mode)
11703                 return modes[4];
11704         else
11705                 return modes[5];
11706 }
11707
11708 #define BNX2X_INFO_STR_MAX 256
11709 static const char *get_bnx2x_flags(uint32_t flags)
11710 {
11711         int i;
11712         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11713                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11714                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11715                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11716         };
11717         static char flag_str[BNX2X_INFO_STR_MAX];
11718         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11719
11720         for (i = 0; i < 5; i++)
11721                 if (flags & (1 << i)) {
11722                         strcat(flag_str, flag[i]);
11723                         flags ^= (1 << i);
11724                 }
11725         if (flags) {
11726                 static char unknown[BNX2X_INFO_STR_MAX];
11727                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11728                 strcat(flag_str, unknown);
11729         }
11730         return flag_str;
11731 }
11732
11733 /*
11734  * Prints useful adapter info.
11735  */
11736 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11737 {
11738         int i = 0;
11739         __rte_unused uint32_t ext_phy_type;
11740
11741         PMD_INIT_FUNC_TRACE(sc);
11742         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11743                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11744                                                               sc->
11745                                                               devinfo.shmem_base
11746                                                               + offsetof(struct
11747                                                                          shmem_region,
11748                                                                          dev_info.port_hw_config
11749                                                                          [0].external_phy_config)));
11750         else
11751                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11752                                                                 sc->
11753                                                                 devinfo.shmem_base
11754                                                                 +
11755                                                                 offsetof(struct
11756                                                                          shmem_region,
11757                                                                          dev_info.port_hw_config
11758                                                                          [0].external_phy_config)));
11759
11760         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11761         /* Hardware chip info. */
11762         PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11763         PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11764                      (CHIP_METAL(sc) >> 4));
11765
11766         /* Bus info. */
11767         PMD_DRV_LOG(INFO, sc,
11768                     "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11769         switch (sc->devinfo.pcie_link_speed) {
11770         case 1:
11771                 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11772                 break;
11773         case 2:
11774                 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11775                 break;
11776         case 4:
11777                 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11778                 break;
11779         default:
11780                 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11781         }
11782
11783         /* Device features. */
11784         PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11785
11786         /* Miscellaneous flags. */
11787         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11788                 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11789                 i++;
11790         }
11791
11792         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11793                 if (i > 0)
11794                         PMD_DRV_LOG(INFO, sc, "|");
11795                 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11796                 i++;
11797         }
11798
11799         if (IS_PF(sc)) {
11800                 PMD_DRV_LOG(INFO, sc, "%12s : ", "Queues");
11801                 switch (sc->sp->rss_rdata.rss_mode) {
11802                 case ETH_RSS_MODE_DISABLED:
11803                         PMD_DRV_LOG(INFO, sc, "%19s", "None");
11804                         break;
11805                 case ETH_RSS_MODE_REGULAR:
11806                         PMD_DRV_LOG(INFO, sc,
11807                                     "%18s : %d", "RSS", sc->num_queues);
11808                         break;
11809                 default:
11810                         PMD_DRV_LOG(INFO, sc, "%22s", "Unknown");
11811                         break;
11812                 }
11813         }
11814
11815         /* RTE and Driver versions */
11816         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11817                         rte_version());
11818         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11819                         bnx2x_pmd_version());
11820
11821         /* Firmware versions and device features. */
11822         PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11823                      "Firmware",
11824                      BNX2X_5710_FW_MAJOR_VERSION,
11825                      BNX2X_5710_FW_MINOR_VERSION,
11826                      BNX2X_5710_FW_REVISION_VERSION);
11827         PMD_DRV_LOG(INFO, sc, "%12s : %s",
11828                      "Bootcode", sc->devinfo.bc_ver_str);
11829
11830         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11831         PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11832         PMD_DRV_LOG(INFO, sc,
11833                     "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11834         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11835                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11836         PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11837         PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11838         PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11839         PMD_DRV_LOG(INFO, sc,
11840                     "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11841         PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11842                         sc->link_params.mac_addr[0],
11843                         sc->link_params.mac_addr[1],
11844                         sc->link_params.mac_addr[2],
11845                         sc->link_params.mac_addr[3],
11846                         sc->link_params.mac_addr[4],
11847                         sc->link_params.mac_addr[5]);
11848         PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11849         PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11850         if (sc->recovery_state)
11851                 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11852                              get_recovery_state(sc->recovery_state));
11853         PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11854                      sc->cq_spq_left, sc->eq_spq_left);
11855         PMD_DRV_LOG(INFO, sc,
11856                     "%12s : %x", "Switch", sc->link_params.switch_cfg);
11857         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11858 }