drivers/net/bnx2x/bnx2x.c

   1 /*-
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015 QLogic Corporation.
  10  * All rights reserved.
  11  * www.qlogic.com
  12  *
  13  * See LICENSE.bnx2x_pmd for copyright and licensing details.
  14  */
  15
  16 #define BNX2X_DRIVER_VERSION "1.78.18"
  17
  18 #include "bnx2x.h"
  19 #include "bnx2x_vfpf.h"
  20 #include "ecore_sp.h"
  21 #include "ecore_init.h"
  22 #include "ecore_init_ops.h"
  23
  24 #include "rte_version.h"
  25
  26 #include <sys/types.h>
  27 #include <sys/stat.h>
  28 #include <fcntl.h>
  29 #include <zlib.h>
  30
  31 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  32 #define BNX2X_PMD_VERSION_MAJOR 1
  33 #define BNX2X_PMD_VERSION_MINOR 0
  34 #define BNX2X_PMD_VERSION_REVISION 1
  35 #define BNX2X_PMD_VERSION_PATCH 1
  36
  37 static inline const char *
  38 bnx2x_pmd_version(void)
  39 {
  40         static char version[32];
  41
  42         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  43                         BNX2X_PMD_VER_PREFIX,
  44                         BNX2X_DRIVER_VERSION,
  45                         BNX2X_PMD_VERSION_MAJOR,
  46                         BNX2X_PMD_VERSION_MINOR,
  47                         BNX2X_PMD_VERSION_REVISION,
  48                         BNX2X_PMD_VERSION_PATCH);
  49
  50         return version;
  51 }
  52
  53 static z_stream zlib_stream;
  54
  55 #define EVL_VLID_MASK 0x0FFF
  56
  57 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  58 #define BNX2X_DEF_SB_IDX     0x0002
  59
  60 /*
  61  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  62  * function HW initialization.
  63  */
  64 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  65 #define FLR_WAIT_INTERVAL 50    /* usecs */
  66 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  67
  68 struct pbf_pN_buf_regs {
  69         int pN;
  70         uint32_t init_crd;
  71         uint32_t crd;
  72         uint32_t crd_freed;
  73 };
  74
  75 struct pbf_pN_cmd_regs {
  76         int pN;
  77         uint32_t lines_occup;
  78         uint32_t lines_freed;
  79 };
  80
  81 /* resources needed for unloading a previously loaded device */
  82
  83 #define BNX2X_PREV_WAIT_NEEDED 1
  84 rte_spinlock_t bnx2x_prev_mtx;
  85 struct bnx2x_prev_list_node {
  86         LIST_ENTRY(bnx2x_prev_list_node) node;
  87         uint8_t bus;
  88         uint8_t slot;
  89         uint8_t path;
  90         uint8_t aer;
  91         uint8_t undi;
  92 };
  93
  94 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  95         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  96
  97 static int load_count[2][3] = { { 0 } };
  98         /* per-path: 0-common, 1-port0, 2-port1 */
  99
 100 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 101                                 uint8_t cmng_type);
 102 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 103 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 104                               uint8_t port);
 105 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 106 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 107 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 108 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 109 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 110                                      uint8_t print);
 111 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 112 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 113 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 114 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 115                                  struct bnx2x_fastpath *fp,
 116                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 117 static void bnx2x_link_report(struct bnx2x_softc *sc);
 118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 123 static __attribute__ ((noinline))
 124 int bnx2x_nic_load(struct bnx2x_softc *sc);
 125
 126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 128 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
 129 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 130                          uint8_t storm, uint16_t index, uint8_t op,
 131                          uint8_t update);
 132
 133 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 134 {
 135         int res;
 136
 137         mb();
 138         res = ((*addr) & (1UL << nr)) != 0;
 139         mb();
 140         return res;
 141 }
 142
 143 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 144 {
 145         __sync_fetch_and_or(addr, (1UL << nr));
 146 }
 147
 148 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 149 {
 150         __sync_fetch_and_and(addr, ~(1UL << nr));
 151 }
 152
 153 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 154 {
 155         unsigned long mask = (1UL << nr);
 156         return __sync_fetch_and_and(addr, ~mask) & mask;
 157 }
 158
 159 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 160 {
 161         return __sync_val_compare_and_swap(addr, old, new);
 162 }
 163
 164 int
 165 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 166               const char *msg, uint32_t align)
 167 {
 168         char mz_name[RTE_MEMZONE_NAMESIZE];
 169         const struct rte_memzone *z;
 170
 171         dma->sc = sc;
 172         if (IS_PF(sc))
 173                 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 174                         rte_get_timer_cycles());
 175         else
 176                 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 177                         rte_get_timer_cycles());
 178
 179         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 180         z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
 181                                         SOCKET_ID_ANY,
 182                                         0, align);
 183         if (z == NULL) {
 184                 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
 185                 return -ENOMEM;
 186         }
 187         dma->paddr = (uint64_t) z->phys_addr;
 188         dma->vaddr = z->addr;
 189
 190         PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 191
 192         return 0;
 193 }
 194
 195 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 196 {
 197         uint32_t lock_status;
 198         uint32_t resource_bit = (1 << resource);
 199         int func = SC_FUNC(sc);
 200         uint32_t hw_lock_control_reg;
 201         int cnt;
 202
 203         PMD_INIT_FUNC_TRACE();
 204
 205         /* validate the resource is within range */
 206         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 207                 PMD_DRV_LOG(NOTICE,
 208                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 209                             resource);
 210                 return -1;
 211         }
 212
 213         if (func <= 5) {
 214                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 215         } else {
 216                 hw_lock_control_reg =
 217                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 218         }
 219
 220         /* validate the resource is not already taken */
 221         lock_status = REG_RD(sc, hw_lock_control_reg);
 222         if (lock_status & resource_bit) {
 223                 PMD_DRV_LOG(NOTICE,
 224                             "resource in use (status 0x%x bit 0x%x)",
 225                             lock_status, resource_bit);
 226                 return -1;
 227         }
 228
 229         /* try every 5ms for 5 seconds */
 230         for (cnt = 0; cnt < 1000; cnt++) {
 231                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 232                 lock_status = REG_RD(sc, hw_lock_control_reg);
 233                 if (lock_status & resource_bit) {
 234                         return 0;
 235                 }
 236                 DELAY(5000);
 237         }
 238
 239         PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
 240         return -1;
 241 }
 242
 243 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 244 {
 245         uint32_t lock_status;
 246         uint32_t resource_bit = (1 << resource);
 247         int func = SC_FUNC(sc);
 248         uint32_t hw_lock_control_reg;
 249
 250         PMD_INIT_FUNC_TRACE();
 251
 252         /* validate the resource is within range */
 253         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 254                 PMD_DRV_LOG(NOTICE,
 255                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 256                             resource);
 257                 return -1;
 258         }
 259
 260         if (func <= 5) {
 261                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 262         } else {
 263                 hw_lock_control_reg =
 264                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 265         }
 266
 267         /* validate the resource is currently taken */
 268         lock_status = REG_RD(sc, hw_lock_control_reg);
 269         if (!(lock_status & resource_bit)) {
 270                 PMD_DRV_LOG(NOTICE,
 271                             "resource not in use (status 0x%x bit 0x%x)",
 272                             lock_status, resource_bit);
 273                 return -1;
 274         }
 275
 276         REG_WR(sc, hw_lock_control_reg, resource_bit);
 277         return 0;
 278 }
 279
 280 /* copy command into DMAE command memory and set DMAE command Go */
 281 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 282 {
 283         uint32_t cmd_offset;
 284         uint32_t i;
 285
 286         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 287         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 288                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 289         }
 290
 291         REG_WR(sc, dmae_reg_go_c[idx], 1);
 292 }
 293
 294 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 295 {
 296         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 297                           DMAE_COMMAND_C_TYPE_ENABLE);
 298 }
 299
 300 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 301 {
 302         return opcode & ~DMAE_COMMAND_SRC_RESET;
 303 }
 304
 305 uint32_t
 306 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 307                 uint8_t with_comp, uint8_t comp_type)
 308 {
 309         uint32_t opcode = 0;
 310
 311         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 312                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 313
 314         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 315
 316         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 317
 318         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 319                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 320
 321         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 322
 323 #ifdef __BIG_ENDIAN
 324         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 325 #else
 326         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 327 #endif
 328
 329         if (with_comp) {
 330                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 331         }
 332
 333         return opcode;
 334 }
 335
 336 static void
 337 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 338                         uint8_t src_type, uint8_t dst_type)
 339 {
 340         memset(dmae, 0, sizeof(struct dmae_command));
 341
 342         /* set the opcode */
 343         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 344                                        TRUE, DMAE_COMP_PCI);
 345
 346         /* fill in the completion parameters */
 347         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 348         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 349         dmae->comp_val = DMAE_COMP_VAL;
 350 }
 351
 352 /* issue a DMAE command over the init channel and wait for completion */
 353 static int
 354 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 355 {
 356         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 357         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 358
 359         /* reset completion */
 360         *wb_comp = 0;
 361
 362         /* post the command on the channel used for initializations */
 363         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 364
 365         /* wait for completion */
 366         DELAY(500);
 367
 368         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 369                 if (!timeout ||
 370                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 371                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 372                         PMD_DRV_LOG(INFO, "DMAE timeout!");
 373                         return DMAE_TIMEOUT;
 374                 }
 375
 376                 timeout--;
 377                 DELAY(50);
 378         }
 379
 380         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 381                 PMD_DRV_LOG(INFO, "DMAE PCI error!");
 382                 return DMAE_PCI_ERROR;
 383         }
 384
 385         return 0;
 386 }
 387
 388 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 389 {
 390         struct dmae_command dmae;
 391         uint32_t *data;
 392         uint32_t i;
 393         int rc;
 394
 395         if (!sc->dmae_ready) {
 396                 data = BNX2X_SP(sc, wb_data[0]);
 397
 398                 for (i = 0; i < len32; i++) {
 399                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 400                 }
 401
 402                 return;
 403         }
 404
 405         /* set opcode and fixed command fields */
 406         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 407
 408         /* fill in addresses and len */
 409         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 410         dmae.src_addr_hi = 0;
 411         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 412         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 413         dmae.len = len32;
 414
 415         /* issue the command and wait for completion */
 416         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 417                 rte_panic("DMAE failed (%d)", rc);
 418         };
 419 }
 420
 421 void
 422 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
 423                uint32_t len32)
 424 {
 425         struct dmae_command dmae;
 426         int rc;
 427
 428         if (!sc->dmae_ready) {
 429                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 430                 return;
 431         }
 432
 433         /* set opcode and fixed command fields */
 434         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 435
 436         /* fill in addresses and len */
 437         dmae.src_addr_lo = U64_LO(dma_addr);
 438         dmae.src_addr_hi = U64_HI(dma_addr);
 439         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 440         dmae.dst_addr_hi = 0;
 441         dmae.len = len32;
 442
 443         /* issue the command and wait for completion */
 444         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 445                 rte_panic("DMAE failed (%d)", rc);
 446         }
 447 }
 448
 449 static void
 450 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
 451                         uint32_t addr, uint32_t len)
 452 {
 453         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 454         uint32_t offset = 0;
 455
 456         while (len > dmae_wr_max) {
 457                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 458                                (addr + offset), /* dst GRC address */
 459                                dmae_wr_max);
 460                 offset += (dmae_wr_max * 4);
 461                 len -= dmae_wr_max;
 462         }
 463
 464         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 465                        (addr + offset), /* dst GRC address */
 466                        len);
 467 }
 468
 469 void
 470 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 471                        uint32_t cid)
 472 {
 473         /* ustorm cxt validation */
 474         cxt->ustorm_ag_context.cdu_usage =
 475             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 476                                    CDU_REGION_NUMBER_UCM_AG,
 477                                    ETH_CONNECTION_TYPE);
 478         /* xcontext validation */
 479         cxt->xstorm_ag_context.cdu_reserved =
 480             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 481                                    CDU_REGION_NUMBER_XCM_AG,
 482                                    ETH_CONNECTION_TYPE);
 483 }
 484
 485 static void
 486 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 487                             uint8_t sb_index, uint8_t ticks)
 488 {
 489         uint32_t addr =
 490             (BAR_CSTRORM_INTMEM +
 491              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 492
 493         REG_WR8(sc, addr, ticks);
 494 }
 495
 496 static void
 497 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 498                             uint8_t sb_index, uint8_t disable)
 499 {
 500         uint32_t enable_flag =
 501             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 502         uint32_t addr =
 503             (BAR_CSTRORM_INTMEM +
 504              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 505         uint8_t flags;
 506
 507         /* clear and set */
 508         flags = REG_RD8(sc, addr);
 509         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 510         flags |= enable_flag;
 511         REG_WR8(sc, addr, flags);
 512 }
 513
 514 void
 515 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 516                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 517 {
 518         uint8_t ticks = (usec / 4);
 519
 520         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 521
 522         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 523         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 524 }
 525
 526 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 527 {
 528         return REG_RD(sc, reg_addr);
 529 }
 530
 531 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 532 {
 533         REG_WR(sc, reg_addr, val);
 534 }
 535
 536 void
 537 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 538                    __rte_unused const elink_log_id_t elink_log_id, ...)
 539 {
 540         PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
 541 }
 542
 543 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 544 {
 545         uint32_t spio_reg;
 546
 547         /* Only 2 SPIOs are configurable */
 548         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 549                 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
 550                 return -1;
 551         }
 552
 553         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 554
 555         /* read SPIO and mask except the float bits */
 556         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 557
 558         switch (mode) {
 559         case MISC_SPIO_OUTPUT_LOW:
 560                 /* clear FLOAT and set CLR */
 561                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 562                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 563                 break;
 564
 565         case MISC_SPIO_OUTPUT_HIGH:
 566                 /* clear FLOAT and set SET */
 567                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 568                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 569                 break;
 570
 571         case MISC_SPIO_INPUT_HI_Z:
 572                 /* set FLOAT */
 573                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 574                 break;
 575
 576         default:
 577                 break;
 578         }
 579
 580         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 581         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 582
 583         return 0;
 584 }
 585
 586 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 587 {
 588         /* The GPIO should be swapped if swap register is set and active */
 589         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 590                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 591         int gpio_shift = gpio_num;
 592         if (gpio_port)
 593                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 594
 595         uint32_t gpio_mask = (1 << gpio_shift);
 596         uint32_t gpio_reg;
 597
 598         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 599                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 600                 return -1;
 601         }
 602
 603         /* read GPIO value */
 604         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 605
 606         /* get the requested pin value */
 607         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 608 }
 609
 610 static int
 611 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 612 {
 613         /* The GPIO should be swapped if swap register is set and active */
 614         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 615                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 616         int gpio_shift = gpio_num;
 617         if (gpio_port)
 618                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 619
 620         uint32_t gpio_mask = (1 << gpio_shift);
 621         uint32_t gpio_reg;
 622
 623         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 624                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 625                 return -1;
 626         }
 627
 628         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 629
 630         /* read GPIO and mask except the float bits */
 631         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 632
 633         switch (mode) {
 634         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 635                 /* clear FLOAT and set CLR */
 636                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 637                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 638                 break;
 639
 640         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 641                 /* clear FLOAT and set SET */
 642                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 643                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 644                 break;
 645
 646         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 647                 /* set FLOAT */
 648                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 649                 break;
 650
 651         default:
 652                 break;
 653         }
 654
 655         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 656         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 657
 658         return 0;
 659 }
 660
 661 static int
 662 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 663 {
 664         uint32_t gpio_reg;
 665
 666         /* any port swapping should be handled by caller */
 667
 668         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 669
 670         /* read GPIO and mask except the float bits */
 671         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 672         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 673         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 674         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 675
 676         switch (mode) {
 677         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 678                 /* set CLR */
 679                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 680                 break;
 681
 682         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 683                 /* set SET */
 684                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 685                 break;
 686
 687         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 688                 /* set FLOAT */
 689                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 690                 break;
 691
 692         default:
 693                 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
 694                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 695                 return -1;
 696         }
 697
 698         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 699         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 700
 701         return 0;
 702 }
 703
 704 static int
 705 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 706                    uint8_t port)
 707 {
 708         /* The GPIO should be swapped if swap register is set and active */
 709         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 710                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 711         int gpio_shift = gpio_num;
 712         if (gpio_port)
 713                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 714
 715         uint32_t gpio_mask = (1 << gpio_shift);
 716         uint32_t gpio_reg;
 717
 718         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 719                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 720                 return -1;
 721         }
 722
 723         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 724
 725         /* read GPIO int */
 726         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 727
 728         switch (mode) {
 729         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 730                 /* clear SET and set CLR */
 731                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 732                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 733                 break;
 734
 735         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 736                 /* clear CLR and set SET */
 737                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 738                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 739                 break;
 740
 741         default:
 742                 break;
 743         }
 744
 745         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 746         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 747
 748         return 0;
 749 }
 750
 751 uint32_t
 752 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 753 {
 754         return bnx2x_gpio_read(sc, gpio_num, port);
 755 }
 756
 757 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 758                             uint8_t port)
 759 {
 760         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 761 }
 762
 763 uint8_t
 764 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 765                          uint8_t mode /* 0=low 1=high */ )
 766 {
 767         return bnx2x_gpio_mult_write(sc, pins, mode);
 768 }
 769
 770 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 771                                 uint8_t port)
 772 {
 773         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 774 }
 775
 776 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 777 {
 778         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 779                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 780 }
 781
 782 /* send the MCP a request, block until there is a reply */
 783 uint32_t
 784 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 785 {
 786         int mb_idx = SC_FW_MB_IDX(sc);
 787         uint32_t seq;
 788         uint32_t rc = 0;
 789         uint32_t cnt = 1;
 790         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 791
 792         seq = ++sc->fw_seq;
 793         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 794         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 795
 796         PMD_DRV_LOG(DEBUG,
 797                     "wrote command 0x%08x to FW MB param 0x%08x",
 798                     (command | seq), param);
 799
 800         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 801         do {
 802                 DELAY(delay * 1000);
 803                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 804         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 805
 806         /* is this a reply to our command? */
 807         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 808                 rc &= FW_MSG_CODE_MASK;
 809         } else {
 810                 /* Ruh-roh! */
 811                 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
 812                 rc = 0;
 813         }
 814
 815         return rc;
 816 }
 817
 818 static uint32_t
 819 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 820 {
 821         return elink_cb_fw_command(sc, command, param);
 822 }
 823
 824 static void
 825 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 826                            phys_addr_t mapping)
 827 {
 828         REG_WR(sc, addr, U64_LO(mapping));
 829         REG_WR(sc, (addr + 4), U64_HI(mapping));
 830 }
 831
 832 static void
 833 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
 834                       uint16_t abs_fid)
 835 {
 836         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 837                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 838         __storm_memset_dma_mapping(sc, addr, mapping);
 839 }
 840
 841 static void
 842 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 843 {
 844         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 845                 pf_id);
 846         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 847                 pf_id);
 848         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 849                 pf_id);
 850         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 851                 pf_id);
 852 }
 853
 854 static void
 855 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 856 {
 857         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 858                 enable);
 859         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 860                 enable);
 861         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 862                 enable);
 863         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 864                 enable);
 865 }
 866
 867 static void
 868 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 869                      uint16_t pfid)
 870 {
 871         uint32_t addr;
 872         size_t size;
 873
 874         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 875         size = sizeof(struct event_ring_data);
 876         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 877 }
 878
 879 static void
 880 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 881 {
 882         uint32_t addr = (BAR_CSTRORM_INTMEM +
 883                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 884         REG_WR16(sc, addr, eq_prod);
 885 }
 886
 887 /*
 888  * Post a slowpath command.
 889  *
 890  * A slowpath command is used to propogate a configuration change through
 891  * the controller in a controlled manner, allowing each STORM processor and
 892  * other H/W blocks to phase in the change.  The commands sent on the
 893  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 894  * completion of the ramrod will occur in different ways.  Here's a
 895  * breakdown of ramrods and how they complete:
 896  *
 897  * RAMROD_CMD_ID_ETH_PORT_SETUP
 898  *   Used to setup the leading connection on a port.  Completes on the
 899  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 900  *
 901  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 902  *   Used to setup an additional connection on a port.  Completes on the
 903  *   RCQ of the multi-queue/RSS connection being initialized.
 904  *
 905  * RAMROD_CMD_ID_ETH_STAT_QUERY
 906  *   Used to force the storm processors to update the statistics database
 907  *   in host memory.  This ramrod is send on the leading connection CID and
 908  *   completes as an index increment of the CSTORM on the default status
 909  *   block.
 910  *
 911  * RAMROD_CMD_ID_ETH_UPDATE
 912  *   Used to update the state of the leading connection, usually to udpate
 913  *   the RSS indirection table.  Completes on the RCQ of the leading
 914  *   connection. (Not currently used under FreeBSD until OS support becomes
 915  *   available.)
 916  *
 917  * RAMROD_CMD_ID_ETH_HALT
 918  *   Used when tearing down a connection prior to driver unload.  Completes
 919  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 920  *   use this on the leading connection.
 921  *
 922  * RAMROD_CMD_ID_ETH_SET_MAC
 923  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 924  *   the RCQ of the leading connection.
 925  *
 926  * RAMROD_CMD_ID_ETH_CFC_DEL
 927  *   Used when tearing down a conneciton prior to driver unload.  Completes
 928  *   on the RCQ of the leading connection (since the current connection
 929  *   has been completely removed from controller memory).
 930  *
 931  * RAMROD_CMD_ID_ETH_PORT_DEL
 932  *   Used to tear down the leading connection prior to driver unload,
 933  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 934  *   default status block.
 935  *
 936  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 937  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 938  *   RSS connection that is being offloaded.  (Not currently used under
 939  *   FreeBSD.)
 940  *
 941  * There can only be one command pending per function.
 942  *
 943  * Returns:
 944  *   0 = Success, !0 = Failure.
 945  */
 946
 947 /* must be called under the spq lock */
 948 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 949 {
 950         struct eth_spe *next_spe = sc->spq_prod_bd;
 951
 952         if (sc->spq_prod_bd == sc->spq_last_bd) {
 953                 /* wrap back to the first eth_spq */
 954                 sc->spq_prod_bd = sc->spq;
 955                 sc->spq_prod_idx = 0;
 956         } else {
 957                 sc->spq_prod_bd++;
 958                 sc->spq_prod_idx++;
 959         }
 960
 961         return next_spe;
 962 }
 963
 964 /* must be called under the spq lock */
 965 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 966 {
 967         int func = SC_FUNC(sc);
 968
 969         /*
 970          * Make sure that BD data is updated before writing the producer.
 971          * BD data is written to the memory, the producer is read from the
 972          * memory, thus we need a full memory barrier to ensure the ordering.
 973          */
 974         mb();
 975
 976         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 977                  sc->spq_prod_idx);
 978
 979         mb();
 980 }
 981
 982 /**
 983  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 984  *
 985  * @cmd:      command to check
 986  * @cmd_type: command type
 987  */
 988 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
 989 {
 990         if ((cmd_type == NONE_CONNECTION_TYPE) ||
 991             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
 992             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
 993             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
 994             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
 995             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
 996             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
 997                 return TRUE;
 998         } else {
 999                 return FALSE;
1000         }
1001 }
1002
1003 /**
1004  * bnx2x_sp_post - place a single command on an SP ring
1005  *
1006  * @sc:         driver handle
1007  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1008  * @cid:        SW CID the command is related to
1009  * @data_hi:    command private data address (high 32 bits)
1010  * @data_lo:    command private data address (low 32 bits)
1011  * @cmd_type:   command type (e.g. NONE, ETH)
1012  *
1013  * SP data is handled as if it's always an address pair, thus data fields are
1014  * not swapped to little endian in upper functions. Instead this function swaps
1015  * data as if it's two uint32 fields.
1016  */
1017 int
1018 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1019             uint32_t data_lo, int cmd_type)
1020 {
1021         struct eth_spe *spe;
1022         uint16_t type;
1023         int common;
1024
1025         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1026
1027         if (common) {
1028                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1029                         PMD_DRV_LOG(INFO, "EQ ring is full!");
1030                         return -1;
1031                 }
1032         } else {
1033                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1034                         PMD_DRV_LOG(INFO, "SPQ ring is full!");
1035                         return -1;
1036                 }
1037         }
1038
1039         spe = bnx2x_sp_get_next(sc);
1040
1041         /* CID needs port number to be encoded int it */
1042         spe->hdr.conn_and_cmd_data =
1043             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1044
1045         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1046
1047         /* TBD: Check if it works for VFs */
1048         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1049                  SPE_HDR_FUNCTION_ID);
1050
1051         spe->hdr.type = htole16(type);
1052
1053         spe->data.update_data_addr.hi = htole32(data_hi);
1054         spe->data.update_data_addr.lo = htole32(data_lo);
1055
1056         /*
1057          * It's ok if the actual decrement is issued towards the memory
1058          * somewhere between the lock and unlock. Thus no more explict
1059          * memory barrier is needed.
1060          */
1061         if (common) {
1062                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1063         } else {
1064                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1065         }
1066
1067         PMD_DRV_LOG(DEBUG,
1068                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1069                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1070                     sc->spq_prod_idx,
1071                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1072                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1073                                 (uint8_t *) sc->spq_prod_bd -
1074                                 (uint8_t *) sc->spq), command, common,
1075                     HW_CID(sc, cid), data_hi, data_lo, type,
1076                     atomic_load_acq_long(&sc->cq_spq_left),
1077                     atomic_load_acq_long(&sc->eq_spq_left));
1078
1079         bnx2x_sp_prod_update(sc);
1080
1081         return 0;
1082 }
1083
1084 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1085 {
1086         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1087                  sc->fw_drv_pulse_wr_seq);
1088 }
1089
1090 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1091 {
1092         uint16_t hw_cons;
1093         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1094
1095         if (unlikely(!txq)) {
1096                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1097                 return 0;
1098         }
1099
1100         mb();                   /* status block fields can change */
1101         hw_cons = le16toh(*fp->tx_cons_sb);
1102         return hw_cons != txq->tx_pkt_head;
1103 }
1104
1105 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1106 {
1107         /* expand this for multi-cos if ever supported */
1108         return bnx2x_tx_queue_has_work(fp);
1109 }
1110
1111 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1112 {
1113         uint16_t rx_cq_cons_sb;
1114         struct bnx2x_rx_queue *rxq;
1115         rxq = fp->sc->rx_queues[fp->index];
1116         if (unlikely(!rxq)) {
1117                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1118                 return 0;
1119         }
1120
1121         mb();                   /* status block fields can change */
1122         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1123         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1124                      MAX_RCQ_ENTRIES(rxq)))
1125                 rx_cq_cons_sb++;
1126         return rxq->rx_cq_head != rx_cq_cons_sb;
1127 }
1128
1129 static void
1130 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1131              union eth_rx_cqe *rr_cqe)
1132 {
1133 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1134         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1135 #endif
1136         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1137         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1138         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1139
1140         PMD_DRV_LOG(DEBUG,
1141                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1142                     fp->index, cid, command, sc->state,
1143                     rr_cqe->ramrod_cqe.ramrod_type);
1144
1145         switch (command) {
1146         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1147                 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1148                 drv_cmd = ECORE_Q_CMD_UPDATE;
1149                 break;
1150
1151         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1152                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1153                 drv_cmd = ECORE_Q_CMD_SETUP;
1154                 break;
1155
1156         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1157                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1158                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1159                 break;
1160
1161         case (RAMROD_CMD_ID_ETH_HALT):
1162                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1163                 drv_cmd = ECORE_Q_CMD_HALT;
1164                 break;
1165
1166         case (RAMROD_CMD_ID_ETH_TERMINATE):
1167                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1168                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1169                 break;
1170
1171         case (RAMROD_CMD_ID_ETH_EMPTY):
1172                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1173                 drv_cmd = ECORE_Q_CMD_EMPTY;
1174                 break;
1175
1176         default:
1177                 PMD_DRV_LOG(DEBUG,
1178                             "ERROR: unexpected MC reply (%d)"
1179                             "on fp[%d]", command, fp->index);
1180                 return;
1181         }
1182
1183         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1184             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1185                 /*
1186                  * q_obj->complete_cmd() failure means that this was
1187                  * an unexpected completion.
1188                  *
1189                  * In this case we don't want to increase the sc->spq_left
1190                  * because apparently we haven't sent this command the first
1191                  * place.
1192                  */
1193                 // rte_panic("Unexpected SP completion");
1194                 return;
1195         }
1196
1197         atomic_add_acq_long(&sc->cq_spq_left, 1);
1198
1199         PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1200                     atomic_load_acq_long(&sc->cq_spq_left));
1201 }
1202
1203 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1204 {
1205         struct bnx2x_rx_queue *rxq;
1206         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1207         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1208
1209         rxq = sc->rx_queues[fp->index];
1210         if (!rxq) {
1211                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1212                 return 0;
1213         }
1214
1215         /* CQ "next element" is of the size of the regular element */
1216         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1217         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1218                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1219                 hw_cq_cons++;
1220         }
1221
1222         bd_cons = rxq->rx_bd_head;
1223         bd_prod = rxq->rx_bd_tail;
1224         bd_prod_fw = bd_prod;
1225         sw_cq_cons = rxq->rx_cq_head;
1226         sw_cq_prod = rxq->rx_cq_tail;
1227
1228         /*
1229          * Memory barrier necessary as speculative reads of the rx
1230          * buffer can be ahead of the index in the status block
1231          */
1232         rmb();
1233
1234         while (sw_cq_cons != hw_cq_cons) {
1235                 union eth_rx_cqe *cqe;
1236                 struct eth_fast_path_rx_cqe *cqe_fp;
1237                 uint8_t cqe_fp_flags;
1238                 enum eth_rx_cqe_type cqe_fp_type;
1239
1240                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1241                 bd_prod = RX_BD(bd_prod, rxq);
1242                 bd_cons = RX_BD(bd_cons, rxq);
1243
1244                 cqe = &rxq->cq_ring[comp_ring_cons];
1245                 cqe_fp = &cqe->fast_path_cqe;
1246                 cqe_fp_flags = cqe_fp->type_error_flags;
1247                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1248
1249                 /* is this a slowpath msg? */
1250                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1251                         bnx2x_sp_event(sc, fp, cqe);
1252                         goto next_cqe;
1253                 }
1254
1255                 /* is this an error packet? */
1256                 if (unlikely(cqe_fp_flags &
1257                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1258                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1259                                    cqe_fp_flags, sw_cq_cons);
1260                         goto next_rx;
1261                 }
1262
1263                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1264
1265 next_rx:
1266                 bd_cons = NEXT_RX_BD(bd_cons);
1267                 bd_prod = NEXT_RX_BD(bd_prod);
1268                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1269
1270 next_cqe:
1271                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1272                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1273
1274         }                       /* while work to do */
1275
1276         rxq->rx_bd_head = bd_cons;
1277         rxq->rx_bd_tail = bd_prod_fw;
1278         rxq->rx_cq_head = sw_cq_cons;
1279         rxq->rx_cq_tail = sw_cq_prod;
1280
1281         /* Update producers */
1282         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1283
1284         return sw_cq_cons != hw_cq_cons;
1285 }
1286
1287 static uint16_t
1288 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1289                 uint16_t pkt_idx, uint16_t bd_idx)
1290 {
1291         struct eth_tx_start_bd *tx_start_bd =
1292             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1293         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1294         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1295
1296         if (likely(tx_mbuf != NULL)) {
1297                 rte_pktmbuf_free_seg(tx_mbuf);
1298         } else {
1299                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1300                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1301         }
1302
1303         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1304         txq->nb_tx_avail += nbd;
1305
1306         while (nbd--)
1307                 bd_idx = NEXT_TX_BD(bd_idx);
1308
1309         return bd_idx;
1310 }
1311
1312 /* processes transmit completions */
1313 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1314 {
1315         uint16_t bd_cons, hw_cons, sw_cons;
1316         __rte_unused uint16_t tx_bd_avail;
1317
1318         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1319
1320         if (unlikely(!txq)) {
1321                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1322                 return 0;
1323         }
1324
1325         bd_cons = txq->tx_bd_head;
1326         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1327         sw_cons = txq->tx_pkt_head;
1328
1329         while (sw_cons != hw_cons) {
1330                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1331                 sw_cons++;
1332         }
1333
1334         txq->tx_pkt_head = sw_cons;
1335         txq->tx_bd_head = bd_cons;
1336
1337         tx_bd_avail = txq->nb_tx_avail;
1338
1339         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1340                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1341                    fp->index, tx_bd_avail, hw_cons,
1342                    txq->tx_pkt_head, txq->tx_pkt_tail,
1343                    txq->tx_bd_head, txq->tx_bd_tail);
1344         return TRUE;
1345 }
1346
1347 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1348 {
1349         struct bnx2x_fastpath *fp;
1350         int i, count;
1351
1352         /* wait until all TX fastpath tasks have completed */
1353         for (i = 0; i < sc->num_queues; i++) {
1354                 fp = &sc->fp[i];
1355
1356                 count = 1000;
1357
1358                 while (bnx2x_has_tx_work(fp)) {
1359                         bnx2x_txeof(sc, fp);
1360
1361                         if (count == 0) {
1362                                 PMD_TX_LOG(ERR,
1363                                            "Timeout waiting for fp[%d] "
1364                                            "transmits to complete!", i);
1365                                 rte_panic("tx drain failure");
1366                                 return;
1367                         }
1368
1369                         count--;
1370                         DELAY(1000);
1371                         rmb();
1372                 }
1373         }
1374
1375         return;
1376 }
1377
1378 static int
1379 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1380                  int mac_type, uint8_t wait_for_comp)
1381 {
1382         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1383         int rc;
1384
1385         /* wait for completion of requested */
1386         if (wait_for_comp) {
1387                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1388         }
1389
1390         /* Set the mac type of addresses we want to clear */
1391         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1392
1393         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1394         if (rc < 0)
1395                 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1396
1397         return rc;
1398 }
1399
1400 static int
1401 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1402                         unsigned long *rx_accept_flags,
1403                         unsigned long *tx_accept_flags)
1404 {
1405         /* Clear the flags first */
1406         *rx_accept_flags = 0;
1407         *tx_accept_flags = 0;
1408
1409         switch (rx_mode) {
1410         case BNX2X_RX_MODE_NONE:
1411                 /*
1412                  * 'drop all' supersedes any accept flags that may have been
1413                  * passed to the function.
1414                  */
1415                 break;
1416
1417         case BNX2X_RX_MODE_NORMAL:
1418                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1419                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1420                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1421
1422                 /* internal switching mode */
1423                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1424                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1425                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1426
1427                 break;
1428
1429         case BNX2X_RX_MODE_ALLMULTI:
1430                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1431                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1432                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1433
1434                 /* internal switching mode */
1435                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1436                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1437                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1438
1439                 break;
1440
1441         case BNX2X_RX_MODE_PROMISC:
1442                 /*
1443                  * According to deffinition of SI mode, iface in promisc mode
1444                  * should receive matched and unmatched (in resolution of port)
1445                  * unicast packets.
1446                  */
1447                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1448                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1449                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1450                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1451
1452                 /* internal switching mode */
1453                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1454                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1455
1456                 if (IS_MF_SI(sc)) {
1457                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1458                 } else {
1459                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1460                 }
1461
1462                 break;
1463
1464         default:
1465                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1466                 return -1;
1467         }
1468
1469         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1470         if (rx_mode != BNX2X_RX_MODE_NONE) {
1471                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1472                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1473         }
1474
1475         return 0;
1476 }
1477
1478 static int
1479 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1480                   unsigned long rx_mode_flags,
1481                   unsigned long rx_accept_flags,
1482                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1483 {
1484         struct ecore_rx_mode_ramrod_params ramrod_param;
1485         int rc;
1486
1487         memset(&ramrod_param, 0, sizeof(ramrod_param));
1488
1489         /* Prepare ramrod parameters */
1490         ramrod_param.cid = 0;
1491         ramrod_param.cl_id = cl_id;
1492         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1493         ramrod_param.func_id = SC_FUNC(sc);
1494
1495         ramrod_param.pstate = &sc->sp_state;
1496         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1497
1498         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1499         ramrod_param.rdata_mapping =
1500             (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1501             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1502
1503         ramrod_param.ramrod_flags = ramrod_flags;
1504         ramrod_param.rx_mode_flags = rx_mode_flags;
1505
1506         ramrod_param.rx_accept_flags = rx_accept_flags;
1507         ramrod_param.tx_accept_flags = tx_accept_flags;
1508
1509         rc = ecore_config_rx_mode(sc, &ramrod_param);
1510         if (rc < 0) {
1511                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1512                 return rc;
1513         }
1514
1515         return 0;
1516 }
1517
1518 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1519 {
1520         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1521         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1522         int rc;
1523
1524         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1525                                    &tx_accept_flags);
1526         if (rc) {
1527                 return rc;
1528         }
1529
1530         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1531         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1532         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1533
1534         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1535                                  rx_accept_flags, tx_accept_flags,
1536                                  ramrod_flags);
1537 }
1538
1539 /* returns the "mcp load_code" according to global load_count array */
1540 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1541 {
1542         int path = SC_PATH(sc);
1543         int port = SC_PORT(sc);
1544
1545         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1546                     path, load_count[path][0], load_count[path][1],
1547                     load_count[path][2]);
1548
1549         load_count[path][0]++;
1550         load_count[path][1 + port]++;
1551         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1552                     path, load_count[path][0], load_count[path][1],
1553                     load_count[path][2]);
1554         if (load_count[path][0] == 1)
1555                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1556         else if (load_count[path][1 + port] == 1)
1557                 return FW_MSG_CODE_DRV_LOAD_PORT;
1558         else
1559                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1560 }
1561
1562 /* returns the "mcp load_code" according to global load_count array */
1563 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1564 {
1565         int port = SC_PORT(sc);
1566         int path = SC_PATH(sc);
1567
1568         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1569                     path, load_count[path][0], load_count[path][1],
1570                     load_count[path][2]);
1571         load_count[path][0]--;
1572         load_count[path][1 + port]--;
1573         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1574                     path, load_count[path][0], load_count[path][1],
1575                     load_count[path][2]);
1576         if (load_count[path][0] == 0) {
1577                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1578         } else if (load_count[path][1 + port] == 0) {
1579                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1580         } else {
1581                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1582         }
1583 }
1584
1585 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1586 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1587 {
1588         uint32_t reset_code = 0;
1589
1590         /* Select the UNLOAD request mode */
1591         if (unload_mode == UNLOAD_NORMAL) {
1592                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1593         } else {
1594                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1595         }
1596
1597         /* Send the request to the MCP */
1598         if (!BNX2X_NOMCP(sc)) {
1599                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1600         } else {
1601                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1602         }
1603
1604         return reset_code;
1605 }
1606
1607 /* send UNLOAD_DONE command to the MCP */
1608 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1609 {
1610         uint32_t reset_param =
1611             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1612
1613         /* Report UNLOAD_DONE to MCP */
1614         if (!BNX2X_NOMCP(sc)) {
1615                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1616         }
1617 }
1618
1619 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1620 {
1621         int tout = 50;
1622
1623         if (!sc->port.pmf) {
1624                 return 0;
1625         }
1626
1627         /*
1628          * (assumption: No Attention from MCP at this stage)
1629          * PMF probably in the middle of TX disable/enable transaction
1630          * 1. Sync IRS for default SB
1631          * 2. Sync SP queue - this guarantees us that attention handling started
1632          * 3. Wait, that TX disable/enable transaction completes
1633          *
1634          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1635          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1636          * received completion for the transaction the state is TX_STOPPED.
1637          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1638          * transaction.
1639          */
1640
1641         while (ecore_func_get_state(sc, &sc->func_obj) !=
1642                ECORE_F_STATE_STARTED && tout--) {
1643                 DELAY(20000);
1644         }
1645
1646         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1647                 /*
1648                  * Failed to complete the transaction in a "good way"
1649                  * Force both transactions with CLR bit.
1650                  */
1651                 struct ecore_func_state_params func_params = { NULL };
1652
1653                 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1654                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1655
1656                 func_params.f_obj = &sc->func_obj;
1657                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1658
1659                 /* STARTED-->TX_STOPPED */
1660                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1661                 ecore_func_state_change(sc, &func_params);
1662
1663                 /* TX_STOPPED-->STARTED */
1664                 func_params.cmd = ECORE_F_CMD_TX_START;
1665                 return ecore_func_state_change(sc, &func_params);
1666         }
1667
1668         return 0;
1669 }
1670
1671 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1672 {
1673         struct bnx2x_fastpath *fp = &sc->fp[index];
1674         struct ecore_queue_state_params q_params = { NULL };
1675         int rc;
1676
1677         PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1678
1679         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1680         /* We want to wait for completion in this context */
1681         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1682
1683         /* Stop the primary connection: */
1684
1685         /* ...halt the connection */
1686         q_params.cmd = ECORE_Q_CMD_HALT;
1687         rc = ecore_queue_state_change(sc, &q_params);
1688         if (rc) {
1689                 return rc;
1690         }
1691
1692         /* ...terminate the connection */
1693         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1694         memset(&q_params.params.terminate, 0,
1695                sizeof(q_params.params.terminate));
1696         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1697         rc = ecore_queue_state_change(sc, &q_params);
1698         if (rc) {
1699                 return rc;
1700         }
1701
1702         /* ...delete cfc entry */
1703         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1704         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1705         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1706         return ecore_queue_state_change(sc, &q_params);
1707 }
1708
1709 /* wait for the outstanding SP commands */
1710 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1711 {
1712         unsigned long tmp;
1713         int tout = 5000;        /* wait for 5 secs tops */
1714
1715         while (tout--) {
1716                 mb();
1717                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1718                         return TRUE;
1719                 }
1720
1721                 DELAY(1000);
1722         }
1723
1724         mb();
1725
1726         tmp = atomic_load_acq_long(&sc->sp_state);
1727         if (tmp & mask) {
1728                 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1729                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1730                 return FALSE;
1731         }
1732
1733         return FALSE;
1734 }
1735
1736 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1737 {
1738         struct ecore_func_state_params func_params = { NULL };
1739         int rc;
1740
1741         /* prepare parameters for function state transitions */
1742         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1743         func_params.f_obj = &sc->func_obj;
1744         func_params.cmd = ECORE_F_CMD_STOP;
1745
1746         /*
1747          * Try to stop the function the 'good way'. If it fails (in case
1748          * of a parity error during bnx2x_chip_cleanup()) and we are
1749          * not in a debug mode, perform a state transaction in order to
1750          * enable further HW_RESET transaction.
1751          */
1752         rc = ecore_func_state_change(sc, &func_params);
1753         if (rc) {
1754                 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1755                             "Running a dry transaction");
1756                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1757                 return ecore_func_state_change(sc, &func_params);
1758         }
1759
1760         return 0;
1761 }
1762
1763 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1764 {
1765         struct ecore_func_state_params func_params = { NULL };
1766
1767         /* Prepare parameters for function state transitions */
1768         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1769
1770         func_params.f_obj = &sc->func_obj;
1771         func_params.cmd = ECORE_F_CMD_HW_RESET;
1772
1773         func_params.params.hw_init.load_phase = load_code;
1774
1775         return ecore_func_state_change(sc, &func_params);
1776 }
1777
1778 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1779 {
1780         if (disable_hw) {
1781                 /* prevent the HW from sending interrupts */
1782                 bnx2x_int_disable(sc);
1783         }
1784 }
1785
1786 static void
1787 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1788 {
1789         int port = SC_PORT(sc);
1790         struct ecore_mcast_ramrod_params rparam = { NULL };
1791         uint32_t reset_code;
1792         int i, rc = 0;
1793
1794         bnx2x_drain_tx_queues(sc);
1795
1796         /* give HW time to discard old tx messages */
1797         DELAY(1000);
1798
1799         /* Clean all ETH MACs */
1800         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1801                               FALSE);
1802         if (rc < 0) {
1803                 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1804         }
1805
1806         /* Clean up UC list  */
1807         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1808                               TRUE);
1809         if (rc < 0) {
1810                 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1811         }
1812
1813         /* Disable LLH */
1814         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1815
1816         /* Set "drop all" to stop Rx */
1817
1818         /*
1819          * We need to take the if_maddr_lock() here in order to prevent
1820          * a race between the completion code and this code.
1821          */
1822
1823         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1824                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1825         } else {
1826                 bnx2x_set_storm_rx_mode(sc);
1827         }
1828
1829         /* Clean up multicast configuration */
1830         rparam.mcast_obj = &sc->mcast_obj;
1831         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1832         if (rc < 0) {
1833                 PMD_DRV_LOG(NOTICE,
1834                             "Failed to send DEL MCAST command (%d)", rc);
1835         }
1836
1837         /*
1838          * Send the UNLOAD_REQUEST to the MCP. This will return if
1839          * this function should perform FUNCTION, PORT, or COMMON HW
1840          * reset.
1841          */
1842         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1843
1844         /*
1845          * (assumption: No Attention from MCP at this stage)
1846          * PMF probably in the middle of TX disable/enable transaction
1847          */
1848         rc = bnx2x_func_wait_started(sc);
1849         if (rc) {
1850                 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1851         }
1852
1853         /*
1854          * Close multi and leading connections
1855          * Completions for ramrods are collected in a synchronous way
1856          */
1857         for (i = 0; i < sc->num_queues; i++) {
1858                 if (bnx2x_stop_queue(sc, i)) {
1859                         goto unload_error;
1860                 }
1861         }
1862
1863         /*
1864          * If SP settings didn't get completed so far - something
1865          * very wrong has happen.
1866          */
1867         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1868                 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1869         }
1870
1871 unload_error:
1872
1873         rc = bnx2x_func_stop(sc);
1874         if (rc) {
1875                 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1876         }
1877
1878         /* disable HW interrupts */
1879         bnx2x_int_disable_sync(sc, TRUE);
1880
1881         /* Reset the chip */
1882         rc = bnx2x_reset_hw(sc, reset_code);
1883         if (rc) {
1884                 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1885         }
1886
1887         /* Report UNLOAD_DONE to MCP */
1888         bnx2x_send_unload_done(sc, keep_link);
1889 }
1890
1891 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1892 {
1893         uint32_t val;
1894
1895         PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1896
1897         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1898         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1899                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1900         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1901 }
1902
1903 /*
1904  * Cleans the object that have internal lists without sending
1905  * ramrods. Should be run when interrutps are disabled.
1906  */
1907 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1908 {
1909         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1910         struct ecore_mcast_ramrod_params rparam = { NULL };
1911         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1912         int rc;
1913
1914         /* Cleanup MACs' object first... */
1915
1916         /* Wait for completion of requested */
1917         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1918         /* Perform a dry cleanup */
1919         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1920
1921         /* Clean ETH primary MAC */
1922         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1923         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1924                                  &ramrod_flags);
1925         if (rc != 0) {
1926                 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1927         }
1928
1929         /* Cleanup UC list */
1930         vlan_mac_flags = 0;
1931         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1932         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1933         if (rc != 0) {
1934                 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1935         }
1936
1937         /* Now clean mcast object... */
1938
1939         rparam.mcast_obj = &sc->mcast_obj;
1940         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1941
1942         /* Add a DEL command... */
1943         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1944         if (rc < 0) {
1945                 PMD_DRV_LOG(NOTICE,
1946                             "Failed to send DEL MCAST command (%d)", rc);
1947         }
1948
1949         /* now wait until all pending commands are cleared */
1950
1951         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1952         while (rc != 0) {
1953                 if (rc < 0) {
1954                         PMD_DRV_LOG(NOTICE,
1955                                     "Failed to clean MCAST object (%d)", rc);
1956                         return;
1957                 }
1958
1959                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1960         }
1961 }
1962
1963 /* stop the controller */
1964 __attribute__ ((noinline))
1965 int
1966 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1967 {
1968         uint8_t global = FALSE;
1969         uint32_t val;
1970
1971         PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1972
1973         /* stop the periodic callout */
1974         bnx2x_periodic_stop(sc);
1975
1976         /* mark driver as unloaded in shmem2 */
1977         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1978                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1979                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1980                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1981         }
1982
1983         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1984             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1985                 /*
1986                  * We can get here if the driver has been unloaded
1987                  * during parity error recovery and is either waiting for a
1988                  * leader to complete or for other functions to unload and
1989                  * then ifconfig down has been issued. In this case we want to
1990                  * unload and let other functions to complete a recovery
1991                  * process.
1992                  */
1993                 sc->recovery_state = BNX2X_RECOVERY_DONE;
1994                 sc->is_leader = 0;
1995                 bnx2x_release_leader_lock(sc);
1996                 mb();
1997
1998                 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1999                 return -1;
2000         }
2001
2002         /*
2003          * Nothing to do during unload if previous bnx2x_nic_load()
2004          * did not completed succesfully - all resourses are released.
2005          */
2006         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2007                 return 0;
2008         }
2009
2010         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2011         mb();
2012
2013         sc->rx_mode = BNX2X_RX_MODE_NONE;
2014         bnx2x_set_rx_mode(sc);
2015         mb();
2016
2017         if (IS_PF(sc)) {
2018                 /* set ALWAYS_ALIVE bit in shmem */
2019                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2020
2021                 bnx2x_drv_pulse(sc);
2022
2023                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2024                 bnx2x_save_statistics(sc);
2025         }
2026
2027         /* wait till consumers catch up with producers in all queues */
2028         bnx2x_drain_tx_queues(sc);
2029
2030         /* if VF indicate to PF this function is going down (PF will delete sp
2031          * elements and clear initializations
2032          */
2033         if (IS_VF(sc)) {
2034                 bnx2x_vf_unload(sc);
2035         } else if (unload_mode != UNLOAD_RECOVERY) {
2036                 /* if this is a normal/close unload need to clean up chip */
2037                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2038         } else {
2039                 /* Send the UNLOAD_REQUEST to the MCP */
2040                 bnx2x_send_unload_req(sc, unload_mode);
2041
2042                 /*
2043                  * Prevent transactions to host from the functions on the
2044                  * engine that doesn't reset global blocks in case of global
2045                  * attention once gloabl blocks are reset and gates are opened
2046                  * (the engine which leader will perform the recovery
2047                  * last).
2048                  */
2049                 if (!CHIP_IS_E1x(sc)) {
2050                         bnx2x_pf_disable(sc);
2051                 }
2052
2053                 /* disable HW interrupts */
2054                 bnx2x_int_disable_sync(sc, TRUE);
2055
2056                 /* Report UNLOAD_DONE to MCP */
2057                 bnx2x_send_unload_done(sc, FALSE);
2058         }
2059
2060         /*
2061          * At this stage no more interrupts will arrive so we may safely clean
2062          * the queue'able objects here in case they failed to get cleaned so far.
2063          */
2064         if (IS_PF(sc)) {
2065                 bnx2x_squeeze_objects(sc);
2066         }
2067
2068         /* There should be no more pending SP commands at this stage */
2069         sc->sp_state = 0;
2070
2071         sc->port.pmf = 0;
2072
2073         if (IS_PF(sc)) {
2074                 bnx2x_free_mem(sc);
2075         }
2076
2077         bnx2x_free_fw_stats_mem(sc);
2078
2079         sc->state = BNX2X_STATE_CLOSED;
2080
2081         /*
2082          * Check if there are pending parity attentions. If there are - set
2083          * RECOVERY_IN_PROGRESS.
2084          */
2085         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2086                 bnx2x_set_reset_in_progress(sc);
2087
2088                 /* Set RESET_IS_GLOBAL if needed */
2089                 if (global) {
2090                         bnx2x_set_reset_global(sc);
2091                 }
2092         }
2093
2094         /*
2095          * The last driver must disable a "close the gate" if there is no
2096          * parity attention or "process kill" pending.
2097          */
2098         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2099             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2100                 bnx2x_disable_close_the_gate(sc);
2101         }
2102
2103         PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2104
2105         return 0;
2106 }
2107
2108 /*
2109  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2110  * visible to the controller.
2111  *
2112  * If an mbuf is submitted to this routine and cannot be given to the
2113  * controller (e.g. it has too many fragments) then the function may free
2114  * the mbuf and return to the caller.
2115  *
2116  * Returns:
2117  *     int: Number of TX BDs used for the mbuf
2118  *
2119  *   Note the side effect that an mbuf may be freed if it causes a problem.
2120  */
2121 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2122 {
2123         struct eth_tx_start_bd *tx_start_bd;
2124         uint16_t bd_prod, pkt_prod;
2125         struct bnx2x_softc *sc;
2126         uint32_t nbds = 0;
2127
2128         sc = txq->sc;
2129         bd_prod = txq->tx_bd_tail;
2130         pkt_prod = txq->tx_pkt_tail;
2131
2132         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2133
2134         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2135
2136         tx_start_bd->addr =
2137             rte_cpu_to_le_64(rte_mbuf_data_dma_addr(m0));
2138         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2139         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2140         tx_start_bd->general_data =
2141             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2142
2143         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2144
2145         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2146                 tx_start_bd->vlan_or_ethertype =
2147                     rte_cpu_to_le_16(m0->vlan_tci);
2148                 tx_start_bd->bd_flags.as_bitfield |=
2149                     (X_ETH_OUTBAND_VLAN <<
2150                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2151         } else {
2152                 if (IS_PF(sc))
2153                         tx_start_bd->vlan_or_ethertype =
2154                             rte_cpu_to_le_16(pkt_prod);
2155                 else {
2156                         struct ether_hdr *eh =
2157                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2158
2159                         tx_start_bd->vlan_or_ethertype =
2160                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2161                 }
2162         }
2163
2164         bd_prod = NEXT_TX_BD(bd_prod);
2165         if (IS_VF(sc)) {
2166                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2167                 const struct ether_hdr *eh =
2168                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2169                 uint8_t mac_type = UNICAST_ADDRESS;
2170
2171                 tx_parse_bd =
2172                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2173                 if (is_multicast_ether_addr(&eh->d_addr)) {
2174                         if (is_broadcast_ether_addr(&eh->d_addr))
2175                                 mac_type = BROADCAST_ADDRESS;
2176                         else
2177                                 mac_type = MULTICAST_ADDRESS;
2178                 }
2179                 tx_parse_bd->parsing_data =
2180                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2181
2182                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2183                            &eh->d_addr.addr_bytes[0], 2);
2184                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2185                            &eh->d_addr.addr_bytes[2], 2);
2186                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2187                            &eh->d_addr.addr_bytes[4], 2);
2188                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2189                            &eh->s_addr.addr_bytes[0], 2);
2190                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2191                            &eh->s_addr.addr_bytes[2], 2);
2192                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2193                            &eh->s_addr.addr_bytes[4], 2);
2194
2195                 tx_parse_bd->data.mac_addr.dst_hi =
2196                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2197                 tx_parse_bd->data.mac_addr.dst_mid =
2198                     rte_cpu_to_be_16(tx_parse_bd->data.
2199                                      mac_addr.dst_mid);
2200                 tx_parse_bd->data.mac_addr.dst_lo =
2201                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2202                 tx_parse_bd->data.mac_addr.src_hi =
2203                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2204                 tx_parse_bd->data.mac_addr.src_mid =
2205                     rte_cpu_to_be_16(tx_parse_bd->data.
2206                                      mac_addr.src_mid);
2207                 tx_parse_bd->data.mac_addr.src_lo =
2208                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2209
2210                 PMD_TX_LOG(DEBUG,
2211                            "PBD dst %x %x %x src %x %x %x p_data %x",
2212                            tx_parse_bd->data.mac_addr.dst_hi,
2213                            tx_parse_bd->data.mac_addr.dst_mid,
2214                            tx_parse_bd->data.mac_addr.dst_lo,
2215                            tx_parse_bd->data.mac_addr.src_hi,
2216                            tx_parse_bd->data.mac_addr.src_mid,
2217                            tx_parse_bd->data.mac_addr.src_lo,
2218                            tx_parse_bd->parsing_data);
2219         }
2220
2221         PMD_TX_LOG(DEBUG,
2222                    "start bd: nbytes %d flags %x vlan %x\n",
2223                    tx_start_bd->nbytes,
2224                    tx_start_bd->bd_flags.as_bitfield,
2225                    tx_start_bd->vlan_or_ethertype);
2226
2227         bd_prod = NEXT_TX_BD(bd_prod);
2228         pkt_prod++;
2229
2230         if (TX_IDX(bd_prod) < 2)
2231                 nbds++;
2232
2233         txq->nb_tx_avail -= 2;
2234         txq->tx_bd_tail = bd_prod;
2235         txq->tx_pkt_tail = pkt_prod;
2236
2237         return nbds + 2;
2238 }
2239
2240 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2241 {
2242         return L2_ILT_LINES(sc);
2243 }
2244
2245 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2246 {
2247         struct ilt_client_info *ilt_client;
2248         struct ecore_ilt *ilt = sc->ilt;
2249         uint16_t line = 0;
2250
2251         PMD_INIT_FUNC_TRACE();
2252
2253         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2254
2255         /* CDU */
2256         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2257         ilt_client->client_num = ILT_CLIENT_CDU;
2258         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2259         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2260         ilt_client->start = line;
2261         line += bnx2x_cid_ilt_lines(sc);
2262
2263         if (CNIC_SUPPORT(sc)) {
2264                 line += CNIC_ILT_LINES;
2265         }
2266
2267         ilt_client->end = (line - 1);
2268
2269         /* QM */
2270         if (QM_INIT(sc->qm_cid_count)) {
2271                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2272                 ilt_client->client_num = ILT_CLIENT_QM;
2273                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2274                 ilt_client->flags = 0;
2275                 ilt_client->start = line;
2276
2277                 /* 4 bytes for each cid */
2278                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2279                                      QM_ILT_PAGE_SZ);
2280
2281                 ilt_client->end = (line - 1);
2282         }
2283
2284         if (CNIC_SUPPORT(sc)) {
2285                 /* SRC */
2286                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2287                 ilt_client->client_num = ILT_CLIENT_SRC;
2288                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2289                 ilt_client->flags = 0;
2290                 ilt_client->start = line;
2291                 line += SRC_ILT_LINES;
2292                 ilt_client->end = (line - 1);
2293
2294                 /* TM */
2295                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2296                 ilt_client->client_num = ILT_CLIENT_TM;
2297                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2298                 ilt_client->flags = 0;
2299                 ilt_client->start = line;
2300                 line += TM_ILT_LINES;
2301                 ilt_client->end = (line - 1);
2302         }
2303
2304         assert((line <= ILT_MAX_LINES));
2305 }
2306
2307 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2308 {
2309         int i;
2310
2311         for (i = 0; i < sc->num_queues; i++) {
2312                 /* get the Rx buffer size for RX frames */
2313                 sc->fp[i].rx_buf_size =
2314                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2315         }
2316 }
2317
2318 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2319 {
2320
2321         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2322
2323         return sc->ilt == NULL;
2324 }
2325
2326 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2327 {
2328         sc->ilt->lines = rte_calloc("",
2329                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2330                                     RTE_CACHE_LINE_SIZE);
2331         return sc->ilt->lines == NULL;
2332 }
2333
2334 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2335 {
2336         rte_free(sc->ilt);
2337         sc->ilt = NULL;
2338 }
2339
2340 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2341 {
2342         if (sc->ilt->lines != NULL) {
2343                 rte_free(sc->ilt->lines);
2344                 sc->ilt->lines = NULL;
2345         }
2346 }
2347
2348 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2349 {
2350         uint32_t i;
2351
2352         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2353                 sc->context[i].vcxt = NULL;
2354                 sc->context[i].size = 0;
2355         }
2356
2357         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2358
2359         bnx2x_free_ilt_lines_mem(sc);
2360 }
2361
2362 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2363 {
2364         int context_size;
2365         int allocated;
2366         int i;
2367         char cdu_name[RTE_MEMZONE_NAMESIZE];
2368
2369         /*
2370          * Allocate memory for CDU context:
2371          * This memory is allocated separately and not in the generic ILT
2372          * functions because CDU differs in few aspects:
2373          * 1. There can be multiple entities allocating memory for context -
2374          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2375          * its own ILT lines.
2376          * 2. Since CDU page-size is not a single 4KB page (which is the case
2377          * for the other ILT clients), to be efficient we want to support
2378          * allocation of sub-page-size in the last entry.
2379          * 3. Context pointers are used by the driver to pass to FW / update
2380          * the context (for the other ILT clients the pointers are used just to
2381          * free the memory during unload).
2382          */
2383         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2384         for (i = 0, allocated = 0; allocated < context_size; i++) {
2385                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2386                                           (context_size - allocated));
2387
2388                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2389                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2390                                   &sc->context[i].vcxt_dma,
2391                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2392                         bnx2x_free_mem(sc);
2393                         return -1;
2394                 }
2395
2396                 sc->context[i].vcxt =
2397                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2398
2399                 allocated += sc->context[i].size;
2400         }
2401
2402         bnx2x_alloc_ilt_lines_mem(sc);
2403
2404         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2405                 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2406                 bnx2x_free_mem(sc);
2407                 return -1;
2408         }
2409
2410         return 0;
2411 }
2412
2413 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2414 {
2415         sc->fw_stats_num = 0;
2416
2417         sc->fw_stats_req_size = 0;
2418         sc->fw_stats_req = NULL;
2419         sc->fw_stats_req_mapping = 0;
2420
2421         sc->fw_stats_data_size = 0;
2422         sc->fw_stats_data = NULL;
2423         sc->fw_stats_data_mapping = 0;
2424 }
2425
2426 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2427 {
2428         uint8_t num_queue_stats;
2429         int num_groups, vf_headroom = 0;
2430
2431         /* number of queues for statistics is number of eth queues */
2432         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2433
2434         /*
2435          * Total number of FW statistics requests =
2436          *   1 for port stats + 1 for PF stats + num of queues
2437          */
2438         sc->fw_stats_num = (2 + num_queue_stats);
2439
2440         /*
2441          * Request is built from stats_query_header and an array of
2442          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2443          * rules. The real number or requests is configured in the
2444          * stats_query_header.
2445          */
2446         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2447         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2448                 num_groups++;
2449
2450         sc->fw_stats_req_size =
2451             (sizeof(struct stats_query_header) +
2452              (num_groups * sizeof(struct stats_query_cmd_group)));
2453
2454         /*
2455          * Data for statistics requests + stats_counter.
2456          * stats_counter holds per-STORM counters that are incremented when
2457          * STORM has finished with the current request. Memory for FCoE
2458          * offloaded statistics are counted anyway, even if they will not be sent.
2459          * VF stats are not accounted for here as the data of VF stats is stored
2460          * in memory allocated by the VF, not here.
2461          */
2462         sc->fw_stats_data_size =
2463             (sizeof(struct stats_counter) +
2464              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2465              /* sizeof(struct fcoe_statistics_params) + */
2466              (sizeof(struct per_queue_stats) * num_queue_stats));
2467
2468         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2469                           &sc->fw_stats_dma, "fw_stats",
2470                           RTE_CACHE_LINE_SIZE) != 0) {
2471                 bnx2x_free_fw_stats_mem(sc);
2472                 return -1;
2473         }
2474
2475         /* set up the shortcuts */
2476
2477         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2478         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2479
2480         sc->fw_stats_data =
2481             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2482                                          sc->fw_stats_req_size);
2483         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2484                                      sc->fw_stats_req_size);
2485
2486         return 0;
2487 }
2488
2489 /*
2490  * Bits map:
2491  * 0-7  - Engine0 load counter.
2492  * 8-15 - Engine1 load counter.
2493  * 16   - Engine0 RESET_IN_PROGRESS bit.
2494  * 17   - Engine1 RESET_IN_PROGRESS bit.
2495  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2496  *        function on the engine
2497  * 19   - Engine1 ONE_IS_LOADED.
2498  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2499  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2500  *        for just the one belonging to its engine).
2501  */
2502 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2503 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2504 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2505 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2506 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2507 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2508 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2509 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2510
2511 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2512 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2513 {
2514         uint32_t val;
2515         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2516         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2517         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2518         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2519 }
2520
2521 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2522 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2523 {
2524         uint32_t val;
2525         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2526         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2527         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2528         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2529 }
2530
2531 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2532 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2533 {
2534         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2535 }
2536
2537 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2538 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2539 {
2540         uint32_t val;
2541         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2542             BNX2X_PATH0_RST_IN_PROG_BIT;
2543
2544         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2545
2546         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2547         /* Clear the bit */
2548         val &= ~bit;
2549         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2550
2551         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2552 }
2553
2554 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2555 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2556 {
2557         uint32_t val;
2558         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2559             BNX2X_PATH0_RST_IN_PROG_BIT;
2560
2561         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2562
2563         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2564         /* Set the bit */
2565         val |= bit;
2566         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2567
2568         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2569 }
2570
2571 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2572 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2573 {
2574         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2575         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2576             BNX2X_PATH0_RST_IN_PROG_BIT;
2577
2578         /* return false if bit is set */
2579         return (val & bit) ? FALSE : TRUE;
2580 }
2581
2582 /* get the load status for an engine, should be run under rtnl lock */
2583 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2584 {
2585         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2586             BNX2X_PATH0_LOAD_CNT_MASK;
2587         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2588             BNX2X_PATH0_LOAD_CNT_SHIFT;
2589         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2590
2591         val = ((val & mask) >> shift);
2592
2593         return val != 0;
2594 }
2595
2596 /* set pf load mark */
2597 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2598 {
2599         uint32_t val;
2600         uint32_t val1;
2601         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2602             BNX2X_PATH0_LOAD_CNT_MASK;
2603         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2604             BNX2X_PATH0_LOAD_CNT_SHIFT;
2605
2606         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2607
2608         PMD_INIT_FUNC_TRACE();
2609
2610         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2611
2612         /* get the current counter value */
2613         val1 = ((val & mask) >> shift);
2614
2615         /* set bit of this PF */
2616         val1 |= (1 << SC_ABS_FUNC(sc));
2617
2618         /* clear the old value */
2619         val &= ~mask;
2620
2621         /* set the new one */
2622         val |= ((val1 << shift) & mask);
2623
2624         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2625
2626         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2627 }
2628
2629 /* clear pf load mark */
2630 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2631 {
2632         uint32_t val1, val;
2633         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2634             BNX2X_PATH0_LOAD_CNT_MASK;
2635         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2636             BNX2X_PATH0_LOAD_CNT_SHIFT;
2637
2638         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2639         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2640
2641         /* get the current counter value */
2642         val1 = (val & mask) >> shift;
2643
2644         /* clear bit of that PF */
2645         val1 &= ~(1 << SC_ABS_FUNC(sc));
2646
2647         /* clear the old value */
2648         val &= ~mask;
2649
2650         /* set the new one */
2651         val |= ((val1 << shift) & mask);
2652
2653         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2654         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2655         return val1 != 0;
2656 }
2657
2658 /* send load requrest to mcp and analyze response */
2659 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2660 {
2661         PMD_INIT_FUNC_TRACE();
2662
2663         /* init fw_seq */
2664         sc->fw_seq =
2665             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2666              DRV_MSG_SEQ_NUMBER_MASK);
2667
2668         PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2669
2670 #ifdef BNX2X_PULSE
2671         /* get the current FW pulse sequence */
2672         sc->fw_drv_pulse_wr_seq =
2673             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2674              DRV_PULSE_SEQ_MASK);
2675 #else
2676         /* set ALWAYS_ALIVE bit in shmem */
2677         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2678         bnx2x_drv_pulse(sc);
2679 #endif
2680
2681         /* load request */
2682         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2683                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2684
2685         /* if the MCP fails to respond we must abort */
2686         if (!(*load_code)) {
2687                 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2688                 return -1;
2689         }
2690
2691         /* if MCP refused then must abort */
2692         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2693                 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2694                 return -1;
2695         }
2696
2697         return 0;
2698 }
2699
2700 /*
2701  * Check whether another PF has already loaded FW to chip. In virtualized
2702  * environments a pf from anoth VM may have already initialized the device
2703  * including loading FW.
2704  */
2705 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2706 {
2707         uint32_t my_fw, loaded_fw;
2708
2709         /* is another pf loaded on this engine? */
2710         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2711             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2712                 /* build my FW version dword */
2713                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2714                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2715                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2716                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2717
2718                 /* read loaded FW from chip */
2719                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2720                 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2721                             loaded_fw, my_fw);
2722
2723                 /* abort nic load if version mismatch */
2724                 if (my_fw != loaded_fw) {
2725                         PMD_DRV_LOG(NOTICE,
2726                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2727                                     loaded_fw, my_fw);
2728                         return -1;
2729                 }
2730         }
2731
2732         return 0;
2733 }
2734
2735 /* mark PMF if applicable */
2736 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2737 {
2738         uint32_t ncsi_oem_data_addr;
2739
2740         PMD_INIT_FUNC_TRACE();
2741
2742         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2743             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2744             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2745                 /*
2746                  * Barrier here for ordering between the writing to sc->port.pmf here
2747                  * and reading it from the periodic task.
2748                  */
2749                 sc->port.pmf = 1;
2750                 mb();
2751         } else {
2752                 sc->port.pmf = 0;
2753         }
2754
2755         PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2756
2757         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2758                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2759                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2760                         if (ncsi_oem_data_addr) {
2761                                 REG_WR(sc,
2762                                        (ncsi_oem_data_addr +
2763                                         offsetof(struct glob_ncsi_oem_data,
2764                                                  driver_version)), 0);
2765                         }
2766                 }
2767         }
2768 }
2769
2770 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2771 {
2772         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2773         int abs_func;
2774         int vn;
2775
2776         if (BNX2X_NOMCP(sc)) {
2777                 return;         /* what should be the default bvalue in this case */
2778         }
2779
2780         /*
2781          * The formula for computing the absolute function number is...
2782          * For 2 port configuration (4 functions per port):
2783          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2784          * For 4 port configuration (2 functions per port):
2785          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2786          */
2787         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2788                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2789                 if (abs_func >= E1H_FUNC_MAX) {
2790                         break;
2791                 }
2792                 sc->devinfo.mf_info.mf_config[vn] =
2793                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2794         }
2795
2796         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2797             FUNC_MF_CFG_FUNC_DISABLED) {
2798                 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2799                 sc->flags |= BNX2X_MF_FUNC_DIS;
2800         } else {
2801                 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2802                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2803         }
2804 }
2805
2806 /* acquire split MCP access lock register */
2807 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2808 {
2809         uint32_t j, val;
2810
2811         for (j = 0; j < 1000; j++) {
2812                 val = (1UL << 31);
2813                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2814                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2815                 if (val & (1L << 31))
2816                         break;
2817
2818                 DELAY(5000);
2819         }
2820
2821         if (!(val & (1L << 31))) {
2822                 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2823                 return -1;
2824         }
2825
2826         return 0;
2827 }
2828
2829 /* release split MCP access lock register */
2830 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2831 {
2832         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2833 }
2834
2835 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2836 {
2837         int port = SC_PORT(sc);
2838         uint32_t ext_phy_config;
2839
2840         /* mark the failure */
2841         ext_phy_config =
2842             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2843
2844         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2845         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2846         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2847                  ext_phy_config);
2848
2849         /* log the failure */
2850         PMD_DRV_LOG(INFO,
2851                     "Fan Failure has caused the driver to shutdown "
2852                     "the card to prevent permanent damage. "
2853                     "Please contact OEM Support for assistance");
2854
2855         rte_panic("Schedule task to handle fan failure");
2856 }
2857
2858 /* this function is called upon a link interrupt */
2859 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2860 {
2861         uint32_t pause_enabled = 0;
2862         struct host_port_stats *pstats;
2863         int cmng_fns;
2864
2865         /* Make sure that we are synced with the current statistics */
2866         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2867
2868         elink_link_update(&sc->link_params, &sc->link_vars);
2869
2870         if (sc->link_vars.link_up) {
2871
2872                 /* dropless flow control */
2873                 if (sc->dropless_fc) {
2874                         pause_enabled = 0;
2875
2876                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2877                                 pause_enabled = 1;
2878                         }
2879
2880                         REG_WR(sc,
2881                                (BAR_USTRORM_INTMEM +
2882                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2883                                pause_enabled);
2884                 }
2885
2886                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2887                         pstats = BNX2X_SP(sc, port_stats);
2888                         /* reset old mac stats */
2889                         memset(&(pstats->mac_stx[0]), 0,
2890                                sizeof(struct mac_stx));
2891                 }
2892
2893                 if (sc->state == BNX2X_STATE_OPEN) {
2894                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2895                 }
2896         }
2897
2898         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2899                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2900
2901                 if (cmng_fns != CMNG_FNS_NONE) {
2902                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2903                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2904                 }
2905         }
2906
2907         bnx2x_link_report(sc);
2908
2909         if (IS_MF(sc)) {
2910                 bnx2x_link_sync_notify(sc);
2911         }
2912 }
2913
2914 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2915 {
2916         int port = SC_PORT(sc);
2917         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2918             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2919         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2920             NIG_REG_MASK_INTERRUPT_PORT0;
2921         uint32_t aeu_mask;
2922         uint32_t nig_mask = 0;
2923         uint32_t reg_addr;
2924         uint32_t igu_acked;
2925         uint32_t cnt;
2926
2927         if (sc->attn_state & asserted) {
2928                 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2929         }
2930
2931         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2932
2933         aeu_mask = REG_RD(sc, aeu_addr);
2934
2935         aeu_mask &= ~(asserted & 0x3ff);
2936
2937         REG_WR(sc, aeu_addr, aeu_mask);
2938
2939         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2940
2941         sc->attn_state |= asserted;
2942
2943         if (asserted & ATTN_HARD_WIRED_MASK) {
2944                 if (asserted & ATTN_NIG_FOR_FUNC) {
2945
2946                         /* save nig interrupt mask */
2947                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2948
2949                         /* If nig_mask is not set, no need to call the update function */
2950                         if (nig_mask) {
2951                                 REG_WR(sc, nig_int_mask_addr, 0);
2952
2953                                 bnx2x_link_attn(sc);
2954                         }
2955
2956                         /* handle unicore attn? */
2957                 }
2958
2959                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2960                         PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2961                 }
2962
2963                 if (asserted & GPIO_2_FUNC) {
2964                         PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2965                 }
2966
2967                 if (asserted & GPIO_3_FUNC) {
2968                         PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2969                 }
2970
2971                 if (asserted & GPIO_4_FUNC) {
2972                         PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2973                 }
2974
2975                 if (port == 0) {
2976                         if (asserted & ATTN_GENERAL_ATTN_1) {
2977                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2978                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2979                         }
2980                         if (asserted & ATTN_GENERAL_ATTN_2) {
2981                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2982                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2983                         }
2984                         if (asserted & ATTN_GENERAL_ATTN_3) {
2985                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2986                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2987                         }
2988                 } else {
2989                         if (asserted & ATTN_GENERAL_ATTN_4) {
2990                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2991                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2992                         }
2993                         if (asserted & ATTN_GENERAL_ATTN_5) {
2994                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2995                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2996                         }
2997                         if (asserted & ATTN_GENERAL_ATTN_6) {
2998                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
2999                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3000                         }
3001                 }
3002         }
3003         /* hardwired */
3004         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3005                 reg_addr =
3006                     (HC_REG_COMMAND_REG + port * 32 +
3007                      COMMAND_REG_ATTN_BITS_SET);
3008         } else {
3009                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3010         }
3011
3012         PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3013                     asserted,
3014                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3015                     reg_addr);
3016         REG_WR(sc, reg_addr, asserted);
3017
3018         /* now set back the mask */
3019         if (asserted & ATTN_NIG_FOR_FUNC) {
3020                 /*
3021                  * Verify that IGU ack through BAR was written before restoring
3022                  * NIG mask. This loop should exit after 2-3 iterations max.
3023                  */
3024                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3025                         cnt = 0;
3026
3027                         do {
3028                                 igu_acked =
3029                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3030                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3031                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3032
3033                         if (!igu_acked) {
3034                                 PMD_DRV_LOG(ERR,
3035                                             "Failed to verify IGU ack on time");
3036                         }
3037
3038                         mb();
3039                 }
3040
3041                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3042
3043         }
3044 }
3045
3046 static void
3047 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3048                      __rte_unused const char *blk)
3049 {
3050         PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3051 }
3052
3053 static int
3054 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3055                               uint8_t print)
3056 {
3057         uint32_t cur_bit = 0;
3058         int i = 0;
3059
3060         for (i = 0; sig; i++) {
3061                 cur_bit = ((uint32_t) 0x1 << i);
3062                 if (sig & cur_bit) {
3063                         switch (cur_bit) {
3064                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3065                                 if (print)
3066                                         bnx2x_print_next_block(sc, par_num++,
3067                                                              "BRB");
3068                                 break;
3069                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3070                                 if (print)
3071                                         bnx2x_print_next_block(sc, par_num++,
3072                                                              "PARSER");
3073                                 break;
3074                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3075                                 if (print)
3076                                         bnx2x_print_next_block(sc, par_num++,
3077                                                              "TSDM");
3078                                 break;
3079                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3080                                 if (print)
3081                                         bnx2x_print_next_block(sc, par_num++,
3082                                                              "SEARCHER");
3083                                 break;
3084                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3085                                 if (print)
3086                                         bnx2x_print_next_block(sc, par_num++,
3087                                                              "TCM");
3088                                 break;
3089                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3090                                 if (print)
3091                                         bnx2x_print_next_block(sc, par_num++,
3092                                                              "TSEMI");
3093                                 break;
3094                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3095                                 if (print)
3096                                         bnx2x_print_next_block(sc, par_num++,
3097                                                              "XPB");
3098                                 break;
3099                         }
3100
3101                         /* Clear the bit */
3102                         sig &= ~cur_bit;
3103                 }
3104         }
3105
3106         return par_num;
3107 }
3108
3109 static int
3110 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3111                               uint8_t * global, uint8_t print)
3112 {
3113         int i = 0;
3114         uint32_t cur_bit = 0;
3115         for (i = 0; sig; i++) {
3116                 cur_bit = ((uint32_t) 0x1 << i);
3117                 if (sig & cur_bit) {
3118                         switch (cur_bit) {
3119                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3120                                 if (print)
3121                                         bnx2x_print_next_block(sc, par_num++,
3122                                                              "PBF");
3123                                 break;
3124                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3125                                 if (print)
3126                                         bnx2x_print_next_block(sc, par_num++,
3127                                                              "QM");
3128                                 break;
3129                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3130                                 if (print)
3131                                         bnx2x_print_next_block(sc, par_num++,
3132                                                              "TM");
3133                                 break;
3134                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3135                                 if (print)
3136                                         bnx2x_print_next_block(sc, par_num++,
3137                                                              "XSDM");
3138                                 break;
3139                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3140                                 if (print)
3141                                         bnx2x_print_next_block(sc, par_num++,
3142                                                              "XCM");
3143                                 break;
3144                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3145                                 if (print)
3146                                         bnx2x_print_next_block(sc, par_num++,
3147                                                              "XSEMI");
3148                                 break;
3149                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3150                                 if (print)
3151                                         bnx2x_print_next_block(sc, par_num++,
3152                                                              "DOORBELLQ");
3153                                 break;
3154                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3155                                 if (print)
3156                                         bnx2x_print_next_block(sc, par_num++,
3157                                                              "NIG");
3158                                 break;
3159                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3160                                 if (print)
3161                                         bnx2x_print_next_block(sc, par_num++,
3162                                                              "VAUX PCI CORE");
3163                                 *global = TRUE;
3164                                 break;
3165                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3166                                 if (print)
3167                                         bnx2x_print_next_block(sc, par_num++,
3168                                                              "DEBUG");
3169                                 break;
3170                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3171                                 if (print)
3172                                         bnx2x_print_next_block(sc, par_num++,
3173                                                              "USDM");
3174                                 break;
3175                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3176                                 if (print)
3177                                         bnx2x_print_next_block(sc, par_num++,
3178                                                              "UCM");
3179                                 break;
3180                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3181                                 if (print)
3182                                         bnx2x_print_next_block(sc, par_num++,
3183                                                              "USEMI");
3184                                 break;
3185                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3186                                 if (print)
3187                                         bnx2x_print_next_block(sc, par_num++,
3188                                                              "UPB");
3189                                 break;
3190                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3191                                 if (print)
3192                                         bnx2x_print_next_block(sc, par_num++,
3193                                                              "CSDM");
3194                                 break;
3195                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3196                                 if (print)
3197                                         bnx2x_print_next_block(sc, par_num++,
3198                                                              "CCM");
3199                                 break;
3200                         }
3201
3202                         /* Clear the bit */
3203                         sig &= ~cur_bit;
3204                 }
3205         }
3206
3207         return par_num;
3208 }
3209
3210 static int
3211 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3212                               uint8_t print)
3213 {
3214         uint32_t cur_bit = 0;
3215         int i = 0;
3216
3217         for (i = 0; sig; i++) {
3218                 cur_bit = ((uint32_t) 0x1 << i);
3219                 if (sig & cur_bit) {
3220                         switch (cur_bit) {
3221                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3222                                 if (print)
3223                                         bnx2x_print_next_block(sc, par_num++,
3224                                                              "CSEMI");
3225                                 break;
3226                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3227                                 if (print)
3228                                         bnx2x_print_next_block(sc, par_num++,
3229                                                              "PXP");
3230                                 break;
3231                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3232                                 if (print)
3233                                         bnx2x_print_next_block(sc, par_num++,
3234                                                              "PXPPCICLOCKCLIENT");
3235                                 break;
3236                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3237                                 if (print)
3238                                         bnx2x_print_next_block(sc, par_num++,
3239                                                              "CFC");
3240                                 break;
3241                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3242                                 if (print)
3243                                         bnx2x_print_next_block(sc, par_num++,
3244                                                              "CDU");
3245                                 break;
3246                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3247                                 if (print)
3248                                         bnx2x_print_next_block(sc, par_num++,
3249                                                              "DMAE");
3250                                 break;
3251                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3252                                 if (print)
3253                                         bnx2x_print_next_block(sc, par_num++,
3254                                                              "IGU");
3255                                 break;
3256                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3257                                 if (print)
3258                                         bnx2x_print_next_block(sc, par_num++,
3259                                                              "MISC");
3260                                 break;
3261                         }
3262
3263                         /* Clear the bit */
3264                         sig &= ~cur_bit;
3265                 }
3266         }
3267
3268         return par_num;
3269 }
3270
3271 static int
3272 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3273                               uint8_t * global, uint8_t print)
3274 {
3275         uint32_t cur_bit = 0;
3276         int i = 0;
3277
3278         for (i = 0; sig; i++) {
3279                 cur_bit = ((uint32_t) 0x1 << i);
3280                 if (sig & cur_bit) {
3281                         switch (cur_bit) {
3282                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3283                                 if (print)
3284                                         bnx2x_print_next_block(sc, par_num++,
3285                                                              "MCP ROM");
3286                                 *global = TRUE;
3287                                 break;
3288                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3289                                 if (print)
3290                                         bnx2x_print_next_block(sc, par_num++,
3291                                                              "MCP UMP RX");
3292                                 *global = TRUE;
3293                                 break;
3294                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3295                                 if (print)
3296                                         bnx2x_print_next_block(sc, par_num++,
3297                                                              "MCP UMP TX");
3298                                 *global = TRUE;
3299                                 break;
3300                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3301                                 if (print)
3302                                         bnx2x_print_next_block(sc, par_num++,
3303                                                              "MCP SCPAD");
3304                                 *global = TRUE;
3305                                 break;
3306                         }
3307
3308                         /* Clear the bit */
3309                         sig &= ~cur_bit;
3310                 }
3311         }
3312
3313         return par_num;
3314 }
3315
3316 static int
3317 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3318                               uint8_t print)
3319 {
3320         uint32_t cur_bit = 0;
3321         int i = 0;
3322
3323         for (i = 0; sig; i++) {
3324                 cur_bit = ((uint32_t) 0x1 << i);
3325                 if (sig & cur_bit) {
3326                         switch (cur_bit) {
3327                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3328                                 if (print)
3329                                         bnx2x_print_next_block(sc, par_num++,
3330                                                              "PGLUE_B");
3331                                 break;
3332                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3333                                 if (print)
3334                                         bnx2x_print_next_block(sc, par_num++,
3335                                                              "ATC");
3336                                 break;
3337                         }
3338
3339                         /* Clear the bit */
3340                         sig &= ~cur_bit;
3341                 }
3342         }
3343
3344         return par_num;
3345 }
3346
3347 static uint8_t
3348 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3349                 uint32_t * sig)
3350 {
3351         int par_num = 0;
3352
3353         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3354             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3355             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3356             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3357             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3358                 PMD_DRV_LOG(ERR,
3359                             "Parity error: HW block parity attention:"
3360                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3361                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3362                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3363                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3364                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3365                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3366
3367                 if (print)
3368                         PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3369
3370                 par_num =
3371                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3372                                                   HW_PRTY_ASSERT_SET_0,
3373                                                   par_num, print);
3374                 par_num =
3375                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3376                                                   HW_PRTY_ASSERT_SET_1,
3377                                                   par_num, global, print);
3378                 par_num =
3379                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3380                                                   HW_PRTY_ASSERT_SET_2,
3381                                                   par_num, print);
3382                 par_num =
3383                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3384                                                   HW_PRTY_ASSERT_SET_3,
3385                                                   par_num, global, print);
3386                 par_num =
3387                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3388                                                   HW_PRTY_ASSERT_SET_4,
3389                                                   par_num, print);
3390
3391                 if (print)
3392                         PMD_DRV_LOG(INFO, "");
3393
3394                 return TRUE;
3395         }
3396
3397         return FALSE;
3398 }
3399
3400 static uint8_t
3401 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3402 {
3403         struct attn_route attn = { {0} };
3404         int port = SC_PORT(sc);
3405
3406         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3407         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3408         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3409         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3410
3411         if (!CHIP_IS_E1x(sc))
3412                 attn.sig[4] =
3413                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3414
3415         return bnx2x_parity_attn(sc, global, print, attn.sig);
3416 }
3417
3418 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3419 {
3420         uint32_t val;
3421
3422         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3423                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3424                 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3425                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3426                         PMD_DRV_LOG(INFO,
3427                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3428                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3429                         PMD_DRV_LOG(INFO,
3430                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3431                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3432                         PMD_DRV_LOG(INFO,
3433                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3434                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3435                         PMD_DRV_LOG(INFO,
3436                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3437                 if (val &
3438                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3439                         PMD_DRV_LOG(INFO,
3440                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3441                 if (val &
3442                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3443                         PMD_DRV_LOG(INFO,
3444                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3445                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3446                         PMD_DRV_LOG(INFO,
3447                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3448                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3449                         PMD_DRV_LOG(INFO,
3450                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3451                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3452                         PMD_DRV_LOG(INFO,
3453                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3454         }
3455
3456         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3457                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3458                 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3459                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3460                         PMD_DRV_LOG(INFO,
3461                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3462                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3463                         PMD_DRV_LOG(INFO,
3464                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3465                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3466                         PMD_DRV_LOG(INFO,
3467                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3468                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3469                         PMD_DRV_LOG(INFO,
3470                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3471                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3472                         PMD_DRV_LOG(INFO,
3473                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3474                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3475                         PMD_DRV_LOG(INFO,
3476                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3477         }
3478
3479         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3480                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3481                 PMD_DRV_LOG(INFO,
3482                             "ERROR: FATAL parity attention set4 0x%08x",
3483                             (uint32_t) (attn &
3484                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3485                                          |
3486                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3487         }
3488 }
3489
3490 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3491 {
3492         int port = SC_PORT(sc);
3493
3494         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3495 }
3496
3497 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3498 {
3499         int port = SC_PORT(sc);
3500
3501         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3502 }
3503
3504 /*
3505  * called due to MCP event (on pmf):
3506  *   reread new bandwidth configuration
3507  *   configure FW
3508  *   notify others function about the change
3509  */
3510 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3511 {
3512         if (sc->link_vars.link_up) {
3513                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3514                 bnx2x_link_sync_notify(sc);
3515         }
3516
3517         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3518 }
3519
3520 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3521 {
3522         bnx2x_config_mf_bw(sc);
3523         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3524 }
3525
3526 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3527 {
3528         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3529 }
3530
3531 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3532
3533 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3534 {
3535         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3536
3537         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3538                 ETH_STAT_INFO_VERSION_LEN);
3539
3540         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3541                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3542                                               ether_stat->mac_local + MAC_PAD,
3543                                               MAC_PAD, ETH_ALEN);
3544
3545         ether_stat->mtu_size = sc->mtu;
3546
3547         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3548         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3549
3550         ether_stat->txq_size = sc->tx_ring_size;
3551         ether_stat->rxq_size = sc->rx_ring_size;
3552 }
3553
3554 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3555 {
3556         enum drv_info_opcode op_code;
3557         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3558
3559         /* if drv_info version supported by MFW doesn't match - send NACK */
3560         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3561                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3562                 return;
3563         }
3564
3565         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3566                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3567
3568         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3569
3570         switch (op_code) {
3571         case ETH_STATS_OPCODE:
3572                 bnx2x_drv_info_ether_stat(sc);
3573                 break;
3574         case FCOE_STATS_OPCODE:
3575         case ISCSI_STATS_OPCODE:
3576         default:
3577                 /* if op code isn't supported - send NACK */
3578                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3579                 return;
3580         }
3581
3582         /*
3583          * If we got drv_info attn from MFW then these fields are defined in
3584          * shmem2 for sure
3585          */
3586         SHMEM2_WR(sc, drv_info_host_addr_lo,
3587                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3588         SHMEM2_WR(sc, drv_info_host_addr_hi,
3589                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3590
3591         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3592 }
3593
3594 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3595 {
3596         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3597 /*
3598  * This is the only place besides the function initialization
3599  * where the sc->flags can change so it is done without any
3600  * locks
3601  */
3602                 if (sc->devinfo.
3603                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3604                         PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3605                         sc->flags |= BNX2X_MF_FUNC_DIS;
3606                         bnx2x_e1h_disable(sc);
3607                 } else {
3608                         PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3609                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3610                         bnx2x_e1h_enable(sc);
3611                 }
3612                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3613         }
3614
3615         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3616                 bnx2x_config_mf_bw(sc);
3617                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3618         }
3619
3620         /* Report results to MCP */
3621         if (dcc_event)
3622                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3623         else
3624                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3625 }
3626
3627 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3628 {
3629         int port = SC_PORT(sc);
3630         uint32_t val;
3631
3632         sc->port.pmf = 1;
3633
3634         /*
3635          * We need the mb() to ensure the ordering between the writing to
3636          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3637          */
3638         mb();
3639
3640         /* enable nig attention */
3641         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3642         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3643                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3644                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3645         } else if (!CHIP_IS_E1x(sc)) {
3646                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3647                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3648         }
3649
3650         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3651 }
3652
3653 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3654 {
3655         char last_idx;
3656         int i, rc = 0;
3657         __rte_unused uint32_t row0, row1, row2, row3;
3658
3659         /* XSTORM */
3660         last_idx =
3661             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3662         if (last_idx)
3663                 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3664
3665         /* print the asserts */
3666         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3667
3668                 row0 =
3669                     REG_RD(sc,
3670                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3671                 row1 =
3672                     REG_RD(sc,
3673                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3674                            4);
3675                 row2 =
3676                     REG_RD(sc,
3677                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3678                            8);
3679                 row3 =
3680                     REG_RD(sc,
3681                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3682                            12);
3683
3684                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3685                         PMD_DRV_LOG(ERR,
3686                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3687                                     i, row3, row2, row1, row0);
3688                         rc++;
3689                 } else {
3690                         break;
3691                 }
3692         }
3693
3694         /* TSTORM */
3695         last_idx =
3696             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3697         if (last_idx) {
3698                 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3699         }
3700
3701         /* print the asserts */
3702         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3703
3704                 row0 =
3705                     REG_RD(sc,
3706                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3707                 row1 =
3708                     REG_RD(sc,
3709                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3710                            4);
3711                 row2 =
3712                     REG_RD(sc,
3713                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3714                            8);
3715                 row3 =
3716                     REG_RD(sc,
3717                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3718                            12);
3719
3720                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3721                         PMD_DRV_LOG(ERR,
3722                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3723                                     i, row3, row2, row1, row0);
3724                         rc++;
3725                 } else {
3726                         break;
3727                 }
3728         }
3729
3730         /* CSTORM */
3731         last_idx =
3732             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3733         if (last_idx) {
3734                 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3735         }
3736
3737         /* print the asserts */
3738         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3739
3740                 row0 =
3741                     REG_RD(sc,
3742                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3743                 row1 =
3744                     REG_RD(sc,
3745                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3746                            4);
3747                 row2 =
3748                     REG_RD(sc,
3749                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3750                            8);
3751                 row3 =
3752                     REG_RD(sc,
3753                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3754                            12);
3755
3756                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3757                         PMD_DRV_LOG(ERR,
3758                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3759                                     i, row3, row2, row1, row0);
3760                         rc++;
3761                 } else {
3762                         break;
3763                 }
3764         }
3765
3766         /* USTORM */
3767         last_idx =
3768             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3769         if (last_idx) {
3770                 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3771         }
3772
3773         /* print the asserts */
3774         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3775
3776                 row0 =
3777                     REG_RD(sc,
3778                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3779                 row1 =
3780                     REG_RD(sc,
3781                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3782                            4);
3783                 row2 =
3784                     REG_RD(sc,
3785                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3786                            8);
3787                 row3 =
3788                     REG_RD(sc,
3789                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3790                            12);
3791
3792                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3793                         PMD_DRV_LOG(ERR,
3794                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3795                                     i, row3, row2, row1, row0);
3796                         rc++;
3797                 } else {
3798                         break;
3799                 }
3800         }
3801
3802         return rc;
3803 }
3804
3805 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3806 {
3807         int func = SC_FUNC(sc);
3808         uint32_t val;
3809
3810         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3811
3812                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3813
3814                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3815                         bnx2x_read_mf_cfg(sc);
3816                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3817                             MFCFG_RD(sc,
3818                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3819                         val =
3820                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3821
3822                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3823                                 bnx2x_dcc_event(sc,
3824                                               (val &
3825                                                DRV_STATUS_DCC_EVENT_MASK));
3826
3827                         if (val & DRV_STATUS_SET_MF_BW)
3828                                 bnx2x_set_mf_bw(sc);
3829
3830                         if (val & DRV_STATUS_DRV_INFO_REQ)
3831                                 bnx2x_handle_drv_info_req(sc);
3832
3833                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3834                                 bnx2x_pmf_update(sc);
3835
3836                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3837                                 bnx2x_handle_eee_event(sc);
3838
3839                         if (sc->link_vars.periodic_flags &
3840                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3841                                 /* sync with link */
3842                                 sc->link_vars.periodic_flags &=
3843                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3844                                 if (IS_MF(sc)) {
3845                                         bnx2x_link_sync_notify(sc);
3846                                 }
3847                                 bnx2x_link_report(sc);
3848                         }
3849
3850                         /*
3851                          * Always call it here: bnx2x_link_report() will
3852                          * prevent the link indication duplication.
3853                          */
3854                         bnx2x_link_status_update(sc);
3855
3856                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3857
3858                         PMD_DRV_LOG(ERR, "MC assert!");
3859                         bnx2x_mc_assert(sc);
3860                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3861                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3862                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3863                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3864                         rte_panic("MC assert!");
3865
3866                 } else if (attn & BNX2X_MCP_ASSERT) {
3867
3868                         PMD_DRV_LOG(ERR, "MCP assert!");
3869                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3870
3871                 } else {
3872                         PMD_DRV_LOG(ERR,
3873                                     "Unknown HW assert! (attn 0x%08x)", attn);
3874                 }
3875         }
3876
3877         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3878                 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3879                 if (attn & BNX2X_GRC_TIMEOUT) {
3880                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3881                         PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3882                 }
3883                 if (attn & BNX2X_GRC_RSV) {
3884                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3885                         PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3886                 }
3887                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3888         }
3889 }
3890
3891 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3892 {
3893         int port = SC_PORT(sc);
3894         int reg_offset;
3895         uint32_t val0, mask0, val1, mask1;
3896         uint32_t val;
3897
3898         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3899                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3900                 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3901 /* CFC error attention */
3902                 if (val & 0x2) {
3903                         PMD_DRV_LOG(ERR, "FATAL error from CFC");
3904                 }
3905         }
3906
3907         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3908                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3909                 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3910 /* RQ_USDMDP_FIFO_OVERFLOW */
3911                 if (val & 0x18000) {
3912                         PMD_DRV_LOG(ERR, "FATAL error from PXP");
3913                 }
3914
3915                 if (!CHIP_IS_E1x(sc)) {
3916                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3917                         PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3918                 }
3919         }
3920 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3921 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3922
3923         if (attn & AEU_PXP2_HW_INT_BIT) {
3924 /*  CQ47854 workaround do not panic on
3925  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3926  */
3927                 if (!CHIP_IS_E1x(sc)) {
3928                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3929                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3930                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3931                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3932                         /*
3933                          * If the olny PXP2_EOP_ERROR_BIT is set in
3934                          * STS0 and STS1 - clear it
3935                          *
3936                          * probably we lose additional attentions between
3937                          * STS0 and STS_CLR0, in this case user will not
3938                          * be notified about them
3939                          */
3940                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3941                             !(val1 & mask1))
3942                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3943
3944                         /* print the register, since no one can restore it */
3945                         PMD_DRV_LOG(ERR,
3946                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3947
3948                         /*
3949                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3950                          * then notify
3951                          */
3952                         if (val0 & PXP2_EOP_ERROR_BIT) {
3953                                 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3954
3955                                 /*
3956                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3957                                  * set then clear attention from PXP2 block without panic
3958                                  */
3959                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3960                                     ((val1 & mask1) == 0))
3961                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3962                         }
3963                 }
3964         }
3965
3966         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3967                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3968                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3969
3970                 val = REG_RD(sc, reg_offset);
3971                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3972                 REG_WR(sc, reg_offset, val);
3973
3974                 PMD_DRV_LOG(ERR,
3975                             "FATAL HW block attention set2 0x%x",
3976                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3977                 rte_panic("HW block attention set2");
3978         }
3979 }
3980
3981 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3982 {
3983         int port = SC_PORT(sc);
3984         int reg_offset;
3985         uint32_t val;
3986
3987         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3988                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3989                 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3990 /* DORQ discard attention */
3991                 if (val & 0x2) {
3992                         PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3993                 }
3994         }
3995
3996         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3997                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3998                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3999
4000                 val = REG_RD(sc, reg_offset);
4001                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4002                 REG_WR(sc, reg_offset, val);
4003
4004                 PMD_DRV_LOG(ERR,
4005                             "FATAL HW block attention set1 0x%08x",
4006                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4007                 rte_panic("HW block attention set1");
4008         }
4009 }
4010
4011 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4012 {
4013         int port = SC_PORT(sc);
4014         int reg_offset;
4015         uint32_t val;
4016
4017         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4018             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4019
4020         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4021                 val = REG_RD(sc, reg_offset);
4022                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4023                 REG_WR(sc, reg_offset, val);
4024
4025                 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4026
4027 /* Fan failure attention */
4028                 elink_hw_reset_phy(&sc->link_params);
4029                 bnx2x_fan_failure(sc);
4030         }
4031
4032         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4033                 elink_handle_module_detect_int(&sc->link_params);
4034         }
4035
4036         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4037                 val = REG_RD(sc, reg_offset);
4038                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4039                 REG_WR(sc, reg_offset, val);
4040
4041                 rte_panic("FATAL HW block attention set0 0x%lx",
4042                           (attn & HW_INTERRUT_ASSERT_SET_0));
4043         }
4044 }
4045
4046 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4047 {
4048         struct attn_route attn;
4049         struct attn_route *group_mask;
4050         int port = SC_PORT(sc);
4051         int index;
4052         uint32_t reg_addr;
4053         uint32_t val;
4054         uint32_t aeu_mask;
4055         uint8_t global = FALSE;
4056
4057         /*
4058          * Need to take HW lock because MCP or other port might also
4059          * try to handle this event.
4060          */
4061         bnx2x_acquire_alr(sc);
4062
4063         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4064                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4065
4066 /* disable HW interrupts */
4067                 bnx2x_int_disable(sc);
4068                 bnx2x_release_alr(sc);
4069                 return;
4070         }
4071
4072         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4073         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4074         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4075         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4076         if (!CHIP_IS_E1x(sc)) {
4077                 attn.sig[4] =
4078                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4079         } else {
4080                 attn.sig[4] = 0;
4081         }
4082
4083         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4084                 if (deasserted & (1 << index)) {
4085                         group_mask = &sc->attn_group[index];
4086
4087                         bnx2x_attn_int_deasserted4(sc,
4088                                                  attn.
4089                                                  sig[4] & group_mask->sig[4]);
4090                         bnx2x_attn_int_deasserted3(sc,
4091                                                  attn.
4092                                                  sig[3] & group_mask->sig[3]);
4093                         bnx2x_attn_int_deasserted1(sc,
4094                                                  attn.
4095                                                  sig[1] & group_mask->sig[1]);
4096                         bnx2x_attn_int_deasserted2(sc,
4097                                                  attn.
4098                                                  sig[2] & group_mask->sig[2]);
4099                         bnx2x_attn_int_deasserted0(sc,
4100                                                  attn.
4101                                                  sig[0] & group_mask->sig[0]);
4102                 }
4103         }
4104
4105         bnx2x_release_alr(sc);
4106
4107         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4108                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4109                             COMMAND_REG_ATTN_BITS_CLR);
4110         } else {
4111                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4112         }
4113
4114         val = ~deasserted;
4115         PMD_DRV_LOG(DEBUG,
4116                     "about to mask 0x%08x at %s addr 0x%08x", val,
4117                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4118                     reg_addr);
4119         REG_WR(sc, reg_addr, val);
4120
4121         if (~sc->attn_state & deasserted) {
4122                 PMD_DRV_LOG(ERR, "IGU error");
4123         }
4124
4125         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4126             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4127
4128         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4129
4130         aeu_mask = REG_RD(sc, reg_addr);
4131
4132         aeu_mask |= (deasserted & 0x3ff);
4133
4134         REG_WR(sc, reg_addr, aeu_mask);
4135         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4136
4137         sc->attn_state &= ~deasserted;
4138 }
4139
4140 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4141 {
4142         /* read local copy of bits */
4143         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4144         uint32_t attn_ack =
4145             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4146         uint32_t attn_state = sc->attn_state;
4147
4148         /* look for changed bits */
4149         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4150         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4151
4152         PMD_DRV_LOG(DEBUG,
4153                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4154                     attn_bits, attn_ack, asserted, deasserted);
4155
4156         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4157                 PMD_DRV_LOG(ERR, "BAD attention state");
4158         }
4159
4160         /* handle bits that were raised */
4161         if (asserted) {
4162                 bnx2x_attn_int_asserted(sc, asserted);
4163         }
4164
4165         if (deasserted) {
4166                 bnx2x_attn_int_deasserted(sc, deasserted);
4167         }
4168 }
4169
4170 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4171 {
4172         struct host_sp_status_block *def_sb = sc->def_sb;
4173         uint16_t rc = 0;
4174
4175         mb();                   /* status block is written to by the chip */
4176
4177         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4178                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4179                 rc |= BNX2X_DEF_SB_ATT_IDX;
4180         }
4181
4182         if (sc->def_idx != def_sb->sp_sb.running_index) {
4183                 sc->def_idx = def_sb->sp_sb.running_index;
4184                 rc |= BNX2X_DEF_SB_IDX;
4185         }
4186
4187         mb();
4188
4189         return rc;
4190 }
4191
4192 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4193                                                           uint32_t cid)
4194 {
4195         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4196 }
4197
4198 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4199 {
4200         struct ecore_mcast_ramrod_params rparam;
4201         int rc;
4202
4203         memset(&rparam, 0, sizeof(rparam));
4204
4205         rparam.mcast_obj = &sc->mcast_obj;
4206
4207         /* clear pending state for the last command */
4208         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4209
4210         /* if there are pending mcast commands - send them */
4211         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4212                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4213                 if (rc < 0) {
4214                         PMD_DRV_LOG(INFO,
4215                                     "Failed to send pending mcast commands (%d)",
4216                                     rc);
4217                 }
4218         }
4219 }
4220
4221 static void
4222 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4223 {
4224         unsigned long ramrod_flags = 0;
4225         int rc = 0;
4226         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4227         struct ecore_vlan_mac_obj *vlan_mac_obj;
4228
4229         /* always push next commands out, don't wait here */
4230         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4231
4232         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4233         case ECORE_FILTER_MAC_PENDING:
4234                 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4235                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4236                 break;
4237
4238         case ECORE_FILTER_MCAST_PENDING:
4239                 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4240                 bnx2x_handle_mcast_eqe(sc);
4241                 return;
4242
4243         default:
4244                 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4245                             elem->message.data.eth_event.echo);
4246                 return;
4247         }
4248
4249         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4250
4251         if (rc < 0) {
4252                 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4253         } else if (rc > 0) {
4254                 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4255         }
4256 }
4257
4258 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4259 {
4260         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4261
4262         /* send rx_mode command again if was requested */
4263         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4264                 bnx2x_set_storm_rx_mode(sc);
4265         }
4266 }
4267
4268 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4269 {
4270         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4271         wmb();                  /* keep prod updates ordered */
4272 }
4273
4274 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4275 {
4276         uint16_t hw_cons, sw_cons, sw_prod;
4277         union event_ring_elem *elem;
4278         uint8_t echo;
4279         uint32_t cid;
4280         uint8_t opcode;
4281         int spqe_cnt = 0;
4282         struct ecore_queue_sp_obj *q_obj;
4283         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4284         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4285
4286         hw_cons = le16toh(*sc->eq_cons_sb);
4287
4288         /*
4289          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4290          * when we get to the next-page we need to adjust so the loop
4291          * condition below will be met. The next element is the size of a
4292          * regular element and hence incrementing by 1
4293          */
4294         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4295                 hw_cons++;
4296         }
4297
4298         /*
4299          * This function may never run in parallel with itself for a
4300          * specific sc and no need for a read memory barrier here.
4301          */
4302         sw_cons = sc->eq_cons;
4303         sw_prod = sc->eq_prod;
4304
4305         for (;
4306              sw_cons != hw_cons;
4307              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4308
4309                 elem = &sc->eq[EQ_DESC(sw_cons)];
4310
4311 /* elem CID originates from FW, actually LE */
4312                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4313                 opcode = elem->message.opcode;
4314
4315 /* handle eq element */
4316                 switch (opcode) {
4317                 case EVENT_RING_OPCODE_STAT_QUERY:
4318                         PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4319                                     sc->stats_comp++);
4320                         /* nothing to do with stats comp */
4321                         goto next_spqe;
4322
4323                 case EVENT_RING_OPCODE_CFC_DEL:
4324                         /* handle according to cid range */
4325                         /* we may want to verify here that the sc state is HALTING */
4326                         PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4327                                     cid);
4328                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4329                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4330                                 break;
4331                         }
4332                         goto next_spqe;
4333
4334                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4335                         PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4336                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4337                                 break;
4338                         }
4339                         goto next_spqe;
4340
4341                 case EVENT_RING_OPCODE_START_TRAFFIC:
4342                         PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4343                         if (f_obj->complete_cmd
4344                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4345                                 break;
4346                         }
4347                         goto next_spqe;
4348
4349                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4350                         echo = elem->message.data.function_update_event.echo;
4351                         if (echo == SWITCH_UPDATE) {
4352                                 PMD_DRV_LOG(DEBUG,
4353                                             "got FUNC_SWITCH_UPDATE ramrod");
4354                                 if (f_obj->complete_cmd(sc, f_obj,
4355                                                         ECORE_F_CMD_SWITCH_UPDATE))
4356                                 {
4357                                         break;
4358                                 }
4359                         } else {
4360                                 PMD_DRV_LOG(DEBUG,
4361                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4362                                 f_obj->complete_cmd(sc, f_obj,
4363                                                     ECORE_F_CMD_AFEX_UPDATE);
4364                         }
4365                         goto next_spqe;
4366
4367                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4368                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4369                         if (q_obj->complete_cmd(sc, q_obj,
4370                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4371                                 break;
4372                         }
4373                         goto next_spqe;
4374
4375                 case EVENT_RING_OPCODE_FUNCTION_START:
4376                         PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4377                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4378                                 break;
4379                         }
4380                         goto next_spqe;
4381
4382                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4383                         PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4384                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4385                                 break;
4386                         }
4387                         goto next_spqe;
4388                 }
4389
4390                 switch (opcode | sc->state) {
4391                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4392                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4393                         cid =
4394                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4395                         PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4396                                     cid);
4397                         rss_raw->clear_pending(rss_raw);
4398                         break;
4399
4400                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4401                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4402                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4403                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4404                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4405                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4406                         PMD_DRV_LOG(DEBUG,
4407                                     "got (un)set mac ramrod");
4408                         bnx2x_handle_classification_eqe(sc, elem);
4409                         break;
4410
4411                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4412                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4413                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4414                         PMD_DRV_LOG(DEBUG,
4415                                     "got mcast ramrod");
4416                         bnx2x_handle_mcast_eqe(sc);
4417                         break;
4418
4419                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4420                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4421                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4422                         PMD_DRV_LOG(DEBUG,
4423                                     "got rx_mode ramrod");
4424                         bnx2x_handle_rx_mode_eqe(sc);
4425                         break;
4426
4427                 default:
4428                         /* unknown event log error and continue */
4429                         PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4430                                     elem->message.opcode, sc->state);
4431                 }
4432
4433 next_spqe:
4434                 spqe_cnt++;
4435         }                       /* for */
4436
4437         mb();
4438         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4439
4440         sc->eq_cons = sw_cons;
4441         sc->eq_prod = sw_prod;
4442
4443         /* make sure that above mem writes were issued towards the memory */
4444         wmb();
4445
4446         /* update producer */
4447         bnx2x_update_eq_prod(sc, sc->eq_prod);
4448 }
4449
4450 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4451 {
4452         uint16_t status;
4453         int rc = 0;
4454
4455         /* what work needs to be performed? */
4456         status = bnx2x_update_dsb_idx(sc);
4457
4458         /* HW attentions */
4459         if (status & BNX2X_DEF_SB_ATT_IDX) {
4460                 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4461                 bnx2x_attn_int(sc);
4462                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4463                 rc = 1;
4464         }
4465
4466         /* SP events: STAT_QUERY and others */
4467         if (status & BNX2X_DEF_SB_IDX) {
4468 /* handle EQ completions */
4469                 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4470                 bnx2x_eq_int(sc);
4471                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4472                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4473                 status &= ~BNX2X_DEF_SB_IDX;
4474         }
4475
4476         /* if status is non zero then something went wrong */
4477         if (unlikely(status)) {
4478                 PMD_DRV_LOG(INFO,
4479                             "Got an unknown SP interrupt! (0x%04x)", status);
4480         }
4481
4482         /* ack status block only if something was actually handled */
4483         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4484                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4485
4486         return rc;
4487 }
4488
4489 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4490 {
4491         struct bnx2x_softc *sc = fp->sc;
4492         uint8_t more_rx = FALSE;
4493
4494         /* update the fastpath index */
4495         bnx2x_update_fp_sb_idx(fp);
4496
4497         if (scan_fp) {
4498                 if (bnx2x_has_rx_work(fp)) {
4499                         more_rx = bnx2x_rxeof(sc, fp);
4500                 }
4501
4502                 if (more_rx) {
4503                         /* still more work to do */
4504                         bnx2x_handle_fp_tq(fp, scan_fp);
4505                         return;
4506                 }
4507         }
4508
4509         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4510                    le16toh(fp->fp_hc_idx), IGU_INT_DISABLE, 1);
4511 }
4512
4513 /*
4514  * Legacy interrupt entry point.
4515  *
4516  * Verifies that the controller generated the interrupt and
4517  * then calls a separate routine to handle the various
4518  * interrupt causes: link, RX, and TX.
4519  */
4520 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4521 {
4522         struct bnx2x_fastpath *fp;
4523         uint32_t status, mask;
4524         int i, rc = 0;
4525
4526         /*
4527          * 0 for ustorm, 1 for cstorm
4528          * the bits returned from ack_int() are 0-15
4529          * bit 0 = attention status block
4530          * bit 1 = fast path status block
4531          * a mask of 0x2 or more = tx/rx event
4532          * a mask of 1 = slow path event
4533          */
4534
4535         status = bnx2x_ack_int(sc);
4536
4537         /* the interrupt is not for us */
4538         if (unlikely(status == 0)) {
4539                 return 0;
4540         }
4541
4542         PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4543         //bnx2x_dump_status_block(sc);
4544
4545         FOR_EACH_ETH_QUEUE(sc, i) {
4546                 fp = &sc->fp[i];
4547                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4548                 if (status & mask) {
4549                         bnx2x_handle_fp_tq(fp, scan_fp);
4550                         status &= ~mask;
4551                 }
4552         }
4553
4554         if (unlikely(status & 0x1)) {
4555                 rc = bnx2x_handle_sp_tq(sc);
4556                 status &= ~0x1;
4557         }
4558
4559         if (unlikely(status)) {
4560                 PMD_DRV_LOG(WARNING,
4561                             "Unexpected fastpath status (0x%08x)!", status);
4562         }
4563
4564         return rc;
4565 }
4566
4567 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4568 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4569 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4570 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4571 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4572 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4573 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4574 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4575 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4576
4577 static struct
4578 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4579         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4580         .init_hw_cmn = bnx2x_init_hw_common,
4581         .init_hw_port = bnx2x_init_hw_port,
4582         .init_hw_func = bnx2x_init_hw_func,
4583
4584         .reset_hw_cmn = bnx2x_reset_common,
4585         .reset_hw_port = bnx2x_reset_port,
4586         .reset_hw_func = bnx2x_reset_func,
4587
4588         .init_fw = bnx2x_init_firmware,
4589         .release_fw = bnx2x_release_firmware,
4590 };
4591
4592 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4593 {
4594         sc->dmae_ready = 0;
4595
4596         PMD_INIT_FUNC_TRACE();
4597
4598         ecore_init_func_obj(sc,
4599                             &sc->func_obj,
4600                             BNX2X_SP(sc, func_rdata),
4601                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4602                             BNX2X_SP(sc, func_afex_rdata),
4603                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4604                             &bnx2x_func_sp_drv);
4605 }
4606
4607 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4608 {
4609         struct ecore_func_state_params func_params = { NULL };
4610         int rc;
4611
4612         PMD_INIT_FUNC_TRACE();
4613
4614         /* prepare the parameters for function state transitions */
4615         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4616
4617         func_params.f_obj = &sc->func_obj;
4618         func_params.cmd = ECORE_F_CMD_HW_INIT;
4619
4620         func_params.params.hw_init.load_phase = load_code;
4621
4622         /*
4623          * Via a plethora of function pointers, we will eventually reach
4624          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4625          */
4626         rc = ecore_func_state_change(sc, &func_params);
4627
4628         return rc;
4629 }
4630
4631 static void
4632 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4633 {
4634         uint32_t i;
4635
4636         if (!(len % 4) && !(addr % 4)) {
4637                 for (i = 0; i < len; i += 4) {
4638                         REG_WR(sc, (addr + i), fill);
4639                 }
4640         } else {
4641                 for (i = 0; i < len; i++) {
4642                         REG_WR8(sc, (addr + i), fill);
4643                 }
4644         }
4645 }
4646
4647 /* writes FP SP data to FW - data_size in dwords */
4648 static void
4649 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4650                   uint32_t data_size)
4651 {
4652         uint32_t index;
4653
4654         for (index = 0; index < data_size; index++) {
4655                 REG_WR(sc,
4656                        (BAR_CSTRORM_INTMEM +
4657                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4658                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4659         }
4660 }
4661
4662 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4663 {
4664         struct hc_status_block_data_e2 sb_data_e2;
4665         struct hc_status_block_data_e1x sb_data_e1x;
4666         uint32_t *sb_data_p;
4667         uint32_t data_size = 0;
4668
4669         if (!CHIP_IS_E1x(sc)) {
4670                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4671                 sb_data_e2.common.state = SB_DISABLED;
4672                 sb_data_e2.common.p_func.vf_valid = FALSE;
4673                 sb_data_p = (uint32_t *) & sb_data_e2;
4674                 data_size = (sizeof(struct hc_status_block_data_e2) /
4675                              sizeof(uint32_t));
4676         } else {
4677                 memset(&sb_data_e1x, 0,
4678                        sizeof(struct hc_status_block_data_e1x));
4679                 sb_data_e1x.common.state = SB_DISABLED;
4680                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4681                 sb_data_p = (uint32_t *) & sb_data_e1x;
4682                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4683                              sizeof(uint32_t));
4684         }
4685
4686         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4687
4688         bnx2x_fill(sc,
4689                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4690                  CSTORM_STATUS_BLOCK_SIZE);
4691         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4692                  0, CSTORM_SYNC_BLOCK_SIZE);
4693 }
4694
4695 static void
4696 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4697                   struct hc_sp_status_block_data *sp_sb_data)
4698 {
4699         uint32_t i;
4700
4701         for (i = 0;
4702              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4703              i++) {
4704                 REG_WR(sc,
4705                        (BAR_CSTRORM_INTMEM +
4706                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4707                         (i * sizeof(uint32_t))),
4708                        *((uint32_t *) sp_sb_data + i));
4709         }
4710 }
4711
4712 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4713 {
4714         struct hc_sp_status_block_data sp_sb_data;
4715
4716         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4717
4718         sp_sb_data.state = SB_DISABLED;
4719         sp_sb_data.p_func.vf_valid = FALSE;
4720
4721         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4722
4723         bnx2x_fill(sc,
4724                  (BAR_CSTRORM_INTMEM +
4725                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4726                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4727         bnx2x_fill(sc,
4728                  (BAR_CSTRORM_INTMEM +
4729                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4730                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4731 }
4732
4733 static void
4734 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4735                              int igu_seg_id)
4736 {
4737         hc_sm->igu_sb_id = igu_sb_id;
4738         hc_sm->igu_seg_id = igu_seg_id;
4739         hc_sm->timer_value = 0xFF;
4740         hc_sm->time_to_expire = 0xFFFFFFFF;
4741 }
4742
4743 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4744 {
4745         /* zero out state machine indices */
4746
4747         /* rx indices */
4748         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4749
4750         /* tx indices */
4751         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4752         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4753         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4754         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4755
4756         /* map indices */
4757
4758         /* rx indices */
4759         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4760             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4761
4762         /* tx indices */
4763         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4764             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4765         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4766             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4767         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4768             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4769         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4770             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4771 }
4772
4773 static void
4774 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4775             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4776 {
4777         struct hc_status_block_data_e2 sb_data_e2;
4778         struct hc_status_block_data_e1x sb_data_e1x;
4779         struct hc_status_block_sm *hc_sm_p;
4780         uint32_t *sb_data_p;
4781         int igu_seg_id;
4782         int data_size;
4783
4784         if (CHIP_INT_MODE_IS_BC(sc)) {
4785                 igu_seg_id = HC_SEG_ACCESS_NORM;
4786         } else {
4787                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4788         }
4789
4790         bnx2x_zero_fp_sb(sc, fw_sb_id);
4791
4792         if (!CHIP_IS_E1x(sc)) {
4793                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4794                 sb_data_e2.common.state = SB_ENABLED;
4795                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4796                 sb_data_e2.common.p_func.vf_id = vfid;
4797                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4798                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4799                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4800                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4801                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4802                 hc_sm_p = sb_data_e2.common.state_machine;
4803                 sb_data_p = (uint32_t *) & sb_data_e2;
4804                 data_size = (sizeof(struct hc_status_block_data_e2) /
4805                              sizeof(uint32_t));
4806                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4807         } else {
4808                 memset(&sb_data_e1x, 0,
4809                        sizeof(struct hc_status_block_data_e1x));
4810                 sb_data_e1x.common.state = SB_ENABLED;
4811                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4812                 sb_data_e1x.common.p_func.vf_id = 0xff;
4813                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4814                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4815                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4816                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4817                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4818                 hc_sm_p = sb_data_e1x.common.state_machine;
4819                 sb_data_p = (uint32_t *) & sb_data_e1x;
4820                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4821                              sizeof(uint32_t));
4822                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4823         }
4824
4825         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4826         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4827
4828         /* write indices to HW - PCI guarantees endianity of regpairs */
4829         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4830 }
4831
4832 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4833 {
4834         if (CHIP_IS_E1x(fp->sc)) {
4835                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4836         } else {
4837                 return fp->cl_id;
4838         }
4839 }
4840
4841 static uint32_t
4842 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4843 {
4844         uint32_t offset = BAR_USTRORM_INTMEM;
4845
4846         if (IS_VF(sc)) {
4847                 return PXP_VF_ADDR_USDM_QUEUES_START +
4848                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4849                          sizeof(struct ustorm_queue_zone_data));
4850         } else if (!CHIP_IS_E1x(sc)) {
4851                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4852         } else {
4853                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4854         }
4855
4856         return offset;
4857 }
4858
4859 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4860 {
4861         struct bnx2x_fastpath *fp = &sc->fp[idx];
4862         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4863         unsigned long q_type = 0;
4864         int cos;
4865
4866         fp->sc = sc;
4867         fp->index = idx;
4868
4869         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4870         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4871
4872         if (CHIP_IS_E1x(sc))
4873                 fp->cl_id = SC_L_ID(sc) + idx;
4874         else
4875 /* want client ID same as IGU SB ID for non-E1 */
4876                 fp->cl_id = fp->igu_sb_id;
4877         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4878
4879         /* setup sb indices */
4880         if (!CHIP_IS_E1x(sc)) {
4881                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4882                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4883         } else {
4884                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4885                 fp->sb_running_index =
4886                     fp->status_block.e1x_sb->sb.running_index;
4887         }
4888
4889         /* init shortcut */
4890         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4891
4892         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4893
4894         for (cos = 0; cos < sc->max_cos; cos++) {
4895                 cids[cos] = idx;
4896         }
4897         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4898
4899         /* nothing more for a VF to do */
4900         if (IS_VF(sc)) {
4901                 return;
4902         }
4903
4904         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4905                     fp->fw_sb_id, fp->igu_sb_id);
4906
4907         bnx2x_update_fp_sb_idx(fp);
4908
4909         /* Configure Queue State object */
4910         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4911         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4912
4913         ecore_init_queue_obj(sc,
4914                              &sc->sp_objs[idx].q_obj,
4915                              fp->cl_id,
4916                              cids,
4917                              sc->max_cos,
4918                              SC_FUNC(sc),
4919                              BNX2X_SP(sc, q_rdata),
4920                              (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4921                              q_type);
4922
4923         /* configure classification DBs */
4924         ecore_init_mac_obj(sc,
4925                            &sc->sp_objs[idx].mac_obj,
4926                            fp->cl_id,
4927                            idx,
4928                            SC_FUNC(sc),
4929                            BNX2X_SP(sc, mac_rdata),
4930                            (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4931                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4932                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4933 }
4934
4935 static void
4936 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4937                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4938 {
4939         union ustorm_eth_rx_producers rx_prods;
4940         uint32_t i;
4941
4942         /* update producers */
4943         rx_prods.prod.bd_prod = rx_bd_prod;
4944         rx_prods.prod.cqe_prod = rx_cq_prod;
4945         rx_prods.prod.reserved = 0;
4946
4947         /*
4948          * Make sure that the BD and SGE data is updated before updating the
4949          * producers since FW might read the BD/SGE right after the producer
4950          * is updated.
4951          * This is only applicable for weak-ordered memory model archs such
4952          * as IA-64. The following barrier is also mandatory since FW will
4953          * assumes BDs must have buffers.
4954          */
4955         wmb();
4956
4957         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4958                 REG_WR(sc,
4959                        (fp->ustorm_rx_prods_offset + (i * 4)),
4960                        rx_prods.raw_data[i]);
4961         }
4962
4963         wmb();                  /* keep prod updates ordered */
4964 }
4965
4966 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4967 {
4968         struct bnx2x_fastpath *fp;
4969         int i;
4970         struct bnx2x_rx_queue *rxq;
4971
4972         for (i = 0; i < sc->num_queues; i++) {
4973                 fp = &sc->fp[i];
4974                 rxq = sc->rx_queues[fp->index];
4975                 if (!rxq) {
4976                         PMD_RX_LOG(ERR, "RX queue is NULL");
4977                         return;
4978                 }
4979
4980                 rxq->rx_bd_head = 0;
4981                 rxq->rx_bd_tail = rxq->nb_rx_desc;
4982                 rxq->rx_cq_head = 0;
4983                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4984                 *fp->rx_cq_cons_sb = 0;
4985
4986                 /*
4987                  * Activate the BD ring...
4988                  * Warning, this will generate an interrupt (to the TSTORM)
4989                  * so this can only be done after the chip is initialized
4990                  */
4991                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4992
4993                 if (i != 0) {
4994                         continue;
4995                 }
4996         }
4997 }
4998
4999 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5000 {
5001         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5002
5003         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5004         fp->tx_db.data.zero_fill1 = 0;
5005         fp->tx_db.data.prod = 0;
5006
5007         if (!txq) {
5008                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5009                 return;
5010         }
5011
5012         txq->tx_pkt_tail = 0;
5013         txq->tx_pkt_head = 0;
5014         txq->tx_bd_tail = 0;
5015         txq->tx_bd_head = 0;
5016 }
5017
5018 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5019 {
5020         int i;
5021
5022         for (i = 0; i < sc->num_queues; i++) {
5023                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5024         }
5025 }
5026
5027 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5028 {
5029         struct host_sp_status_block *def_sb = sc->def_sb;
5030         phys_addr_t mapping = sc->def_sb_dma.paddr;
5031         int igu_sp_sb_index;
5032         int igu_seg_id;
5033         int port = SC_PORT(sc);
5034         int func = SC_FUNC(sc);
5035         int reg_offset, reg_offset_en5;
5036         uint64_t section;
5037         int index, sindex;
5038         struct hc_sp_status_block_data sp_sb_data;
5039
5040         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5041
5042         if (CHIP_INT_MODE_IS_BC(sc)) {
5043                 igu_sp_sb_index = DEF_SB_IGU_ID;
5044                 igu_seg_id = HC_SEG_ACCESS_DEF;
5045         } else {
5046                 igu_sp_sb_index = sc->igu_dsb_id;
5047                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5048         }
5049
5050         /* attentions */
5051         section = ((uint64_t) mapping +
5052                    offsetof(struct host_sp_status_block, atten_status_block));
5053         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5054         sc->attn_state = 0;
5055
5056         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5057             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5058
5059         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5060             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5061
5062         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5063 /* take care of sig[0]..sig[4] */
5064                 for (sindex = 0; sindex < 4; sindex++) {
5065                         sc->attn_group[index].sig[sindex] =
5066                             REG_RD(sc,
5067                                    (reg_offset + (sindex * 0x4) +
5068                                     (0x10 * index)));
5069                 }
5070
5071                 if (!CHIP_IS_E1x(sc)) {
5072                         /*
5073                          * enable5 is separate from the rest of the registers,
5074                          * and the address skip is 4 and not 16 between the
5075                          * different groups
5076                          */
5077                         sc->attn_group[index].sig[4] =
5078                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5079                 } else {
5080                         sc->attn_group[index].sig[4] = 0;
5081                 }
5082         }
5083
5084         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5085                 reg_offset =
5086                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5087                 REG_WR(sc, reg_offset, U64_LO(section));
5088                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5089         } else if (!CHIP_IS_E1x(sc)) {
5090                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5091                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5092         }
5093
5094         section = ((uint64_t) mapping +
5095                    offsetof(struct host_sp_status_block, sp_sb));
5096
5097         bnx2x_zero_sp_sb(sc);
5098
5099         /* PCI guarantees endianity of regpair */
5100         sp_sb_data.state = SB_ENABLED;
5101         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5102         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5103         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5104         sp_sb_data.igu_seg_id = igu_seg_id;
5105         sp_sb_data.p_func.pf_id = func;
5106         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5107         sp_sb_data.p_func.vf_id = 0xff;
5108
5109         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5110
5111         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5112 }
5113
5114 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5115 {
5116         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5117         sc->spq_prod_idx = 0;
5118         sc->dsb_sp_prod =
5119             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5120         sc->spq_prod_bd = sc->spq;
5121         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5122 }
5123
5124 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5125 {
5126         union event_ring_elem *elem;
5127         int i;
5128
5129         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5130                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5131
5132                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5133                                                          BNX2X_PAGE_SIZE *
5134                                                          (i % NUM_EQ_PAGES)));
5135                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5136                                                          BNX2X_PAGE_SIZE *
5137                                                          (i % NUM_EQ_PAGES)));
5138         }
5139
5140         sc->eq_cons = 0;
5141         sc->eq_prod = NUM_EQ_DESC;
5142         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5143
5144         atomic_store_rel_long(&sc->eq_spq_left,
5145                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5146                                    NUM_EQ_DESC) - 1));
5147 }
5148
5149 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5150 {
5151         int i;
5152
5153         if (IS_MF_SI(sc)) {
5154 /*
5155  * In switch independent mode, the TSTORM needs to accept
5156  * packets that failed classification, since approximate match
5157  * mac addresses aren't written to NIG LLH.
5158  */
5159                 REG_WR8(sc,
5160                         (BAR_TSTRORM_INTMEM +
5161                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5162         } else
5163                 REG_WR8(sc,
5164                         (BAR_TSTRORM_INTMEM +
5165                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5166
5167         /*
5168          * Zero this manually as its initialization is currently missing
5169          * in the initTool.
5170          */
5171         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5172                 REG_WR(sc,
5173                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5174                        0);
5175         }
5176
5177         if (!CHIP_IS_E1x(sc)) {
5178                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5179                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5180                         HC_IGU_NBC_MODE);
5181         }
5182 }
5183
5184 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5185 {
5186         switch (load_code) {
5187         case FW_MSG_CODE_DRV_LOAD_COMMON:
5188         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5189                 bnx2x_init_internal_common(sc);
5190                 /* no break */
5191
5192         case FW_MSG_CODE_DRV_LOAD_PORT:
5193                 /* nothing to do */
5194                 /* no break */
5195
5196         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5197                 /* internal memory per function is initialized inside bnx2x_pf_init */
5198                 break;
5199
5200         default:
5201                 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5202                             load_code);
5203                 break;
5204         }
5205 }
5206
5207 static void
5208 storm_memset_func_cfg(struct bnx2x_softc *sc,
5209                       struct tstorm_eth_function_common_config *tcfg,
5210                       uint16_t abs_fid)
5211 {
5212         uint32_t addr;
5213         size_t size;
5214
5215         addr = (BAR_TSTRORM_INTMEM +
5216                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5217         size = sizeof(struct tstorm_eth_function_common_config);
5218         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5219 }
5220
5221 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5222 {
5223         struct tstorm_eth_function_common_config tcfg = { 0 };
5224
5225         if (CHIP_IS_E1x(sc)) {
5226                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5227         }
5228
5229         /* Enable the function in the FW */
5230         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5231         storm_memset_func_en(sc, p->func_id, 1);
5232
5233         /* spq */
5234         if (p->func_flgs & FUNC_FLG_SPQ) {
5235                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5236                 REG_WR(sc,
5237                        (XSEM_REG_FAST_MEMORY +
5238                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5239         }
5240 }
5241
5242 /*
5243  * Calculates the sum of vn_min_rates.
5244  * It's needed for further normalizing of the min_rates.
5245  * Returns:
5246  *   sum of vn_min_rates.
5247  *     or
5248  *   0 - if all the min_rates are 0.
5249  * In the later case fainess algorithm should be deactivated.
5250  * If all min rates are not zero then those that are zeroes will be set to 1.
5251  */
5252 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5253 {
5254         uint32_t vn_cfg;
5255         uint32_t vn_min_rate;
5256         int all_zero = 1;
5257         int vn;
5258
5259         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5260                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5261                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5262                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5263
5264                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5265                         /* skip hidden VNs */
5266                         vn_min_rate = 0;
5267                 } else if (!vn_min_rate) {
5268                         /* If min rate is zero - set it to 100 */
5269                         vn_min_rate = DEF_MIN_RATE;
5270                 } else {
5271                         all_zero = 0;
5272                 }
5273
5274                 input->vnic_min_rate[vn] = vn_min_rate;
5275         }
5276
5277         /* if ETS or all min rates are zeros - disable fairness */
5278         if (all_zero) {
5279                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5280         } else {
5281                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5282         }
5283 }
5284
5285 static uint16_t
5286 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5287 {
5288         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5289                             FUNC_MF_CFG_MAX_BW_SHIFT);
5290
5291         if (!max_cfg) {
5292                 PMD_DRV_LOG(DEBUG,
5293                             "Max BW configured to 0 - using 100 instead");
5294                 max_cfg = 100;
5295         }
5296
5297         return max_cfg;
5298 }
5299
5300 static void
5301 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5302 {
5303         uint16_t vn_max_rate;
5304         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5305         uint32_t max_cfg;
5306
5307         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5308                 vn_max_rate = 0;
5309         } else {
5310                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5311
5312                 if (IS_MF_SI(sc)) {
5313                         /* max_cfg in percents of linkspeed */
5314                         vn_max_rate =
5315                             ((sc->link_vars.line_speed * max_cfg) / 100);
5316                 } else {        /* SD modes */
5317                         /* max_cfg is absolute in 100Mb units */
5318                         vn_max_rate = (max_cfg * 100);
5319                 }
5320         }
5321
5322         input->vnic_max_rate[vn] = vn_max_rate;
5323 }
5324
5325 static void
5326 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5327 {
5328         struct cmng_init_input input;
5329         int vn;
5330
5331         memset(&input, 0, sizeof(struct cmng_init_input));
5332
5333         input.port_rate = sc->link_vars.line_speed;
5334
5335         if (cmng_type == CMNG_FNS_MINMAX) {
5336 /* read mf conf from shmem */
5337                 if (read_cfg) {
5338                         bnx2x_read_mf_cfg(sc);
5339                 }
5340
5341 /* get VN min rate and enable fairness if not 0 */
5342                 bnx2x_calc_vn_min(sc, &input);
5343
5344 /* get VN max rate */
5345                 if (sc->port.pmf) {
5346                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5347                                 bnx2x_calc_vn_max(sc, vn, &input);
5348                         }
5349                 }
5350
5351 /* always enable rate shaping and fairness */
5352                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5353
5354                 ecore_init_cmng(&input, &sc->cmng);
5355                 return;
5356         }
5357 }
5358
5359 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5360 {
5361         if (CHIP_REV_IS_SLOW(sc)) {
5362                 return CMNG_FNS_NONE;
5363         }
5364
5365         if (IS_MF(sc)) {
5366                 return CMNG_FNS_MINMAX;
5367         }
5368
5369         return CMNG_FNS_NONE;
5370 }
5371
5372 static void
5373 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5374 {
5375         int vn;
5376         int func;
5377         uint32_t addr;
5378         size_t size;
5379
5380         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5381         size = sizeof(struct cmng_struct_per_port);
5382         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5383
5384         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5385                 func = func_by_vn(sc, vn);
5386
5387                 addr = (BAR_XSTRORM_INTMEM +
5388                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5389                 size = sizeof(struct rate_shaping_vars_per_vn);
5390                 ecore_storm_memset_struct(sc, addr, size,
5391                                           (uint32_t *) & cmng->
5392                                           vnic.vnic_max_rate[vn]);
5393
5394                 addr = (BAR_XSTRORM_INTMEM +
5395                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5396                 size = sizeof(struct fairness_vars_per_vn);
5397                 ecore_storm_memset_struct(sc, addr, size,
5398                                           (uint32_t *) & cmng->
5399                                           vnic.vnic_min_rate[vn]);
5400         }
5401 }
5402
5403 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5404 {
5405         struct bnx2x_func_init_params func_init;
5406         struct event_ring_data eq_data;
5407         uint16_t flags;
5408
5409         memset(&eq_data, 0, sizeof(struct event_ring_data));
5410         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5411
5412         if (!CHIP_IS_E1x(sc)) {
5413 /* reset IGU PF statistics: MSIX + ATTN */
5414 /* PF */
5415                 REG_WR(sc,
5416                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5417                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5418                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5419                          4)), 0);
5420 /* ATTN */
5421                 REG_WR(sc,
5422                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5423                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5424                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5425                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5426                          4)), 0);
5427         }
5428
5429         /* function setup flags */
5430         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5431
5432         func_init.func_flgs = flags;
5433         func_init.pf_id = SC_FUNC(sc);
5434         func_init.func_id = SC_FUNC(sc);
5435         func_init.spq_map = sc->spq_dma.paddr;
5436         func_init.spq_prod = sc->spq_prod_idx;
5437
5438         bnx2x_func_init(sc, &func_init);
5439
5440         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5441
5442         /*
5443          * Congestion management values depend on the link rate.
5444          * There is no active link so initial link rate is set to 10Gbps.
5445          * When the link comes up the congestion management values are
5446          * re-calculated according to the actual link rate.
5447          */
5448         sc->link_vars.line_speed = SPEED_10000;
5449         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5450
5451         /* Only the PMF sets the HW */
5452         if (sc->port.pmf) {
5453                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5454         }
5455
5456         /* init Event Queue - PCI bus guarantees correct endainity */
5457         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5458         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5459         eq_data.producer = sc->eq_prod;
5460         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5461         eq_data.sb_id = DEF_SB_ID;
5462         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5463 }
5464
5465 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5466 {
5467         int port = SC_PORT(sc);
5468         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5469         uint32_t val = REG_RD(sc, addr);
5470         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5471             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5472         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5473         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5474
5475         if (msix) {
5476                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5477                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5478                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5479                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5480                 if (single_msix) {
5481                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5482                 }
5483         } else if (msi) {
5484                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5485                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5486                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5487                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5488         } else {
5489                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5490                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5491                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5492                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5493
5494                 REG_WR(sc, addr, val);
5495
5496                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5497         }
5498
5499         REG_WR(sc, addr, val);
5500
5501         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5502         mb();
5503
5504         /* init leading/trailing edge */
5505         if (IS_MF(sc)) {
5506                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5507                 if (sc->port.pmf) {
5508                         /* enable nig and gpio3 attention */
5509                         val |= 0x1100;
5510                 }
5511         } else {
5512                 val = 0xffff;
5513         }
5514
5515         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5516         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5517
5518         /* make sure that interrupts are indeed enabled from here on */
5519         mb();
5520 }
5521
5522 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5523 {
5524         uint32_t val;
5525         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5526             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5527         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5528         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5529
5530         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5531
5532         if (msix) {
5533                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5534                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5535                 if (single_msix) {
5536                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5537                 }
5538         } else if (msi) {
5539                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5540                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5541                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5542         } else {
5543                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5544                 val |= (IGU_PF_CONF_INT_LINE_EN |
5545                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5546         }
5547
5548         /* clean previous status - need to configure igu prior to ack */
5549         if ((!msix) || single_msix) {
5550                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5551                 bnx2x_ack_int(sc);
5552         }
5553
5554         val |= IGU_PF_CONF_FUNC_EN;
5555
5556         PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5557                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5558
5559         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5560
5561         mb();
5562
5563         /* init leading/trailing edge */
5564         if (IS_MF(sc)) {
5565                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5566                 if (sc->port.pmf) {
5567                         /* enable nig and gpio3 attention */
5568                         val |= 0x1100;
5569                 }
5570         } else {
5571                 val = 0xffff;
5572         }
5573
5574         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5575         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5576
5577         /* make sure that interrupts are indeed enabled from here on */
5578         mb();
5579 }
5580
5581 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5582 {
5583         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5584                 bnx2x_hc_int_enable(sc);
5585         } else {
5586                 bnx2x_igu_int_enable(sc);
5587         }
5588 }
5589
5590 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5591 {
5592         int port = SC_PORT(sc);
5593         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5594         uint32_t val = REG_RD(sc, addr);
5595
5596         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5597                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5598                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5599         /* flush all outstanding writes */
5600         mb();
5601
5602         REG_WR(sc, addr, val);
5603         if (REG_RD(sc, addr) != val) {
5604                 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5605         }
5606 }
5607
5608 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5609 {
5610         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5611
5612         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5613                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5614
5615         PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5616
5617         /* flush all outstanding writes */
5618         mb();
5619
5620         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5621         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5622                 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5623         }
5624 }
5625
5626 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5627 {
5628         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5629                 bnx2x_hc_int_disable(sc);
5630         } else {
5631                 bnx2x_igu_int_disable(sc);
5632         }
5633 }
5634
5635 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5636 {
5637         int i;
5638
5639         PMD_INIT_FUNC_TRACE();
5640
5641         for (i = 0; i < sc->num_queues; i++) {
5642                 bnx2x_init_eth_fp(sc, i);
5643         }
5644
5645         rmb();                  /* ensure status block indices were read */
5646
5647         bnx2x_init_rx_rings(sc);
5648         bnx2x_init_tx_rings(sc);
5649
5650         if (IS_VF(sc)) {
5651                 bnx2x_memset_stats(sc);
5652                 return;
5653         }
5654
5655         /* initialize MOD_ABS interrupts */
5656         elink_init_mod_abs_int(sc, &sc->link_vars,
5657                                sc->devinfo.chip_id,
5658                                sc->devinfo.shmem_base,
5659                                sc->devinfo.shmem2_base, SC_PORT(sc));
5660
5661         bnx2x_init_def_sb(sc);
5662         bnx2x_update_dsb_idx(sc);
5663         bnx2x_init_sp_ring(sc);
5664         bnx2x_init_eq_ring(sc);
5665         bnx2x_init_internal(sc, load_code);
5666         bnx2x_pf_init(sc);
5667         bnx2x_stats_init(sc);
5668
5669         /* flush all before enabling interrupts */
5670         mb();
5671
5672         bnx2x_int_enable(sc);
5673
5674         /* check for SPIO5 */
5675         bnx2x_attn_int_deasserted0(sc,
5676                                  REG_RD(sc,
5677                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5678                                          SC_PORT(sc) * 4)) &
5679                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5680 }
5681
5682 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5683 {
5684         /* mcast rules must be added to tx if tx switching is enabled */
5685         ecore_obj_type o_type;
5686         if (sc->flags & BNX2X_TX_SWITCHING)
5687                 o_type = ECORE_OBJ_TYPE_RX_TX;
5688         else
5689                 o_type = ECORE_OBJ_TYPE_RX;
5690
5691         /* RX_MODE controlling object */
5692         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5693
5694         /* multicast configuration controlling object */
5695         ecore_init_mcast_obj(sc,
5696                              &sc->mcast_obj,
5697                              sc->fp[0].cl_id,
5698                              sc->fp[0].index,
5699                              SC_FUNC(sc),
5700                              SC_FUNC(sc),
5701                              BNX2X_SP(sc, mcast_rdata),
5702                              (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5703                              ECORE_FILTER_MCAST_PENDING,
5704                              &sc->sp_state, o_type);
5705
5706         /* Setup CAM credit pools */
5707         ecore_init_mac_credit_pool(sc,
5708                                    &sc->macs_pool,
5709                                    SC_FUNC(sc),
5710                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5711                                    VNICS_PER_PATH(sc));
5712
5713         ecore_init_vlan_credit_pool(sc,
5714                                     &sc->vlans_pool,
5715                                     SC_ABS_FUNC(sc) >> 1,
5716                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5717                                     VNICS_PER_PATH(sc));
5718
5719         /* RSS configuration object */
5720         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5721                                   sc->fp[0].cl_id,
5722                                   sc->fp[0].index,
5723                                   SC_FUNC(sc),
5724                                   SC_FUNC(sc),
5725                                   BNX2X_SP(sc, rss_rdata),
5726                                   (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5727                                   ECORE_FILTER_RSS_CONF_PENDING,
5728                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5729 }
5730
5731 /*
5732  * Initialize the function. This must be called before sending CLIENT_SETUP
5733  * for the first client.
5734  */
5735 static int bnx2x_func_start(struct bnx2x_softc *sc)
5736 {
5737         struct ecore_func_state_params func_params = { NULL };
5738         struct ecore_func_start_params *start_params =
5739             &func_params.params.start;
5740
5741         /* Prepare parameters for function state transitions */
5742         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5743
5744         func_params.f_obj = &sc->func_obj;
5745         func_params.cmd = ECORE_F_CMD_START;
5746
5747         /* Function parameters */
5748         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5749         start_params->sd_vlan_tag = OVLAN(sc);
5750
5751         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5752                 start_params->network_cos_mode = STATIC_COS;
5753         } else {                /* CHIP_IS_E1X */
5754                 start_params->network_cos_mode = FW_WRR;
5755         }
5756
5757         start_params->gre_tunnel_mode = 0;
5758         start_params->gre_tunnel_rss = 0;
5759
5760         return ecore_func_state_change(sc, &func_params);
5761 }
5762
5763 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5764 {
5765         uint16_t pmcsr;
5766
5767         /* If there is no power capability, silently succeed */
5768         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5769                 PMD_DRV_LOG(WARNING, "No power capability");
5770                 return 0;
5771         }
5772
5773         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5774                  2);
5775
5776         switch (state) {
5777         case PCI_PM_D0:
5778                 pci_write_word(sc,
5779                                (sc->devinfo.pcie_pm_cap_reg +
5780                                 PCIR_POWER_STATUS),
5781                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5782
5783                 if (pmcsr & PCIM_PSTAT_DMASK) {
5784                         /* delay required during transition out of D3hot */
5785                         DELAY(20000);
5786                 }
5787
5788                 break;
5789
5790         case PCI_PM_D3hot:
5791                 /* don't shut down the power for emulation and FPGA */
5792                 if (CHIP_REV_IS_SLOW(sc)) {
5793                         return 0;
5794                 }
5795
5796                 pmcsr &= ~PCIM_PSTAT_DMASK;
5797                 pmcsr |= PCIM_PSTAT_D3;
5798
5799                 if (sc->wol) {
5800                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5801                 }
5802
5803                 pci_write_long(sc,
5804                                (sc->devinfo.pcie_pm_cap_reg +
5805                                 PCIR_POWER_STATUS), pmcsr);
5806
5807                 /*
5808                  * No more memory access after this point until device is brought back
5809                  * to D0 state.
5810                  */
5811                 break;
5812
5813         default:
5814                 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5815                             state);
5816                 return -1;
5817         }
5818
5819         return 0;
5820 }
5821
5822 /* return true if succeeded to acquire the lock */
5823 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5824 {
5825         uint32_t lock_status;
5826         uint32_t resource_bit = (1 << resource);
5827         int func = SC_FUNC(sc);
5828         uint32_t hw_lock_control_reg;
5829
5830         /* Validating that the resource is within range */
5831         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5832                 PMD_DRV_LOG(INFO,
5833                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5834                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5835                 return FALSE;
5836         }
5837
5838         if (func <= 5) {
5839                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5840         } else {
5841                 hw_lock_control_reg =
5842                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5843         }
5844
5845         /* try to acquire the lock */
5846         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5847         lock_status = REG_RD(sc, hw_lock_control_reg);
5848         if (lock_status & resource_bit) {
5849                 return TRUE;
5850         }
5851
5852         PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5853
5854         return FALSE;
5855 }
5856
5857 /*
5858  * Get the recovery leader resource id according to the engine this function
5859  * belongs to. Currently only only 2 engines is supported.
5860  */
5861 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5862 {
5863         if (SC_PATH(sc)) {
5864                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5865         } else {
5866                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5867         }
5868 }
5869
5870 /* try to acquire a leader lock for current engine */
5871 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5872 {
5873         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5874 }
5875
5876 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5877 {
5878         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5879 }
5880
5881 /* close gates #2, #3 and #4 */
5882 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5883 {
5884         uint32_t val;
5885
5886         /* gates #2 and #4a are closed/opened */
5887         /* #4 */
5888         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5889         /* #2 */
5890         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5891
5892         /* #3 */
5893         if (CHIP_IS_E1x(sc)) {
5894 /* prevent interrupts from HC on both ports */
5895                 val = REG_RD(sc, HC_REG_CONFIG_1);
5896                 if (close)
5897                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5898                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5899                 else
5900                         REG_WR(sc, HC_REG_CONFIG_1,
5901                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5902
5903                 val = REG_RD(sc, HC_REG_CONFIG_0);
5904                 if (close)
5905                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5906                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5907                 else
5908                         REG_WR(sc, HC_REG_CONFIG_0,
5909                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5910
5911         } else {
5912 /* Prevent incomming interrupts in IGU */
5913                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5914
5915                 if (close)
5916                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5917                                (val & ~(uint32_t)
5918                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5919                 else
5920                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5921                                (val |
5922                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5923         }
5924
5925         wmb();
5926 }
5927
5928 /* poll for pending writes bit, it should get cleared in no more than 1s */
5929 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5930 {
5931         uint32_t cnt = 1000;
5932         uint32_t pend_bits = 0;
5933
5934         do {
5935                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5936
5937                 if (pend_bits == 0) {
5938                         break;
5939                 }
5940
5941                 DELAY(1000);
5942         } while (cnt-- > 0);
5943
5944         if (cnt <= 0) {
5945                 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5946                             pend_bits);
5947                 return -1;
5948         }
5949
5950         return 0;
5951 }
5952
5953 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5954
5955 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5956 {
5957         /* Do some magic... */
5958         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5959         *magic_val = val & SHARED_MF_CLP_MAGIC;
5960         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5961 }
5962
5963 /* restore the value of the 'magic' bit */
5964 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5965 {
5966         /* Restore the 'magic' bit value... */
5967         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5968         MFCFG_WR(sc, shared_mf_config.clp_mb,
5969                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5970 }
5971
5972 /* prepare for MCP reset, takes care of CLP configurations */
5973 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5974 {
5975         uint32_t shmem;
5976         uint32_t validity_offset;
5977
5978         /* set `magic' bit in order to save MF config */
5979         bnx2x_clp_reset_prep(sc, magic_val);
5980
5981         /* get shmem offset */
5982         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5983         validity_offset =
5984             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5985
5986         /* Clear validity map flags */
5987         if (shmem > 0) {
5988                 REG_WR(sc, shmem + validity_offset, 0);
5989         }
5990 }
5991
5992 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
5993 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
5994
5995 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5996 {
5997         /* special handling for emulation and FPGA (10 times longer) */
5998         if (CHIP_REV_IS_SLOW(sc)) {
5999                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6000         } else {
6001                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6002         }
6003 }
6004
6005 /* initialize shmem_base and waits for validity signature to appear */
6006 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6007 {
6008         int cnt = 0;
6009         uint32_t val = 0;
6010
6011         do {
6012                 sc->devinfo.shmem_base =
6013                     sc->link_params.shmem_base =
6014                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6015
6016                 if (sc->devinfo.shmem_base) {
6017                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6018                         if (val & SHR_MEM_VALIDITY_MB)
6019                                 return 0;
6020                 }
6021
6022                 bnx2x_mcp_wait_one(sc);
6023
6024         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6025
6026         PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6027
6028         return -1;
6029 }
6030
6031 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6032 {
6033         int rc = bnx2x_init_shmem(sc);
6034
6035         /* Restore the `magic' bit value */
6036         bnx2x_clp_reset_done(sc, magic_val);
6037
6038         return rc;
6039 }
6040
6041 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6042 {
6043         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6044         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6045         wmb();
6046 }
6047
6048 /*
6049  * Reset the whole chip except for:
6050  *      - PCIE core
6051  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6052  *      - IGU
6053  *      - MISC (including AEU)
6054  *      - GRC
6055  *      - RBCN, RBCP
6056  */
6057 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6058 {
6059         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6060         uint32_t global_bits2, stay_reset2;
6061
6062         /*
6063          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6064          * (per chip) blocks.
6065          */
6066         global_bits2 =
6067             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6068             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6069
6070         /*
6071          * Don't reset the following blocks.
6072          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6073          *            reset, as in 4 port device they might still be owned
6074          *            by the MCP (there is only one leader per path).
6075          */
6076         not_reset_mask1 =
6077             MISC_REGISTERS_RESET_REG_1_RST_HC |
6078             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6079             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6080
6081         not_reset_mask2 =
6082             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6083             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6084             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6085             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6086             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6087             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6088             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6089             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6090             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6091             MISC_REGISTERS_RESET_REG_2_PGLC |
6092             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6093             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6094             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6095             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6096             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6097
6098         /*
6099          * Keep the following blocks in reset:
6100          *  - all xxMACs are handled by the elink code.
6101          */
6102         stay_reset2 =
6103             MISC_REGISTERS_RESET_REG_2_XMAC |
6104             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6105
6106         /* Full reset masks according to the chip */
6107         reset_mask1 = 0xffffffff;
6108
6109         if (CHIP_IS_E1H(sc))
6110                 reset_mask2 = 0x1ffff;
6111         else if (CHIP_IS_E2(sc))
6112                 reset_mask2 = 0xfffff;
6113         else                    /* CHIP_IS_E3 */
6114                 reset_mask2 = 0x3ffffff;
6115
6116         /* Don't reset global blocks unless we need to */
6117         if (!global)
6118                 reset_mask2 &= ~global_bits2;
6119
6120         /*
6121          * In case of attention in the QM, we need to reset PXP
6122          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6123          * because otherwise QM reset would release 'close the gates' shortly
6124          * before resetting the PXP, then the PSWRQ would send a write
6125          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6126          * read the payload data from PSWWR, but PSWWR would not
6127          * respond. The write queue in PGLUE would stuck, dmae commands
6128          * would not return. Therefore it's important to reset the second
6129          * reset register (containing the
6130          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6131          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6132          * bit).
6133          */
6134         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6135                reset_mask2 & (~not_reset_mask2));
6136
6137         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6138                reset_mask1 & (~not_reset_mask1));
6139
6140         mb();
6141         wmb();
6142
6143         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6144                reset_mask2 & (~stay_reset2));
6145
6146         mb();
6147         wmb();
6148
6149         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6150         wmb();
6151 }
6152
6153 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6154 {
6155         int cnt = 1000;
6156         uint32_t val = 0;
6157         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6158         uint32_t tags_63_32 = 0;
6159
6160         /* Empty the Tetris buffer, wait for 1s */
6161         do {
6162                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6163                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6164                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6165                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6166                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6167                 if (CHIP_IS_E3(sc)) {
6168                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6169                 }
6170
6171                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6172                     ((port_is_idle_0 & 0x1) == 0x1) &&
6173                     ((port_is_idle_1 & 0x1) == 0x1) &&
6174                     (pgl_exp_rom2 == 0xffffffff) &&
6175                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6176                         break;
6177                 DELAY(1000);
6178         } while (cnt-- > 0);
6179
6180         if (cnt <= 0) {
6181                 PMD_DRV_LOG(NOTICE,
6182                             "ERROR: Tetris buffer didn't get empty or there "
6183                             "are still outstanding read requests after 1s! "
6184                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6185                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6186                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6187                             pgl_exp_rom2);
6188                 return -1;
6189         }
6190
6191         mb();
6192
6193         /* Close gates #2, #3 and #4 */
6194         bnx2x_set_234_gates(sc, TRUE);
6195
6196         /* Poll for IGU VQs for 57712 and newer chips */
6197         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6198                 return -1;
6199         }
6200
6201         /* clear "unprepared" bit */
6202         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6203         mb();
6204
6205         /* Make sure all is written to the chip before the reset */
6206         wmb();
6207
6208         /*
6209          * Wait for 1ms to empty GLUE and PCI-E core queues,
6210          * PSWHST, GRC and PSWRD Tetris buffer.
6211          */
6212         DELAY(1000);
6213
6214         /* Prepare to chip reset: */
6215         /* MCP */
6216         if (global) {
6217                 bnx2x_reset_mcp_prep(sc, &val);
6218         }
6219
6220         /* PXP */
6221         bnx2x_pxp_prep(sc);
6222         mb();
6223
6224         /* reset the chip */
6225         bnx2x_process_kill_chip_reset(sc, global);
6226         mb();
6227
6228         /* Recover after reset: */
6229         /* MCP */
6230         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6231                 return -1;
6232         }
6233
6234         /* Open the gates #2, #3 and #4 */
6235         bnx2x_set_234_gates(sc, FALSE);
6236
6237         return 0;
6238 }
6239
6240 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6241 {
6242         int rc = 0;
6243         uint8_t global = bnx2x_reset_is_global(sc);
6244         uint32_t load_code;
6245
6246         /*
6247          * If not going to reset MCP, load "fake" driver to reset HW while
6248          * driver is owner of the HW.
6249          */
6250         if (!global && !BNX2X_NOMCP(sc)) {
6251                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6252                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6253                 if (!load_code) {
6254                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6255                         rc = -1;
6256                         goto exit_leader_reset;
6257                 }
6258
6259                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6260                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6261                         PMD_DRV_LOG(NOTICE,
6262                                     "MCP unexpected response, aborting");
6263                         rc = -1;
6264                         goto exit_leader_reset2;
6265                 }
6266
6267                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6268                 if (!load_code) {
6269                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6270                         rc = -1;
6271                         goto exit_leader_reset2;
6272                 }
6273         }
6274
6275         /* try to recover after the failure */
6276         if (bnx2x_process_kill(sc, global)) {
6277                 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6278                             SC_PATH(sc));
6279                 rc = -1;
6280                 goto exit_leader_reset2;
6281         }
6282
6283         /*
6284          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6285          * state.
6286          */
6287         bnx2x_set_reset_done(sc);
6288         if (global) {
6289                 bnx2x_clear_reset_global(sc);
6290         }
6291
6292 exit_leader_reset2:
6293
6294         /* unload "fake driver" if it was loaded */
6295         if (!global &&!BNX2X_NOMCP(sc)) {
6296                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6297                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6298         }
6299
6300 exit_leader_reset:
6301
6302         sc->is_leader = 0;
6303         bnx2x_release_leader_lock(sc);
6304
6305         mb();
6306         return rc;
6307 }
6308
6309 /*
6310  * prepare INIT transition, parameters configured:
6311  *   - HC configuration
6312  *   - Queue's CDU context
6313  */
6314 static void
6315 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6316                    struct ecore_queue_init_params *init_params)
6317 {
6318         uint8_t cos;
6319         int cxt_index, cxt_offset;
6320
6321         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6322         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6323
6324         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6325         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6326
6327         /* HC rate */
6328         init_params->rx.hc_rate =
6329             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6330         init_params->tx.hc_rate =
6331             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6332
6333         /* FW SB ID */
6334         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6335
6336         /* CQ index among the SB indices */
6337         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6338         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6339
6340         /* set maximum number of COSs supported by this queue */
6341         init_params->max_cos = sc->max_cos;
6342
6343         /* set the context pointers queue object */
6344         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6345                 cxt_index = fp->index / ILT_PAGE_CIDS;
6346                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6347                 init_params->cxts[cos] =
6348                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6349         }
6350 }
6351
6352 /* set flags that are common for the Tx-only and not normal connections */
6353 static unsigned long
6354 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6355 {
6356         unsigned long flags = 0;
6357
6358         /* PF driver will always initialize the Queue to an ACTIVE state */
6359         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6360
6361         /*
6362          * tx only connections collect statistics (on the same index as the
6363          * parent connection). The statistics are zeroed when the parent
6364          * connection is initialized.
6365          */
6366
6367         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6368         if (zero_stats) {
6369                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6370         }
6371
6372         /*
6373          * tx only connections can support tx-switching, though their
6374          * CoS-ness doesn't survive the loopback
6375          */
6376         if (sc->flags & BNX2X_TX_SWITCHING) {
6377                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6378         }
6379
6380         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6381
6382         return flags;
6383 }
6384
6385 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6386 {
6387         unsigned long flags = 0;
6388
6389         if (IS_MF_SD(sc)) {
6390                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6391         }
6392
6393         if (leading) {
6394                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6395                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6396         }
6397
6398         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6399
6400         /* merge with common flags */
6401         return flags | bnx2x_get_common_flags(sc, TRUE);
6402 }
6403
6404 static void
6405 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6406                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6407 {
6408         gen_init->stat_id = bnx2x_stats_id(fp);
6409         gen_init->spcl_id = fp->cl_id;
6410         gen_init->mtu = sc->mtu;
6411         gen_init->cos = cos;
6412 }
6413
6414 static void
6415 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6416                  struct rxq_pause_params *pause,
6417                  struct ecore_rxq_setup_params *rxq_init)
6418 {
6419         struct bnx2x_rx_queue *rxq;
6420
6421         rxq = sc->rx_queues[fp->index];
6422         if (!rxq) {
6423                 PMD_RX_LOG(ERR, "RX queue is NULL");
6424                 return;
6425         }
6426         /* pause */
6427         pause->bd_th_lo = BD_TH_LO(sc);
6428         pause->bd_th_hi = BD_TH_HI(sc);
6429
6430         pause->rcq_th_lo = RCQ_TH_LO(sc);
6431         pause->rcq_th_hi = RCQ_TH_HI(sc);
6432
6433         /* validate rings have enough entries to cross high thresholds */
6434         if (sc->dropless_fc &&
6435             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6436                 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6437         }
6438
6439         if (sc->dropless_fc &&
6440             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6441                 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6442         }
6443
6444         pause->pri_map = 1;
6445
6446         /* rxq setup */
6447         rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6448         rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6449         rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6450                                               BNX2X_PAGE_SIZE);
6451
6452         /*
6453          * This should be a maximum number of data bytes that may be
6454          * placed on the BD (not including paddings).
6455          */
6456         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6457
6458         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6459         rxq_init->rss_engine_id = SC_FUNC(sc);
6460         rxq_init->mcast_engine_id = SC_FUNC(sc);
6461
6462         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6463         rxq_init->fw_sb_id = fp->fw_sb_id;
6464
6465         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6466
6467         /*
6468          * configure silent vlan removal
6469          * if multi function mode is afex, then mask default vlan
6470          */
6471         if (IS_MF_AFEX(sc)) {
6472                 rxq_init->silent_removal_value =
6473                     sc->devinfo.mf_info.afex_def_vlan_tag;
6474                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6475         }
6476 }
6477
6478 static void
6479 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6480                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6481 {
6482         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6483
6484         if (!txq) {
6485                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6486                 return;
6487         }
6488         txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6489         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6490         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6491         txq_init->fw_sb_id = fp->fw_sb_id;
6492
6493         /*
6494          * set the TSS leading client id for TX classfication to the
6495          * leading RSS client id
6496          */
6497         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6498 }
6499
6500 /*
6501  * This function performs 2 steps in a queue state machine:
6502  *   1) RESET->INIT
6503  *   2) INIT->SETUP
6504  */
6505 static int
6506 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6507 {
6508         struct ecore_queue_state_params q_params = { NULL };
6509         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6510         int rc;
6511
6512         PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6513
6514         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6515
6516         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6517
6518         /* we want to wait for completion in this context */
6519         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6520
6521         /* prepare the INIT parameters */
6522         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6523
6524         /* Set the command */
6525         q_params.cmd = ECORE_Q_CMD_INIT;
6526
6527         /* Change the state to INIT */
6528         rc = ecore_queue_state_change(sc, &q_params);
6529         if (rc) {
6530                 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6531                 return rc;
6532         }
6533
6534         PMD_DRV_LOG(DEBUG, "init complete");
6535
6536         /* now move the Queue to the SETUP state */
6537         memset(setup_params, 0, sizeof(*setup_params));
6538
6539         /* set Queue flags */
6540         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6541
6542         /* set general SETUP parameters */
6543         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6544                               FIRST_TX_COS_INDEX);
6545
6546         bnx2x_pf_rx_q_prep(sc, fp,
6547                          &setup_params->pause_params,
6548                          &setup_params->rxq_params);
6549
6550         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6551
6552         /* Set the command */
6553         q_params.cmd = ECORE_Q_CMD_SETUP;
6554
6555         /* change the state to SETUP */
6556         rc = ecore_queue_state_change(sc, &q_params);
6557         if (rc) {
6558                 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6559                 return rc;
6560         }
6561
6562         return rc;
6563 }
6564
6565 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6566 {
6567         if (IS_PF(sc))
6568                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6569         else                    /* VF */
6570                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6571 }
6572
6573 static int
6574 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6575                   uint8_t config_hash)
6576 {
6577         struct ecore_config_rss_params params = { NULL };
6578         uint32_t i;
6579
6580         /*
6581          * Although RSS is meaningless when there is a single HW queue we
6582          * still need it enabled in order to have HW Rx hash generated.
6583          */
6584
6585         params.rss_obj = rss_obj;
6586
6587         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6588
6589         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6590
6591         /* RSS configuration */
6592         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6593         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6594         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6595         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6596         if (rss_obj->udp_rss_v4) {
6597                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6598         }
6599         if (rss_obj->udp_rss_v6) {
6600                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6601         }
6602
6603         /* Hash bits */
6604         params.rss_result_mask = MULTI_MASK;
6605
6606         (void)rte_memcpy(params.ind_table, rss_obj->ind_table,
6607                          sizeof(params.ind_table));
6608
6609         if (config_hash) {
6610 /* RSS keys */
6611                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6612                         params.rss_key[i] = (uint32_t) rte_rand();
6613                 }
6614
6615                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6616         }
6617
6618         if (IS_PF(sc))
6619                 return ecore_config_rss(sc, &params);
6620         else
6621                 return bnx2x_vf_config_rss(sc, &params);
6622 }
6623
6624 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6625 {
6626         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6627 }
6628
6629 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6630 {
6631         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6632         uint32_t i;
6633
6634         /*
6635          * Prepare the initial contents of the indirection table if
6636          * RSS is enabled
6637          */
6638         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6639                 sc->rss_conf_obj.ind_table[i] =
6640                     (sc->fp->cl_id + (i % num_eth_queues));
6641         }
6642
6643         if (sc->udp_rss) {
6644                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6645         }
6646
6647         /*
6648          * For 57711 SEARCHER configuration (rss_keys) is
6649          * per-port, so if explicit configuration is needed, do it only
6650          * for a PMF.
6651          *
6652          * For 57712 and newer it's a per-function configuration.
6653          */
6654         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6655 }
6656
6657 static int
6658 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6659                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6660                 unsigned long *ramrod_flags)
6661 {
6662         struct ecore_vlan_mac_ramrod_params ramrod_param;
6663         int rc;
6664
6665         memset(&ramrod_param, 0, sizeof(ramrod_param));
6666
6667         /* fill in general parameters */
6668         ramrod_param.vlan_mac_obj = obj;
6669         ramrod_param.ramrod_flags = *ramrod_flags;
6670
6671         /* fill a user request section if needed */
6672         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6673                 (void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6674                                  ETH_ALEN);
6675
6676                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6677
6678 /* Set the command: ADD or DEL */
6679                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6680                     ECORE_VLAN_MAC_DEL;
6681         }
6682
6683         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6684
6685         if (rc == ECORE_EXISTS) {
6686                 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6687 /* do not treat adding same MAC as error */
6688                 rc = 0;
6689         } else if (rc < 0) {
6690                 PMD_DRV_LOG(ERR,
6691                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6692         }
6693
6694         return rc;
6695 }
6696
6697 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6698 {
6699         unsigned long ramrod_flags = 0;
6700
6701         PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6702
6703         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6704
6705         /* Eth MAC is set on RSS leading client (fp[0]) */
6706         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6707                                &sc->sp_objs->mac_obj,
6708                                set, ECORE_ETH_MAC, &ramrod_flags);
6709 }
6710
6711 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6712 {
6713         uint32_t sel_phy_idx = 0;
6714
6715         if (sc->link_params.num_phys <= 1) {
6716                 return ELINK_INT_PHY;
6717         }
6718
6719         if (sc->link_vars.link_up) {
6720                 sel_phy_idx = ELINK_EXT_PHY1;
6721 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6722                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6723                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6724                      ELINK_SUPPORTED_FIBRE))
6725                         sel_phy_idx = ELINK_EXT_PHY2;
6726         } else {
6727                 switch (elink_phy_selection(&sc->link_params)) {
6728                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6729                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6730                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6731                         sel_phy_idx = ELINK_EXT_PHY1;
6732                         break;
6733                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6734                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6735                         sel_phy_idx = ELINK_EXT_PHY2;
6736                         break;
6737                 }
6738         }
6739
6740         return sel_phy_idx;
6741 }
6742
6743 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6744 {
6745         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6746
6747         /*
6748          * The selected activated PHY is always after swapping (in case PHY
6749          * swapping is enabled). So when swapping is enabled, we need to reverse
6750          * the configuration
6751          */
6752
6753         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6754                 if (sel_phy_idx == ELINK_EXT_PHY1)
6755                         sel_phy_idx = ELINK_EXT_PHY2;
6756                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6757                         sel_phy_idx = ELINK_EXT_PHY1;
6758         }
6759
6760         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6761 }
6762
6763 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6764 {
6765         /*
6766          * Initialize link parameters structure variables
6767          * It is recommended to turn off RX FC for jumbo frames
6768          * for better performance
6769          */
6770         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6771                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6772         } else {
6773                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6774         }
6775 }
6776
6777 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6778 {
6779         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6780         switch (sc->link_vars.ieee_fc &
6781                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6782         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6783         default:
6784                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6785                                                    ADVERTISED_Pause);
6786                 break;
6787
6788         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6789                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6790                                                   ADVERTISED_Pause);
6791                 break;
6792
6793         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6794                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6795                 break;
6796         }
6797 }
6798
6799 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6800 {
6801         uint16_t line_speed = sc->link_vars.line_speed;
6802         if (IS_MF(sc)) {
6803                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6804                                                       sc->devinfo.
6805                                                       mf_info.mf_config[SC_VN
6806                                                                         (sc)]);
6807
6808 /* calculate the current MAX line speed limit for the MF devices */
6809                 if (IS_MF_SI(sc)) {
6810                         line_speed = (line_speed * maxCfg) / 100;
6811                 } else {        /* SD mode */
6812                         uint16_t vn_max_rate = maxCfg * 100;
6813
6814                         if (vn_max_rate < line_speed) {
6815                                 line_speed = vn_max_rate;
6816                         }
6817                 }
6818         }
6819
6820         return line_speed;
6821 }
6822
6823 static void
6824 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6825 {
6826         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6827
6828         memset(data, 0, sizeof(*data));
6829
6830         /* fill the report data with the effective line speed */
6831         data->line_speed = line_speed;
6832
6833         /* Link is down */
6834         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6835                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6836                             &data->link_report_flags);
6837         }
6838
6839         /* Full DUPLEX */
6840         if (sc->link_vars.duplex == DUPLEX_FULL) {
6841                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6842                             &data->link_report_flags);
6843         }
6844
6845         /* Rx Flow Control is ON */
6846         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6847                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6848         }
6849
6850         /* Tx Flow Control is ON */
6851         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6852                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6853         }
6854 }
6855
6856 /* report link status to OS, should be called under phy_lock */
6857 static void bnx2x_link_report(struct bnx2x_softc *sc)
6858 {
6859         struct bnx2x_link_report_data cur_data;
6860
6861         /* reread mf_cfg */
6862         if (IS_PF(sc)) {
6863                 bnx2x_read_mf_cfg(sc);
6864         }
6865
6866         /* Read the current link report info */
6867         bnx2x_fill_report_data(sc, &cur_data);
6868
6869         /* Don't report link down or exactly the same link status twice */
6870         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6871             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6872                           &sc->last_reported_link.link_report_flags) &&
6873              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6874                           &cur_data.link_report_flags))) {
6875                 return;
6876         }
6877
6878         sc->link_cnt++;
6879
6880         /* report new link params and remember the state for the next time */
6881         (void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6882
6883         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6884                          &cur_data.link_report_flags)) {
6885                 PMD_DRV_LOG(INFO, "NIC Link is Down");
6886         } else {
6887                 __rte_unused const char *duplex;
6888                 __rte_unused const char *flow;
6889
6890                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6891                                            &cur_data.link_report_flags)) {
6892                         duplex = "full";
6893                 } else {
6894                         duplex = "half";
6895                 }
6896
6897 /*
6898  * Handle the FC at the end so that only these flags would be
6899  * possibly set. This way we may easily check if there is no FC
6900  * enabled.
6901  */
6902                 if (cur_data.link_report_flags) {
6903                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6904                                          &cur_data.link_report_flags) &&
6905                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6906                                          &cur_data.link_report_flags)) {
6907                                 flow = "ON - receive & transmit";
6908                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6909                                                 &cur_data.link_report_flags) &&
6910                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6911                                                  &cur_data.link_report_flags)) {
6912                                 flow = "ON - receive";
6913                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6914                                                  &cur_data.link_report_flags) &&
6915                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6916                                                 &cur_data.link_report_flags)) {
6917                                 flow = "ON - transmit";
6918                         } else {
6919                                 flow = "none";  /* possible? */
6920                         }
6921                 } else {
6922                         flow = "none";
6923                 }
6924
6925                 PMD_DRV_LOG(INFO,
6926                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6927                             cur_data.line_speed, duplex, flow);
6928         }
6929 }
6930
6931 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6932 {
6933         if (sc->state != BNX2X_STATE_OPEN) {
6934                 return;
6935         }
6936
6937         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6938                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6939         } else {
6940                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6941                                           ELINK_SUPPORTED_10baseT_Full |
6942                                           ELINK_SUPPORTED_100baseT_Half |
6943                                           ELINK_SUPPORTED_100baseT_Full |
6944                                           ELINK_SUPPORTED_1000baseT_Full |
6945                                           ELINK_SUPPORTED_2500baseX_Full |
6946                                           ELINK_SUPPORTED_10000baseT_Full |
6947                                           ELINK_SUPPORTED_TP |
6948                                           ELINK_SUPPORTED_FIBRE |
6949                                           ELINK_SUPPORTED_Autoneg |
6950                                           ELINK_SUPPORTED_Pause |
6951                                           ELINK_SUPPORTED_Asym_Pause);
6952                 sc->port.advertising[0] = sc->port.supported[0];
6953
6954                 sc->link_params.sc = sc;
6955                 sc->link_params.port = SC_PORT(sc);
6956                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6957                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6958                 sc->link_params.req_line_speed[0] = SPEED_10000;
6959                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6960                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6961
6962                 if (CHIP_REV_IS_FPGA(sc)) {
6963                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6964                         sc->link_vars.line_speed = ELINK_SPEED_1000;
6965                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6966                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6967                 } else {
6968                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6969                         sc->link_vars.line_speed = ELINK_SPEED_10000;
6970                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6971                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6972                 }
6973
6974                 sc->link_vars.link_up = 1;
6975
6976                 sc->link_vars.duplex = DUPLEX_FULL;
6977                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6978
6979                 if (IS_PF(sc)) {
6980                         REG_WR(sc,
6981                                NIG_REG_EGRESS_DRAIN0_MODE +
6982                                sc->link_params.port * 4, 0);
6983                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6984                         bnx2x_link_report(sc);
6985                 }
6986         }
6987
6988         if (IS_PF(sc)) {
6989                 if (sc->link_vars.link_up) {
6990                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6991                 } else {
6992                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
6993                 }
6994                 bnx2x_link_report(sc);
6995         } else {
6996                 bnx2x_link_report(sc);
6997                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6998         }
6999 }
7000
7001 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7002 {
7003         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7004 }
7005
7006 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7007 {
7008         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7009 }
7010
7011 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7012 {
7013         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7014         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7015         struct elink_params *lp = &sc->link_params;
7016
7017         bnx2x_set_requested_fc(sc);
7018
7019         if (load_mode == LOAD_DIAG) {
7020                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7021 /* Prefer doing PHY loopback at 10G speed, if possible */
7022                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7023                         if (lp->speed_cap_mask[cfg_idx] &
7024                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7025                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7026                         } else {
7027                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7028                         }
7029                 }
7030         }
7031
7032         if (load_mode == LOAD_LOOPBACK_EXT) {
7033                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7034         }
7035
7036         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7037
7038         bnx2x_calc_fc_adv(sc);
7039
7040         if (sc->link_vars.link_up) {
7041                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7042                 bnx2x_link_report(sc);
7043         }
7044
7045         if (!CHIP_REV_IS_SLOW(sc)) {
7046                 bnx2x_periodic_start(sc);
7047         }
7048
7049         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7050         return rc;
7051 }
7052
7053 /* update flags in shmem */
7054 static void
7055 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7056 {
7057         uint32_t drv_flags;
7058
7059         if (SHMEM2_HAS(sc, drv_flags)) {
7060                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7061                 drv_flags = SHMEM2_RD(sc, drv_flags);
7062
7063                 if (set) {
7064                         drv_flags |= flags;
7065                 } else {
7066                         drv_flags &= ~flags;
7067                 }
7068
7069                 SHMEM2_WR(sc, drv_flags, drv_flags);
7070
7071                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7072         }
7073 }
7074
7075 /* periodic timer callout routine, only runs when the interface is up */
7076 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7077 {
7078         if ((sc->state != BNX2X_STATE_OPEN) ||
7079             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7080                 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7081                             sc->state);
7082                 return;
7083         }
7084         if (!CHIP_REV_IS_SLOW(sc)) {
7085 /*
7086  * This barrier is needed to ensure the ordering between the writing
7087  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7088  * the reading here.
7089  */
7090                 mb();
7091                 if (sc->port.pmf) {
7092                         elink_period_func(&sc->link_params, &sc->link_vars);
7093                 }
7094         }
7095 #ifdef BNX2X_PULSE
7096         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7097                 int mb_idx = SC_FW_MB_IDX(sc);
7098                 uint32_t drv_pulse;
7099                 uint32_t mcp_pulse;
7100
7101                 ++sc->fw_drv_pulse_wr_seq;
7102                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7103
7104                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7105                 bnx2x_drv_pulse(sc);
7106
7107                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7108                              MCP_PULSE_SEQ_MASK);
7109
7110 /*
7111  * The delta between driver pulse and mcp response should
7112  * be 1 (before mcp response) or 0 (after mcp response).
7113  */
7114                 if ((drv_pulse != mcp_pulse) &&
7115                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7116                         /* someone lost a heartbeat... */
7117                         PMD_DRV_LOG(ERR,
7118                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7119                                     drv_pulse, mcp_pulse);
7120                 }
7121         }
7122 #endif
7123 }
7124
7125 /* start the controller */
7126 static __attribute__ ((noinline))
7127 int bnx2x_nic_load(struct bnx2x_softc *sc)
7128 {
7129         uint32_t val;
7130         uint32_t load_code = 0;
7131         int i, rc = 0;
7132
7133         PMD_INIT_FUNC_TRACE();
7134
7135         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7136
7137         if (IS_PF(sc)) {
7138 /* must be called before memory allocation and HW init */
7139                 bnx2x_ilt_set_info(sc);
7140         }
7141
7142         bnx2x_set_fp_rx_buf_size(sc);
7143
7144         if (IS_PF(sc)) {
7145                 if (bnx2x_alloc_mem(sc) != 0) {
7146                         sc->state = BNX2X_STATE_CLOSED;
7147                         rc = -ENOMEM;
7148                         goto bnx2x_nic_load_error0;
7149                 }
7150         }
7151
7152         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7153                 sc->state = BNX2X_STATE_CLOSED;
7154                 rc = -ENOMEM;
7155                 goto bnx2x_nic_load_error0;
7156         }
7157
7158         if (IS_VF(sc)) {
7159                 rc = bnx2x_vf_init(sc);
7160                 if (rc) {
7161                         sc->state = BNX2X_STATE_ERROR;
7162                         goto bnx2x_nic_load_error0;
7163                 }
7164         }
7165
7166         if (IS_PF(sc)) {
7167 /* set pf load just before approaching the MCP */
7168                 bnx2x_set_pf_load(sc);
7169
7170 /* if MCP exists send load request and analyze response */
7171                 if (!BNX2X_NOMCP(sc)) {
7172                         /* attempt to load pf */
7173                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7174                                 sc->state = BNX2X_STATE_CLOSED;
7175                                 rc = -ENXIO;
7176                                 goto bnx2x_nic_load_error1;
7177                         }
7178
7179                         /* what did the MCP say? */
7180                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7181                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7182                                 sc->state = BNX2X_STATE_CLOSED;
7183                                 rc = -ENXIO;
7184                                 goto bnx2x_nic_load_error2;
7185                         }
7186                 } else {
7187                         PMD_DRV_LOG(INFO, "Device has no MCP!");
7188                         load_code = bnx2x_nic_load_no_mcp(sc);
7189                 }
7190
7191 /* mark PMF if applicable */
7192                 bnx2x_nic_load_pmf(sc, load_code);
7193
7194 /* Init Function state controlling object */
7195                 bnx2x_init_func_obj(sc);
7196
7197 /* Initialize HW */
7198                 if (bnx2x_init_hw(sc, load_code) != 0) {
7199                         PMD_DRV_LOG(NOTICE, "HW init failed");
7200                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7201                         sc->state = BNX2X_STATE_CLOSED;
7202                         rc = -ENXIO;
7203                         goto bnx2x_nic_load_error2;
7204                 }
7205         }
7206
7207         bnx2x_nic_init(sc, load_code);
7208
7209         /* Init per-function objects */
7210         if (IS_PF(sc)) {
7211                 bnx2x_init_objs(sc);
7212
7213 /* set AFEX default VLAN tag to an invalid value */
7214                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7215
7216                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7217                 rc = bnx2x_func_start(sc);
7218                 if (rc) {
7219                         PMD_DRV_LOG(NOTICE, "Function start failed!");
7220                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7221                         sc->state = BNX2X_STATE_ERROR;
7222                         goto bnx2x_nic_load_error3;
7223                 }
7224
7225 /* send LOAD_DONE command to MCP */
7226                 if (!BNX2X_NOMCP(sc)) {
7227                         load_code =
7228                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7229                         if (!load_code) {
7230                                 PMD_DRV_LOG(NOTICE,
7231                                             "MCP response failure, aborting");
7232                                 sc->state = BNX2X_STATE_ERROR;
7233                                 rc = -ENXIO;
7234                                 goto bnx2x_nic_load_error3;
7235                         }
7236                 }
7237         }
7238
7239         rc = bnx2x_setup_leading(sc);
7240         if (rc) {
7241                 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7242                 sc->state = BNX2X_STATE_ERROR;
7243                 goto bnx2x_nic_load_error3;
7244         }
7245
7246         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7247                 if (IS_PF(sc))
7248                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7249                 else            /* IS_VF(sc) */
7250                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7251
7252                 if (rc) {
7253                         PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7254                         sc->state = BNX2X_STATE_ERROR;
7255                         goto bnx2x_nic_load_error3;
7256                 }
7257         }
7258
7259         rc = bnx2x_init_rss_pf(sc);
7260         if (rc) {
7261                 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7262                 sc->state = BNX2X_STATE_ERROR;
7263                 goto bnx2x_nic_load_error3;
7264         }
7265
7266         /* now when Clients are configured we are ready to work */
7267         sc->state = BNX2X_STATE_OPEN;
7268
7269         /* Configure a ucast MAC */
7270         if (IS_PF(sc)) {
7271                 rc = bnx2x_set_eth_mac(sc, TRUE);
7272         } else {                /* IS_VF(sc) */
7273                 rc = bnx2x_vf_set_mac(sc, TRUE);
7274         }
7275
7276         if (rc) {
7277                 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7278                 sc->state = BNX2X_STATE_ERROR;
7279                 goto bnx2x_nic_load_error3;
7280         }
7281
7282         if (sc->port.pmf) {
7283                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7284                 if (rc) {
7285                         sc->state = BNX2X_STATE_ERROR;
7286                         goto bnx2x_nic_load_error3;
7287                 }
7288         }
7289
7290         sc->link_params.feature_config_flags &=
7291             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7292
7293         /* start the Tx */
7294         switch (LOAD_OPEN) {
7295         case LOAD_NORMAL:
7296         case LOAD_OPEN:
7297                 break;
7298
7299         case LOAD_DIAG:
7300         case LOAD_LOOPBACK_EXT:
7301                 sc->state = BNX2X_STATE_DIAG;
7302                 break;
7303
7304         default:
7305                 break;
7306         }
7307
7308         if (sc->port.pmf) {
7309                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7310         } else {
7311                 bnx2x_link_status_update(sc);
7312         }
7313
7314         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7315 /* mark driver is loaded in shmem2 */
7316                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7317                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7318                           (val |
7319                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7320                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7321         }
7322
7323         /* start fast path */
7324         /* Initialize Rx filter */
7325         bnx2x_set_rx_mode(sc);
7326
7327         /* wait for all pending SP commands to complete */
7328         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7329                 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7330                 bnx2x_periodic_stop(sc);
7331                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7332                 return -ENXIO;
7333         }
7334
7335         PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7336
7337         return 0;
7338
7339 bnx2x_nic_load_error3:
7340
7341         if (IS_PF(sc)) {
7342                 bnx2x_int_disable_sync(sc, 1);
7343
7344 /* clean out queued objects */
7345                 bnx2x_squeeze_objects(sc);
7346         }
7347
7348 bnx2x_nic_load_error2:
7349
7350         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7351                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7352                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7353         }
7354
7355         sc->port.pmf = 0;
7356
7357 bnx2x_nic_load_error1:
7358
7359         /* clear pf_load status, as it was already set */
7360         if (IS_PF(sc)) {
7361                 bnx2x_clear_pf_load(sc);
7362         }
7363
7364 bnx2x_nic_load_error0:
7365
7366         bnx2x_free_fw_stats_mem(sc);
7367         bnx2x_free_mem(sc);
7368
7369         return rc;
7370 }
7371
7372 /*
7373 * Handles controller initialization.
7374 */
7375 int bnx2x_init(struct bnx2x_softc *sc)
7376 {
7377         int other_engine = SC_PATH(sc) ? 0 : 1;
7378         uint8_t other_load_status, load_status;
7379         uint8_t global = FALSE;
7380         int rc;
7381
7382         /* Check if the driver is still running and bail out if it is. */
7383         if (sc->state != BNX2X_STATE_CLOSED) {
7384                 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7385                 rc = 0;
7386                 goto bnx2x_init_done;
7387         }
7388
7389         bnx2x_set_power_state(sc, PCI_PM_D0);
7390
7391         /*
7392          * If parity occurred during the unload, then attentions and/or
7393          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7394          * loaded on the current engine to complete the recovery. Parity recovery
7395          * is only relevant for PF driver.
7396          */
7397         if (IS_PF(sc)) {
7398                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7399                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7400
7401                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7402                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7403                         do {
7404                                 /*
7405                                  * If there are attentions and they are in global blocks, set
7406                                  * the GLOBAL_RESET bit regardless whether it will be this
7407                                  * function that will complete the recovery or not.
7408                                  */
7409                                 if (global) {
7410                                         bnx2x_set_reset_global(sc);
7411                                 }
7412
7413                                 /*
7414                                  * Only the first function on the current engine should try
7415                                  * to recover in open. In case of attentions in global blocks
7416                                  * only the first in the chip should try to recover.
7417                                  */
7418                                 if ((!load_status
7419                                      && (!global ||!other_load_status))
7420                                     && bnx2x_trylock_leader_lock(sc)
7421                                     && !bnx2x_leader_reset(sc)) {
7422                                         PMD_DRV_LOG(INFO,
7423                                                     "Recovered during init");
7424                                         break;
7425                                 }
7426
7427                                 /* recovery has failed... */
7428                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7429
7430                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7431
7432                                 PMD_DRV_LOG(NOTICE,
7433                                             "Recovery flow hasn't properly "
7434                                             "completed yet, try again later. "
7435                                             "If you still see this message after a "
7436                                             "few retries then power cycle is required.");
7437
7438                                 rc = -ENXIO;
7439                                 goto bnx2x_init_done;
7440                         } while (0);
7441                 }
7442         }
7443
7444         sc->recovery_state = BNX2X_RECOVERY_DONE;
7445
7446         rc = bnx2x_nic_load(sc);
7447
7448 bnx2x_init_done:
7449
7450         if (rc) {
7451                 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7452                             "stack notified driver is NOT running!");
7453         }
7454
7455         return rc;
7456 }
7457
7458 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7459 {
7460         uint32_t val = 0;
7461
7462         /*
7463          * Read the ME register to get the function number. The ME register
7464          * holds the relative-function number and absolute-function number. The
7465          * absolute-function number appears only in E2 and above. Before that
7466          * these bits always contained zero, therefore we cannot blindly use them.
7467          */
7468
7469         val = REG_RD(sc, BAR_ME_REGISTER);
7470
7471         sc->pfunc_rel =
7472             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7473         sc->path_id =
7474             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7475             1;
7476
7477         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7478                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7479         } else {
7480                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7481         }
7482
7483         PMD_DRV_LOG(DEBUG,
7484                     "Relative function %d, Absolute function %d, Path %d",
7485                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7486 }
7487
7488 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7489 {
7490         uint32_t shmem2_size;
7491         uint32_t offset;
7492         uint32_t mf_cfg_offset_value;
7493
7494         /* Non 57712 */
7495         offset = (SHMEM_ADDR(sc, func_mb) +
7496                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7497
7498         /* 57712 plus */
7499         if (sc->devinfo.shmem2_base != 0) {
7500                 shmem2_size = SHMEM2_RD(sc, size);
7501                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7502                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7503                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7504                                 offset = mf_cfg_offset_value;
7505                         }
7506                 }
7507         }
7508
7509         return offset;
7510 }
7511
7512 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7513 {
7514         uint32_t ret;
7515         struct bnx2x_pci_cap *caps;
7516
7517         /* ensure PCIe capability is enabled */
7518         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7519         if (NULL != caps) {
7520                 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7521                             "id=0x%04X type=0x%04X addr=0x%08X",
7522                             caps->id, caps->type, caps->addr);
7523                 pci_read(sc, (caps->addr + reg), &ret, 2);
7524                 return ret;
7525         }
7526
7527         PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7528
7529         return 0;
7530 }
7531
7532 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7533 {
7534         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7535                 PCIM_EXP_STA_TRANSACTION_PND;
7536 }
7537
7538 /*
7539 * Walk the PCI capabiites list for the device to find what features are
7540 * supported. These capabilites may be enabled/disabled by firmware so it's
7541 * best to walk the list rather than make assumptions.
7542 */
7543 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7544 {
7545         PMD_INIT_FUNC_TRACE();
7546
7547         struct bnx2x_pci_cap *caps;
7548         uint16_t link_status;
7549 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7550         int reg = 0;
7551 #endif
7552
7553         /* check if PCI Power Management is enabled */
7554         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7555         if (NULL != caps) {
7556                 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7557                             "id=0x%04X type=0x%04X addr=0x%08X",
7558                             caps->id, caps->type, caps->addr);
7559
7560                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7561                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7562         }
7563
7564         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7565
7566         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7567         sc->devinfo.pcie_link_width =
7568             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7569
7570         PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7571                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7572
7573         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7574
7575         /* check if MSI capability is enabled */
7576         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7577         if (NULL != caps) {
7578                 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7579
7580                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7581                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7582         }
7583
7584         /* check if MSI-X capability is enabled */
7585         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7586         if (NULL != caps) {
7587                 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7588
7589                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7590                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7591         }
7592 }
7593
7594 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7595 {
7596         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7597         uint32_t val;
7598
7599         /* get the outer vlan if we're in switch-dependent mode */
7600
7601         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7602         mf_info->ext_id = (uint16_t) val;
7603
7604         mf_info->multi_vnics_mode = 1;
7605
7606         if (!VALID_OVLAN(mf_info->ext_id)) {
7607                 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7608                 return 1;
7609         }
7610
7611         /* get the capabilities */
7612         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7613             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7614                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7615         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7616                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7617                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7618         } else {
7619                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7620         }
7621
7622         mf_info->vnics_per_port =
7623             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7624
7625         return 0;
7626 }
7627
7628 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7629 {
7630         uint32_t retval = 0;
7631         uint32_t val;
7632
7633         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7634
7635         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7636                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7637                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7638                 }
7639                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7640                         retval |= MF_PROTO_SUPPORT_ISCSI;
7641                 }
7642                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7643                         retval |= MF_PROTO_SUPPORT_FCOE;
7644                 }
7645         }
7646
7647         return retval;
7648 }
7649
7650 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7651 {
7652         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7653         uint32_t val;
7654
7655         /*
7656          * There is no outer vlan if we're in switch-independent mode.
7657          * If the mac is valid then assume multi-function.
7658          */
7659
7660         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7661
7662         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7663
7664         mf_info->mf_protos_supported =
7665             bnx2x_get_shmem_ext_proto_support_flags(sc);
7666
7667         mf_info->vnics_per_port =
7668             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7669
7670         return 0;
7671 }
7672
7673 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7674 {
7675         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7676         uint32_t e1hov_tag;
7677         uint32_t func_config;
7678         uint32_t niv_config;
7679
7680         mf_info->multi_vnics_mode = 1;
7681
7682         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7683         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7684         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7685
7686         mf_info->ext_id =
7687             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7688                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7689
7690         mf_info->default_vlan =
7691             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7692                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7693
7694         mf_info->niv_allowed_priorities =
7695             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7696                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7697
7698         mf_info->niv_default_cos =
7699             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7700                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7701
7702         mf_info->afex_vlan_mode =
7703             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7704              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7705
7706         mf_info->niv_mba_enabled =
7707             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7708              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7709
7710         mf_info->mf_protos_supported =
7711             bnx2x_get_shmem_ext_proto_support_flags(sc);
7712
7713         mf_info->vnics_per_port =
7714             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7715
7716         return 0;
7717 }
7718
7719 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7720 {
7721         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7722         uint32_t mf_cfg1;
7723         uint32_t mf_cfg2;
7724         uint32_t ovlan1;
7725         uint32_t ovlan2;
7726         uint8_t i, j;
7727
7728         /* various MF mode sanity checks... */
7729
7730         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7731                 PMD_DRV_LOG(NOTICE,
7732                             "Enumerated function %d is marked as hidden",
7733                             SC_PORT(sc));
7734                 return 1;
7735         }
7736
7737         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7738                 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7739                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7740                 return 1;
7741         }
7742
7743         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7744 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7745                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7746                         PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7747                                     SC_VN(sc), OVLAN(sc));
7748                         return 1;
7749                 }
7750
7751                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7752                         PMD_DRV_LOG(NOTICE,
7753                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7754                                     mf_info->multi_vnics_mode, OVLAN(sc));
7755                         return 1;
7756                 }
7757
7758 /*
7759  * Verify all functions are either MF or SF mode. If MF, make sure
7760  * sure that all non-hidden functions have a valid ovlan. If SF,
7761  * make sure that all non-hidden functions have an invalid ovlan.
7762  */
7763                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7764                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7765                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7766                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7767                             (((mf_info->multi_vnics_mode)
7768                               && !VALID_OVLAN(ovlan1))
7769                              || ((!mf_info->multi_vnics_mode)
7770                                  && VALID_OVLAN(ovlan1)))) {
7771                                 PMD_DRV_LOG(NOTICE,
7772                                             "mf_mode=SD function %d MF config "
7773                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7774                                             i, mf_info->multi_vnics_mode,
7775                                             ovlan1);
7776                                 return 1;
7777                         }
7778                 }
7779
7780 /* Verify all funcs on the same port each have a different ovlan. */
7781                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7782                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7783                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7784                         /* iterate from the next function on the port to the max func */
7785                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7786                                 mf_cfg2 =
7787                                     MFCFG_RD(sc, func_mf_config[j].config);
7788                                 ovlan2 =
7789                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7790                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7791                                     && VALID_OVLAN(ovlan1)
7792                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7793                                     && VALID_OVLAN(ovlan2)
7794                                     && (ovlan1 == ovlan2)) {
7795                                         PMD_DRV_LOG(NOTICE,
7796                                                     "mf_mode=SD functions %d and %d "
7797                                                     "have the same ovlan (%d)",
7798                                                     i, j, ovlan1);
7799                                         return 1;
7800                                 }
7801                         }
7802                 }
7803         }
7804         /* MULTI_FUNCTION_SD */
7805         return 0;
7806 }
7807
7808 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7809 {
7810         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7811         uint32_t val, mac_upper;
7812         uint8_t i, vnic;
7813
7814         /* initialize mf_info defaults */
7815         mf_info->vnics_per_port = 1;
7816         mf_info->multi_vnics_mode = FALSE;
7817         mf_info->path_has_ovlan = FALSE;
7818         mf_info->mf_mode = SINGLE_FUNCTION;
7819
7820         if (!CHIP_IS_MF_CAP(sc)) {
7821                 return 0;
7822         }
7823
7824         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7825                 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7826                 return 1;
7827         }
7828
7829         /* get the MF mode (switch dependent / independent / single-function) */
7830
7831         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7832
7833         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7834         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7835
7836                 mac_upper =
7837                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7838
7839                 /* check for legal upper mac bytes */
7840                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7841                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7842                 } else {
7843                         PMD_DRV_LOG(NOTICE,
7844                                     "Invalid config for Switch Independent mode");
7845                 }
7846
7847                 break;
7848
7849         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7850         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7851
7852                 /* get outer vlan configuration */
7853                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7854
7855                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7856                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7857                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7858                 } else {
7859                         PMD_DRV_LOG(NOTICE,
7860                                     "Invalid config for Switch Dependent mode");
7861                 }
7862
7863                 break;
7864
7865         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7866
7867                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7868                 return 0;
7869
7870         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7871
7872                 /*
7873                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7874                  * and the MAC address is valid.
7875                  */
7876                 mac_upper =
7877                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7878
7879                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7880                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7881                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7882                 } else {
7883                         PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7884                 }
7885
7886                 break;
7887
7888         default:
7889
7890                 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7891                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7892
7893                 return 1;
7894         }
7895
7896         /* set path mf_mode (which could be different than function mf_mode) */
7897         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7898                 mf_info->path_has_ovlan = TRUE;
7899         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7900 /*
7901  * Decide on path multi vnics mode. If we're not in MF mode and in
7902  * 4-port mode, this is good enough to check vnic-0 of the other port
7903  * on the same path
7904  */
7905                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7906                         uint8_t other_port = !(PORT_ID(sc) & 1);
7907                         uint8_t abs_func_other_port =
7908                             (SC_PATH(sc) + (2 * other_port));
7909
7910                         val =
7911                             MFCFG_RD(sc,
7912                                      func_mf_config
7913                                      [abs_func_other_port].e1hov_tag);
7914
7915                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7916                 }
7917         }
7918
7919         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7920 /* invalid MF config */
7921                 if (SC_VN(sc) >= 1) {
7922                         PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7923                         return 1;
7924                 }
7925
7926                 return 0;
7927         }
7928
7929         /* get the MF configuration */
7930         mf_info->mf_config[SC_VN(sc)] =
7931             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7932
7933         switch (mf_info->mf_mode) {
7934         case MULTI_FUNCTION_SD:
7935
7936                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7937                 break;
7938
7939         case MULTI_FUNCTION_SI:
7940
7941                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7942                 break;
7943
7944         case MULTI_FUNCTION_AFEX:
7945
7946                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7947                 break;
7948
7949         default:
7950
7951                 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7952                             mf_info->mf_mode);
7953                 return 1;
7954         }
7955
7956         /* get the congestion management parameters */
7957
7958         vnic = 0;
7959         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7960 /* get min/max bw */
7961                 val = MFCFG_RD(sc, func_mf_config[i].config);
7962                 mf_info->min_bw[vnic] =
7963                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7964                      FUNC_MF_CFG_MIN_BW_SHIFT);
7965                 mf_info->max_bw[vnic] =
7966                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7967                      FUNC_MF_CFG_MAX_BW_SHIFT);
7968                 vnic++;
7969         }
7970
7971         return bnx2x_check_valid_mf_cfg(sc);
7972 }
7973
7974 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
7975 {
7976         int port;
7977         uint32_t mac_hi, mac_lo, val;
7978
7979         PMD_INIT_FUNC_TRACE();
7980
7981         port = SC_PORT(sc);
7982         mac_hi = mac_lo = 0;
7983
7984         sc->link_params.sc = sc;
7985         sc->link_params.port = port;
7986
7987         /* get the hardware config info */
7988         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
7989         sc->devinfo.hw_config2 =
7990             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
7991
7992         sc->link_params.hw_led_mode =
7993             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
7994              SHARED_HW_CFG_LED_MODE_SHIFT);
7995
7996         /* get the port feature config */
7997         sc->port.config =
7998             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
7999
8000         /* get the link params */
8001         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8002             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8003             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8004         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8005             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8006             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8007
8008         /* get the lane config */
8009         sc->link_params.lane_config =
8010             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8011
8012         /* get the link config */
8013         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8014         sc->port.link_config[ELINK_INT_PHY] = val;
8015         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8016         sc->port.link_config[ELINK_EXT_PHY1] =
8017             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8018
8019         /* get the override preemphasis flag and enable it or turn it off */
8020         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8021         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8022                 sc->link_params.feature_config_flags |=
8023                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8024         } else {
8025                 sc->link_params.feature_config_flags &=
8026                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8027         }
8028
8029         /* get the initial value of the link params */
8030         sc->link_params.multi_phy_config =
8031             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8032
8033         /* get external phy info */
8034         sc->port.ext_phy_config =
8035             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8036
8037         /* get the multifunction configuration */
8038         bnx2x_get_mf_cfg_info(sc);
8039
8040         /* get the mac address */
8041         if (IS_MF(sc)) {
8042                 mac_hi =
8043                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8044                 mac_lo =
8045                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8046         } else {
8047                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8048                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8049         }
8050
8051         if ((mac_lo == 0) && (mac_hi == 0)) {
8052                 *sc->mac_addr_str = 0;
8053                 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8054         } else {
8055                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8056                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8057                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8058                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8059                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8060                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8061                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8062                          "%02x:%02x:%02x:%02x:%02x:%02x",
8063                          sc->link_params.mac_addr[0],
8064                          sc->link_params.mac_addr[1],
8065                          sc->link_params.mac_addr[2],
8066                          sc->link_params.mac_addr[3],
8067                          sc->link_params.mac_addr[4],
8068                          sc->link_params.mac_addr[5]);
8069                 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8070         }
8071
8072         return 0;
8073 }
8074
8075 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8076 {
8077         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8078         switch (sc->link_params.phy[phy_idx].media_type) {
8079         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8080         case ELINK_ETH_PHY_SFP_1G_FIBER:
8081         case ELINK_ETH_PHY_XFP_FIBER:
8082         case ELINK_ETH_PHY_KR:
8083         case ELINK_ETH_PHY_CX4:
8084                 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8085                 sc->media = IFM_10G_CX4;
8086                 break;
8087         case ELINK_ETH_PHY_DA_TWINAX:
8088                 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8089                 sc->media = IFM_10G_TWINAX;
8090                 break;
8091         case ELINK_ETH_PHY_BASE_T:
8092                 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8093                 sc->media = IFM_10G_T;
8094                 break;
8095         case ELINK_ETH_PHY_NOT_PRESENT:
8096                 PMD_DRV_LOG(INFO, "Media not present.");
8097                 sc->media = 0;
8098                 break;
8099         case ELINK_ETH_PHY_UNSPECIFIED:
8100         default:
8101                 PMD_DRV_LOG(INFO, "Unknown media!");
8102                 sc->media = 0;
8103                 break;
8104         }
8105 }
8106
8107 #define GET_FIELD(value, fname)                     \
8108 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8109 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8110 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8111
8112 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8113 {
8114         int pfid = SC_FUNC(sc);
8115         int igu_sb_id;
8116         uint32_t val;
8117         uint8_t fid, igu_sb_cnt = 0;
8118
8119         sc->igu_base_sb = 0xff;
8120
8121         if (CHIP_INT_MODE_IS_BC(sc)) {
8122                 int vn = SC_VN(sc);
8123                 igu_sb_cnt = sc->igu_sb_cnt;
8124                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8125                                    FP_SB_MAX_E1x);
8126                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8127                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8128                 return 0;
8129         }
8130
8131         /* IGU in normal mode - read CAM */
8132         for (igu_sb_id = 0;
8133              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8134                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8135                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8136                         continue;
8137                 }
8138                 fid = IGU_FID(val);
8139                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8140                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8141                                 continue;
8142                         }
8143                         if (IGU_VEC(val) == 0) {
8144                                 /* default status block */
8145                                 sc->igu_dsb_id = igu_sb_id;
8146                         } else {
8147                                 if (sc->igu_base_sb == 0xff) {
8148                                         sc->igu_base_sb = igu_sb_id;
8149                                 }
8150                                 igu_sb_cnt++;
8151                         }
8152                 }
8153         }
8154
8155         /*
8156          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8157          * that number of CAM entries will not be equal to the value advertised in
8158          * PCI. Driver should use the minimal value of both as the actual status
8159          * block count
8160          */
8161         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8162
8163         if (igu_sb_cnt == 0) {
8164                 PMD_DRV_LOG(ERR, "CAM configuration error");
8165                 return -1;
8166         }
8167
8168         return 0;
8169 }
8170
8171 /*
8172 * Gather various information from the device config space, the device itself,
8173 * shmem, and the user input.
8174 */
8175 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8176 {
8177         uint32_t val;
8178         int rc;
8179
8180         /* get the chip revision (chip metal comes from pci config space) */
8181         sc->devinfo.chip_id = sc->link_params.chip_id =
8182             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8183              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8184              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8185              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8186
8187         /* force 57811 according to MISC register */
8188         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8189                 if (CHIP_IS_57810(sc)) {
8190                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8191                                                (sc->
8192                                                 devinfo.chip_id & 0x0000ffff));
8193                 } else if (CHIP_IS_57810_MF(sc)) {
8194                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8195                                                (sc->
8196                                                 devinfo.chip_id & 0x0000ffff));
8197                 }
8198                 sc->devinfo.chip_id |= 0x1;
8199         }
8200
8201         PMD_DRV_LOG(DEBUG,
8202                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8203                     sc->devinfo.chip_id,
8204                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8205                     ((sc->devinfo.chip_id >> 12) & 0xf),
8206                     ((sc->devinfo.chip_id >> 4) & 0xff),
8207                     ((sc->devinfo.chip_id >> 0) & 0xf));
8208
8209         val = (REG_RD(sc, 0x2874) & 0x55);
8210         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8211                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8212                 PMD_DRV_LOG(DEBUG, "single port device");
8213         }
8214
8215         /* set the doorbell size */
8216         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8217
8218         /* determine whether the device is in 2 port or 4 port mode */
8219         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8220         if (CHIP_IS_E2E3(sc)) {
8221 /*
8222  * Read port4mode_en_ovwr[0]:
8223  *   If 1, four port mode is in port4mode_en_ovwr[1].
8224  *   If 0, four port mode is in port4mode_en[0].
8225  */
8226                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8227                 if (val & 1) {
8228                         val = ((val >> 1) & 1);
8229                 } else {
8230                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8231                 }
8232
8233                 sc->devinfo.chip_port_mode =
8234                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8235
8236                 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8237         }
8238
8239         /* get the function and path info for the device */
8240         bnx2x_get_function_num(sc);
8241
8242         /* get the shared memory base address */
8243         sc->devinfo.shmem_base =
8244             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8245         sc->devinfo.shmem2_base =
8246             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8247                         MISC_REG_GENERIC_CR_0));
8248
8249         if (!sc->devinfo.shmem_base) {
8250 /* this should ONLY prevent upcoming shmem reads */
8251                 PMD_DRV_LOG(INFO, "MCP not active");
8252                 sc->flags |= BNX2X_NO_MCP_FLAG;
8253                 return 0;
8254         }
8255
8256         /* make sure the shared memory contents are valid */
8257         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8258         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8259             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8260                 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8261                             val);
8262                 return 0;
8263         }
8264
8265         /* get the bootcode version */
8266         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8267         snprintf(sc->devinfo.bc_ver_str,
8268                  sizeof(sc->devinfo.bc_ver_str),
8269                  "%d.%d.%d",
8270                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8271                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8272                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8273         PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8274
8275         /* get the bootcode shmem address */
8276         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8277
8278         /* clean indirect addresses as they're not used */
8279         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8280         if (IS_PF(sc)) {
8281                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8282                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8283                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8284                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8285                 if (CHIP_IS_E1x(sc)) {
8286                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8287                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8288                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8289                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8290                 }
8291
8292 /*
8293  * Enable internal target-read (in case we are probed after PF
8294  * FLR). Must be done prior to any BAR read access. Only for
8295  * 57712 and up
8296  */
8297                 if (!CHIP_IS_E1x(sc)) {
8298                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
8299                                1);
8300                 }
8301         }
8302
8303         /* get the nvram size */
8304         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8305         sc->devinfo.flash_size =
8306             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8307
8308         bnx2x_set_power_state(sc, PCI_PM_D0);
8309         /* get various configuration parameters from shmem */
8310         bnx2x_get_shmem_info(sc);
8311
8312         /* initialize IGU parameters */
8313         if (CHIP_IS_E1x(sc)) {
8314                 sc->devinfo.int_block = INT_BLOCK_HC;
8315                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8316                 sc->igu_base_sb = 0;
8317         } else {
8318                 sc->devinfo.int_block = INT_BLOCK_IGU;
8319
8320 /* do not allow device reset during IGU info preocessing */
8321                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8322
8323                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8324
8325                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8326                         int tout = 5000;
8327
8328                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8329                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8330                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8331
8332                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8333                                 tout--;
8334                                 DELAY(1000);
8335                         }
8336
8337                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8338                                 PMD_DRV_LOG(NOTICE,
8339                                             "FORCING IGU Normal Mode failed!!!");
8340                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8341                                 return -1;
8342                         }
8343                 }
8344
8345                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8346                         PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8347                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8348                 } else {
8349                         PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8350                 }
8351
8352                 rc = bnx2x_get_igu_cam_info(sc);
8353
8354                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8355
8356                 if (rc) {
8357                         return rc;
8358                 }
8359         }
8360
8361         /*
8362          * Get base FW non-default (fast path) status block ID. This value is
8363          * used to initialize the fw_sb_id saved on the fp/queue structure to
8364          * determine the id used by the FW.
8365          */
8366         if (CHIP_IS_E1x(sc)) {
8367                 sc->base_fw_ndsb =
8368                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8369         } else {
8370 /*
8371  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8372  * the same queue are indicated on the same IGU SB). So we prefer
8373  * FW and IGU SBs to be the same value.
8374  */
8375                 sc->base_fw_ndsb = sc->igu_base_sb;
8376         }
8377
8378         elink_phy_probe(&sc->link_params);
8379
8380         return 0;
8381 }
8382
8383 static void
8384 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8385 {
8386         uint32_t cfg_size = 0;
8387         uint32_t idx;
8388         uint8_t port = SC_PORT(sc);
8389
8390         /* aggregation of supported attributes of all external phys */
8391         sc->port.supported[0] = 0;
8392         sc->port.supported[1] = 0;
8393
8394         switch (sc->link_params.num_phys) {
8395         case 1:
8396                 sc->port.supported[0] =
8397                     sc->link_params.phy[ELINK_INT_PHY].supported;
8398                 cfg_size = 1;
8399                 break;
8400         case 2:
8401                 sc->port.supported[0] =
8402                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8403                 cfg_size = 1;
8404                 break;
8405         case 3:
8406                 if (sc->link_params.multi_phy_config &
8407                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8408                         sc->port.supported[1] =
8409                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8410                         sc->port.supported[0] =
8411                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8412                 } else {
8413                         sc->port.supported[0] =
8414                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8415                         sc->port.supported[1] =
8416                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8417                 }
8418                 cfg_size = 2;
8419                 break;
8420         }
8421
8422         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8423                 PMD_DRV_LOG(ERR,
8424                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8425                             SHMEM_RD(sc,
8426                                      dev_info.port_hw_config
8427                                      [port].external_phy_config),
8428                             SHMEM_RD(sc,
8429                                      dev_info.port_hw_config
8430                                      [port].external_phy_config2));
8431                 return;
8432         }
8433
8434         if (CHIP_IS_E3(sc))
8435                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8436         else {
8437                 switch (switch_cfg) {
8438                 case ELINK_SWITCH_CFG_1G:
8439                         sc->port.phy_addr =
8440                             REG_RD(sc,
8441                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8442                         break;
8443                 case ELINK_SWITCH_CFG_10G:
8444                         sc->port.phy_addr =
8445                             REG_RD(sc,
8446                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8447                         break;
8448                 default:
8449                         PMD_DRV_LOG(ERR,
8450                                     "Invalid switch config in"
8451                                     "link_config=0x%08x",
8452                                     sc->port.link_config[0]);
8453                         return;
8454                 }
8455         }
8456
8457         PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8458
8459         /* mask what we support according to speed_cap_mask per configuration */
8460         for (idx = 0; idx < cfg_size; idx++) {
8461                 if (!(sc->link_params.speed_cap_mask[idx] &
8462                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8463                         sc->port.supported[idx] &=
8464                             ~ELINK_SUPPORTED_10baseT_Half;
8465                 }
8466
8467                 if (!(sc->link_params.speed_cap_mask[idx] &
8468                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8469                         sc->port.supported[idx] &=
8470                             ~ELINK_SUPPORTED_10baseT_Full;
8471                 }
8472
8473                 if (!(sc->link_params.speed_cap_mask[idx] &
8474                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8475                         sc->port.supported[idx] &=
8476                             ~ELINK_SUPPORTED_100baseT_Half;
8477                 }
8478
8479                 if (!(sc->link_params.speed_cap_mask[idx] &
8480                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8481                         sc->port.supported[idx] &=
8482                             ~ELINK_SUPPORTED_100baseT_Full;
8483                 }
8484
8485                 if (!(sc->link_params.speed_cap_mask[idx] &
8486                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8487                         sc->port.supported[idx] &=
8488                             ~ELINK_SUPPORTED_1000baseT_Full;
8489                 }
8490
8491                 if (!(sc->link_params.speed_cap_mask[idx] &
8492                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8493                         sc->port.supported[idx] &=
8494                             ~ELINK_SUPPORTED_2500baseX_Full;
8495                 }
8496
8497                 if (!(sc->link_params.speed_cap_mask[idx] &
8498                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8499                         sc->port.supported[idx] &=
8500                             ~ELINK_SUPPORTED_10000baseT_Full;
8501                 }
8502
8503                 if (!(sc->link_params.speed_cap_mask[idx] &
8504                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8505                         sc->port.supported[idx] &=
8506                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8507                 }
8508         }
8509
8510         PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8511                     sc->port.supported[0], sc->port.supported[1]);
8512 }
8513
8514 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8515 {
8516         uint32_t link_config;
8517         uint32_t idx;
8518         uint32_t cfg_size = 0;
8519
8520         sc->port.advertising[0] = 0;
8521         sc->port.advertising[1] = 0;
8522
8523         switch (sc->link_params.num_phys) {
8524         case 1:
8525         case 2:
8526                 cfg_size = 1;
8527                 break;
8528         case 3:
8529                 cfg_size = 2;
8530                 break;
8531         }
8532
8533         for (idx = 0; idx < cfg_size; idx++) {
8534                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8535                 link_config = sc->port.link_config[idx];
8536
8537                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8538                 case PORT_FEATURE_LINK_SPEED_AUTO:
8539                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8540                                 sc->link_params.req_line_speed[idx] =
8541                                     ELINK_SPEED_AUTO_NEG;
8542                                 sc->port.advertising[idx] |=
8543                                     sc->port.supported[idx];
8544                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8545                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8546                                         sc->port.advertising[idx] |=
8547                                             (ELINK_SUPPORTED_100baseT_Half |
8548                                              ELINK_SUPPORTED_100baseT_Full);
8549                         } else {
8550                                 /* force 10G, no AN */
8551                                 sc->link_params.req_line_speed[idx] =
8552                                     ELINK_SPEED_10000;
8553                                 sc->port.advertising[idx] |=
8554                                     (ADVERTISED_10000baseT_Full |
8555                                      ADVERTISED_FIBRE);
8556                                 continue;
8557                         }
8558                         break;
8559
8560                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8561                         if (sc->
8562                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8563                         {
8564                                 sc->link_params.req_line_speed[idx] =
8565                                     ELINK_SPEED_10;
8566                                 sc->port.advertising[idx] |=
8567                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8568                         } else {
8569                                 PMD_DRV_LOG(ERR,
8570                                             "Invalid NVRAM config link_config=0x%08x "
8571                                             "speed_cap_mask=0x%08x",
8572                                             link_config,
8573                                             sc->
8574                                             link_params.speed_cap_mask[idx]);
8575                                 return;
8576                         }
8577                         break;
8578
8579                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8580                         if (sc->
8581                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8582                         {
8583                                 sc->link_params.req_line_speed[idx] =
8584                                     ELINK_SPEED_10;
8585                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8586                                 sc->port.advertising[idx] |=
8587                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8588                         } else {
8589                                 PMD_DRV_LOG(ERR,
8590                                             "Invalid NVRAM config link_config=0x%08x "
8591                                             "speed_cap_mask=0x%08x",
8592                                             link_config,
8593                                             sc->
8594                                             link_params.speed_cap_mask[idx]);
8595                                 return;
8596                         }
8597                         break;
8598
8599                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8600                         if (sc->
8601                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8602                         {
8603                                 sc->link_params.req_line_speed[idx] =
8604                                     ELINK_SPEED_100;
8605                                 sc->port.advertising[idx] |=
8606                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8607                         } else {
8608                                 PMD_DRV_LOG(ERR,
8609                                             "Invalid NVRAM config link_config=0x%08x "
8610                                             "speed_cap_mask=0x%08x",
8611                                             link_config,
8612                                             sc->
8613                                             link_params.speed_cap_mask[idx]);
8614                                 return;
8615                         }
8616                         break;
8617
8618                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8619                         if (sc->
8620                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8621                         {
8622                                 sc->link_params.req_line_speed[idx] =
8623                                     ELINK_SPEED_100;
8624                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8625                                 sc->port.advertising[idx] |=
8626                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8627                         } else {
8628                                 PMD_DRV_LOG(ERR,
8629                                             "Invalid NVRAM config link_config=0x%08x "
8630                                             "speed_cap_mask=0x%08x",
8631                                             link_config,
8632                                             sc->
8633                                             link_params.speed_cap_mask[idx]);
8634                                 return;
8635                         }
8636                         break;
8637
8638                 case PORT_FEATURE_LINK_SPEED_1G:
8639                         if (sc->port.supported[idx] &
8640                             ELINK_SUPPORTED_1000baseT_Full) {
8641                                 sc->link_params.req_line_speed[idx] =
8642                                     ELINK_SPEED_1000;
8643                                 sc->port.advertising[idx] |=
8644                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8645                         } else {
8646                                 PMD_DRV_LOG(ERR,
8647                                             "Invalid NVRAM config link_config=0x%08x "
8648                                             "speed_cap_mask=0x%08x",
8649                                             link_config,
8650                                             sc->
8651                                             link_params.speed_cap_mask[idx]);
8652                                 return;
8653                         }
8654                         break;
8655
8656                 case PORT_FEATURE_LINK_SPEED_2_5G:
8657                         if (sc->port.supported[idx] &
8658                             ELINK_SUPPORTED_2500baseX_Full) {
8659                                 sc->link_params.req_line_speed[idx] =
8660                                     ELINK_SPEED_2500;
8661                                 sc->port.advertising[idx] |=
8662                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8663                         } else {
8664                                 PMD_DRV_LOG(ERR,
8665                                             "Invalid NVRAM config link_config=0x%08x "
8666                                             "speed_cap_mask=0x%08x",
8667                                             link_config,
8668                                             sc->
8669                                             link_params.speed_cap_mask[idx]);
8670                                 return;
8671                         }
8672                         break;
8673
8674                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8675                         if (sc->port.supported[idx] &
8676                             ELINK_SUPPORTED_10000baseT_Full) {
8677                                 sc->link_params.req_line_speed[idx] =
8678                                     ELINK_SPEED_10000;
8679                                 sc->port.advertising[idx] |=
8680                                     (ADVERTISED_10000baseT_Full |
8681                                      ADVERTISED_FIBRE);
8682                         } else {
8683                                 PMD_DRV_LOG(ERR,
8684                                             "Invalid NVRAM config link_config=0x%08x "
8685                                             "speed_cap_mask=0x%08x",
8686                                             link_config,
8687                                             sc->
8688                                             link_params.speed_cap_mask[idx]);
8689                                 return;
8690                         }
8691                         break;
8692
8693                 case PORT_FEATURE_LINK_SPEED_20G:
8694                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8695                         break;
8696
8697                 default:
8698                         PMD_DRV_LOG(ERR,
8699                                     "Invalid NVRAM config link_config=0x%08x "
8700                                     "speed_cap_mask=0x%08x", link_config,
8701                                     sc->link_params.speed_cap_mask[idx]);
8702                         sc->link_params.req_line_speed[idx] =
8703                             ELINK_SPEED_AUTO_NEG;
8704                         sc->port.advertising[idx] = sc->port.supported[idx];
8705                         break;
8706                 }
8707
8708                 sc->link_params.req_flow_ctrl[idx] =
8709                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8710
8711                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8712                         if (!
8713                             (sc->
8714                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8715                                 sc->link_params.req_flow_ctrl[idx] =
8716                                     ELINK_FLOW_CTRL_NONE;
8717                         } else {
8718                                 bnx2x_set_requested_fc(sc);
8719                         }
8720                 }
8721         }
8722 }
8723
8724 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8725 {
8726         uint8_t port = SC_PORT(sc);
8727         uint32_t eee_mode;
8728
8729         PMD_INIT_FUNC_TRACE();
8730
8731         /* shmem data already read in bnx2x_get_shmem_info() */
8732
8733         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8734         bnx2x_link_settings_requested(sc);
8735
8736         /* configure link feature according to nvram value */
8737         eee_mode =
8738             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8739               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8740              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8741         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8742                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8743                                             ELINK_EEE_MODE_ENABLE_LPI |
8744                                             ELINK_EEE_MODE_OUTPUT_TIME);
8745         } else {
8746                 sc->link_params.eee_mode = 0;
8747         }
8748
8749         /* get the media type */
8750         bnx2x_media_detect(sc);
8751 }
8752
8753 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8754 {
8755         uint32_t flags = MODE_ASIC | MODE_PORT2;
8756
8757         if (CHIP_IS_E2(sc)) {
8758                 flags |= MODE_E2;
8759         } else if (CHIP_IS_E3(sc)) {
8760                 flags |= MODE_E3;
8761                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8762                         flags |= MODE_E3_A0;
8763                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8764
8765                         flags |= MODE_E3_B0 | MODE_COS3;
8766                 }
8767         }
8768
8769         if (IS_MF(sc)) {
8770                 flags |= MODE_MF;
8771                 switch (sc->devinfo.mf_info.mf_mode) {
8772                 case MULTI_FUNCTION_SD:
8773                         flags |= MODE_MF_SD;
8774                         break;
8775                 case MULTI_FUNCTION_SI:
8776                         flags |= MODE_MF_SI;
8777                         break;
8778                 case MULTI_FUNCTION_AFEX:
8779                         flags |= MODE_MF_AFEX;
8780                         break;
8781                 }
8782         } else {
8783                 flags |= MODE_SF;
8784         }
8785
8786 #if defined(__LITTLE_ENDIAN)
8787         flags |= MODE_LITTLE_ENDIAN;
8788 #else /* __BIG_ENDIAN */
8789         flags |= MODE_BIG_ENDIAN;
8790 #endif
8791
8792         INIT_MODE_FLAGS(sc) = flags;
8793 }
8794
8795 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8796 {
8797         struct bnx2x_fastpath *fp;
8798         char buf[32];
8799         uint32_t i;
8800
8801         if (IS_PF(sc)) {
8802 /************************/
8803 /* DEFAULT STATUS BLOCK */
8804 /************************/
8805
8806                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8807                                   &sc->def_sb_dma, "def_sb",
8808                                   RTE_CACHE_LINE_SIZE) != 0) {
8809                         return -1;
8810                 }
8811
8812                 sc->def_sb =
8813                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8814 /***************/
8815 /* EVENT QUEUE */
8816 /***************/
8817
8818                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8819                                   &sc->eq_dma, "ev_queue",
8820                                   RTE_CACHE_LINE_SIZE) != 0) {
8821                         sc->def_sb = NULL;
8822                         return -1;
8823                 }
8824
8825                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8826
8827 /*************/
8828 /* SLOW PATH */
8829 /*************/
8830
8831                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8832                                   &sc->sp_dma, "sp",
8833                                   RTE_CACHE_LINE_SIZE) != 0) {
8834                         sc->eq = NULL;
8835                         sc->def_sb = NULL;
8836                         return -1;
8837                 }
8838
8839                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8840
8841 /*******************/
8842 /* SLOW PATH QUEUE */
8843 /*******************/
8844
8845                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8846                                   &sc->spq_dma, "sp_queue",
8847                                   RTE_CACHE_LINE_SIZE) != 0) {
8848                         sc->sp = NULL;
8849                         sc->eq = NULL;
8850                         sc->def_sb = NULL;
8851                         return -1;
8852                 }
8853
8854                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8855
8856 /***************************/
8857 /* FW DECOMPRESSION BUFFER */
8858 /***************************/
8859
8860                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8861                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8862                         sc->spq = NULL;
8863                         sc->sp = NULL;
8864                         sc->eq = NULL;
8865                         sc->def_sb = NULL;
8866                         return -1;
8867                 }
8868
8869                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8870         }
8871
8872         /*************/
8873         /* FASTPATHS */
8874         /*************/
8875
8876         /* allocate DMA memory for each fastpath structure */
8877         for (i = 0; i < sc->num_queues; i++) {
8878                 fp = &sc->fp[i];
8879                 fp->sc = sc;
8880                 fp->index = i;
8881
8882 /*******************/
8883 /* FP STATUS BLOCK */
8884 /*******************/
8885
8886                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8887                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8888                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8889                         PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8890                         return -1;
8891                 } else {
8892                         if (CHIP_IS_E2E3(sc)) {
8893                                 fp->status_block.e2_sb =
8894                                     (struct host_hc_status_block_e2 *)
8895                                     fp->sb_dma.vaddr;
8896                         } else {
8897                                 fp->status_block.e1x_sb =
8898                                     (struct host_hc_status_block_e1x *)
8899                                     fp->sb_dma.vaddr;
8900                         }
8901                 }
8902         }
8903
8904         return 0;
8905 }
8906
8907 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8908 {
8909         struct bnx2x_fastpath *fp;
8910         int i;
8911
8912         for (i = 0; i < sc->num_queues; i++) {
8913                 fp = &sc->fp[i];
8914
8915 /*******************/
8916 /* FP STATUS BLOCK */
8917 /*******************/
8918
8919                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8920         }
8921
8922         /***************************/
8923         /* FW DECOMPRESSION BUFFER */
8924         /***************************/
8925
8926         sc->gz_buf = NULL;
8927
8928         /*******************/
8929         /* SLOW PATH QUEUE */
8930         /*******************/
8931
8932         sc->spq = NULL;
8933
8934         /*************/
8935         /* SLOW PATH */
8936         /*************/
8937
8938         sc->sp = NULL;
8939
8940         /***************/
8941         /* EVENT QUEUE */
8942         /***************/
8943
8944         sc->eq = NULL;
8945
8946         /************************/
8947         /* DEFAULT STATUS BLOCK */
8948         /************************/
8949
8950         sc->def_sb = NULL;
8951
8952 }
8953
8954 /*
8955 * Previous driver DMAE transaction may have occurred when pre-boot stage
8956 * ended and boot began. This would invalidate the addresses of the
8957 * transaction, resulting in was-error bit set in the PCI causing all
8958 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8959 * the interrupt which detected this from the pglueb and the was-done bit
8960 */
8961 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8962 {
8963         uint32_t val;
8964
8965         if (!CHIP_IS_E1x(sc)) {
8966                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8967                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8968                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8969                                1 << SC_FUNC(sc));
8970                 }
8971         }
8972 }
8973
8974 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
8975 {
8976         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
8977                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
8978         if (!rc) {
8979                 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
8980                 return -1;
8981         }
8982
8983         return 0;
8984 }
8985
8986 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
8987 {
8988         struct bnx2x_prev_list_node *tmp;
8989
8990         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
8991                 if ((sc->pcie_bus == tmp->bus) &&
8992                     (sc->pcie_device == tmp->slot) &&
8993                     (SC_PATH(sc) == tmp->path)) {
8994                         return tmp;
8995                 }
8996         }
8997
8998         return NULL;
8999 }
9000
9001 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9002 {
9003         struct bnx2x_prev_list_node *tmp;
9004         int rc = FALSE;
9005
9006         rte_spinlock_lock(&bnx2x_prev_mtx);
9007
9008         tmp = bnx2x_prev_path_get_entry(sc);
9009         if (tmp) {
9010                 if (tmp->aer) {
9011                         PMD_DRV_LOG(DEBUG,
9012                                     "Path %d/%d/%d was marked by AER",
9013                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9014                 } else {
9015                         rc = TRUE;
9016                         PMD_DRV_LOG(DEBUG,
9017                                     "Path %d/%d/%d was already cleaned from previous drivers",
9018                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9019                 }
9020         }
9021
9022         rte_spinlock_unlock(&bnx2x_prev_mtx);
9023
9024         return rc;
9025 }
9026
9027 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9028 {
9029         struct bnx2x_prev_list_node *tmp;
9030
9031         rte_spinlock_lock(&bnx2x_prev_mtx);
9032
9033         /* Check whether the entry for this path already exists */
9034         tmp = bnx2x_prev_path_get_entry(sc);
9035         if (tmp) {
9036                 if (!tmp->aer) {
9037                         PMD_DRV_LOG(DEBUG,
9038                                     "Re-marking AER in path %d/%d/%d",
9039                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9040                 } else {
9041                         PMD_DRV_LOG(DEBUG,
9042                                     "Removing AER indication from path %d/%d/%d",
9043                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9044                         tmp->aer = 0;
9045                 }
9046
9047                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9048                 return 0;
9049         }
9050
9051         rte_spinlock_unlock(&bnx2x_prev_mtx);
9052
9053         /* Create an entry for this path and add it */
9054         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9055                          RTE_CACHE_LINE_SIZE);
9056         if (!tmp) {
9057                 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9058                 return -1;
9059         }
9060
9061         tmp->bus = sc->pcie_bus;
9062         tmp->slot = sc->pcie_device;
9063         tmp->path = SC_PATH(sc);
9064         tmp->aer = 0;
9065         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9066
9067         rte_spinlock_lock(&bnx2x_prev_mtx);
9068
9069         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9070
9071         rte_spinlock_unlock(&bnx2x_prev_mtx);
9072
9073         return 0;
9074 }
9075
9076 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9077 {
9078         int i;
9079
9080         /* only E2 and onwards support FLR */
9081         if (CHIP_IS_E1x(sc)) {
9082                 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9083                 return -1;
9084         }
9085
9086         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9087         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9088                 PMD_DRV_LOG(WARNING,
9089                             "FLR not supported by BC_VER: 0x%08x",
9090                             sc->devinfo.bc_ver);
9091                 return -1;
9092         }
9093
9094         /* Wait for Transaction Pending bit clean */
9095         for (i = 0; i < 4; i++) {
9096                 if (i) {
9097                         DELAY(((1 << (i - 1)) * 100) * 1000);
9098                 }
9099
9100                 if (!bnx2x_is_pcie_pending(sc)) {
9101                         goto clear;
9102                 }
9103         }
9104
9105         PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9106                     "proceeding with reset anyway");
9107
9108 clear:
9109         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9110
9111         return 0;
9112 }
9113
9114 struct bnx2x_mac_vals {
9115         uint32_t xmac_addr;
9116         uint32_t xmac_val;
9117         uint32_t emac_addr;
9118         uint32_t emac_val;
9119         uint32_t umac_addr;
9120         uint32_t umac_val;
9121         uint32_t bmac_addr;
9122         uint32_t bmac_val[2];
9123 };
9124
9125 static void
9126 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9127 {
9128         uint32_t val, base_addr, offset, mask, reset_reg;
9129         uint8_t mac_stopped = FALSE;
9130         uint8_t port = SC_PORT(sc);
9131         uint32_t wb_data[2];
9132
9133         /* reset addresses as they also mark which values were changed */
9134         vals->bmac_addr = 0;
9135         vals->umac_addr = 0;
9136         vals->xmac_addr = 0;
9137         vals->emac_addr = 0;
9138
9139         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9140
9141         if (!CHIP_IS_E3(sc)) {
9142                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9143                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9144                 if ((mask & reset_reg) && val) {
9145                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9146                             : NIG_REG_INGRESS_BMAC0_MEM;
9147                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9148                             : BIGMAC_REGISTER_BMAC_CONTROL;
9149
9150                         /*
9151                          * use rd/wr since we cannot use dmae. This is safe
9152                          * since MCP won't access the bus due to the request
9153                          * to unload, and no function on the path can be
9154                          * loaded at this time.
9155                          */
9156                         wb_data[0] = REG_RD(sc, base_addr + offset);
9157                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9158                         vals->bmac_addr = base_addr + offset;
9159                         vals->bmac_val[0] = wb_data[0];
9160                         vals->bmac_val[1] = wb_data[1];
9161                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9162                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9163                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9164                 }
9165
9166                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9167                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9168                 REG_WR(sc, vals->emac_addr, 0);
9169                 mac_stopped = TRUE;
9170         } else {
9171                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9172                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9173                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9174                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9175                                val & ~(1 << 1));
9176                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9177                                val | (1 << 1));
9178                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9179                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9180                         REG_WR(sc, vals->xmac_addr, 0);
9181                         mac_stopped = TRUE;
9182                 }
9183
9184                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9185                 if (mask & reset_reg) {
9186                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9187                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9188                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9189                         REG_WR(sc, vals->umac_addr, 0);
9190                         mac_stopped = TRUE;
9191                 }
9192         }
9193
9194         if (mac_stopped) {
9195                 DELAY(20000);
9196         }
9197 }
9198
9199 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9200 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9201 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9202 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9203
9204 static void
9205 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9206 {
9207         uint16_t rcq, bd;
9208         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9209
9210         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9211         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9212
9213         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9214         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9215 }
9216
9217 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9218 {
9219         uint32_t reset_reg, tmp_reg = 0, rc;
9220         uint8_t prev_undi = FALSE;
9221         struct bnx2x_mac_vals mac_vals;
9222         uint32_t timer_count = 1000;
9223         uint32_t prev_brb;
9224
9225         /*
9226          * It is possible a previous function received 'common' answer,
9227          * but hasn't loaded yet, therefore creating a scenario of
9228          * multiple functions receiving 'common' on the same path.
9229          */
9230         memset(&mac_vals, 0, sizeof(mac_vals));
9231
9232         if (bnx2x_prev_is_path_marked(sc)) {
9233                 return bnx2x_prev_mcp_done(sc);
9234         }
9235
9236         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9237
9238         /* Reset should be performed after BRB is emptied */
9239         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9240                 /* Close the MAC Rx to prevent BRB from filling up */
9241                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9242
9243                 /* close LLH filters towards the BRB */
9244                 elink_set_rx_filter(&sc->link_params, 0);
9245
9246                 /*
9247                  * Check if the UNDI driver was previously loaded.
9248                  * UNDI driver initializes CID offset for normal bell to 0x7
9249                  */
9250                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9251                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9252                         if (tmp_reg == 0x7) {
9253                                 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9254                                 prev_undi = TRUE;
9255                                 /* clear the UNDI indication */
9256                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9257                                 /* clear possible idle check errors */
9258                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9259                         }
9260                 }
9261
9262                 /* wait until BRB is empty */
9263                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9264                 while (timer_count) {
9265                         prev_brb = tmp_reg;
9266
9267                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9268                         if (!tmp_reg) {
9269                                 break;
9270                         }
9271
9272                         PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9273
9274                         /* reset timer as long as BRB actually gets emptied */
9275                         if (prev_brb > tmp_reg) {
9276                                 timer_count = 1000;
9277                         } else {
9278                                 timer_count--;
9279                         }
9280
9281                         /* If UNDI resides in memory, manually increment it */
9282                         if (prev_undi) {
9283                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9284                         }
9285
9286                         DELAY(10);
9287                 }
9288
9289                 if (!timer_count) {
9290                         PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9291                 }
9292         }
9293
9294         /* No packets are in the pipeline, path is ready for reset */
9295         bnx2x_reset_common(sc);
9296
9297         if (mac_vals.xmac_addr) {
9298                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9299         }
9300         if (mac_vals.umac_addr) {
9301                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9302         }
9303         if (mac_vals.emac_addr) {
9304                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9305         }
9306         if (mac_vals.bmac_addr) {
9307                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9308                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9309         }
9310
9311         rc = bnx2x_prev_mark_path(sc, prev_undi);
9312         if (rc) {
9313                 bnx2x_prev_mcp_done(sc);
9314                 return rc;
9315         }
9316
9317         return bnx2x_prev_mcp_done(sc);
9318 }
9319
9320 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9321 {
9322         int rc;
9323
9324         /* Test if previous unload process was already finished for this path */
9325         if (bnx2x_prev_is_path_marked(sc)) {
9326                 return bnx2x_prev_mcp_done(sc);
9327         }
9328
9329         /*
9330          * If function has FLR capabilities, and existing FW version matches
9331          * the one required, then FLR will be sufficient to clean any residue
9332          * left by previous driver
9333          */
9334         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9335         if (!rc) {
9336                 /* fw version is good */
9337                 rc = bnx2x_do_flr(sc);
9338         }
9339
9340         if (!rc) {
9341                 /* FLR was performed */
9342                 return 0;
9343         }
9344
9345         PMD_DRV_LOG(INFO, "Could not FLR");
9346
9347         /* Close the MCP request, return failure */
9348         rc = bnx2x_prev_mcp_done(sc);
9349         if (!rc) {
9350                 rc = BNX2X_PREV_WAIT_NEEDED;
9351         }
9352
9353         return rc;
9354 }
9355
9356 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9357 {
9358         int time_counter = 10;
9359         uint32_t fw, hw_lock_reg, hw_lock_val;
9360         uint32_t rc = 0;
9361
9362         /*
9363          * Clear HW from errors which may have resulted from an interrupted
9364          * DMAE transaction.
9365          */
9366         bnx2x_prev_interrupted_dmae(sc);
9367
9368         /* Release previously held locks */
9369         if (SC_FUNC(sc) <= 5)
9370                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9371         else
9372                 hw_lock_reg =
9373                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9374
9375         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9376         if (hw_lock_val) {
9377                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9378                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9379                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9380                 }
9381                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9382         }
9383
9384         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9385                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9386         }
9387
9388         do {
9389                 /* Lock MCP using an unload request */
9390                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9391                 if (!fw) {
9392                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9393                         rc = -1;
9394                         break;
9395                 }
9396
9397                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9398                         rc = bnx2x_prev_unload_common(sc);
9399                         break;
9400                 }
9401
9402                 /* non-common reply from MCP might require looping */
9403                 rc = bnx2x_prev_unload_uncommon(sc);
9404                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9405                         break;
9406                 }
9407
9408                 DELAY(20000);
9409         } while (--time_counter);
9410
9411         if (!time_counter || rc) {
9412                 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9413                 rc = -1;
9414         }
9415
9416         return rc;
9417 }
9418
9419 static void
9420 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9421 {
9422         if (!CHIP_IS_E1x(sc)) {
9423                 sc->dcb_state = dcb_on;
9424                 sc->dcbx_enabled = dcbx_enabled;
9425         } else {
9426                 sc->dcb_state = FALSE;
9427                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9428         }
9429         PMD_DRV_LOG(DEBUG,
9430                     "DCB state [%s:%s]",
9431                     dcb_on ? "ON" : "OFF",
9432                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9433                     (dcbx_enabled ==
9434                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9435                     : (dcbx_enabled ==
9436                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9437                     "on-chip with negotiation" : "invalid");
9438 }
9439
9440 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9441 {
9442         int cid_count = BNX2X_L2_MAX_CID(sc);
9443
9444         if (CNIC_SUPPORT(sc)) {
9445                 cid_count += CNIC_CID_MAX;
9446         }
9447
9448         return roundup(cid_count, QM_CID_ROUND);
9449 }
9450
9451 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9452 {
9453         int pri, cos;
9454
9455         uint32_t pri_map = 0;
9456
9457         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9458                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9459                 if (cos < sc->max_cos) {
9460                         sc->prio_to_cos[pri] = cos;
9461                 } else {
9462                         PMD_DRV_LOG(WARNING,
9463                                     "Invalid COS %d for priority %d "
9464                                     "(max COS is %d), setting to 0", cos, pri,
9465                                     (sc->max_cos - 1));
9466                         sc->prio_to_cos[pri] = 0;
9467                 }
9468         }
9469 }
9470
9471 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9472 {
9473         struct {
9474                 uint8_t id;
9475                 uint8_t next;
9476         } pci_cap;
9477         uint16_t status;
9478         struct bnx2x_pci_cap *cap;
9479
9480         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9481                                          RTE_CACHE_LINE_SIZE);
9482         if (!cap) {
9483                 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9484                 return -ENOMEM;
9485         }
9486
9487 #ifndef __FreeBSD__
9488         pci_read(sc, PCI_STATUS, &status, 2);
9489         if (!(status & PCI_STATUS_CAP_LIST)) {
9490 #else
9491         pci_read(sc, PCIR_STATUS, &status, 2);
9492         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9493 #endif
9494                 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9495                 return -1;
9496         }
9497
9498 #ifndef __FreeBSD__
9499         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9500 #else
9501         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9502 #endif
9503         while (pci_cap.next) {
9504                 cap->addr = pci_cap.next & ~3;
9505                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9506                 if (pci_cap.id == 0xff)
9507                         break;
9508                 cap->id = pci_cap.id;
9509                 cap->type = BNX2X_PCI_CAP;
9510                 cap->next = rte_zmalloc("pci_cap",
9511                                         sizeof(struct bnx2x_pci_cap),
9512                                         RTE_CACHE_LINE_SIZE);
9513                 if (!cap->next) {
9514                         PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9515                         return -ENOMEM;
9516                 }
9517                 cap = cap->next;
9518         }
9519
9520         return 0;
9521 }
9522
9523 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9524 {
9525         if (IS_VF(sc)) {
9526                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9527                                         sc->igu_sb_cnt);
9528                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9529                                         sc->igu_sb_cnt);
9530         } else {
9531                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9532                 sc->max_tx_queues = sc->max_rx_queues;
9533         }
9534 }
9535
9536 #define FW_HEADER_LEN 104
9537 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9538 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9539
9540 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9541 {
9542         const char *fwname;
9543         int f;
9544         struct stat st;
9545
9546         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9547                 ? FW_NAME_57711 : FW_NAME_57810;
9548         f = open(fwname, O_RDONLY);
9549         if (f < 0) {
9550                 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9551                 return;
9552         }
9553
9554         if (fstat(f, &st) < 0) {
9555                 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9556                 close(f);
9557                 return;
9558         }
9559
9560         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9561         if (!sc->firmware) {
9562                 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9563                 close(f);
9564                 return;
9565         }
9566
9567         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9568                 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9569                 close(f);
9570                 return;
9571         }
9572         close(f);
9573
9574         sc->fw_len = st.st_size;
9575         if (sc->fw_len < FW_HEADER_LEN) {
9576                 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9577                 return;
9578         }
9579         PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9580 }
9581
9582 static void
9583 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9584 {
9585         uint32_t *src = (uint32_t *) data;
9586         uint32_t i, j, tmp;
9587
9588         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9589                 tmp = rte_be_to_cpu_32(src[j]);
9590                 dst[i].op = (tmp >> 24) & 0xFF;
9591                 dst[i].offset = tmp & 0xFFFFFF;
9592                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9593         }
9594 }
9595
9596 static void
9597 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9598 {
9599         uint16_t *src = (uint16_t *) data;
9600         uint32_t i;
9601
9602         for (i = 0; i < len / 2; ++i)
9603                 dst[i] = rte_be_to_cpu_16(src[i]);
9604 }
9605
9606 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9607 {
9608         uint32_t *src = (uint32_t *) data;
9609         uint32_t i;
9610
9611         for (i = 0; i < len / 4; ++i)
9612                 dst[i] = rte_be_to_cpu_32(src[i]);
9613 }
9614
9615 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9616 {
9617         uint32_t *src = (uint32_t *) data;
9618         uint32_t i, j, tmp;
9619
9620         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9621                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9622                 tmp = rte_be_to_cpu_32(src[j]);
9623                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9624                 dst[i].m2 = tmp & 0xFFFF;
9625                 ++j;
9626                 tmp = rte_be_to_cpu_32(src[j]);
9627                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9628                 dst[i].size = tmp & 0xFFFF;
9629         }
9630 }
9631
9632 /*
9633 * Device attach function.
9634 *
9635 * Allocates device resources, performs secondary chip identification, and
9636 * initializes driver instance variables. This function is called from driver
9637 * load after a successful probe.
9638 *
9639 * Returns:
9640 *   0 = Success, >0 = Failure
9641 */
9642 int bnx2x_attach(struct bnx2x_softc *sc)
9643 {
9644         int rc;
9645
9646         PMD_DRV_LOG(DEBUG, "Starting attach...");
9647
9648         rc = bnx2x_pci_get_caps(sc);
9649         if (rc) {
9650                 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9651                 return rc;
9652         }
9653
9654         sc->state = BNX2X_STATE_CLOSED;
9655
9656         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9657
9658         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9659
9660         /* get PCI capabilites */
9661         bnx2x_probe_pci_caps(sc);
9662
9663         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9664                 uint32_t val;
9665                 pci_read(sc,
9666                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9667                          2);
9668                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9669         } else {
9670                 sc->igu_sb_cnt = 1;
9671         }
9672
9673         /* Init RTE stuff */
9674         bnx2x_init_rte(sc);
9675
9676         if (IS_PF(sc)) {
9677 /* get device info and set params */
9678                 if (bnx2x_get_device_info(sc) != 0) {
9679                         PMD_DRV_LOG(NOTICE, "getting device info");
9680                         return -ENXIO;
9681                 }
9682
9683 /* get phy settings from shmem and 'and' against admin settings */
9684                 bnx2x_get_phy_info(sc);
9685         } else {
9686 /* Left mac of VF unfilled, PF should set it for VF */
9687                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9688         }
9689
9690         sc->wol = 0;
9691
9692         /* set the default MTU (changed via ifconfig) */
9693         sc->mtu = ETHER_MTU;
9694
9695         bnx2x_set_modes_bitmap(sc);
9696
9697         /* need to reset chip if UNDI was active */
9698         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9699 /* init fw_seq */
9700                 sc->fw_seq =
9701                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9702                      DRV_MSG_SEQ_NUMBER_MASK);
9703                 bnx2x_prev_unload(sc);
9704         }
9705
9706         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9707
9708         /* calculate qm_cid_count */
9709         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9710
9711         sc->max_cos = 1;
9712         bnx2x_init_multi_cos(sc);
9713
9714         return 0;
9715 }
9716
9717 static void
9718 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9719                uint16_t index, uint8_t op, uint8_t update)
9720 {
9721         uint32_t igu_addr = sc->igu_base_addr;
9722         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9723         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9724 }
9725
9726 static void
9727 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9728            uint16_t index, uint8_t op, uint8_t update)
9729 {
9730         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9731                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9732         else {
9733                 uint8_t segment;
9734                 if (CHIP_INT_MODE_IS_BC(sc)) {
9735                         segment = storm;
9736                 } else if (igu_sb_id != sc->igu_dsb_id) {
9737                         segment = IGU_SEG_ACCESS_DEF;
9738                 } else if (storm == ATTENTION_ID) {
9739                         segment = IGU_SEG_ACCESS_ATTN;
9740                 } else {
9741                         segment = IGU_SEG_ACCESS_DEF;
9742                 }
9743                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9744         }
9745 }
9746
9747 static void
9748 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9749                      uint8_t is_pf)
9750 {
9751         uint32_t data, ctl, cnt = 100;
9752         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9753         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9754         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9755             (idu_sb_id / 32) * 4;
9756         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9757         uint32_t func_encode = func |
9758             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9759         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9760
9761         /* Not supported in BC mode */
9762         if (CHIP_INT_MODE_IS_BC(sc)) {
9763                 return;
9764         }
9765
9766         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9767                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9768                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9769
9770         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9771                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9772                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9773
9774         REG_WR(sc, igu_addr_data, data);
9775
9776         mb();
9777
9778         PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9779                     ctl, igu_addr_ctl);
9780         REG_WR(sc, igu_addr_ctl, ctl);
9781
9782         mb();
9783
9784         /* wait for clean up to finish */
9785         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9786                 DELAY(20000);
9787         }
9788
9789         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9790                 PMD_DRV_LOG(DEBUG,
9791                             "Unable to finish IGU cleanup: "
9792                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9793                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9794         }
9795 }
9796
9797 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9798 {
9799         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9800 }
9801
9802 /*******************/
9803 /* ECORE CALLBACKS */
9804 /*******************/
9805
9806 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9807 {
9808         uint32_t val = 0x1400;
9809
9810         PMD_INIT_FUNC_TRACE();
9811
9812         /* reset_common */
9813         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9814                0xd3ffff7f);
9815
9816         if (CHIP_IS_E3(sc)) {
9817                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9818                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9819         }
9820
9821         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9822 }
9823
9824 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9825 {
9826         uint32_t shmem_base[2];
9827         uint32_t shmem2_base[2];
9828
9829         /* Avoid common init in case MFW supports LFA */
9830         if (SHMEM2_RD(sc, size) >
9831             (uint32_t) offsetof(struct shmem2_region,
9832                                 lfa_host_addr[SC_PORT(sc)])) {
9833                 return;
9834         }
9835
9836         shmem_base[0] = sc->devinfo.shmem_base;
9837         shmem2_base[0] = sc->devinfo.shmem2_base;
9838
9839         if (!CHIP_IS_E1x(sc)) {
9840                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9841                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9842         }
9843
9844         elink_common_init_phy(sc, shmem_base, shmem2_base,
9845                               sc->devinfo.chip_id, 0);
9846 }
9847
9848 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9849 {
9850         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9851
9852         val &= ~IGU_PF_CONF_FUNC_EN;
9853
9854         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9855         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9856         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9857 }
9858
9859 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9860 {
9861         uint16_t devctl;
9862         int r_order, w_order;
9863
9864         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9865
9866         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9867         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9868
9869         ecore_init_pxp_arb(sc, r_order, w_order);
9870 }
9871
9872 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9873 {
9874         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9875         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9876         return base + (SC_ABS_FUNC(sc)) * stride;
9877 }
9878
9879 /*
9880  * Called only on E1H or E2.
9881  * When pretending to be PF, the pretend value is the function number 0..7.
9882  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9883  * combination.
9884  */
9885 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9886 {
9887         uint32_t pretend_reg;
9888
9889         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9890                 return -1;
9891
9892         /* get my own pretend register */
9893         pretend_reg = bnx2x_get_pretend_reg(sc);
9894         REG_WR(sc, pretend_reg, pretend_func_val);
9895         REG_RD(sc, pretend_reg);
9896         return 0;
9897 }
9898
9899 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9900 {
9901         int is_required;
9902         uint32_t val;
9903         int port;
9904
9905         is_required = 0;
9906         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9907                SHARED_HW_CFG_FAN_FAILURE_MASK);
9908
9909         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9910                 is_required = 1;
9911         }
9912         /*
9913          * The fan failure mechanism is usually related to the PHY type since
9914          * the power consumption of the board is affected by the PHY. Currently,
9915          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9916          */
9917         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9918                 for (port = PORT_0; port < PORT_MAX; port++) {
9919                         is_required |= elink_fan_failure_det_req(sc,
9920                                                                  sc->
9921                                                                  devinfo.shmem_base,
9922                                                                  sc->
9923                                                                  devinfo.shmem2_base,
9924                                                                  port);
9925                 }
9926         }
9927
9928         if (is_required == 0) {
9929                 return;
9930         }
9931
9932         /* Fan failure is indicated by SPIO 5 */
9933         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9934
9935         /* set to active low mode */
9936         val = REG_RD(sc, MISC_REG_SPIO_INT);
9937         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9938         REG_WR(sc, MISC_REG_SPIO_INT, val);
9939
9940         /* enable interrupt to signal the IGU */
9941         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9942         val |= MISC_SPIO_SPIO5;
9943         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9944 }
9945
9946 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9947 {
9948         uint32_t val;
9949
9950         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9951         if (!CHIP_IS_E1x(sc)) {
9952                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9953         } else {
9954                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9955         }
9956         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9957         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9958         /*
9959          * mask read length error interrupts in brb for parser
9960          * (parsing unit and 'checksum and crc' unit)
9961          * these errors are legal (PU reads fixed length and CAC can cause
9962          * read length error on truncated packets)
9963          */
9964         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9965         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9966         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9967         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9968         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9969         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9970         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9971         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9972         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9973         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
9974         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
9975         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
9976         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
9977         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
9978         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
9979         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
9980         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
9981         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
9982         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
9983
9984         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
9985                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
9986                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
9987         if (!CHIP_IS_E1x(sc)) {
9988                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
9989                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
9990         }
9991         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
9992
9993         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
9994         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
9995         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
9996         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
9997
9998         if (!CHIP_IS_E1x(sc)) {
9999 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10000                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10001         }
10002
10003         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10004         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10005         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10006         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10007 }
10008
10009 /**
10010  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10011  *
10012  * @sc:     driver handle
10013  */
10014 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10015 {
10016         uint8_t abs_func_id;
10017         uint32_t val;
10018
10019         PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10020
10021         /*
10022          * take the RESET lock to protect undi_unload flow from accessing
10023          * registers while we are resetting the chip
10024          */
10025         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10026
10027         bnx2x_reset_common(sc);
10028
10029         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10030
10031         val = 0xfffc;
10032         if (CHIP_IS_E3(sc)) {
10033                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10034                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10035         }
10036
10037         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10038
10039         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10040
10041         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10042
10043         if (!CHIP_IS_E1x(sc)) {
10044 /*
10045  * 4-port mode or 2-port mode we need to turn off master-enable for
10046  * everyone. After that we turn it back on for self. So, we disregard
10047  * multi-function, and always disable all functions on the given path,
10048  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10049  */
10050                 for (abs_func_id = SC_PATH(sc);
10051                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10052                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10053                                 REG_WR(sc,
10054                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10055                                        1);
10056                                 continue;
10057                         }
10058
10059                         bnx2x_pretend_func(sc, abs_func_id);
10060
10061                         /* clear pf enable */
10062                         bnx2x_pf_disable(sc);
10063
10064                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10065                 }
10066         }
10067
10068         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10069
10070         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10071         bnx2x_init_pxp(sc);
10072
10073 #ifdef __BIG_ENDIAN
10074         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10075         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10076         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10077         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10078         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10079         /* make sure this value is 0 */
10080         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10081
10082         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10083         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10084         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10085         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10086         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10087 #endif
10088
10089         ecore_ilt_init_page_size(sc, INITOP_SET);
10090
10091         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10092                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10093         }
10094
10095         /* let the HW do it's magic... */
10096         DELAY(100000);
10097
10098         /* finish PXP init */
10099
10100         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10101         if (val != 1) {
10102                 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10103                 return -1;
10104         }
10105         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10106         if (val != 1) {
10107                 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10108                 return -1;
10109         }
10110
10111         /*
10112          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10113          * entries with value "0" and valid bit on. This needs to be done by the
10114          * first PF that is loaded in a path (i.e. common phase)
10115          */
10116         if (!CHIP_IS_E1x(sc)) {
10117 /*
10118  * In E2 there is a bug in the timers block that can cause function 6 / 7
10119  * (i.e. vnic3) to start even if it is marked as "scan-off".
10120  * This occurs when a different function (func2,3) is being marked
10121  * as "scan-off". Real-life scenario for example: if a driver is being
10122  * load-unloaded while func6,7 are down. This will cause the timer to access
10123  * the ilt, translate to a logical address and send a request to read/write.
10124  * Since the ilt for the function that is down is not valid, this will cause
10125  * a translation error which is unrecoverable.
10126  * The Workaround is intended to make sure that when this happens nothing
10127  * fatal will occur. The workaround:
10128  *  1.  First PF driver which loads on a path will:
10129  *      a.  After taking the chip out of reset, by using pretend,
10130  *          it will write "0" to the following registers of
10131  *          the other vnics.
10132  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10133  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10134  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10135  *          And for itself it will write '1' to
10136  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10137  *          dmae-operations (writing to pram for example.)
10138  *          note: can be done for only function 6,7 but cleaner this
10139  *            way.
10140  *      b.  Write zero+valid to the entire ILT.
10141  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10142  *          VNIC3 (of that port). The range allocated will be the
10143  *          entire ILT. This is needed to prevent  ILT range error.
10144  *  2.  Any PF driver load flow:
10145  *      a.  ILT update with the physical addresses of the allocated
10146  *          logical pages.
10147  *      b.  Wait 20msec. - note that this timeout is needed to make
10148  *          sure there are no requests in one of the PXP internal
10149  *          queues with "old" ILT addresses.
10150  *      c.  PF enable in the PGLC.
10151  *      d.  Clear the was_error of the PF in the PGLC. (could have
10152  *          occurred while driver was down)
10153  *      e.  PF enable in the CFC (WEAK + STRONG)
10154  *      f.  Timers scan enable
10155  *  3.  PF driver unload flow:
10156  *      a.  Clear the Timers scan_en.
10157  *      b.  Polling for scan_on=0 for that PF.
10158  *      c.  Clear the PF enable bit in the PXP.
10159  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10160  *      e.  Write zero+valid to all ILT entries (The valid bit must
10161  *          stay set)
10162  *      f.  If this is VNIC 3 of a port then also init
10163  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10164  *          to the last enrty in the ILT.
10165  *
10166  *      Notes:
10167  *      Currently the PF error in the PGLC is non recoverable.
10168  *      In the future the there will be a recovery routine for this error.
10169  *      Currently attention is masked.
10170  *      Having an MCP lock on the load/unload process does not guarantee that
10171  *      there is no Timer disable during Func6/7 enable. This is because the
10172  *      Timers scan is currently being cleared by the MCP on FLR.
10173  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10174  *      there is error before clearing it. But the flow above is simpler and
10175  *      more general.
10176  *      All ILT entries are written by zero+valid and not just PF6/7
10177  *      ILT entries since in the future the ILT entries allocation for
10178  *      PF-s might be dynamic.
10179  */
10180                 struct ilt_client_info ilt_cli;
10181                 struct ecore_ilt ilt;
10182
10183                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10184                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10185
10186 /* initialize dummy TM client */
10187                 ilt_cli.start = 0;
10188                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10189                 ilt_cli.client_num = ILT_CLIENT_TM;
10190
10191 /*
10192  * Step 1: set zeroes to all ilt page entries with valid bit on
10193  * Step 2: set the timers first/last ilt entry to point
10194  * to the entire range to prevent ILT range error for 3rd/4th
10195  * vnic (this code assumes existence of the vnic)
10196  *
10197  * both steps performed by call to ecore_ilt_client_init_op()
10198  * with dummy TM client
10199  *
10200  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10201  * and his brother are split registers
10202  */
10203
10204                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10205                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10206                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10207
10208                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10209                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10210                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10211         }
10212
10213         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10214         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10215
10216         if (!CHIP_IS_E1x(sc)) {
10217                 int factor = 0;
10218
10219                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10220                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10221
10222 /* let the HW do it's magic... */
10223                 do {
10224                         DELAY(200000);
10225                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10226                 } while (factor-- && (val != 1));
10227
10228                 if (val != 1) {
10229                         PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10230                         return -1;
10231                 }
10232         }
10233
10234         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10235
10236         /* clean the DMAE memory */
10237         sc->dmae_ready = 1;
10238         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10239
10240         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10241
10242         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10243
10244         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10245
10246         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10247
10248         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10249         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10250         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10251         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10252
10253         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10254
10255         /* QM queues pointers table */
10256         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10257
10258         /* soft reset pulse */
10259         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10260         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10261
10262         if (CNIC_SUPPORT(sc))
10263                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10264
10265         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10266         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10267
10268         if (!CHIP_REV_IS_SLOW(sc)) {
10269 /* enable hw interrupt from doorbell Q */
10270                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10271         }
10272
10273         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10274
10275         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10276         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10277         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10278
10279         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10280                 if (IS_MF_AFEX(sc)) {
10281                         /*
10282                          * configure that AFEX and VLAN headers must be
10283                          * received in AFEX mode
10284                          */
10285                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10286                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10287                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10288                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10289                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10290                 } else {
10291                         /*
10292                          * Bit-map indicating which L2 hdrs may appear
10293                          * after the basic Ethernet header
10294                          */
10295                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10296                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10297                 }
10298         }
10299
10300         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10301         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10302         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10303         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10304
10305         if (!CHIP_IS_E1x(sc)) {
10306 /* reset VFC memories */
10307                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10308                        VFC_MEMORIES_RST_REG_CAM_RST |
10309                        VFC_MEMORIES_RST_REG_RAM_RST);
10310                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10311                        VFC_MEMORIES_RST_REG_CAM_RST |
10312                        VFC_MEMORIES_RST_REG_RAM_RST);
10313
10314                 DELAY(20000);
10315         }
10316
10317         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10318         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10319         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10320         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10321
10322         /* sync semi rtc */
10323         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10324         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10325
10326         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10327         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10328         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10329
10330         if (!CHIP_IS_E1x(sc)) {
10331                 if (IS_MF_AFEX(sc)) {
10332                         /*
10333                          * configure that AFEX and VLAN headers must be
10334                          * sent in AFEX mode
10335                          */
10336                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10337                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10338                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10339                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10340                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10341                 } else {
10342                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10343                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10344                 }
10345         }
10346
10347         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10348
10349         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10350
10351         if (CNIC_SUPPORT(sc)) {
10352                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10353                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10354                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10355                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10356                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10357                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10358                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10359                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10360                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10361                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10362         }
10363         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10364
10365         if (sizeof(union cdu_context) != 1024) {
10366 /* we currently assume that a context is 1024 bytes */
10367                 PMD_DRV_LOG(NOTICE,
10368                             "please adjust the size of cdu_context(%ld)",
10369                             (long)sizeof(union cdu_context));
10370         }
10371
10372         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10373         val = (4 << 24) + (0 << 12) + 1024;
10374         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10375
10376         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10377
10378         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10379         /* enable context validation interrupt from CFC */
10380         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10381
10382         /* set the thresholds to prevent CFC/CDU race */
10383         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10384         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10385
10386         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10387                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10388         }
10389
10390         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10391         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10392
10393         /* Reset PCIE errors for debug */
10394         REG_WR(sc, 0x2814, 0xffffffff);
10395         REG_WR(sc, 0x3820, 0xffffffff);
10396
10397         if (!CHIP_IS_E1x(sc)) {
10398                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10399                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10400                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10401                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10402                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10403                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10404                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10405                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10406                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10407                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10408                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10409         }
10410
10411         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10412
10413         /* in E3 this done in per-port section */
10414         if (!CHIP_IS_E3(sc))
10415                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10416
10417         if (CHIP_IS_E1H(sc)) {
10418 /* not applicable for E2 (and above ...) */
10419                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10420         }
10421
10422         if (CHIP_REV_IS_SLOW(sc)) {
10423                 DELAY(200000);
10424         }
10425
10426         /* finish CFC init */
10427         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10428         if (val != 1) {
10429                 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10430                 return -1;
10431         }
10432         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10433         if (val != 1) {
10434                 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10435                 return -1;
10436         }
10437         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10438         if (val != 1) {
10439                 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10440                 return -1;
10441         }
10442         REG_WR(sc, CFC_REG_DEBUG0, 0);
10443
10444         bnx2x_setup_fan_failure_detection(sc);
10445
10446         /* clear PXP2 attentions */
10447         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10448
10449         bnx2x_enable_blocks_attention(sc);
10450
10451         if (!CHIP_REV_IS_SLOW(sc)) {
10452                 ecore_enable_blocks_parity(sc);
10453         }
10454
10455         if (!BNX2X_NOMCP(sc)) {
10456                 if (CHIP_IS_E1x(sc)) {
10457                         bnx2x_common_init_phy(sc);
10458                 }
10459         }
10460
10461         return 0;
10462 }
10463
10464 /**
10465  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10466  *
10467  * @sc:     driver handle
10468  */
10469 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10470 {
10471         int rc = bnx2x_init_hw_common(sc);
10472
10473         if (rc) {
10474                 return rc;
10475         }
10476
10477         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10478         if (!BNX2X_NOMCP(sc)) {
10479                 bnx2x_common_init_phy(sc);
10480         }
10481
10482         return 0;
10483 }
10484
10485 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10486 {
10487         int port = SC_PORT(sc);
10488         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10489         uint32_t low, high;
10490         uint32_t val;
10491
10492         PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10493
10494         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10495
10496         ecore_init_block(sc, BLOCK_MISC, init_phase);
10497         ecore_init_block(sc, BLOCK_PXP, init_phase);
10498         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10499
10500         /*
10501          * Timers bug workaround: disables the pf_master bit in pglue at
10502          * common phase, we need to enable it here before any dmae access are
10503          * attempted. Therefore we manually added the enable-master to the
10504          * port phase (it also happens in the function phase)
10505          */
10506         if (!CHIP_IS_E1x(sc)) {
10507                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10508         }
10509
10510         ecore_init_block(sc, BLOCK_ATC, init_phase);
10511         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10512         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10513         ecore_init_block(sc, BLOCK_QM, init_phase);
10514
10515         ecore_init_block(sc, BLOCK_TCM, init_phase);
10516         ecore_init_block(sc, BLOCK_UCM, init_phase);
10517         ecore_init_block(sc, BLOCK_CCM, init_phase);
10518         ecore_init_block(sc, BLOCK_XCM, init_phase);
10519
10520         /* QM cid (connection) count */
10521         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10522
10523         if (CNIC_SUPPORT(sc)) {
10524                 ecore_init_block(sc, BLOCK_TM, init_phase);
10525                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10526                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10527         }
10528
10529         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10530
10531         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10532
10533         if (CHIP_IS_E1H(sc)) {
10534                 if (IS_MF(sc)) {
10535                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10536                 } else if (sc->mtu > 4096) {
10537                         if (BNX2X_ONE_PORT(sc)) {
10538                                 low = 160;
10539                         } else {
10540                                 val = sc->mtu;
10541                                 /* (24*1024 + val*4)/256 */
10542                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10543                         }
10544                 } else {
10545                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10546                 }
10547                 high = (low + 56);      /* 14*1024/256 */
10548                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10549                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10550         }
10551
10552         if (CHIP_IS_MODE_4_PORT(sc)) {
10553                 REG_WR(sc, SC_PORT(sc) ?
10554                        BRB1_REG_MAC_GUARANTIED_1 :
10555                        BRB1_REG_MAC_GUARANTIED_0, 40);
10556         }
10557
10558         ecore_init_block(sc, BLOCK_PRS, init_phase);
10559         if (CHIP_IS_E3B0(sc)) {
10560                 if (IS_MF_AFEX(sc)) {
10561                         /* configure headers for AFEX mode */
10562                         if (SC_PORT(sc)) {
10563                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10564                                        0xE);
10565                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10566                                        0x6);
10567                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10568                         } else {
10569                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10570                                        0xE);
10571                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10572                                        0x6);
10573                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10574                         }
10575                 } else {
10576                         /* Ovlan exists only if we are in multi-function +
10577                          * switch-dependent mode, in switch-independent there
10578                          * is no ovlan headers
10579                          */
10580                         REG_WR(sc, SC_PORT(sc) ?
10581                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10582                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10583                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10584                 }
10585         }
10586
10587         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10588         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10589         ecore_init_block(sc, BLOCK_USDM, init_phase);
10590         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10591
10592         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10593         ecore_init_block(sc, BLOCK_USEM, init_phase);
10594         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10595         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10596
10597         ecore_init_block(sc, BLOCK_UPB, init_phase);
10598         ecore_init_block(sc, BLOCK_XPB, init_phase);
10599
10600         ecore_init_block(sc, BLOCK_PBF, init_phase);
10601
10602         if (CHIP_IS_E1x(sc)) {
10603 /* configure PBF to work without PAUSE mtu 9000 */
10604                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10605
10606 /* update threshold */
10607                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10608 /* update init credit */
10609                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10610                        (9040 / 16) + 553 - 22);
10611
10612 /* probe changes */
10613                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10614                 DELAY(50);
10615                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10616         }
10617
10618         if (CNIC_SUPPORT(sc)) {
10619                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10620         }
10621
10622         ecore_init_block(sc, BLOCK_CDU, init_phase);
10623         ecore_init_block(sc, BLOCK_CFC, init_phase);
10624         ecore_init_block(sc, BLOCK_HC, init_phase);
10625         ecore_init_block(sc, BLOCK_IGU, init_phase);
10626         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10627         /* init aeu_mask_attn_func_0/1:
10628          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10629          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10630          *             bits 4-7 are used for "per vn group attention" */
10631         val = IS_MF(sc) ? 0xF7 : 0x7;
10632         val |= 0x10;
10633         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10634
10635         ecore_init_block(sc, BLOCK_NIG, init_phase);
10636
10637         if (!CHIP_IS_E1x(sc)) {
10638 /* Bit-map indicating which L2 hdrs may appear after the
10639  * basic Ethernet header
10640  */
10641                 if (IS_MF_AFEX(sc)) {
10642                         REG_WR(sc, SC_PORT(sc) ?
10643                                NIG_REG_P1_HDRS_AFTER_BASIC :
10644                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10645                 } else {
10646                         REG_WR(sc, SC_PORT(sc) ?
10647                                NIG_REG_P1_HDRS_AFTER_BASIC :
10648                                NIG_REG_P0_HDRS_AFTER_BASIC,
10649                                IS_MF_SD(sc) ? 7 : 6);
10650                 }
10651
10652                 if (CHIP_IS_E3(sc)) {
10653                         REG_WR(sc, SC_PORT(sc) ?
10654                                NIG_REG_LLH1_MF_MODE :
10655                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10656                 }
10657         }
10658         if (!CHIP_IS_E3(sc)) {
10659                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10660         }
10661
10662         /* 0x2 disable mf_ov, 0x1 enable */
10663         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10664                (IS_MF_SD(sc) ? 0x1 : 0x2));
10665
10666         if (!CHIP_IS_E1x(sc)) {
10667                 val = 0;
10668                 switch (sc->devinfo.mf_info.mf_mode) {
10669                 case MULTI_FUNCTION_SD:
10670                         val = 1;
10671                         break;
10672                 case MULTI_FUNCTION_SI:
10673                 case MULTI_FUNCTION_AFEX:
10674                         val = 2;
10675                         break;
10676                 }
10677
10678                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10679                             NIG_REG_LLH0_CLS_TYPE), val);
10680         }
10681         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10682         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10683         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10684
10685         /* If SPIO5 is set to generate interrupts, enable it for this port */
10686         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10687         if (val & MISC_SPIO_SPIO5) {
10688                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10689                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10690                 val = REG_RD(sc, reg_addr);
10691                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10692                 REG_WR(sc, reg_addr, val);
10693         }
10694
10695         return 0;
10696 }
10697
10698 static uint32_t
10699 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10700                        uint32_t expected, uint32_t poll_count)
10701 {
10702         uint32_t cur_cnt = poll_count;
10703         uint32_t val;
10704
10705         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10706                 DELAY(FLR_WAIT_INTERVAL);
10707         }
10708
10709         return val;
10710 }
10711
10712 static int
10713 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10714                               __rte_unused const char *msg, uint32_t poll_cnt)
10715 {
10716         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10717
10718         if (val != 0) {
10719                 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10720                 return -1;
10721         }
10722
10723         return 0;
10724 }
10725
10726 /* Common routines with VF FLR cleanup */
10727 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10728 {
10729         /* adjust polling timeout */
10730         if (CHIP_REV_IS_EMUL(sc)) {
10731                 return FLR_POLL_CNT * 2000;
10732         }
10733
10734         if (CHIP_REV_IS_FPGA(sc)) {
10735                 return FLR_POLL_CNT * 120;
10736         }
10737
10738         return FLR_POLL_CNT;
10739 }
10740
10741 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10742 {
10743         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10744         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10745                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10746                                           "CFC PF usage counter timed out",
10747                                           poll_cnt)) {
10748                 return -1;
10749         }
10750
10751         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10752         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10753                                           DORQ_REG_PF_USAGE_CNT,
10754                                           "DQ PF usage counter timed out",
10755                                           poll_cnt)) {
10756                 return -1;
10757         }
10758
10759         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10760         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10761                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10762                                           "QM PF usage counter timed out",
10763                                           poll_cnt)) {
10764                 return -1;
10765         }
10766
10767         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10768         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10769                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10770                                           "Timers VNIC usage counter timed out",
10771                                           poll_cnt)) {
10772                 return -1;
10773         }
10774
10775         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10776                                           TM_REG_LIN0_NUM_SCANS +
10777                                           4 * SC_PORT(sc),
10778                                           "Timers NUM_SCANS usage counter timed out",
10779                                           poll_cnt)) {
10780                 return -1;
10781         }
10782
10783         /* Wait DMAE PF usage counter to zero */
10784         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10785                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10786                                           "DMAE dommand register timed out",
10787                                           poll_cnt)) {
10788                 return -1;
10789         }
10790
10791         return 0;
10792 }
10793
10794 #define OP_GEN_PARAM(param)                                            \
10795         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10796 #define OP_GEN_TYPE(type)                                           \
10797         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10798 #define OP_GEN_AGG_VECT(index)                                             \
10799         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10800
10801 static int
10802 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10803                      uint32_t poll_cnt)
10804 {
10805         uint32_t op_gen_command = 0;
10806         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10807                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10808         int ret = 0;
10809
10810         if (REG_RD(sc, comp_addr)) {
10811                 PMD_DRV_LOG(NOTICE,
10812                             "Cleanup complete was not 0 before sending");
10813                 return -1;
10814         }
10815
10816         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10817         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10818         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10819         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10820
10821         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10822
10823         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10824                 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10825                 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10826                             (REG_RD(sc, comp_addr)));
10827                 rte_panic("FLR cleanup failed");
10828                 return -1;
10829         }
10830
10831         /* Zero completion for nxt FLR */
10832         REG_WR(sc, comp_addr, 0);
10833
10834         return ret;
10835 }
10836
10837 static void
10838 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10839                        uint32_t poll_count)
10840 {
10841         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10842         uint32_t cur_cnt = poll_count;
10843
10844         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10845         crd = crd_start = REG_RD(sc, regs->crd);
10846         init_crd = REG_RD(sc, regs->init_crd);
10847
10848         while ((crd != init_crd) &&
10849                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10850                 (init_crd - crd_start))) {
10851                 if (cur_cnt--) {
10852                         DELAY(FLR_WAIT_INTERVAL);
10853                         crd = REG_RD(sc, regs->crd);
10854                         crd_freed = REG_RD(sc, regs->crd_freed);
10855                 } else {
10856                         break;
10857                 }
10858         }
10859 }
10860
10861 static void
10862 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10863                        uint32_t poll_count)
10864 {
10865         uint32_t occup, to_free, freed, freed_start;
10866         uint32_t cur_cnt = poll_count;
10867
10868         occup = to_free = REG_RD(sc, regs->lines_occup);
10869         freed = freed_start = REG_RD(sc, regs->lines_freed);
10870
10871         while (occup &&
10872                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10873                 to_free)) {
10874                 if (cur_cnt--) {
10875                         DELAY(FLR_WAIT_INTERVAL);
10876                         occup = REG_RD(sc, regs->lines_occup);
10877                         freed = REG_RD(sc, regs->lines_freed);
10878                 } else {
10879                         break;
10880                 }
10881         }
10882 }
10883
10884 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10885 {
10886         struct pbf_pN_cmd_regs cmd_regs[] = {
10887                 {0, (CHIP_IS_E3B0(sc)) ?
10888                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10889                  (CHIP_IS_E3B0(sc)) ?
10890                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10891                 {1, (CHIP_IS_E3B0(sc)) ?
10892                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10893                  (CHIP_IS_E3B0(sc)) ?
10894                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10895                 {4, (CHIP_IS_E3B0(sc)) ?
10896                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10897                  (CHIP_IS_E3B0(sc)) ?
10898                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10899                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10900         };
10901
10902         struct pbf_pN_buf_regs buf_regs[] = {
10903                 {0, (CHIP_IS_E3B0(sc)) ?
10904                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10905                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10906                  (CHIP_IS_E3B0(sc)) ?
10907                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10908                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10909                 {1, (CHIP_IS_E3B0(sc)) ?
10910                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10911                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10912                  (CHIP_IS_E3B0(sc)) ?
10913                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10914                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10915                 {4, (CHIP_IS_E3B0(sc)) ?
10916                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10917                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10918                  (CHIP_IS_E3B0(sc)) ?
10919                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10920                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10921         };
10922
10923         uint32_t i;
10924
10925         /* Verify the command queues are flushed P0, P1, P4 */
10926         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10927                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10928         }
10929
10930         /* Verify the transmission buffers are flushed P0, P1, P4 */
10931         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10932                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10933         }
10934 }
10935
10936 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10937 {
10938         __rte_unused uint32_t val;
10939
10940         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10941         PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10942
10943         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10944         PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10945
10946         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10947         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10948
10949         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10950         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10951
10952         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10953         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10954
10955         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10956         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10957
10958         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10959         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10960
10961         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10962         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10963                     val);
10964 }
10965
10966 /**
10967  *      bnx2x_pf_flr_clnup
10968  *      a. re-enable target read on the PF
10969  *      b. poll cfc per function usgae counter
10970  *      c. poll the qm perfunction usage counter
10971  *      d. poll the tm per function usage counter
10972  *      e. poll the tm per function scan-done indication
10973  *      f. clear the dmae channel associated wit hthe PF
10974  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
10975  *      h. call the common flr cleanup code with -1 (pf indication)
10976  */
10977 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
10978 {
10979         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
10980
10981         /* Re-enable PF target read access */
10982         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10983
10984         /* Poll HW usage counters */
10985         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
10986                 return -1;
10987         }
10988
10989         /* Zero the igu 'trailing edge' and 'leading edge' */
10990
10991         /* Send the FW cleanup command */
10992         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
10993                 return -1;
10994         }
10995
10996         /* ATC cleanup */
10997
10998         /* Verify TX hw is flushed */
10999         bnx2x_tx_hw_flushed(sc, poll_cnt);
11000
11001         /* Wait 100ms (not adjusted according to platform) */
11002         DELAY(100000);
11003
11004         /* Verify no pending pci transactions */
11005         if (bnx2x_is_pcie_pending(sc)) {
11006                 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11007         }
11008
11009         /* Debug */
11010         bnx2x_hw_enable_status(sc);
11011
11012         /*
11013          * Master enable - Due to WB DMAE writes performed before this
11014          * register is re-initialized as part of the regular function init
11015          */
11016         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11017
11018         return 0;
11019 }
11020
11021 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11022 {
11023         int port = SC_PORT(sc);
11024         int func = SC_FUNC(sc);
11025         int init_phase = PHASE_PF0 + func;
11026         struct ecore_ilt *ilt = sc->ilt;
11027         uint16_t cdu_ilt_start;
11028         uint32_t addr, val;
11029         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11030         int main_mem_width, rc;
11031         uint32_t i;
11032
11033         PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11034
11035         /* FLR cleanup */
11036         if (!CHIP_IS_E1x(sc)) {
11037                 rc = bnx2x_pf_flr_clnup(sc);
11038                 if (rc) {
11039                         PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11040                         return rc;
11041                 }
11042         }
11043
11044         /* set MSI reconfigure capability */
11045         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11046                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11047                 val = REG_RD(sc, addr);
11048                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11049                 REG_WR(sc, addr, val);
11050         }
11051
11052         ecore_init_block(sc, BLOCK_PXP, init_phase);
11053         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11054
11055         ilt = sc->ilt;
11056         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11057
11058         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11059                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11060                 ilt->lines[cdu_ilt_start + i].page_mapping =
11061                     (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11062                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11063         }
11064         ecore_ilt_init_op(sc, INITOP_SET);
11065
11066         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11067
11068         if (!CHIP_IS_E1x(sc)) {
11069                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11070
11071 /* Turn on a single ISR mode in IGU if driver is going to use
11072  * INT#x or MSI
11073  */
11074                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11075                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11076                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11077                 }
11078
11079 /*
11080  * Timers workaround bug: function init part.
11081  * Need to wait 20msec after initializing ILT,
11082  * needed to make sure there are no requests in
11083  * one of the PXP internal queues with "old" ILT addresses
11084  */
11085                 DELAY(20000);
11086
11087 /*
11088  * Master enable - Due to WB DMAE writes performed before this
11089  * register is re-initialized as part of the regular function
11090  * init
11091  */
11092                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11093 /* Enable the function in IGU */
11094                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11095         }
11096
11097         sc->dmae_ready = 1;
11098
11099         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11100
11101         if (!CHIP_IS_E1x(sc))
11102                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11103
11104         ecore_init_block(sc, BLOCK_ATC, init_phase);
11105         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11106         ecore_init_block(sc, BLOCK_NIG, init_phase);
11107         ecore_init_block(sc, BLOCK_SRC, init_phase);
11108         ecore_init_block(sc, BLOCK_MISC, init_phase);
11109         ecore_init_block(sc, BLOCK_TCM, init_phase);
11110         ecore_init_block(sc, BLOCK_UCM, init_phase);
11111         ecore_init_block(sc, BLOCK_CCM, init_phase);
11112         ecore_init_block(sc, BLOCK_XCM, init_phase);
11113         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11114         ecore_init_block(sc, BLOCK_USEM, init_phase);
11115         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11116         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11117
11118         if (!CHIP_IS_E1x(sc))
11119                 REG_WR(sc, QM_REG_PF_EN, 1);
11120
11121         if (!CHIP_IS_E1x(sc)) {
11122                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11123                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11124                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11125                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11126         }
11127         ecore_init_block(sc, BLOCK_QM, init_phase);
11128
11129         ecore_init_block(sc, BLOCK_TM, init_phase);
11130         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11131
11132         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11133         ecore_init_block(sc, BLOCK_PRS, init_phase);
11134         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11135         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11136         ecore_init_block(sc, BLOCK_USDM, init_phase);
11137         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11138         ecore_init_block(sc, BLOCK_UPB, init_phase);
11139         ecore_init_block(sc, BLOCK_XPB, init_phase);
11140         ecore_init_block(sc, BLOCK_PBF, init_phase);
11141         if (!CHIP_IS_E1x(sc))
11142                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11143
11144         ecore_init_block(sc, BLOCK_CDU, init_phase);
11145
11146         ecore_init_block(sc, BLOCK_CFC, init_phase);
11147
11148         if (!CHIP_IS_E1x(sc))
11149                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11150
11151         if (IS_MF(sc)) {
11152                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11153                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11154         }
11155
11156         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11157
11158         /* HC init per function */
11159         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11160                 if (CHIP_IS_E1H(sc)) {
11161                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11162
11163                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11164                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11165                 }
11166                 ecore_init_block(sc, BLOCK_HC, init_phase);
11167
11168         } else {
11169                 uint32_t num_segs, sb_idx, prod_offset;
11170
11171                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11172
11173                 if (!CHIP_IS_E1x(sc)) {
11174                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11175                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11176                 }
11177
11178                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11179
11180                 if (!CHIP_IS_E1x(sc)) {
11181                         int dsb_idx = 0;
11182         /**
11183          * Producer memory:
11184          * E2 mode: address 0-135 match to the mapping memory;
11185          * 136 - PF0 default prod; 137 - PF1 default prod;
11186          * 138 - PF2 default prod; 139 - PF3 default prod;
11187          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11188          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11189          * 144-147 reserved.
11190          *
11191          * E1.5 mode - In backward compatible mode;
11192          * for non default SB; each even line in the memory
11193          * holds the U producer and each odd line hold
11194          * the C producer. The first 128 producers are for
11195          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11196          * producers are for the DSB for each PF.
11197          * Each PF has five segments: (the order inside each
11198          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11199          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11200          * 144-147 attn prods;
11201          */
11202                         /* non-default-status-blocks */
11203                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11204                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11205                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11206                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11207                                     num_segs;
11208
11209                                 for (i = 0; i < num_segs; i++) {
11210                                         addr = IGU_REG_PROD_CONS_MEMORY +
11211                                             (prod_offset + i) * 4;
11212                                         REG_WR(sc, addr, 0);
11213                                 }
11214                                 /* send consumer update with value 0 */
11215                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11216                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11217                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11218                         }
11219
11220                         /* default-status-blocks */
11221                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11222                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11223
11224                         if (CHIP_IS_MODE_4_PORT(sc))
11225                                 dsb_idx = SC_FUNC(sc);
11226                         else
11227                                 dsb_idx = SC_VN(sc);
11228
11229                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11230                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11231                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11232
11233                         /*
11234                          * igu prods come in chunks of E1HVN_MAX (4) -
11235                          * does not matters what is the current chip mode
11236                          */
11237                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11238                                 addr = IGU_REG_PROD_CONS_MEMORY +
11239                                     (prod_offset + i) * 4;
11240                                 REG_WR(sc, addr, 0);
11241                         }
11242                         /* send consumer update with 0 */
11243                         if (CHIP_INT_MODE_IS_BC(sc)) {
11244                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11245                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11246                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11247                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11248                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11249                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11250                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11251                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11252                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11253                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11254                         } else {
11255                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11256                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11257                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11258                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11259                         }
11260                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11261
11262                         /* !!! these should become driver const once
11263                            rf-tool supports split-68 const */
11264                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11265                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11266                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11267                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11268                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11269                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11270                 }
11271         }
11272
11273         /* Reset PCIE errors for debug */
11274         REG_WR(sc, 0x2114, 0xffffffff);
11275         REG_WR(sc, 0x2120, 0xffffffff);
11276
11277         if (CHIP_IS_E1x(sc)) {
11278                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11279                 main_mem_base = HC_REG_MAIN_MEMORY +
11280                     SC_PORT(sc) * (main_mem_size * 4);
11281                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11282                 main_mem_width = 8;
11283
11284                 val = REG_RD(sc, main_mem_prty_clr);
11285                 if (val) {
11286                         PMD_DRV_LOG(DEBUG,
11287                                     "Parity errors in HC block during function init (0x%x)!",
11288                                     val);
11289                 }
11290
11291 /* Clear "false" parity errors in MSI-X table */
11292                 for (i = main_mem_base;
11293                      i < main_mem_base + main_mem_size * 4;
11294                      i += main_mem_width) {
11295                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11296                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11297                                        i, main_mem_width / 4);
11298                 }
11299 /* Clear HC parity attention */
11300                 REG_RD(sc, main_mem_prty_clr);
11301         }
11302
11303         /* Enable STORMs SP logging */
11304         REG_WR8(sc, BAR_USTRORM_INTMEM +
11305                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11306         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11307                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11308         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11309                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11310         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11311                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11312
11313         elink_phy_probe(&sc->link_params);
11314
11315         return 0;
11316 }
11317
11318 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11319 {
11320         if (!BNX2X_NOMCP(sc)) {
11321                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11322         } else {
11323                 if (!CHIP_REV_IS_SLOW(sc)) {
11324                         PMD_DRV_LOG(WARNING,
11325                                     "Bootcode is missing - cannot reset link");
11326                 }
11327         }
11328 }
11329
11330 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11331 {
11332         int port = SC_PORT(sc);
11333         uint32_t val;
11334
11335         /* reset physical Link */
11336         bnx2x_link_reset(sc);
11337
11338         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11339
11340         /* Do not rcv packets to BRB */
11341         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11342         /* Do not direct rcv packets that are not for MCP to the BRB */
11343         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11344                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11345
11346         /* Configure AEU */
11347         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11348
11349         DELAY(100000);
11350
11351         /* Check for BRB port occupancy */
11352         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11353         if (val) {
11354                 PMD_DRV_LOG(DEBUG,
11355                             "BRB1 is not empty, %d blocks are occupied", val);
11356         }
11357 }
11358
11359 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11360 {
11361         int reg;
11362         uint32_t wb_write[2];
11363
11364         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11365
11366         wb_write[0] = ONCHIP_ADDR1(addr);
11367         wb_write[1] = ONCHIP_ADDR2(addr);
11368         REG_WR_DMAE(sc, reg, wb_write, 2);
11369 }
11370
11371 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11372 {
11373         uint32_t i, base = FUNC_ILT_BASE(func);
11374         for (i = base; i < base + ILT_PER_FUNC; i++) {
11375                 bnx2x_ilt_wr(sc, i, 0);
11376         }
11377 }
11378
11379 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11380 {
11381         struct bnx2x_fastpath *fp;
11382         int port = SC_PORT(sc);
11383         int func = SC_FUNC(sc);
11384         int i;
11385
11386         /* Disable the function in the FW */
11387         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11388         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11389         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11390         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11391
11392         /* FP SBs */
11393         FOR_EACH_ETH_QUEUE(sc, i) {
11394                 fp = &sc->fp[i];
11395                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11396                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11397                         SB_DISABLED);
11398         }
11399
11400         /* SP SB */
11401         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11402                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11403
11404         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11405                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11406                        0);
11407         }
11408
11409         /* Configure IGU */
11410         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11411                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11412                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11413         } else {
11414                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11415                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11416         }
11417
11418         if (CNIC_LOADED(sc)) {
11419 /* Disable Timer scan */
11420                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11421 /*
11422  * Wait for at least 10ms and up to 2 second for the timers
11423  * scan to complete
11424  */
11425                 for (i = 0; i < 200; i++) {
11426                         DELAY(10000);
11427                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11428                                 break;
11429                 }
11430         }
11431
11432         /* Clear ILT */
11433         bnx2x_clear_func_ilt(sc, func);
11434
11435         /*
11436          * Timers workaround bug for E2: if this is vnic-3,
11437          * we need to set the entire ilt range for this timers.
11438          */
11439         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11440                 struct ilt_client_info ilt_cli;
11441 /* use dummy TM client */
11442                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11443                 ilt_cli.start = 0;
11444                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11445                 ilt_cli.client_num = ILT_CLIENT_TM;
11446
11447                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11448         }
11449
11450         /* this assumes that reset_port() called before reset_func() */
11451         if (!CHIP_IS_E1x(sc)) {
11452                 bnx2x_pf_disable(sc);
11453         }
11454
11455         sc->dmae_ready = 0;
11456 }
11457
11458 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11459 {
11460         rte_free(sc->init_ops);
11461         rte_free(sc->init_ops_offsets);
11462         rte_free(sc->init_data);
11463         rte_free(sc->iro_array);
11464 }
11465
11466 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11467 {
11468         uint32_t len, i;
11469         uint8_t *p = sc->firmware;
11470         uint32_t off[24];
11471
11472         for (i = 0; i < 24; ++i)
11473                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11474
11475         len = off[0];
11476         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11477         if (!sc->init_ops)
11478                 goto alloc_failed;
11479         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11480
11481         len = off[2];
11482         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11483         if (!sc->init_ops_offsets)
11484                 goto alloc_failed;
11485         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11486
11487         len = off[4];
11488         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11489         if (!sc->init_data)
11490                 goto alloc_failed;
11491         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11492
11493         sc->tsem_int_table_data = p + off[7];
11494         sc->tsem_pram_data = p + off[9];
11495         sc->usem_int_table_data = p + off[11];
11496         sc->usem_pram_data = p + off[13];
11497         sc->csem_int_table_data = p + off[15];
11498         sc->csem_pram_data = p + off[17];
11499         sc->xsem_int_table_data = p + off[19];
11500         sc->xsem_pram_data = p + off[21];
11501
11502         len = off[22];
11503         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11504         if (!sc->iro_array)
11505                 goto alloc_failed;
11506         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11507
11508         return 0;
11509
11510 alloc_failed:
11511         bnx2x_release_firmware(sc);
11512         return -1;
11513 }
11514
11515 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11516 {
11517 #define MIN_PREFIX_SIZE (10)
11518
11519         int n = MIN_PREFIX_SIZE;
11520         uint16_t xlen;
11521
11522         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11523             len <= MIN_PREFIX_SIZE) {
11524                 return -1;
11525         }
11526
11527         /* optional extra fields are present */
11528         if (zbuf[3] & 0x4) {
11529                 xlen = zbuf[13];
11530                 xlen <<= 8;
11531                 xlen += zbuf[12];
11532
11533                 n += xlen;
11534         }
11535         /* file name is present */
11536         if (zbuf[3] & 0x8) {
11537                 while ((zbuf[n++] != 0) && (n < len)) ;
11538         }
11539
11540         return n;
11541 }
11542
11543 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11544 {
11545         int ret;
11546         int data_begin = cut_gzip_prefix(zbuf, len);
11547
11548         PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11549
11550         if (data_begin <= 0) {
11551                 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11552                 return -1;
11553         }
11554
11555         memset(&zlib_stream, 0, sizeof(zlib_stream));
11556         zlib_stream.next_in = zbuf + data_begin;
11557         zlib_stream.avail_in = len - data_begin;
11558         zlib_stream.next_out = sc->gz_buf;
11559         zlib_stream.avail_out = FW_BUF_SIZE;
11560
11561         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11562         if (ret != Z_OK) {
11563                 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11564                 return ret;
11565         }
11566
11567         ret = inflate(&zlib_stream, Z_FINISH);
11568         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11569                 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11570                             zlib_stream.msg);
11571         }
11572
11573         sc->gz_outlen = zlib_stream.total_out;
11574         if (sc->gz_outlen & 0x3) {
11575                 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11576                             sc->gz_outlen);
11577         }
11578         sc->gz_outlen >>= 2;
11579
11580         inflateEnd(&zlib_stream);
11581
11582         if (ret == Z_STREAM_END)
11583                 return 0;
11584
11585         return ret;
11586 }
11587
11588 static void
11589 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11590                           uint32_t addr, uint32_t len)
11591 {
11592         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11593 }
11594
11595 void
11596 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11597                           uint32_t * data)
11598 {
11599         uint8_t i;
11600         for (i = 0; i < size / 4; i++) {
11601                 REG_WR(sc, addr + (i * 4), data[i]);
11602         }
11603 }
11604
11605 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11606 {
11607         uint32_t phy_type_idx = ext_phy_type >> 8;
11608         static const char *types[] =
11609             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11610                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11611                 "BNX2X-8727",
11612                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11613         };
11614
11615         if (phy_type_idx < 12)
11616                 return types[phy_type_idx];
11617         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11618                 return types[12];
11619         else
11620                 return types[13];
11621 }
11622
11623 static const char *get_state(uint32_t state)
11624 {
11625         uint32_t state_idx = state >> 12;
11626         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11627                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11628                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11629                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11630                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11631         };
11632
11633         if (state_idx <= 0xF)
11634                 return states[state_idx];
11635         else
11636                 return states[0x10];
11637 }
11638
11639 static const char *get_recovery_state(uint32_t state)
11640 {
11641         static const char *states[] = { "NONE", "DONE", "INIT",
11642                 "WAIT", "FAILED", "NIC_LOADING"
11643         };
11644         return states[state];
11645 }
11646
11647 static const char *get_rx_mode(uint32_t mode)
11648 {
11649         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11650                 "PROMISC", "MAX_MULTICAST", "ERROR"
11651         };
11652
11653         if (mode < 0x4)
11654                 return modes[mode];
11655         else if (BNX2X_MAX_MULTICAST == mode)
11656                 return modes[4];
11657         else
11658                 return modes[5];
11659 }
11660
11661 #define BNX2X_INFO_STR_MAX 256
11662 static const char *get_bnx2x_flags(uint32_t flags)
11663 {
11664         int i;
11665         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11666                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11667                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11668                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11669         };
11670         static char flag_str[BNX2X_INFO_STR_MAX];
11671         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11672
11673         for (i = 0; i < 5; i++)
11674                 if (flags & (1 << i)) {
11675                         strcat(flag_str, flag[i]);
11676                         flags ^= (1 << i);
11677                 }
11678         if (flags) {
11679                 static char unknown[BNX2X_INFO_STR_MAX];
11680                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11681                 strcat(flag_str, unknown);
11682         }
11683         return flag_str;
11684 }
11685
11686 /*
11687  * Prints useful adapter info.
11688  */
11689 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11690 {
11691         int i = 0;
11692         __rte_unused uint32_t ext_phy_type;
11693
11694         PMD_INIT_FUNC_TRACE();
11695         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11696                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11697                                                               sc->
11698                                                               devinfo.shmem_base
11699                                                               + offsetof(struct
11700                                                                          shmem_region,
11701                                                                          dev_info.port_hw_config
11702                                                                          [0].external_phy_config)));
11703         else
11704                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11705                                                                 sc->
11706                                                                 devinfo.shmem_base
11707                                                                 +
11708                                                                 offsetof(struct
11709                                                                          shmem_region,
11710                                                                          dev_info.port_hw_config
11711                                                                          [0].external_phy_config)));
11712
11713         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11714         /* Hardware chip info. */
11715         PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11716         PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11717                      (CHIP_METAL(sc) >> 4));
11718
11719         /* Bus info. */
11720         PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11721         switch (sc->devinfo.pcie_link_speed) {
11722         case 1:
11723                 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11724                 break;
11725         case 2:
11726                 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11727                 break;
11728         case 4:
11729                 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11730                 break;
11731         default:
11732                 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11733         }
11734
11735         /* Device features. */
11736         PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11737
11738         /* Miscellaneous flags. */
11739         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11740                 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11741                 i++;
11742         }
11743
11744         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11745                 if (i > 0)
11746                         PMD_INIT_LOG(DEBUG, "|");
11747                 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11748                 i++;
11749         }
11750
11751         if (IS_PF(sc)) {
11752                 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11753                 switch (sc->sp->rss_rdata.rss_mode) {
11754                 case ETH_RSS_MODE_DISABLED:
11755                         PMD_INIT_LOG(DEBUG, "%19s", "None");
11756                         break;
11757                 case ETH_RSS_MODE_REGULAR:
11758                         PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11759                         break;
11760                 default:
11761                         PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11762                         break;
11763                 }
11764         }
11765
11766         /* RTE and Driver versions */
11767         PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11768                      rte_version());
11769         PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11770                      bnx2x_pmd_version());
11771
11772         /* Firmware versions and device features. */
11773         PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11774                      "Firmware",
11775                      BNX2X_5710_FW_MAJOR_VERSION,
11776                      BNX2X_5710_FW_MINOR_VERSION,
11777                      BNX2X_5710_FW_REVISION_VERSION);
11778         PMD_INIT_LOG(DEBUG, "%12s : %s",
11779                      "Bootcode", sc->devinfo.bc_ver_str);
11780
11781         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11782         PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11783         PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11784         PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11785                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11786         PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11787         PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11788         PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11789         PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11790         PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11791                         sc->link_params.mac_addr[0],
11792                         sc->link_params.mac_addr[1],
11793                         sc->link_params.mac_addr[2],
11794                         sc->link_params.mac_addr[3],
11795                         sc->link_params.mac_addr[4],
11796                         sc->link_params.mac_addr[5]);
11797         PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11798         PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11799         if (sc->recovery_state)
11800                 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11801                              get_recovery_state(sc->recovery_state));
11802         PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11803                      sc->cq_spq_left, sc->eq_spq_left);
11804         PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11805         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11806 }