drivers/net/bnx2x/bnx2x.c

   1 /*-
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015 QLogic Corporation.
  10  * All rights reserved.
  11  * www.qlogic.com
  12  *
  13  * See LICENSE.bnx2x_pmd for copyright and licensing details.
  14  */
  15
  16 #define BNX2X_DRIVER_VERSION "1.78.18"
  17
  18 #include "bnx2x.h"
  19 #include "bnx2x_vfpf.h"
  20 #include "ecore_sp.h"
  21 #include "ecore_init.h"
  22 #include "ecore_init_ops.h"
  23
  24 #include "rte_version.h"
  25 #include "rte_pci_dev_ids.h"
  26
  27 #include <sys/types.h>
  28 #include <sys/stat.h>
  29 #include <fcntl.h>
  30 #include <zlib.h>
  31
  32 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  33 #define BNX2X_PMD_VERSION_MAJOR 1
  34 #define BNX2X_PMD_VERSION_MINOR 0
  35 #define BNX2X_PMD_VERSION_REVISION 1
  36 #define BNX2X_PMD_VERSION_PATCH 1
  37
  38 static inline const char *
  39 bnx2x_pmd_version(void)
  40 {
  41         static char version[32];
  42
  43         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  44                         BNX2X_PMD_VER_PREFIX,
  45                         BNX2X_DRIVER_VERSION,
  46                         BNX2X_PMD_VERSION_MAJOR,
  47                         BNX2X_PMD_VERSION_MINOR,
  48                         BNX2X_PMD_VERSION_REVISION,
  49                         BNX2X_PMD_VERSION_PATCH);
  50
  51         return version;
  52 }
  53
  54 static z_stream zlib_stream;
  55
  56 #define EVL_VLID_MASK 0x0FFF
  57
  58 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  59 #define BNX2X_DEF_SB_IDX     0x0002
  60
  61 /*
  62  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  63  * function HW initialization.
  64  */
  65 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  66 #define FLR_WAIT_INTERVAL 50    /* usecs */
  67 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  68
  69 struct pbf_pN_buf_regs {
  70         int pN;
  71         uint32_t init_crd;
  72         uint32_t crd;
  73         uint32_t crd_freed;
  74 };
  75
  76 struct pbf_pN_cmd_regs {
  77         int pN;
  78         uint32_t lines_occup;
  79         uint32_t lines_freed;
  80 };
  81
  82 /* resources needed for unloading a previously loaded device */
  83
  84 #define BNX2X_PREV_WAIT_NEEDED 1
  85 rte_spinlock_t bnx2x_prev_mtx;
  86 struct bnx2x_prev_list_node {
  87         LIST_ENTRY(bnx2x_prev_list_node) node;
  88         uint8_t bus;
  89         uint8_t slot;
  90         uint8_t path;
  91         uint8_t aer;
  92         uint8_t undi;
  93 };
  94
  95 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  96         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  97
  98 static int load_count[2][3] = { { 0 } };
  99         /* per-path: 0-common, 1-port0, 2-port1 */
 100
 101 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 102                                 uint8_t cmng_type);
 103 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 104 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 105                               uint8_t port);
 106 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 107 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 108 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 109 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 110 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 111                                      uint8_t print);
 112 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 113 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 114 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 115 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 116                                  struct bnx2x_fastpath *fp,
 117                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 118 static void bnx2x_link_report(struct bnx2x_softc *sc);
 119 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 120 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 121 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 122 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 123 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 124 static __attribute__ ((noinline))
 125 int bnx2x_nic_load(struct bnx2x_softc *sc);
 126
 127 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 128 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 129 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
 130 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 131                          uint8_t storm, uint16_t index, uint8_t op,
 132                          uint8_t update);
 133
 134 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 135 {
 136         int res;
 137
 138         mb();
 139         res = ((*addr) & (1UL << nr)) != 0;
 140         mb();
 141         return res;
 142 }
 143
 144 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 145 {
 146         __sync_fetch_and_or(addr, (1UL << nr));
 147 }
 148
 149 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 150 {
 151         __sync_fetch_and_and(addr, ~(1UL << nr));
 152 }
 153
 154 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 155 {
 156         unsigned long mask = (1UL << nr);
 157         return __sync_fetch_and_and(addr, ~mask) & mask;
 158 }
 159
 160 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 161 {
 162         return __sync_val_compare_and_swap(addr, old, new);
 163 }
 164
 165 int
 166 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 167               const char *msg, uint32_t align)
 168 {
 169         char mz_name[RTE_MEMZONE_NAMESIZE];
 170         const struct rte_memzone *z;
 171
 172         dma->sc = sc;
 173         if (IS_PF(sc))
 174                 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 175                         rte_get_timer_cycles());
 176         else
 177                 sprintf(mz_name, "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 178                         rte_get_timer_cycles());
 179
 180         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 181         z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
 182                                         rte_lcore_to_socket_id(rte_lcore_id()),
 183                                         0, align);
 184         if (z == NULL) {
 185                 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
 186                 return -ENOMEM;
 187         }
 188         dma->paddr = (uint64_t) z->phys_addr;
 189         dma->vaddr = z->addr;
 190
 191         PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 192
 193         return 0;
 194 }
 195
 196 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 197 {
 198         uint32_t lock_status;
 199         uint32_t resource_bit = (1 << resource);
 200         int func = SC_FUNC(sc);
 201         uint32_t hw_lock_control_reg;
 202         int cnt;
 203
 204         PMD_INIT_FUNC_TRACE();
 205
 206         /* validate the resource is within range */
 207         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 208                 PMD_DRV_LOG(NOTICE,
 209                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 210                             resource);
 211                 return -1;
 212         }
 213
 214         if (func <= 5) {
 215                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 216         } else {
 217                 hw_lock_control_reg =
 218                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 219         }
 220
 221         /* validate the resource is not already taken */
 222         lock_status = REG_RD(sc, hw_lock_control_reg);
 223         if (lock_status & resource_bit) {
 224                 PMD_DRV_LOG(NOTICE,
 225                             "resource in use (status 0x%x bit 0x%x)",
 226                             lock_status, resource_bit);
 227                 return -1;
 228         }
 229
 230         /* try every 5ms for 5 seconds */
 231         for (cnt = 0; cnt < 1000; cnt++) {
 232                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 233                 lock_status = REG_RD(sc, hw_lock_control_reg);
 234                 if (lock_status & resource_bit) {
 235                         return 0;
 236                 }
 237                 DELAY(5000);
 238         }
 239
 240         PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
 241         return -1;
 242 }
 243
 244 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 245 {
 246         uint32_t lock_status;
 247         uint32_t resource_bit = (1 << resource);
 248         int func = SC_FUNC(sc);
 249         uint32_t hw_lock_control_reg;
 250
 251         PMD_INIT_FUNC_TRACE();
 252
 253         /* validate the resource is within range */
 254         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 255                 PMD_DRV_LOG(NOTICE,
 256                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 257                             resource);
 258                 return -1;
 259         }
 260
 261         if (func <= 5) {
 262                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 263         } else {
 264                 hw_lock_control_reg =
 265                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 266         }
 267
 268         /* validate the resource is currently taken */
 269         lock_status = REG_RD(sc, hw_lock_control_reg);
 270         if (!(lock_status & resource_bit)) {
 271                 PMD_DRV_LOG(NOTICE,
 272                             "resource not in use (status 0x%x bit 0x%x)",
 273                             lock_status, resource_bit);
 274                 return -1;
 275         }
 276
 277         REG_WR(sc, hw_lock_control_reg, resource_bit);
 278         return 0;
 279 }
 280
 281 /* copy command into DMAE command memory and set DMAE command Go */
 282 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 283 {
 284         uint32_t cmd_offset;
 285         uint32_t i;
 286
 287         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 288         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 289                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 290         }
 291
 292         REG_WR(sc, dmae_reg_go_c[idx], 1);
 293 }
 294
 295 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 296 {
 297         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 298                           DMAE_COMMAND_C_TYPE_ENABLE);
 299 }
 300
 301 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 302 {
 303         return opcode & ~DMAE_COMMAND_SRC_RESET;
 304 }
 305
 306 uint32_t
 307 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 308                 uint8_t with_comp, uint8_t comp_type)
 309 {
 310         uint32_t opcode = 0;
 311
 312         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 313                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 314
 315         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 316
 317         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 318
 319         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 320                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 321
 322         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 323
 324 #ifdef __BIG_ENDIAN
 325         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 326 #else
 327         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 328 #endif
 329
 330         if (with_comp) {
 331                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 332         }
 333
 334         return opcode;
 335 }
 336
 337 static void
 338 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 339                         uint8_t src_type, uint8_t dst_type)
 340 {
 341         memset(dmae, 0, sizeof(struct dmae_command));
 342
 343         /* set the opcode */
 344         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 345                                        TRUE, DMAE_COMP_PCI);
 346
 347         /* fill in the completion parameters */
 348         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 349         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 350         dmae->comp_val = DMAE_COMP_VAL;
 351 }
 352
 353 /* issue a DMAE command over the init channel and wait for completion */
 354 static int
 355 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 356 {
 357         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 358         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 359
 360         /* reset completion */
 361         *wb_comp = 0;
 362
 363         /* post the command on the channel used for initializations */
 364         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 365
 366         /* wait for completion */
 367         DELAY(500);
 368
 369         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 370                 if (!timeout ||
 371                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 372                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 373                         PMD_DRV_LOG(INFO, "DMAE timeout!");
 374                         return DMAE_TIMEOUT;
 375                 }
 376
 377                 timeout--;
 378                 DELAY(50);
 379         }
 380
 381         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 382                 PMD_DRV_LOG(INFO, "DMAE PCI error!");
 383                 return DMAE_PCI_ERROR;
 384         }
 385
 386         return 0;
 387 }
 388
 389 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 390 {
 391         struct dmae_command dmae;
 392         uint32_t *data;
 393         uint32_t i;
 394         int rc;
 395
 396         if (!sc->dmae_ready) {
 397                 data = BNX2X_SP(sc, wb_data[0]);
 398
 399                 for (i = 0; i < len32; i++) {
 400                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 401                 }
 402
 403                 return;
 404         }
 405
 406         /* set opcode and fixed command fields */
 407         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 408
 409         /* fill in addresses and len */
 410         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 411         dmae.src_addr_hi = 0;
 412         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 413         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 414         dmae.len = len32;
 415
 416         /* issue the command and wait for completion */
 417         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 418                 rte_panic("DMAE failed (%d)", rc);
 419         };
 420 }
 421
 422 void
 423 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
 424                uint32_t len32)
 425 {
 426         struct dmae_command dmae;
 427         int rc;
 428
 429         if (!sc->dmae_ready) {
 430                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 431                 return;
 432         }
 433
 434         /* set opcode and fixed command fields */
 435         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 436
 437         /* fill in addresses and len */
 438         dmae.src_addr_lo = U64_LO(dma_addr);
 439         dmae.src_addr_hi = U64_HI(dma_addr);
 440         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 441         dmae.dst_addr_hi = 0;
 442         dmae.len = len32;
 443
 444         /* issue the command and wait for completion */
 445         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 446                 rte_panic("DMAE failed (%d)", rc);
 447         }
 448 }
 449
 450 static void
 451 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
 452                         uint32_t addr, uint32_t len)
 453 {
 454         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 455         uint32_t offset = 0;
 456
 457         while (len > dmae_wr_max) {
 458                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 459                                (addr + offset), /* dst GRC address */
 460                                dmae_wr_max);
 461                 offset += (dmae_wr_max * 4);
 462                 len -= dmae_wr_max;
 463         }
 464
 465         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 466                        (addr + offset), /* dst GRC address */
 467                        len);
 468 }
 469
 470 void
 471 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 472                        uint32_t cid)
 473 {
 474         /* ustorm cxt validation */
 475         cxt->ustorm_ag_context.cdu_usage =
 476             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 477                                    CDU_REGION_NUMBER_UCM_AG,
 478                                    ETH_CONNECTION_TYPE);
 479         /* xcontext validation */
 480         cxt->xstorm_ag_context.cdu_reserved =
 481             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 482                                    CDU_REGION_NUMBER_XCM_AG,
 483                                    ETH_CONNECTION_TYPE);
 484 }
 485
 486 static void
 487 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 488                             uint8_t sb_index, uint8_t ticks)
 489 {
 490         uint32_t addr =
 491             (BAR_CSTRORM_INTMEM +
 492              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 493
 494         REG_WR8(sc, addr, ticks);
 495 }
 496
 497 static void
 498 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 499                             uint8_t sb_index, uint8_t disable)
 500 {
 501         uint32_t enable_flag =
 502             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 503         uint32_t addr =
 504             (BAR_CSTRORM_INTMEM +
 505              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 506         uint8_t flags;
 507
 508         /* clear and set */
 509         flags = REG_RD8(sc, addr);
 510         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 511         flags |= enable_flag;
 512         REG_WR8(sc, addr, flags);
 513 }
 514
 515 void
 516 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 517                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 518 {
 519         uint8_t ticks = (usec / 4);
 520
 521         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 522
 523         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 524         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 525 }
 526
 527 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 528 {
 529         return REG_RD(sc, reg_addr);
 530 }
 531
 532 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 533 {
 534         REG_WR(sc, reg_addr, val);
 535 }
 536
 537 void
 538 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 539                    __rte_unused const elink_log_id_t elink_log_id, ...)
 540 {
 541         PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
 542 }
 543
 544 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 545 {
 546         uint32_t spio_reg;
 547
 548         /* Only 2 SPIOs are configurable */
 549         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 550                 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
 551                 return -1;
 552         }
 553
 554         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 555
 556         /* read SPIO and mask except the float bits */
 557         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 558
 559         switch (mode) {
 560         case MISC_SPIO_OUTPUT_LOW:
 561                 /* clear FLOAT and set CLR */
 562                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 563                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 564                 break;
 565
 566         case MISC_SPIO_OUTPUT_HIGH:
 567                 /* clear FLOAT and set SET */
 568                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 569                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 570                 break;
 571
 572         case MISC_SPIO_INPUT_HI_Z:
 573                 /* set FLOAT */
 574                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 575                 break;
 576
 577         default:
 578                 break;
 579         }
 580
 581         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 582         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 583
 584         return 0;
 585 }
 586
 587 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 588 {
 589         /* The GPIO should be swapped if swap register is set and active */
 590         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 591                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 592         int gpio_shift = gpio_num;
 593         if (gpio_port)
 594                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 595
 596         uint32_t gpio_mask = (1 << gpio_shift);
 597         uint32_t gpio_reg;
 598
 599         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 600                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 601                 return -1;
 602         }
 603
 604         /* read GPIO value */
 605         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 606
 607         /* get the requested pin value */
 608         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 609 }
 610
 611 static int
 612 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 613 {
 614         /* The GPIO should be swapped if swap register is set and active */
 615         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 616                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 617         int gpio_shift = gpio_num;
 618         if (gpio_port)
 619                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 620
 621         uint32_t gpio_mask = (1 << gpio_shift);
 622         uint32_t gpio_reg;
 623
 624         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 625                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 626                 return -1;
 627         }
 628
 629         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 630
 631         /* read GPIO and mask except the float bits */
 632         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 633
 634         switch (mode) {
 635         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 636                 /* clear FLOAT and set CLR */
 637                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 638                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 639                 break;
 640
 641         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 642                 /* clear FLOAT and set SET */
 643                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 644                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 645                 break;
 646
 647         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 648                 /* set FLOAT */
 649                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 650                 break;
 651
 652         default:
 653                 break;
 654         }
 655
 656         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 657         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 658
 659         return 0;
 660 }
 661
 662 static int
 663 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 664 {
 665         uint32_t gpio_reg;
 666
 667         /* any port swapping should be handled by caller */
 668
 669         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 670
 671         /* read GPIO and mask except the float bits */
 672         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 673         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 674         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 675         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 676
 677         switch (mode) {
 678         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 679                 /* set CLR */
 680                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 681                 break;
 682
 683         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 684                 /* set SET */
 685                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 686                 break;
 687
 688         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 689                 /* set FLOAT */
 690                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 691                 break;
 692
 693         default:
 694                 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
 695                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 696                 return -1;
 697         }
 698
 699         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 700         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 701
 702         return 0;
 703 }
 704
 705 static int
 706 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 707                    uint8_t port)
 708 {
 709         /* The GPIO should be swapped if swap register is set and active */
 710         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 711                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 712         int gpio_shift = gpio_num;
 713         if (gpio_port)
 714                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 715
 716         uint32_t gpio_mask = (1 << gpio_shift);
 717         uint32_t gpio_reg;
 718
 719         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 720                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 721                 return -1;
 722         }
 723
 724         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 725
 726         /* read GPIO int */
 727         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 728
 729         switch (mode) {
 730         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 731                 /* clear SET and set CLR */
 732                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 733                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 734                 break;
 735
 736         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 737                 /* clear CLR and set SET */
 738                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 739                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 740                 break;
 741
 742         default:
 743                 break;
 744         }
 745
 746         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 747         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 748
 749         return 0;
 750 }
 751
 752 uint32_t
 753 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 754 {
 755         return bnx2x_gpio_read(sc, gpio_num, port);
 756 }
 757
 758 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 759                             uint8_t port)
 760 {
 761         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 762 }
 763
 764 uint8_t
 765 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 766                          uint8_t mode /* 0=low 1=high */ )
 767 {
 768         return bnx2x_gpio_mult_write(sc, pins, mode);
 769 }
 770
 771 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 772                                 uint8_t port)
 773 {
 774         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 775 }
 776
 777 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 778 {
 779         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 780                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 781 }
 782
 783 /* send the MCP a request, block until there is a reply */
 784 uint32_t
 785 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 786 {
 787         int mb_idx = SC_FW_MB_IDX(sc);
 788         uint32_t seq;
 789         uint32_t rc = 0;
 790         uint32_t cnt = 1;
 791         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 792
 793         seq = ++sc->fw_seq;
 794         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 795         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 796
 797         PMD_DRV_LOG(DEBUG,
 798                     "wrote command 0x%08x to FW MB param 0x%08x",
 799                     (command | seq), param);
 800
 801         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 802         do {
 803                 DELAY(delay * 1000);
 804                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 805         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 806
 807         /* is this a reply to our command? */
 808         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 809                 rc &= FW_MSG_CODE_MASK;
 810         } else {
 811                 /* Ruh-roh! */
 812                 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
 813                 rc = 0;
 814         }
 815
 816         return rc;
 817 }
 818
 819 static uint32_t
 820 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 821 {
 822         return elink_cb_fw_command(sc, command, param);
 823 }
 824
 825 static void
 826 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 827                            phys_addr_t mapping)
 828 {
 829         REG_WR(sc, addr, U64_LO(mapping));
 830         REG_WR(sc, (addr + 4), U64_HI(mapping));
 831 }
 832
 833 static void
 834 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
 835                       uint16_t abs_fid)
 836 {
 837         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 838                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 839         __storm_memset_dma_mapping(sc, addr, mapping);
 840 }
 841
 842 static void
 843 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 844 {
 845         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 846                 pf_id);
 847         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 848                 pf_id);
 849         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 850                 pf_id);
 851         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 852                 pf_id);
 853 }
 854
 855 static void
 856 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 857 {
 858         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 859                 enable);
 860         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 861                 enable);
 862         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 863                 enable);
 864         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 865                 enable);
 866 }
 867
 868 static void
 869 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 870                      uint16_t pfid)
 871 {
 872         uint32_t addr;
 873         size_t size;
 874
 875         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 876         size = sizeof(struct event_ring_data);
 877         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 878 }
 879
 880 static void
 881 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 882 {
 883         uint32_t addr = (BAR_CSTRORM_INTMEM +
 884                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 885         REG_WR16(sc, addr, eq_prod);
 886 }
 887
 888 /*
 889  * Post a slowpath command.
 890  *
 891  * A slowpath command is used to propogate a configuration change through
 892  * the controller in a controlled manner, allowing each STORM processor and
 893  * other H/W blocks to phase in the change.  The commands sent on the
 894  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 895  * completion of the ramrod will occur in different ways.  Here's a
 896  * breakdown of ramrods and how they complete:
 897  *
 898  * RAMROD_CMD_ID_ETH_PORT_SETUP
 899  *   Used to setup the leading connection on a port.  Completes on the
 900  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 901  *
 902  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 903  *   Used to setup an additional connection on a port.  Completes on the
 904  *   RCQ of the multi-queue/RSS connection being initialized.
 905  *
 906  * RAMROD_CMD_ID_ETH_STAT_QUERY
 907  *   Used to force the storm processors to update the statistics database
 908  *   in host memory.  This ramrod is send on the leading connection CID and
 909  *   completes as an index increment of the CSTORM on the default status
 910  *   block.
 911  *
 912  * RAMROD_CMD_ID_ETH_UPDATE
 913  *   Used to update the state of the leading connection, usually to udpate
 914  *   the RSS indirection table.  Completes on the RCQ of the leading
 915  *   connection. (Not currently used under FreeBSD until OS support becomes
 916  *   available.)
 917  *
 918  * RAMROD_CMD_ID_ETH_HALT
 919  *   Used when tearing down a connection prior to driver unload.  Completes
 920  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 921  *   use this on the leading connection.
 922  *
 923  * RAMROD_CMD_ID_ETH_SET_MAC
 924  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 925  *   the RCQ of the leading connection.
 926  *
 927  * RAMROD_CMD_ID_ETH_CFC_DEL
 928  *   Used when tearing down a conneciton prior to driver unload.  Completes
 929  *   on the RCQ of the leading connection (since the current connection
 930  *   has been completely removed from controller memory).
 931  *
 932  * RAMROD_CMD_ID_ETH_PORT_DEL
 933  *   Used to tear down the leading connection prior to driver unload,
 934  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 935  *   default status block.
 936  *
 937  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 938  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 939  *   RSS connection that is being offloaded.  (Not currently used under
 940  *   FreeBSD.)
 941  *
 942  * There can only be one command pending per function.
 943  *
 944  * Returns:
 945  *   0 = Success, !0 = Failure.
 946  */
 947
 948 /* must be called under the spq lock */
 949 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 950 {
 951         struct eth_spe *next_spe = sc->spq_prod_bd;
 952
 953         if (sc->spq_prod_bd == sc->spq_last_bd) {
 954                 /* wrap back to the first eth_spq */
 955                 sc->spq_prod_bd = sc->spq;
 956                 sc->spq_prod_idx = 0;
 957         } else {
 958                 sc->spq_prod_bd++;
 959                 sc->spq_prod_idx++;
 960         }
 961
 962         return next_spe;
 963 }
 964
 965 /* must be called under the spq lock */
 966 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 967 {
 968         int func = SC_FUNC(sc);
 969
 970         /*
 971          * Make sure that BD data is updated before writing the producer.
 972          * BD data is written to the memory, the producer is read from the
 973          * memory, thus we need a full memory barrier to ensure the ordering.
 974          */
 975         mb();
 976
 977         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 978                  sc->spq_prod_idx);
 979
 980         mb();
 981 }
 982
 983 /**
 984  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 985  *
 986  * @cmd:      command to check
 987  * @cmd_type: command type
 988  */
 989 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
 990 {
 991         if ((cmd_type == NONE_CONNECTION_TYPE) ||
 992             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
 993             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
 994             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
 995             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
 996             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
 997             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
 998                 return TRUE;
 999         } else {
1000                 return FALSE;
1001         }
1002 }
1003
1004 /**
1005  * bnx2x_sp_post - place a single command on an SP ring
1006  *
1007  * @sc:         driver handle
1008  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1009  * @cid:        SW CID the command is related to
1010  * @data_hi:    command private data address (high 32 bits)
1011  * @data_lo:    command private data address (low 32 bits)
1012  * @cmd_type:   command type (e.g. NONE, ETH)
1013  *
1014  * SP data is handled as if it's always an address pair, thus data fields are
1015  * not swapped to little endian in upper functions. Instead this function swaps
1016  * data as if it's two uint32 fields.
1017  */
1018 int
1019 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1020             uint32_t data_lo, int cmd_type)
1021 {
1022         struct eth_spe *spe;
1023         uint16_t type;
1024         int common;
1025
1026         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1027
1028         if (common) {
1029                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1030                         PMD_DRV_LOG(INFO, "EQ ring is full!");
1031                         return -1;
1032                 }
1033         } else {
1034                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1035                         PMD_DRV_LOG(INFO, "SPQ ring is full!");
1036                         return -1;
1037                 }
1038         }
1039
1040         spe = bnx2x_sp_get_next(sc);
1041
1042         /* CID needs port number to be encoded int it */
1043         spe->hdr.conn_and_cmd_data =
1044             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1045
1046         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1047
1048         /* TBD: Check if it works for VFs */
1049         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1050                  SPE_HDR_FUNCTION_ID);
1051
1052         spe->hdr.type = htole16(type);
1053
1054         spe->data.update_data_addr.hi = htole32(data_hi);
1055         spe->data.update_data_addr.lo = htole32(data_lo);
1056
1057         /*
1058          * It's ok if the actual decrement is issued towards the memory
1059          * somewhere between the lock and unlock. Thus no more explict
1060          * memory barrier is needed.
1061          */
1062         if (common) {
1063                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1064         } else {
1065                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1066         }
1067
1068         PMD_DRV_LOG(DEBUG,
1069                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1070                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1071                     sc->spq_prod_idx,
1072                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1073                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1074                                 (uint8_t *) sc->spq_prod_bd -
1075                                 (uint8_t *) sc->spq), command, common,
1076                     HW_CID(sc, cid), data_hi, data_lo, type,
1077                     atomic_load_acq_long(&sc->cq_spq_left),
1078                     atomic_load_acq_long(&sc->eq_spq_left));
1079
1080         bnx2x_sp_prod_update(sc);
1081
1082         return 0;
1083 }
1084
1085 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1086 {
1087         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1088                  sc->fw_drv_pulse_wr_seq);
1089 }
1090
1091 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1092 {
1093         uint16_t hw_cons;
1094         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1095
1096         if (unlikely(!txq)) {
1097                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1098                 return 0;
1099         }
1100
1101         mb();                   /* status block fields can change */
1102         hw_cons = le16toh(*fp->tx_cons_sb);
1103         return hw_cons != txq->tx_pkt_head;
1104 }
1105
1106 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1107 {
1108         /* expand this for multi-cos if ever supported */
1109         return bnx2x_tx_queue_has_work(fp);
1110 }
1111
1112 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1113 {
1114         uint16_t rx_cq_cons_sb;
1115         struct bnx2x_rx_queue *rxq;
1116         rxq = fp->sc->rx_queues[fp->index];
1117         if (unlikely(!rxq)) {
1118                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1119                 return 0;
1120         }
1121
1122         mb();                   /* status block fields can change */
1123         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1124         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1125                      MAX_RCQ_ENTRIES(rxq)))
1126                 rx_cq_cons_sb++;
1127         return rxq->rx_cq_head != rx_cq_cons_sb;
1128 }
1129
1130 static void
1131 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1132              union eth_rx_cqe *rr_cqe)
1133 {
1134 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1135         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1136 #endif
1137         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1138         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1139         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1140
1141         PMD_DRV_LOG(DEBUG,
1142                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1143                     fp->index, cid, command, sc->state,
1144                     rr_cqe->ramrod_cqe.ramrod_type);
1145
1146         switch (command) {
1147         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1148                 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1149                 drv_cmd = ECORE_Q_CMD_UPDATE;
1150                 break;
1151
1152         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1153                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1154                 drv_cmd = ECORE_Q_CMD_SETUP;
1155                 break;
1156
1157         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1158                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1159                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1160                 break;
1161
1162         case (RAMROD_CMD_ID_ETH_HALT):
1163                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1164                 drv_cmd = ECORE_Q_CMD_HALT;
1165                 break;
1166
1167         case (RAMROD_CMD_ID_ETH_TERMINATE):
1168                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1169                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1170                 break;
1171
1172         case (RAMROD_CMD_ID_ETH_EMPTY):
1173                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1174                 drv_cmd = ECORE_Q_CMD_EMPTY;
1175                 break;
1176
1177         default:
1178                 PMD_DRV_LOG(DEBUG,
1179                             "ERROR: unexpected MC reply (%d)"
1180                             "on fp[%d]", command, fp->index);
1181                 return;
1182         }
1183
1184         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1185             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1186                 /*
1187                  * q_obj->complete_cmd() failure means that this was
1188                  * an unexpected completion.
1189                  *
1190                  * In this case we don't want to increase the sc->spq_left
1191                  * because apparently we haven't sent this command the first
1192                  * place.
1193                  */
1194                 // rte_panic("Unexpected SP completion");
1195                 return;
1196         }
1197
1198         atomic_add_acq_long(&sc->cq_spq_left, 1);
1199
1200         PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1201                     atomic_load_acq_long(&sc->cq_spq_left));
1202 }
1203
1204 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1205 {
1206         struct bnx2x_rx_queue *rxq;
1207         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1208         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1209
1210         rxq = sc->rx_queues[fp->index];
1211         if (!rxq) {
1212                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1213                 return 0;
1214         }
1215
1216         /* CQ "next element" is of the size of the regular element */
1217         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1218         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1219                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1220                 hw_cq_cons++;
1221         }
1222
1223         bd_cons = rxq->rx_bd_head;
1224         bd_prod = rxq->rx_bd_tail;
1225         bd_prod_fw = bd_prod;
1226         sw_cq_cons = rxq->rx_cq_head;
1227         sw_cq_prod = rxq->rx_cq_tail;
1228
1229         /*
1230          * Memory barrier necessary as speculative reads of the rx
1231          * buffer can be ahead of the index in the status block
1232          */
1233         rmb();
1234
1235         while (sw_cq_cons != hw_cq_cons) {
1236                 union eth_rx_cqe *cqe;
1237                 struct eth_fast_path_rx_cqe *cqe_fp;
1238                 uint8_t cqe_fp_flags;
1239                 enum eth_rx_cqe_type cqe_fp_type;
1240
1241                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1242                 bd_prod = RX_BD(bd_prod, rxq);
1243                 bd_cons = RX_BD(bd_cons, rxq);
1244
1245                 cqe = &rxq->cq_ring[comp_ring_cons];
1246                 cqe_fp = &cqe->fast_path_cqe;
1247                 cqe_fp_flags = cqe_fp->type_error_flags;
1248                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1249
1250                 /* is this a slowpath msg? */
1251                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1252                         bnx2x_sp_event(sc, fp, cqe);
1253                         goto next_cqe;
1254                 }
1255
1256                 /* is this an error packet? */
1257                 if (unlikely(cqe_fp_flags &
1258                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1259                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1260                                    cqe_fp_flags, sw_cq_cons);
1261                         goto next_rx;
1262                 }
1263
1264                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1265
1266 next_rx:
1267                 bd_cons = NEXT_RX_BD(bd_cons);
1268                 bd_prod = NEXT_RX_BD(bd_prod);
1269                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1270
1271 next_cqe:
1272                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1273                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1274
1275         }                       /* while work to do */
1276
1277         rxq->rx_bd_head = bd_cons;
1278         rxq->rx_bd_tail = bd_prod_fw;
1279         rxq->rx_cq_head = sw_cq_cons;
1280         rxq->rx_cq_tail = sw_cq_prod;
1281
1282         /* Update producers */
1283         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1284
1285         return sw_cq_cons != hw_cq_cons;
1286 }
1287
1288 static uint16_t
1289 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1290                 uint16_t pkt_idx, uint16_t bd_idx)
1291 {
1292         struct eth_tx_start_bd *tx_start_bd =
1293             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1294         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1295         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1296
1297         if (likely(tx_mbuf != NULL)) {
1298                 rte_pktmbuf_free_seg(tx_mbuf);
1299         } else {
1300                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1301                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1302         }
1303
1304         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1305         txq->nb_tx_avail += nbd;
1306
1307         while (nbd--)
1308                 bd_idx = NEXT_TX_BD(bd_idx);
1309
1310         return bd_idx;
1311 }
1312
1313 /* processes transmit completions */
1314 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1315 {
1316         uint16_t bd_cons, hw_cons, sw_cons;
1317         __rte_unused uint16_t tx_bd_avail;
1318
1319         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1320
1321         if (unlikely(!txq)) {
1322                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1323                 return 0;
1324         }
1325
1326         bd_cons = txq->tx_bd_head;
1327         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1328         sw_cons = txq->tx_pkt_head;
1329
1330         while (sw_cons != hw_cons) {
1331                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1332                 sw_cons++;
1333         }
1334
1335         txq->tx_pkt_head = sw_cons;
1336         txq->tx_bd_head = bd_cons;
1337
1338         tx_bd_avail = txq->nb_tx_avail;
1339
1340         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1341                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1342                    fp->index, tx_bd_avail, hw_cons,
1343                    txq->tx_pkt_head, txq->tx_pkt_tail,
1344                    txq->tx_bd_head, txq->tx_bd_tail);
1345         return TRUE;
1346 }
1347
1348 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1349 {
1350         struct bnx2x_fastpath *fp;
1351         int i, count;
1352
1353         /* wait until all TX fastpath tasks have completed */
1354         for (i = 0; i < sc->num_queues; i++) {
1355                 fp = &sc->fp[i];
1356
1357                 count = 1000;
1358
1359                 while (bnx2x_has_tx_work(fp)) {
1360                         bnx2x_txeof(sc, fp);
1361
1362                         if (count == 0) {
1363                                 PMD_TX_LOG(ERR,
1364                                            "Timeout waiting for fp[%d] "
1365                                            "transmits to complete!", i);
1366                                 rte_panic("tx drain failure");
1367                                 return;
1368                         }
1369
1370                         count--;
1371                         DELAY(1000);
1372                         rmb();
1373                 }
1374         }
1375
1376         return;
1377 }
1378
1379 static int
1380 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1381                  int mac_type, uint8_t wait_for_comp)
1382 {
1383         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1384         int rc;
1385
1386         /* wait for completion of requested */
1387         if (wait_for_comp) {
1388                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1389         }
1390
1391         /* Set the mac type of addresses we want to clear */
1392         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1393
1394         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1395         if (rc < 0)
1396                 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1397
1398         return rc;
1399 }
1400
1401 int
1402 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1403                       unsigned long *rx_accept_flags,
1404                       unsigned long *tx_accept_flags)
1405 {
1406         /* Clear the flags first */
1407         *rx_accept_flags = 0;
1408         *tx_accept_flags = 0;
1409
1410         switch (rx_mode) {
1411         case BNX2X_RX_MODE_NONE:
1412                 /*
1413                  * 'drop all' supersedes any accept flags that may have been
1414                  * passed to the function.
1415                  */
1416                 break;
1417
1418         case BNX2X_RX_MODE_NORMAL:
1419                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1420                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1421                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1422
1423                 /* internal switching mode */
1424                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1425                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1426                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1427
1428                 break;
1429
1430         case BNX2X_RX_MODE_ALLMULTI:
1431                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1432                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1433                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1434
1435                 /* internal switching mode */
1436                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1437                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1438                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1439
1440                 break;
1441
1442         case BNX2X_RX_MODE_PROMISC:
1443                 /*
1444                  * According to deffinition of SI mode, iface in promisc mode
1445                  * should receive matched and unmatched (in resolution of port)
1446                  * unicast packets.
1447                  */
1448                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1449                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1450                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1451                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1452
1453                 /* internal switching mode */
1454                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1455                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1456
1457                 if (IS_MF_SI(sc)) {
1458                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1459                 } else {
1460                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1461                 }
1462
1463                 break;
1464
1465         default:
1466                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1467                 return -1;
1468         }
1469
1470         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1471         if (rx_mode != BNX2X_RX_MODE_NONE) {
1472                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1473                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1474         }
1475
1476         return 0;
1477 }
1478
1479 static int
1480 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1481                   unsigned long rx_mode_flags,
1482                   unsigned long rx_accept_flags,
1483                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1484 {
1485         struct ecore_rx_mode_ramrod_params ramrod_param;
1486         int rc;
1487
1488         memset(&ramrod_param, 0, sizeof(ramrod_param));
1489
1490         /* Prepare ramrod parameters */
1491         ramrod_param.cid = 0;
1492         ramrod_param.cl_id = cl_id;
1493         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1494         ramrod_param.func_id = SC_FUNC(sc);
1495
1496         ramrod_param.pstate = &sc->sp_state;
1497         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1498
1499         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1500         ramrod_param.rdata_mapping =
1501             (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1502             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1503
1504         ramrod_param.ramrod_flags = ramrod_flags;
1505         ramrod_param.rx_mode_flags = rx_mode_flags;
1506
1507         ramrod_param.rx_accept_flags = rx_accept_flags;
1508         ramrod_param.tx_accept_flags = tx_accept_flags;
1509
1510         rc = ecore_config_rx_mode(sc, &ramrod_param);
1511         if (rc < 0) {
1512                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1513                 return rc;
1514         }
1515
1516         return 0;
1517 }
1518
1519 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1520 {
1521         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1522         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1523         int rc;
1524
1525         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1526                                    &tx_accept_flags);
1527         if (rc) {
1528                 return rc;
1529         }
1530
1531         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1532         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1533         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1534
1535         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1536                                  rx_accept_flags, tx_accept_flags,
1537                                  ramrod_flags);
1538 }
1539
1540 /* returns the "mcp load_code" according to global load_count array */
1541 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1542 {
1543         int path = SC_PATH(sc);
1544         int port = SC_PORT(sc);
1545
1546         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1547                     path, load_count[path][0], load_count[path][1],
1548                     load_count[path][2]);
1549
1550         load_count[path][0]++;
1551         load_count[path][1 + port]++;
1552         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1553                     path, load_count[path][0], load_count[path][1],
1554                     load_count[path][2]);
1555         if (load_count[path][0] == 1)
1556                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1557         else if (load_count[path][1 + port] == 1)
1558                 return FW_MSG_CODE_DRV_LOAD_PORT;
1559         else
1560                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1561 }
1562
1563 /* returns the "mcp load_code" according to global load_count array */
1564 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1565 {
1566         int port = SC_PORT(sc);
1567         int path = SC_PATH(sc);
1568
1569         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1570                     path, load_count[path][0], load_count[path][1],
1571                     load_count[path][2]);
1572         load_count[path][0]--;
1573         load_count[path][1 + port]--;
1574         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1575                     path, load_count[path][0], load_count[path][1],
1576                     load_count[path][2]);
1577         if (load_count[path][0] == 0) {
1578                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1579         } else if (load_count[path][1 + port] == 0) {
1580                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1581         } else {
1582                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1583         }
1584 }
1585
1586 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1587 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1588 {
1589         uint32_t reset_code = 0;
1590
1591         /* Select the UNLOAD request mode */
1592         if (unload_mode == UNLOAD_NORMAL) {
1593                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1594         } else {
1595                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1596         }
1597
1598         /* Send the request to the MCP */
1599         if (!BNX2X_NOMCP(sc)) {
1600                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1601         } else {
1602                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1603         }
1604
1605         return reset_code;
1606 }
1607
1608 /* send UNLOAD_DONE command to the MCP */
1609 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1610 {
1611         uint32_t reset_param =
1612             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1613
1614         /* Report UNLOAD_DONE to MCP */
1615         if (!BNX2X_NOMCP(sc)) {
1616                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1617         }
1618 }
1619
1620 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1621 {
1622         int tout = 50;
1623
1624         if (!sc->port.pmf) {
1625                 return 0;
1626         }
1627
1628         /*
1629          * (assumption: No Attention from MCP at this stage)
1630          * PMF probably in the middle of TX disable/enable transaction
1631          * 1. Sync IRS for default SB
1632          * 2. Sync SP queue - this guarantees us that attention handling started
1633          * 3. Wait, that TX disable/enable transaction completes
1634          *
1635          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1636          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1637          * received completion for the transaction the state is TX_STOPPED.
1638          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1639          * transaction.
1640          */
1641
1642         while (ecore_func_get_state(sc, &sc->func_obj) !=
1643                ECORE_F_STATE_STARTED && tout--) {
1644                 DELAY(20000);
1645         }
1646
1647         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1648                 /*
1649                  * Failed to complete the transaction in a "good way"
1650                  * Force both transactions with CLR bit.
1651                  */
1652                 struct ecore_func_state_params func_params = { NULL };
1653
1654                 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1655                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1656
1657                 func_params.f_obj = &sc->func_obj;
1658                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1659
1660                 /* STARTED-->TX_STOPPED */
1661                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1662                 ecore_func_state_change(sc, &func_params);
1663
1664                 /* TX_STOPPED-->STARTED */
1665                 func_params.cmd = ECORE_F_CMD_TX_START;
1666                 return ecore_func_state_change(sc, &func_params);
1667         }
1668
1669         return 0;
1670 }
1671
1672 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1673 {
1674         struct bnx2x_fastpath *fp = &sc->fp[index];
1675         struct ecore_queue_state_params q_params = { NULL };
1676         int rc;
1677
1678         PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1679
1680         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1681         /* We want to wait for completion in this context */
1682         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1683
1684         /* Stop the primary connection: */
1685
1686         /* ...halt the connection */
1687         q_params.cmd = ECORE_Q_CMD_HALT;
1688         rc = ecore_queue_state_change(sc, &q_params);
1689         if (rc) {
1690                 return rc;
1691         }
1692
1693         /* ...terminate the connection */
1694         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1695         memset(&q_params.params.terminate, 0,
1696                sizeof(q_params.params.terminate));
1697         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1698         rc = ecore_queue_state_change(sc, &q_params);
1699         if (rc) {
1700                 return rc;
1701         }
1702
1703         /* ...delete cfc entry */
1704         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1705         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1706         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1707         return ecore_queue_state_change(sc, &q_params);
1708 }
1709
1710 /* wait for the outstanding SP commands */
1711 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1712 {
1713         unsigned long tmp;
1714         int tout = 5000;        /* wait for 5 secs tops */
1715
1716         while (tout--) {
1717                 mb();
1718                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1719                         return TRUE;
1720                 }
1721
1722                 DELAY(1000);
1723         }
1724
1725         mb();
1726
1727         tmp = atomic_load_acq_long(&sc->sp_state);
1728         if (tmp & mask) {
1729                 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1730                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1731                 return FALSE;
1732         }
1733
1734         return FALSE;
1735 }
1736
1737 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1738 {
1739         struct ecore_func_state_params func_params = { NULL };
1740         int rc;
1741
1742         /* prepare parameters for function state transitions */
1743         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1744         func_params.f_obj = &sc->func_obj;
1745         func_params.cmd = ECORE_F_CMD_STOP;
1746
1747         /*
1748          * Try to stop the function the 'good way'. If it fails (in case
1749          * of a parity error during bnx2x_chip_cleanup()) and we are
1750          * not in a debug mode, perform a state transaction in order to
1751          * enable further HW_RESET transaction.
1752          */
1753         rc = ecore_func_state_change(sc, &func_params);
1754         if (rc) {
1755                 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1756                             "Running a dry transaction");
1757                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1758                 return ecore_func_state_change(sc, &func_params);
1759         }
1760
1761         return 0;
1762 }
1763
1764 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1765 {
1766         struct ecore_func_state_params func_params = { NULL };
1767
1768         /* Prepare parameters for function state transitions */
1769         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1770
1771         func_params.f_obj = &sc->func_obj;
1772         func_params.cmd = ECORE_F_CMD_HW_RESET;
1773
1774         func_params.params.hw_init.load_phase = load_code;
1775
1776         return ecore_func_state_change(sc, &func_params);
1777 }
1778
1779 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1780 {
1781         if (disable_hw) {
1782                 /* prevent the HW from sending interrupts */
1783                 bnx2x_int_disable(sc);
1784         }
1785 }
1786
1787 static void
1788 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1789 {
1790         int port = SC_PORT(sc);
1791         struct ecore_mcast_ramrod_params rparam = { NULL };
1792         uint32_t reset_code;
1793         int i, rc = 0;
1794
1795         bnx2x_drain_tx_queues(sc);
1796
1797         /* give HW time to discard old tx messages */
1798         DELAY(1000);
1799
1800         /* Clean all ETH MACs */
1801         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1802                               FALSE);
1803         if (rc < 0) {
1804                 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1805         }
1806
1807         /* Clean up UC list  */
1808         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1809                               TRUE);
1810         if (rc < 0) {
1811                 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1812         }
1813
1814         /* Disable LLH */
1815         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1816
1817         /* Set "drop all" to stop Rx */
1818
1819         /*
1820          * We need to take the if_maddr_lock() here in order to prevent
1821          * a race between the completion code and this code.
1822          */
1823
1824         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1825                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1826         } else {
1827                 bnx2x_set_storm_rx_mode(sc);
1828         }
1829
1830         /* Clean up multicast configuration */
1831         rparam.mcast_obj = &sc->mcast_obj;
1832         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1833         if (rc < 0) {
1834                 PMD_DRV_LOG(NOTICE,
1835                             "Failed to send DEL MCAST command (%d)", rc);
1836         }
1837
1838         /*
1839          * Send the UNLOAD_REQUEST to the MCP. This will return if
1840          * this function should perform FUNCTION, PORT, or COMMON HW
1841          * reset.
1842          */
1843         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1844
1845         /*
1846          * (assumption: No Attention from MCP at this stage)
1847          * PMF probably in the middle of TX disable/enable transaction
1848          */
1849         rc = bnx2x_func_wait_started(sc);
1850         if (rc) {
1851                 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1852         }
1853
1854         /*
1855          * Close multi and leading connections
1856          * Completions for ramrods are collected in a synchronous way
1857          */
1858         for (i = 0; i < sc->num_queues; i++) {
1859                 if (bnx2x_stop_queue(sc, i)) {
1860                         goto unload_error;
1861                 }
1862         }
1863
1864         /*
1865          * If SP settings didn't get completed so far - something
1866          * very wrong has happen.
1867          */
1868         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1869                 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1870         }
1871
1872 unload_error:
1873
1874         rc = bnx2x_func_stop(sc);
1875         if (rc) {
1876                 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1877         }
1878
1879         /* disable HW interrupts */
1880         bnx2x_int_disable_sync(sc, TRUE);
1881
1882         /* Reset the chip */
1883         rc = bnx2x_reset_hw(sc, reset_code);
1884         if (rc) {
1885                 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1886         }
1887
1888         /* Report UNLOAD_DONE to MCP */
1889         bnx2x_send_unload_done(sc, keep_link);
1890 }
1891
1892 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1893 {
1894         uint32_t val;
1895
1896         PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1897
1898         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1899         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1900                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1901         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1902 }
1903
1904 /*
1905  * Cleans the object that have internal lists without sending
1906  * ramrods. Should be run when interrutps are disabled.
1907  */
1908 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1909 {
1910         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1911         struct ecore_mcast_ramrod_params rparam = { NULL };
1912         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1913         int rc;
1914
1915         /* Cleanup MACs' object first... */
1916
1917         /* Wait for completion of requested */
1918         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1919         /* Perform a dry cleanup */
1920         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1921
1922         /* Clean ETH primary MAC */
1923         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1924         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1925                                  &ramrod_flags);
1926         if (rc != 0) {
1927                 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1928         }
1929
1930         /* Cleanup UC list */
1931         vlan_mac_flags = 0;
1932         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1933         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1934         if (rc != 0) {
1935                 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1936         }
1937
1938         /* Now clean mcast object... */
1939
1940         rparam.mcast_obj = &sc->mcast_obj;
1941         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1942
1943         /* Add a DEL command... */
1944         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1945         if (rc < 0) {
1946                 PMD_DRV_LOG(NOTICE,
1947                             "Failed to send DEL MCAST command (%d)", rc);
1948         }
1949
1950         /* now wait until all pending commands are cleared */
1951
1952         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1953         while (rc != 0) {
1954                 if (rc < 0) {
1955                         PMD_DRV_LOG(NOTICE,
1956                                     "Failed to clean MCAST object (%d)", rc);
1957                         return;
1958                 }
1959
1960                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1961         }
1962 }
1963
1964 /* stop the controller */
1965 __attribute__ ((noinline))
1966 int
1967 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1968 {
1969         uint8_t global = FALSE;
1970         uint32_t val;
1971
1972         PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1973
1974         /* stop the periodic callout */
1975         bnx2x_periodic_stop(sc);
1976
1977         /* mark driver as unloaded in shmem2 */
1978         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1979                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1980                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1981                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1982         }
1983
1984         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1985             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1986                 /*
1987                  * We can get here if the driver has been unloaded
1988                  * during parity error recovery and is either waiting for a
1989                  * leader to complete or for other functions to unload and
1990                  * then ifconfig down has been issued. In this case we want to
1991                  * unload and let other functions to complete a recovery
1992                  * process.
1993                  */
1994                 sc->recovery_state = BNX2X_RECOVERY_DONE;
1995                 sc->is_leader = 0;
1996                 bnx2x_release_leader_lock(sc);
1997                 mb();
1998
1999                 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
2000                 return -1;
2001         }
2002
2003         /*
2004          * Nothing to do during unload if previous bnx2x_nic_load()
2005          * did not completed succesfully - all resourses are released.
2006          */
2007         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2008                 return 0;
2009         }
2010
2011         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2012         mb();
2013
2014         sc->rx_mode = BNX2X_RX_MODE_NONE;
2015         bnx2x_set_rx_mode(sc);
2016         mb();
2017
2018         if (IS_PF(sc)) {
2019                 /* set ALWAYS_ALIVE bit in shmem */
2020                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2021
2022                 bnx2x_drv_pulse(sc);
2023
2024                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2025                 bnx2x_save_statistics(sc);
2026         }
2027
2028         /* wait till consumers catch up with producers in all queues */
2029         bnx2x_drain_tx_queues(sc);
2030
2031         /* if VF indicate to PF this function is going down (PF will delete sp
2032          * elements and clear initializations
2033          */
2034         if (IS_VF(sc)) {
2035                 bnx2x_vf_unload(sc);
2036         } else if (unload_mode != UNLOAD_RECOVERY) {
2037                 /* if this is a normal/close unload need to clean up chip */
2038                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2039         } else {
2040                 /* Send the UNLOAD_REQUEST to the MCP */
2041                 bnx2x_send_unload_req(sc, unload_mode);
2042
2043                 /*
2044                  * Prevent transactions to host from the functions on the
2045                  * engine that doesn't reset global blocks in case of global
2046                  * attention once gloabl blocks are reset and gates are opened
2047                  * (the engine which leader will perform the recovery
2048                  * last).
2049                  */
2050                 if (!CHIP_IS_E1x(sc)) {
2051                         bnx2x_pf_disable(sc);
2052                 }
2053
2054                 /* disable HW interrupts */
2055                 bnx2x_int_disable_sync(sc, TRUE);
2056
2057                 /* Report UNLOAD_DONE to MCP */
2058                 bnx2x_send_unload_done(sc, FALSE);
2059         }
2060
2061         /*
2062          * At this stage no more interrupts will arrive so we may safely clean
2063          * the queue'able objects here in case they failed to get cleaned so far.
2064          */
2065         if (IS_PF(sc)) {
2066                 bnx2x_squeeze_objects(sc);
2067         }
2068
2069         /* There should be no more pending SP commands at this stage */
2070         sc->sp_state = 0;
2071
2072         sc->port.pmf = 0;
2073
2074         if (IS_PF(sc)) {
2075                 bnx2x_free_mem(sc);
2076         }
2077
2078         bnx2x_free_fw_stats_mem(sc);
2079
2080         sc->state = BNX2X_STATE_CLOSED;
2081
2082         /*
2083          * Check if there are pending parity attentions. If there are - set
2084          * RECOVERY_IN_PROGRESS.
2085          */
2086         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2087                 bnx2x_set_reset_in_progress(sc);
2088
2089                 /* Set RESET_IS_GLOBAL if needed */
2090                 if (global) {
2091                         bnx2x_set_reset_global(sc);
2092                 }
2093         }
2094
2095         /*
2096          * The last driver must disable a "close the gate" if there is no
2097          * parity attention or "process kill" pending.
2098          */
2099         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2100             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2101                 bnx2x_disable_close_the_gate(sc);
2102         }
2103
2104         PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2105
2106         return 0;
2107 }
2108
2109 /*
2110  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2111  * visible to the controller.
2112  *
2113  * If an mbuf is submitted to this routine and cannot be given to the
2114  * controller (e.g. it has too many fragments) then the function may free
2115  * the mbuf and return to the caller.
2116  *
2117  * Returns:
2118  *     int: Number of TX BDs used for the mbuf
2119  *
2120  *   Note the side effect that an mbuf may be freed if it causes a problem.
2121  */
2122 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2123 {
2124         struct eth_tx_start_bd *tx_start_bd;
2125         uint16_t bd_prod, pkt_prod;
2126         struct bnx2x_softc *sc;
2127         uint32_t nbds = 0;
2128
2129         sc = txq->sc;
2130         bd_prod = txq->tx_bd_tail;
2131         pkt_prod = txq->tx_pkt_tail;
2132
2133         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2134
2135         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2136
2137         tx_start_bd->addr =
2138             rte_cpu_to_le_64(rte_mbuf_data_dma_addr(m0));
2139         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2140         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2141         tx_start_bd->general_data =
2142             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2143
2144         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2145
2146         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2147                 tx_start_bd->vlan_or_ethertype =
2148                     rte_cpu_to_le_16(m0->vlan_tci);
2149                 tx_start_bd->bd_flags.as_bitfield |=
2150                     (X_ETH_OUTBAND_VLAN <<
2151                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2152         } else {
2153                 if (IS_PF(sc))
2154                         tx_start_bd->vlan_or_ethertype =
2155                             rte_cpu_to_le_16(pkt_prod);
2156                 else {
2157                         struct ether_hdr *eh =
2158                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2159
2160                         tx_start_bd->vlan_or_ethertype =
2161                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2162                 }
2163         }
2164
2165         bd_prod = NEXT_TX_BD(bd_prod);
2166         if (IS_VF(sc)) {
2167                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2168                 const struct ether_hdr *eh =
2169                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2170                 uint8_t mac_type = UNICAST_ADDRESS;
2171
2172                 tx_parse_bd =
2173                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2174                 if (is_multicast_ether_addr(&eh->d_addr)) {
2175                         if (is_broadcast_ether_addr(&eh->d_addr))
2176                                 mac_type = BROADCAST_ADDRESS;
2177                         else
2178                                 mac_type = MULTICAST_ADDRESS;
2179                 }
2180                 tx_parse_bd->parsing_data =
2181                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2182
2183                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2184                            &eh->d_addr.addr_bytes[0], 2);
2185                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2186                            &eh->d_addr.addr_bytes[2], 2);
2187                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2188                            &eh->d_addr.addr_bytes[4], 2);
2189                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2190                            &eh->s_addr.addr_bytes[0], 2);
2191                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2192                            &eh->s_addr.addr_bytes[2], 2);
2193                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2194                            &eh->s_addr.addr_bytes[4], 2);
2195
2196                 tx_parse_bd->data.mac_addr.dst_hi =
2197                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2198                 tx_parse_bd->data.mac_addr.dst_mid =
2199                     rte_cpu_to_be_16(tx_parse_bd->data.
2200                                      mac_addr.dst_mid);
2201                 tx_parse_bd->data.mac_addr.dst_lo =
2202                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2203                 tx_parse_bd->data.mac_addr.src_hi =
2204                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2205                 tx_parse_bd->data.mac_addr.src_mid =
2206                     rte_cpu_to_be_16(tx_parse_bd->data.
2207                                      mac_addr.src_mid);
2208                 tx_parse_bd->data.mac_addr.src_lo =
2209                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2210
2211                 PMD_TX_LOG(DEBUG,
2212                            "PBD dst %x %x %x src %x %x %x p_data %x",
2213                            tx_parse_bd->data.mac_addr.dst_hi,
2214                            tx_parse_bd->data.mac_addr.dst_mid,
2215                            tx_parse_bd->data.mac_addr.dst_lo,
2216                            tx_parse_bd->data.mac_addr.src_hi,
2217                            tx_parse_bd->data.mac_addr.src_mid,
2218                            tx_parse_bd->data.mac_addr.src_lo,
2219                            tx_parse_bd->parsing_data);
2220         }
2221
2222         PMD_TX_LOG(DEBUG,
2223                    "start bd: nbytes %d flags %x vlan %x\n",
2224                    tx_start_bd->nbytes,
2225                    tx_start_bd->bd_flags.as_bitfield,
2226                    tx_start_bd->vlan_or_ethertype);
2227
2228         bd_prod = NEXT_TX_BD(bd_prod);
2229         pkt_prod++;
2230
2231         if (TX_IDX(bd_prod) < 2)
2232                 nbds++;
2233
2234         txq->nb_tx_avail -= 2;
2235         txq->tx_bd_tail = bd_prod;
2236         txq->tx_pkt_tail = pkt_prod;
2237
2238         return nbds + 2;
2239 }
2240
2241 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2242 {
2243         return L2_ILT_LINES(sc);
2244 }
2245
2246 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2247 {
2248         struct ilt_client_info *ilt_client;
2249         struct ecore_ilt *ilt = sc->ilt;
2250         uint16_t line = 0;
2251
2252         PMD_INIT_FUNC_TRACE();
2253
2254         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2255
2256         /* CDU */
2257         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2258         ilt_client->client_num = ILT_CLIENT_CDU;
2259         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2260         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2261         ilt_client->start = line;
2262         line += bnx2x_cid_ilt_lines(sc);
2263
2264         if (CNIC_SUPPORT(sc)) {
2265                 line += CNIC_ILT_LINES;
2266         }
2267
2268         ilt_client->end = (line - 1);
2269
2270         /* QM */
2271         if (QM_INIT(sc->qm_cid_count)) {
2272                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2273                 ilt_client->client_num = ILT_CLIENT_QM;
2274                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2275                 ilt_client->flags = 0;
2276                 ilt_client->start = line;
2277
2278                 /* 4 bytes for each cid */
2279                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2280                                      QM_ILT_PAGE_SZ);
2281
2282                 ilt_client->end = (line - 1);
2283         }
2284
2285         if (CNIC_SUPPORT(sc)) {
2286                 /* SRC */
2287                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2288                 ilt_client->client_num = ILT_CLIENT_SRC;
2289                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2290                 ilt_client->flags = 0;
2291                 ilt_client->start = line;
2292                 line += SRC_ILT_LINES;
2293                 ilt_client->end = (line - 1);
2294
2295                 /* TM */
2296                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2297                 ilt_client->client_num = ILT_CLIENT_TM;
2298                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2299                 ilt_client->flags = 0;
2300                 ilt_client->start = line;
2301                 line += TM_ILT_LINES;
2302                 ilt_client->end = (line - 1);
2303         }
2304
2305         assert((line <= ILT_MAX_LINES));
2306 }
2307
2308 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2309 {
2310         int i;
2311
2312         for (i = 0; i < sc->num_queues; i++) {
2313                 /* get the Rx buffer size for RX frames */
2314                 sc->fp[i].rx_buf_size =
2315                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2316         }
2317 }
2318
2319 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2320 {
2321
2322         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2323
2324         return sc->ilt == NULL;
2325 }
2326
2327 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2328 {
2329         sc->ilt->lines = rte_calloc("",
2330                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2331                                     RTE_CACHE_LINE_SIZE);
2332         return sc->ilt->lines == NULL;
2333 }
2334
2335 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2336 {
2337         rte_free(sc->ilt);
2338         sc->ilt = NULL;
2339 }
2340
2341 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2342 {
2343         if (sc->ilt->lines != NULL) {
2344                 rte_free(sc->ilt->lines);
2345                 sc->ilt->lines = NULL;
2346         }
2347 }
2348
2349 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2350 {
2351         uint32_t i;
2352
2353         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2354                 sc->context[i].vcxt = NULL;
2355                 sc->context[i].size = 0;
2356         }
2357
2358         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2359
2360         bnx2x_free_ilt_lines_mem(sc);
2361 }
2362
2363 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2364 {
2365         int context_size;
2366         int allocated;
2367         int i;
2368         char cdu_name[RTE_MEMZONE_NAMESIZE];
2369
2370         /*
2371          * Allocate memory for CDU context:
2372          * This memory is allocated separately and not in the generic ILT
2373          * functions because CDU differs in few aspects:
2374          * 1. There can be multiple entities allocating memory for context -
2375          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2376          * its own ILT lines.
2377          * 2. Since CDU page-size is not a single 4KB page (which is the case
2378          * for the other ILT clients), to be efficient we want to support
2379          * allocation of sub-page-size in the last entry.
2380          * 3. Context pointers are used by the driver to pass to FW / update
2381          * the context (for the other ILT clients the pointers are used just to
2382          * free the memory during unload).
2383          */
2384         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2385         for (i = 0, allocated = 0; allocated < context_size; i++) {
2386                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2387                                           (context_size - allocated));
2388
2389                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2390                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2391                                   &sc->context[i].vcxt_dma,
2392                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2393                         bnx2x_free_mem(sc);
2394                         return -1;
2395                 }
2396
2397                 sc->context[i].vcxt =
2398                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2399
2400                 allocated += sc->context[i].size;
2401         }
2402
2403         bnx2x_alloc_ilt_lines_mem(sc);
2404
2405         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2406                 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2407                 bnx2x_free_mem(sc);
2408                 return -1;
2409         }
2410
2411         return 0;
2412 }
2413
2414 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2415 {
2416         sc->fw_stats_num = 0;
2417
2418         sc->fw_stats_req_size = 0;
2419         sc->fw_stats_req = NULL;
2420         sc->fw_stats_req_mapping = 0;
2421
2422         sc->fw_stats_data_size = 0;
2423         sc->fw_stats_data = NULL;
2424         sc->fw_stats_data_mapping = 0;
2425 }
2426
2427 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2428 {
2429         uint8_t num_queue_stats;
2430         int num_groups, vf_headroom = 0;
2431
2432         /* number of queues for statistics is number of eth queues */
2433         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2434
2435         /*
2436          * Total number of FW statistics requests =
2437          *   1 for port stats + 1 for PF stats + num of queues
2438          */
2439         sc->fw_stats_num = (2 + num_queue_stats);
2440
2441         /*
2442          * Request is built from stats_query_header and an array of
2443          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2444          * rules. The real number or requests is configured in the
2445          * stats_query_header.
2446          */
2447         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2448         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2449                 num_groups++;
2450
2451         sc->fw_stats_req_size =
2452             (sizeof(struct stats_query_header) +
2453              (num_groups * sizeof(struct stats_query_cmd_group)));
2454
2455         /*
2456          * Data for statistics requests + stats_counter.
2457          * stats_counter holds per-STORM counters that are incremented when
2458          * STORM has finished with the current request. Memory for FCoE
2459          * offloaded statistics are counted anyway, even if they will not be sent.
2460          * VF stats are not accounted for here as the data of VF stats is stored
2461          * in memory allocated by the VF, not here.
2462          */
2463         sc->fw_stats_data_size =
2464             (sizeof(struct stats_counter) +
2465              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2466              /* sizeof(struct fcoe_statistics_params) + */
2467              (sizeof(struct per_queue_stats) * num_queue_stats));
2468
2469         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2470                           &sc->fw_stats_dma, "fw_stats",
2471                           RTE_CACHE_LINE_SIZE) != 0) {
2472                 bnx2x_free_fw_stats_mem(sc);
2473                 return -1;
2474         }
2475
2476         /* set up the shortcuts */
2477
2478         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2479         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2480
2481         sc->fw_stats_data =
2482             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2483                                          sc->fw_stats_req_size);
2484         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2485                                      sc->fw_stats_req_size);
2486
2487         return 0;
2488 }
2489
2490 /*
2491  * Bits map:
2492  * 0-7  - Engine0 load counter.
2493  * 8-15 - Engine1 load counter.
2494  * 16   - Engine0 RESET_IN_PROGRESS bit.
2495  * 17   - Engine1 RESET_IN_PROGRESS bit.
2496  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2497  *        function on the engine
2498  * 19   - Engine1 ONE_IS_LOADED.
2499  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2500  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2501  *        for just the one belonging to its engine).
2502  */
2503 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2504 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2505 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2506 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2507 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2508 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2509 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2510 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2511
2512 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2513 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2514 {
2515         uint32_t val;
2516         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2517         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2518         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2519         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2520 }
2521
2522 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2523 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2524 {
2525         uint32_t val;
2526         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2527         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2528         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2529         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2530 }
2531
2532 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2533 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2534 {
2535         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2536 }
2537
2538 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2539 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2540 {
2541         uint32_t val;
2542         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2543             BNX2X_PATH0_RST_IN_PROG_BIT;
2544
2545         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2546
2547         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2548         /* Clear the bit */
2549         val &= ~bit;
2550         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2551
2552         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2553 }
2554
2555 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2556 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2557 {
2558         uint32_t val;
2559         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2560             BNX2X_PATH0_RST_IN_PROG_BIT;
2561
2562         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2563
2564         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2565         /* Set the bit */
2566         val |= bit;
2567         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2568
2569         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2570 }
2571
2572 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2573 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2574 {
2575         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2576         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2577             BNX2X_PATH0_RST_IN_PROG_BIT;
2578
2579         /* return false if bit is set */
2580         return (val & bit) ? FALSE : TRUE;
2581 }
2582
2583 /* get the load status for an engine, should be run under rtnl lock */
2584 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2585 {
2586         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2587             BNX2X_PATH0_LOAD_CNT_MASK;
2588         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2589             BNX2X_PATH0_LOAD_CNT_SHIFT;
2590         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2591
2592         val = ((val & mask) >> shift);
2593
2594         return val != 0;
2595 }
2596
2597 /* set pf load mark */
2598 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2599 {
2600         uint32_t val;
2601         uint32_t val1;
2602         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2603             BNX2X_PATH0_LOAD_CNT_MASK;
2604         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2605             BNX2X_PATH0_LOAD_CNT_SHIFT;
2606
2607         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2608
2609         PMD_INIT_FUNC_TRACE();
2610
2611         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2612
2613         /* get the current counter value */
2614         val1 = ((val & mask) >> shift);
2615
2616         /* set bit of this PF */
2617         val1 |= (1 << SC_ABS_FUNC(sc));
2618
2619         /* clear the old value */
2620         val &= ~mask;
2621
2622         /* set the new one */
2623         val |= ((val1 << shift) & mask);
2624
2625         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2626
2627         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2628 }
2629
2630 /* clear pf load mark */
2631 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2632 {
2633         uint32_t val1, val;
2634         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2635             BNX2X_PATH0_LOAD_CNT_MASK;
2636         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2637             BNX2X_PATH0_LOAD_CNT_SHIFT;
2638
2639         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2640         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2641
2642         /* get the current counter value */
2643         val1 = (val & mask) >> shift;
2644
2645         /* clear bit of that PF */
2646         val1 &= ~(1 << SC_ABS_FUNC(sc));
2647
2648         /* clear the old value */
2649         val &= ~mask;
2650
2651         /* set the new one */
2652         val |= ((val1 << shift) & mask);
2653
2654         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2655         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2656         return val1 != 0;
2657 }
2658
2659 /* send load requrest to mcp and analyze response */
2660 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2661 {
2662         PMD_INIT_FUNC_TRACE();
2663
2664         /* init fw_seq */
2665         sc->fw_seq =
2666             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2667              DRV_MSG_SEQ_NUMBER_MASK);
2668
2669         PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2670
2671 #ifdef BNX2X_PULSE
2672         /* get the current FW pulse sequence */
2673         sc->fw_drv_pulse_wr_seq =
2674             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2675              DRV_PULSE_SEQ_MASK);
2676 #else
2677         /* set ALWAYS_ALIVE bit in shmem */
2678         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2679         bnx2x_drv_pulse(sc);
2680 #endif
2681
2682         /* load request */
2683         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2684                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2685
2686         /* if the MCP fails to respond we must abort */
2687         if (!(*load_code)) {
2688                 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2689                 return -1;
2690         }
2691
2692         /* if MCP refused then must abort */
2693         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2694                 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2695                 return -1;
2696         }
2697
2698         return 0;
2699 }
2700
2701 /*
2702  * Check whether another PF has already loaded FW to chip. In virtualized
2703  * environments a pf from anoth VM may have already initialized the device
2704  * including loading FW.
2705  */
2706 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2707 {
2708         uint32_t my_fw, loaded_fw;
2709
2710         /* is another pf loaded on this engine? */
2711         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2712             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2713                 /* build my FW version dword */
2714                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2715                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2716                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2717                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2718
2719                 /* read loaded FW from chip */
2720                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2721                 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2722                             loaded_fw, my_fw);
2723
2724                 /* abort nic load if version mismatch */
2725                 if (my_fw != loaded_fw) {
2726                         PMD_DRV_LOG(NOTICE,
2727                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2728                                     loaded_fw, my_fw);
2729                         return -1;
2730                 }
2731         }
2732
2733         return 0;
2734 }
2735
2736 /* mark PMF if applicable */
2737 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2738 {
2739         uint32_t ncsi_oem_data_addr;
2740
2741         PMD_INIT_FUNC_TRACE();
2742
2743         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2744             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2745             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2746                 /*
2747                  * Barrier here for ordering between the writing to sc->port.pmf here
2748                  * and reading it from the periodic task.
2749                  */
2750                 sc->port.pmf = 1;
2751                 mb();
2752         } else {
2753                 sc->port.pmf = 0;
2754         }
2755
2756         PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2757
2758         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2759                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2760                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2761                         if (ncsi_oem_data_addr) {
2762                                 REG_WR(sc,
2763                                        (ncsi_oem_data_addr +
2764                                         offsetof(struct glob_ncsi_oem_data,
2765                                                  driver_version)), 0);
2766                         }
2767                 }
2768         }
2769 }
2770
2771 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2772 {
2773         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2774         int abs_func;
2775         int vn;
2776
2777         if (BNX2X_NOMCP(sc)) {
2778                 return;         /* what should be the default bvalue in this case */
2779         }
2780
2781         /*
2782          * The formula for computing the absolute function number is...
2783          * For 2 port configuration (4 functions per port):
2784          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2785          * For 4 port configuration (2 functions per port):
2786          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2787          */
2788         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2789                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2790                 if (abs_func >= E1H_FUNC_MAX) {
2791                         break;
2792                 }
2793                 sc->devinfo.mf_info.mf_config[vn] =
2794                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2795         }
2796
2797         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2798             FUNC_MF_CFG_FUNC_DISABLED) {
2799                 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2800                 sc->flags |= BNX2X_MF_FUNC_DIS;
2801         } else {
2802                 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2803                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2804         }
2805 }
2806
2807 /* acquire split MCP access lock register */
2808 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2809 {
2810         uint32_t j, val;
2811
2812         for (j = 0; j < 1000; j++) {
2813                 val = (1UL << 31);
2814                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2815                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2816                 if (val & (1L << 31))
2817                         break;
2818
2819                 DELAY(5000);
2820         }
2821
2822         if (!(val & (1L << 31))) {
2823                 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2824                 return -1;
2825         }
2826
2827         return 0;
2828 }
2829
2830 /* release split MCP access lock register */
2831 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2832 {
2833         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2834 }
2835
2836 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2837 {
2838         int port = SC_PORT(sc);
2839         uint32_t ext_phy_config;
2840
2841         /* mark the failure */
2842         ext_phy_config =
2843             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2844
2845         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2846         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2847         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2848                  ext_phy_config);
2849
2850         /* log the failure */
2851         PMD_DRV_LOG(INFO,
2852                     "Fan Failure has caused the driver to shutdown "
2853                     "the card to prevent permanent damage. "
2854                     "Please contact OEM Support for assistance");
2855
2856         rte_panic("Schedule task to handle fan failure");
2857 }
2858
2859 /* this function is called upon a link interrupt */
2860 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2861 {
2862         uint32_t pause_enabled = 0;
2863         struct host_port_stats *pstats;
2864         int cmng_fns;
2865
2866         /* Make sure that we are synced with the current statistics */
2867         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2868
2869         elink_link_update(&sc->link_params, &sc->link_vars);
2870
2871         if (sc->link_vars.link_up) {
2872
2873                 /* dropless flow control */
2874                 if (sc->dropless_fc) {
2875                         pause_enabled = 0;
2876
2877                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2878                                 pause_enabled = 1;
2879                         }
2880
2881                         REG_WR(sc,
2882                                (BAR_USTRORM_INTMEM +
2883                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2884                                pause_enabled);
2885                 }
2886
2887                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2888                         pstats = BNX2X_SP(sc, port_stats);
2889                         /* reset old mac stats */
2890                         memset(&(pstats->mac_stx[0]), 0,
2891                                sizeof(struct mac_stx));
2892                 }
2893
2894                 if (sc->state == BNX2X_STATE_OPEN) {
2895                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2896                 }
2897         }
2898
2899         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2900                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2901
2902                 if (cmng_fns != CMNG_FNS_NONE) {
2903                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2904                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2905                 }
2906         }
2907
2908         bnx2x_link_report(sc);
2909
2910         if (IS_MF(sc)) {
2911                 bnx2x_link_sync_notify(sc);
2912         }
2913 }
2914
2915 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2916 {
2917         int port = SC_PORT(sc);
2918         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2919             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2920         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2921             NIG_REG_MASK_INTERRUPT_PORT0;
2922         uint32_t aeu_mask;
2923         uint32_t nig_mask = 0;
2924         uint32_t reg_addr;
2925         uint32_t igu_acked;
2926         uint32_t cnt;
2927
2928         if (sc->attn_state & asserted) {
2929                 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2930         }
2931
2932         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2933
2934         aeu_mask = REG_RD(sc, aeu_addr);
2935
2936         aeu_mask &= ~(asserted & 0x3ff);
2937
2938         REG_WR(sc, aeu_addr, aeu_mask);
2939
2940         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2941
2942         sc->attn_state |= asserted;
2943
2944         if (asserted & ATTN_HARD_WIRED_MASK) {
2945                 if (asserted & ATTN_NIG_FOR_FUNC) {
2946
2947                         /* save nig interrupt mask */
2948                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2949
2950                         /* If nig_mask is not set, no need to call the update function */
2951                         if (nig_mask) {
2952                                 REG_WR(sc, nig_int_mask_addr, 0);
2953
2954                                 bnx2x_link_attn(sc);
2955                         }
2956
2957                         /* handle unicore attn? */
2958                 }
2959
2960                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2961                         PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2962                 }
2963
2964                 if (asserted & GPIO_2_FUNC) {
2965                         PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2966                 }
2967
2968                 if (asserted & GPIO_3_FUNC) {
2969                         PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2970                 }
2971
2972                 if (asserted & GPIO_4_FUNC) {
2973                         PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2974                 }
2975
2976                 if (port == 0) {
2977                         if (asserted & ATTN_GENERAL_ATTN_1) {
2978                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2979                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2980                         }
2981                         if (asserted & ATTN_GENERAL_ATTN_2) {
2982                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2983                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2984                         }
2985                         if (asserted & ATTN_GENERAL_ATTN_3) {
2986                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2987                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2988                         }
2989                 } else {
2990                         if (asserted & ATTN_GENERAL_ATTN_4) {
2991                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2992                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2993                         }
2994                         if (asserted & ATTN_GENERAL_ATTN_5) {
2995                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2996                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2997                         }
2998                         if (asserted & ATTN_GENERAL_ATTN_6) {
2999                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
3000                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3001                         }
3002                 }
3003         }
3004         /* hardwired */
3005         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3006                 reg_addr =
3007                     (HC_REG_COMMAND_REG + port * 32 +
3008                      COMMAND_REG_ATTN_BITS_SET);
3009         } else {
3010                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3011         }
3012
3013         PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3014                     asserted,
3015                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3016                     reg_addr);
3017         REG_WR(sc, reg_addr, asserted);
3018
3019         /* now set back the mask */
3020         if (asserted & ATTN_NIG_FOR_FUNC) {
3021                 /*
3022                  * Verify that IGU ack through BAR was written before restoring
3023                  * NIG mask. This loop should exit after 2-3 iterations max.
3024                  */
3025                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3026                         cnt = 0;
3027
3028                         do {
3029                                 igu_acked =
3030                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3031                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3032                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3033
3034                         if (!igu_acked) {
3035                                 PMD_DRV_LOG(ERR,
3036                                             "Failed to verify IGU ack on time");
3037                         }
3038
3039                         mb();
3040                 }
3041
3042                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3043
3044         }
3045 }
3046
3047 static void
3048 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3049                      __rte_unused const char *blk)
3050 {
3051         PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3052 }
3053
3054 static int
3055 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3056                               uint8_t print)
3057 {
3058         uint32_t cur_bit = 0;
3059         int i = 0;
3060
3061         for (i = 0; sig; i++) {
3062                 cur_bit = ((uint32_t) 0x1 << i);
3063                 if (sig & cur_bit) {
3064                         switch (cur_bit) {
3065                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3066                                 if (print)
3067                                         bnx2x_print_next_block(sc, par_num++,
3068                                                              "BRB");
3069                                 break;
3070                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3071                                 if (print)
3072                                         bnx2x_print_next_block(sc, par_num++,
3073                                                              "PARSER");
3074                                 break;
3075                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3076                                 if (print)
3077                                         bnx2x_print_next_block(sc, par_num++,
3078                                                              "TSDM");
3079                                 break;
3080                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3081                                 if (print)
3082                                         bnx2x_print_next_block(sc, par_num++,
3083                                                              "SEARCHER");
3084                                 break;
3085                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3086                                 if (print)
3087                                         bnx2x_print_next_block(sc, par_num++,
3088                                                              "TCM");
3089                                 break;
3090                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3091                                 if (print)
3092                                         bnx2x_print_next_block(sc, par_num++,
3093                                                              "TSEMI");
3094                                 break;
3095                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3096                                 if (print)
3097                                         bnx2x_print_next_block(sc, par_num++,
3098                                                              "XPB");
3099                                 break;
3100                         }
3101
3102                         /* Clear the bit */
3103                         sig &= ~cur_bit;
3104                 }
3105         }
3106
3107         return par_num;
3108 }
3109
3110 static int
3111 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3112                               uint8_t * global, uint8_t print)
3113 {
3114         int i = 0;
3115         uint32_t cur_bit = 0;
3116         for (i = 0; sig; i++) {
3117                 cur_bit = ((uint32_t) 0x1 << i);
3118                 if (sig & cur_bit) {
3119                         switch (cur_bit) {
3120                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3121                                 if (print)
3122                                         bnx2x_print_next_block(sc, par_num++,
3123                                                              "PBF");
3124                                 break;
3125                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3126                                 if (print)
3127                                         bnx2x_print_next_block(sc, par_num++,
3128                                                              "QM");
3129                                 break;
3130                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3131                                 if (print)
3132                                         bnx2x_print_next_block(sc, par_num++,
3133                                                              "TM");
3134                                 break;
3135                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3136                                 if (print)
3137                                         bnx2x_print_next_block(sc, par_num++,
3138                                                              "XSDM");
3139                                 break;
3140                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3141                                 if (print)
3142                                         bnx2x_print_next_block(sc, par_num++,
3143                                                              "XCM");
3144                                 break;
3145                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3146                                 if (print)
3147                                         bnx2x_print_next_block(sc, par_num++,
3148                                                              "XSEMI");
3149                                 break;
3150                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3151                                 if (print)
3152                                         bnx2x_print_next_block(sc, par_num++,
3153                                                              "DOORBELLQ");
3154                                 break;
3155                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3156                                 if (print)
3157                                         bnx2x_print_next_block(sc, par_num++,
3158                                                              "NIG");
3159                                 break;
3160                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3161                                 if (print)
3162                                         bnx2x_print_next_block(sc, par_num++,
3163                                                              "VAUX PCI CORE");
3164                                 *global = TRUE;
3165                                 break;
3166                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3167                                 if (print)
3168                                         bnx2x_print_next_block(sc, par_num++,
3169                                                              "DEBUG");
3170                                 break;
3171                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3172                                 if (print)
3173                                         bnx2x_print_next_block(sc, par_num++,
3174                                                              "USDM");
3175                                 break;
3176                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3177                                 if (print)
3178                                         bnx2x_print_next_block(sc, par_num++,
3179                                                              "UCM");
3180                                 break;
3181                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3182                                 if (print)
3183                                         bnx2x_print_next_block(sc, par_num++,
3184                                                              "USEMI");
3185                                 break;
3186                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3187                                 if (print)
3188                                         bnx2x_print_next_block(sc, par_num++,
3189                                                              "UPB");
3190                                 break;
3191                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3192                                 if (print)
3193                                         bnx2x_print_next_block(sc, par_num++,
3194                                                              "CSDM");
3195                                 break;
3196                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3197                                 if (print)
3198                                         bnx2x_print_next_block(sc, par_num++,
3199                                                              "CCM");
3200                                 break;
3201                         }
3202
3203                         /* Clear the bit */
3204                         sig &= ~cur_bit;
3205                 }
3206         }
3207
3208         return par_num;
3209 }
3210
3211 static int
3212 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3213                               uint8_t print)
3214 {
3215         uint32_t cur_bit = 0;
3216         int i = 0;
3217
3218         for (i = 0; sig; i++) {
3219                 cur_bit = ((uint32_t) 0x1 << i);
3220                 if (sig & cur_bit) {
3221                         switch (cur_bit) {
3222                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3223                                 if (print)
3224                                         bnx2x_print_next_block(sc, par_num++,
3225                                                              "CSEMI");
3226                                 break;
3227                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3228                                 if (print)
3229                                         bnx2x_print_next_block(sc, par_num++,
3230                                                              "PXP");
3231                                 break;
3232                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3233                                 if (print)
3234                                         bnx2x_print_next_block(sc, par_num++,
3235                                                              "PXPPCICLOCKCLIENT");
3236                                 break;
3237                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3238                                 if (print)
3239                                         bnx2x_print_next_block(sc, par_num++,
3240                                                              "CFC");
3241                                 break;
3242                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3243                                 if (print)
3244                                         bnx2x_print_next_block(sc, par_num++,
3245                                                              "CDU");
3246                                 break;
3247                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3248                                 if (print)
3249                                         bnx2x_print_next_block(sc, par_num++,
3250                                                              "DMAE");
3251                                 break;
3252                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3253                                 if (print)
3254                                         bnx2x_print_next_block(sc, par_num++,
3255                                                              "IGU");
3256                                 break;
3257                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3258                                 if (print)
3259                                         bnx2x_print_next_block(sc, par_num++,
3260                                                              "MISC");
3261                                 break;
3262                         }
3263
3264                         /* Clear the bit */
3265                         sig &= ~cur_bit;
3266                 }
3267         }
3268
3269         return par_num;
3270 }
3271
3272 static int
3273 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3274                               uint8_t * global, uint8_t print)
3275 {
3276         uint32_t cur_bit = 0;
3277         int i = 0;
3278
3279         for (i = 0; sig; i++) {
3280                 cur_bit = ((uint32_t) 0x1 << i);
3281                 if (sig & cur_bit) {
3282                         switch (cur_bit) {
3283                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3284                                 if (print)
3285                                         bnx2x_print_next_block(sc, par_num++,
3286                                                              "MCP ROM");
3287                                 *global = TRUE;
3288                                 break;
3289                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3290                                 if (print)
3291                                         bnx2x_print_next_block(sc, par_num++,
3292                                                              "MCP UMP RX");
3293                                 *global = TRUE;
3294                                 break;
3295                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3296                                 if (print)
3297                                         bnx2x_print_next_block(sc, par_num++,
3298                                                              "MCP UMP TX");
3299                                 *global = TRUE;
3300                                 break;
3301                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3302                                 if (print)
3303                                         bnx2x_print_next_block(sc, par_num++,
3304                                                              "MCP SCPAD");
3305                                 *global = TRUE;
3306                                 break;
3307                         }
3308
3309                         /* Clear the bit */
3310                         sig &= ~cur_bit;
3311                 }
3312         }
3313
3314         return par_num;
3315 }
3316
3317 static int
3318 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3319                               uint8_t print)
3320 {
3321         uint32_t cur_bit = 0;
3322         int i = 0;
3323
3324         for (i = 0; sig; i++) {
3325                 cur_bit = ((uint32_t) 0x1 << i);
3326                 if (sig & cur_bit) {
3327                         switch (cur_bit) {
3328                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3329                                 if (print)
3330                                         bnx2x_print_next_block(sc, par_num++,
3331                                                              "PGLUE_B");
3332                                 break;
3333                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3334                                 if (print)
3335                                         bnx2x_print_next_block(sc, par_num++,
3336                                                              "ATC");
3337                                 break;
3338                         }
3339
3340                         /* Clear the bit */
3341                         sig &= ~cur_bit;
3342                 }
3343         }
3344
3345         return par_num;
3346 }
3347
3348 static uint8_t
3349 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3350                 uint32_t * sig)
3351 {
3352         int par_num = 0;
3353
3354         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3355             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3356             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3357             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3358             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3359                 PMD_DRV_LOG(ERR,
3360                             "Parity error: HW block parity attention:"
3361                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3362                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3363                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3364                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3365                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3366                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3367
3368                 if (print)
3369                         PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3370
3371                 par_num =
3372                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3373                                                   HW_PRTY_ASSERT_SET_0,
3374                                                   par_num, print);
3375                 par_num =
3376                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3377                                                   HW_PRTY_ASSERT_SET_1,
3378                                                   par_num, global, print);
3379                 par_num =
3380                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3381                                                   HW_PRTY_ASSERT_SET_2,
3382                                                   par_num, print);
3383                 par_num =
3384                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3385                                                   HW_PRTY_ASSERT_SET_3,
3386                                                   par_num, global, print);
3387                 par_num =
3388                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3389                                                   HW_PRTY_ASSERT_SET_4,
3390                                                   par_num, print);
3391
3392                 if (print)
3393                         PMD_DRV_LOG(INFO, "");
3394
3395                 return TRUE;
3396         }
3397
3398         return FALSE;
3399 }
3400
3401 static uint8_t
3402 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3403 {
3404         struct attn_route attn = { {0} };
3405         int port = SC_PORT(sc);
3406
3407         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3408         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3409         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3410         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3411
3412         if (!CHIP_IS_E1x(sc))
3413                 attn.sig[4] =
3414                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3415
3416         return bnx2x_parity_attn(sc, global, print, attn.sig);
3417 }
3418
3419 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3420 {
3421         uint32_t val;
3422
3423         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3424                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3425                 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3426                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3427                         PMD_DRV_LOG(INFO,
3428                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3429                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3430                         PMD_DRV_LOG(INFO,
3431                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3432                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3433                         PMD_DRV_LOG(INFO,
3434                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3435                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3436                         PMD_DRV_LOG(INFO,
3437                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3438                 if (val &
3439                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3440                         PMD_DRV_LOG(INFO,
3441                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3442                 if (val &
3443                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3444                         PMD_DRV_LOG(INFO,
3445                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3446                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3447                         PMD_DRV_LOG(INFO,
3448                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3449                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3450                         PMD_DRV_LOG(INFO,
3451                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3452                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3453                         PMD_DRV_LOG(INFO,
3454                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3455         }
3456
3457         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3458                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3459                 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3460                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3461                         PMD_DRV_LOG(INFO,
3462                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3463                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3464                         PMD_DRV_LOG(INFO,
3465                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3466                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3467                         PMD_DRV_LOG(INFO,
3468                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3469                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3470                         PMD_DRV_LOG(INFO,
3471                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3472                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3473                         PMD_DRV_LOG(INFO,
3474                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3475                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3476                         PMD_DRV_LOG(INFO,
3477                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3478         }
3479
3480         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3481                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3482                 PMD_DRV_LOG(INFO,
3483                             "ERROR: FATAL parity attention set4 0x%08x",
3484                             (uint32_t) (attn &
3485                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3486                                          |
3487                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3488         }
3489 }
3490
3491 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3492 {
3493         int port = SC_PORT(sc);
3494
3495         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3496 }
3497
3498 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3499 {
3500         int port = SC_PORT(sc);
3501
3502         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3503 }
3504
3505 /*
3506  * called due to MCP event (on pmf):
3507  *   reread new bandwidth configuration
3508  *   configure FW
3509  *   notify others function about the change
3510  */
3511 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3512 {
3513         if (sc->link_vars.link_up) {
3514                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3515                 bnx2x_link_sync_notify(sc);
3516         }
3517
3518         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3519 }
3520
3521 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3522 {
3523         bnx2x_config_mf_bw(sc);
3524         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3525 }
3526
3527 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3528 {
3529         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3530 }
3531
3532 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3533
3534 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3535 {
3536         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3537
3538         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3539                 ETH_STAT_INFO_VERSION_LEN);
3540
3541         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3542                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3543                                               ether_stat->mac_local + MAC_PAD,
3544                                               MAC_PAD, ETH_ALEN);
3545
3546         ether_stat->mtu_size = sc->mtu;
3547
3548         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3549         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3550
3551         ether_stat->txq_size = sc->tx_ring_size;
3552         ether_stat->rxq_size = sc->rx_ring_size;
3553 }
3554
3555 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3556 {
3557         enum drv_info_opcode op_code;
3558         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3559
3560         /* if drv_info version supported by MFW doesn't match - send NACK */
3561         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3562                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3563                 return;
3564         }
3565
3566         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3567                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3568
3569         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3570
3571         switch (op_code) {
3572         case ETH_STATS_OPCODE:
3573                 bnx2x_drv_info_ether_stat(sc);
3574                 break;
3575         case FCOE_STATS_OPCODE:
3576         case ISCSI_STATS_OPCODE:
3577         default:
3578                 /* if op code isn't supported - send NACK */
3579                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3580                 return;
3581         }
3582
3583         /*
3584          * If we got drv_info attn from MFW then these fields are defined in
3585          * shmem2 for sure
3586          */
3587         SHMEM2_WR(sc, drv_info_host_addr_lo,
3588                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3589         SHMEM2_WR(sc, drv_info_host_addr_hi,
3590                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3591
3592         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3593 }
3594
3595 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3596 {
3597         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3598 /*
3599  * This is the only place besides the function initialization
3600  * where the sc->flags can change so it is done without any
3601  * locks
3602  */
3603                 if (sc->devinfo.
3604                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3605                         PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3606                         sc->flags |= BNX2X_MF_FUNC_DIS;
3607                         bnx2x_e1h_disable(sc);
3608                 } else {
3609                         PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3610                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3611                         bnx2x_e1h_enable(sc);
3612                 }
3613                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3614         }
3615
3616         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3617                 bnx2x_config_mf_bw(sc);
3618                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3619         }
3620
3621         /* Report results to MCP */
3622         if (dcc_event)
3623                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3624         else
3625                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3626 }
3627
3628 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3629 {
3630         int port = SC_PORT(sc);
3631         uint32_t val;
3632
3633         sc->port.pmf = 1;
3634
3635         /*
3636          * We need the mb() to ensure the ordering between the writing to
3637          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3638          */
3639         mb();
3640
3641         /* enable nig attention */
3642         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3643         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3644                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3645                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3646         } else if (!CHIP_IS_E1x(sc)) {
3647                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3648                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3649         }
3650
3651         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3652 }
3653
3654 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3655 {
3656         char last_idx;
3657         int i, rc = 0;
3658         __rte_unused uint32_t row0, row1, row2, row3;
3659
3660         /* XSTORM */
3661         last_idx =
3662             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3663         if (last_idx)
3664                 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3665
3666         /* print the asserts */
3667         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3668
3669                 row0 =
3670                     REG_RD(sc,
3671                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3672                 row1 =
3673                     REG_RD(sc,
3674                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3675                            4);
3676                 row2 =
3677                     REG_RD(sc,
3678                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3679                            8);
3680                 row3 =
3681                     REG_RD(sc,
3682                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3683                            12);
3684
3685                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3686                         PMD_DRV_LOG(ERR,
3687                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3688                                     i, row3, row2, row1, row0);
3689                         rc++;
3690                 } else {
3691                         break;
3692                 }
3693         }
3694
3695         /* TSTORM */
3696         last_idx =
3697             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3698         if (last_idx) {
3699                 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3700         }
3701
3702         /* print the asserts */
3703         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3704
3705                 row0 =
3706                     REG_RD(sc,
3707                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3708                 row1 =
3709                     REG_RD(sc,
3710                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3711                            4);
3712                 row2 =
3713                     REG_RD(sc,
3714                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3715                            8);
3716                 row3 =
3717                     REG_RD(sc,
3718                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3719                            12);
3720
3721                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3722                         PMD_DRV_LOG(ERR,
3723                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3724                                     i, row3, row2, row1, row0);
3725                         rc++;
3726                 } else {
3727                         break;
3728                 }
3729         }
3730
3731         /* CSTORM */
3732         last_idx =
3733             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3734         if (last_idx) {
3735                 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3736         }
3737
3738         /* print the asserts */
3739         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3740
3741                 row0 =
3742                     REG_RD(sc,
3743                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3744                 row1 =
3745                     REG_RD(sc,
3746                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3747                            4);
3748                 row2 =
3749                     REG_RD(sc,
3750                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3751                            8);
3752                 row3 =
3753                     REG_RD(sc,
3754                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3755                            12);
3756
3757                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3758                         PMD_DRV_LOG(ERR,
3759                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3760                                     i, row3, row2, row1, row0);
3761                         rc++;
3762                 } else {
3763                         break;
3764                 }
3765         }
3766
3767         /* USTORM */
3768         last_idx =
3769             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3770         if (last_idx) {
3771                 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3772         }
3773
3774         /* print the asserts */
3775         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3776
3777                 row0 =
3778                     REG_RD(sc,
3779                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3780                 row1 =
3781                     REG_RD(sc,
3782                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3783                            4);
3784                 row2 =
3785                     REG_RD(sc,
3786                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3787                            8);
3788                 row3 =
3789                     REG_RD(sc,
3790                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3791                            12);
3792
3793                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3794                         PMD_DRV_LOG(ERR,
3795                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3796                                     i, row3, row2, row1, row0);
3797                         rc++;
3798                 } else {
3799                         break;
3800                 }
3801         }
3802
3803         return rc;
3804 }
3805
3806 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3807 {
3808         int func = SC_FUNC(sc);
3809         uint32_t val;
3810
3811         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3812
3813                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3814
3815                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3816                         bnx2x_read_mf_cfg(sc);
3817                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3818                             MFCFG_RD(sc,
3819                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3820                         val =
3821                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3822
3823                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3824                                 bnx2x_dcc_event(sc,
3825                                               (val &
3826                                                DRV_STATUS_DCC_EVENT_MASK));
3827
3828                         if (val & DRV_STATUS_SET_MF_BW)
3829                                 bnx2x_set_mf_bw(sc);
3830
3831                         if (val & DRV_STATUS_DRV_INFO_REQ)
3832                                 bnx2x_handle_drv_info_req(sc);
3833
3834                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3835                                 bnx2x_pmf_update(sc);
3836
3837                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3838                                 bnx2x_handle_eee_event(sc);
3839
3840                         if (sc->link_vars.periodic_flags &
3841                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3842                                 /* sync with link */
3843                                 sc->link_vars.periodic_flags &=
3844                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3845                                 if (IS_MF(sc)) {
3846                                         bnx2x_link_sync_notify(sc);
3847                                 }
3848                                 bnx2x_link_report(sc);
3849                         }
3850
3851                         /*
3852                          * Always call it here: bnx2x_link_report() will
3853                          * prevent the link indication duplication.
3854                          */
3855                         bnx2x_link_status_update(sc);
3856
3857                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3858
3859                         PMD_DRV_LOG(ERR, "MC assert!");
3860                         bnx2x_mc_assert(sc);
3861                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3862                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3863                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3864                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3865                         rte_panic("MC assert!");
3866
3867                 } else if (attn & BNX2X_MCP_ASSERT) {
3868
3869                         PMD_DRV_LOG(ERR, "MCP assert!");
3870                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3871
3872                 } else {
3873                         PMD_DRV_LOG(ERR,
3874                                     "Unknown HW assert! (attn 0x%08x)", attn);
3875                 }
3876         }
3877
3878         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3879                 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3880                 if (attn & BNX2X_GRC_TIMEOUT) {
3881                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3882                         PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3883                 }
3884                 if (attn & BNX2X_GRC_RSV) {
3885                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3886                         PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3887                 }
3888                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3889         }
3890 }
3891
3892 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3893 {
3894         int port = SC_PORT(sc);
3895         int reg_offset;
3896         uint32_t val0, mask0, val1, mask1;
3897         uint32_t val;
3898
3899         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3900                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3901                 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3902 /* CFC error attention */
3903                 if (val & 0x2) {
3904                         PMD_DRV_LOG(ERR, "FATAL error from CFC");
3905                 }
3906         }
3907
3908         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3909                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3910                 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3911 /* RQ_USDMDP_FIFO_OVERFLOW */
3912                 if (val & 0x18000) {
3913                         PMD_DRV_LOG(ERR, "FATAL error from PXP");
3914                 }
3915
3916                 if (!CHIP_IS_E1x(sc)) {
3917                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3918                         PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3919                 }
3920         }
3921 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3922 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3923
3924         if (attn & AEU_PXP2_HW_INT_BIT) {
3925 /*  CQ47854 workaround do not panic on
3926  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3927  */
3928                 if (!CHIP_IS_E1x(sc)) {
3929                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3930                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3931                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3932                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3933                         /*
3934                          * If the olny PXP2_EOP_ERROR_BIT is set in
3935                          * STS0 and STS1 - clear it
3936                          *
3937                          * probably we lose additional attentions between
3938                          * STS0 and STS_CLR0, in this case user will not
3939                          * be notified about them
3940                          */
3941                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3942                             !(val1 & mask1))
3943                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3944
3945                         /* print the register, since no one can restore it */
3946                         PMD_DRV_LOG(ERR,
3947                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3948
3949                         /*
3950                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3951                          * then notify
3952                          */
3953                         if (val0 & PXP2_EOP_ERROR_BIT) {
3954                                 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3955
3956                                 /*
3957                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3958                                  * set then clear attention from PXP2 block without panic
3959                                  */
3960                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3961                                     ((val1 & mask1) == 0))
3962                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3963                         }
3964                 }
3965         }
3966
3967         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3968                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3969                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3970
3971                 val = REG_RD(sc, reg_offset);
3972                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3973                 REG_WR(sc, reg_offset, val);
3974
3975                 PMD_DRV_LOG(ERR,
3976                             "FATAL HW block attention set2 0x%x",
3977                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3978                 rte_panic("HW block attention set2");
3979         }
3980 }
3981
3982 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3983 {
3984         int port = SC_PORT(sc);
3985         int reg_offset;
3986         uint32_t val;
3987
3988         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3989                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3990                 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3991 /* DORQ discard attention */
3992                 if (val & 0x2) {
3993                         PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3994                 }
3995         }
3996
3997         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3998                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3999                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4000
4001                 val = REG_RD(sc, reg_offset);
4002                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4003                 REG_WR(sc, reg_offset, val);
4004
4005                 PMD_DRV_LOG(ERR,
4006                             "FATAL HW block attention set1 0x%08x",
4007                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4008                 rte_panic("HW block attention set1");
4009         }
4010 }
4011
4012 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4013 {
4014         int port = SC_PORT(sc);
4015         int reg_offset;
4016         uint32_t val;
4017
4018         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4019             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4020
4021         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4022                 val = REG_RD(sc, reg_offset);
4023                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4024                 REG_WR(sc, reg_offset, val);
4025
4026                 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4027
4028 /* Fan failure attention */
4029                 elink_hw_reset_phy(&sc->link_params);
4030                 bnx2x_fan_failure(sc);
4031         }
4032
4033         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4034                 elink_handle_module_detect_int(&sc->link_params);
4035         }
4036
4037         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4038                 val = REG_RD(sc, reg_offset);
4039                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4040                 REG_WR(sc, reg_offset, val);
4041
4042                 rte_panic("FATAL HW block attention set0 0x%lx",
4043                           (attn & HW_INTERRUT_ASSERT_SET_0));
4044         }
4045 }
4046
4047 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4048 {
4049         struct attn_route attn;
4050         struct attn_route *group_mask;
4051         int port = SC_PORT(sc);
4052         int index;
4053         uint32_t reg_addr;
4054         uint32_t val;
4055         uint32_t aeu_mask;
4056         uint8_t global = FALSE;
4057
4058         /*
4059          * Need to take HW lock because MCP or other port might also
4060          * try to handle this event.
4061          */
4062         bnx2x_acquire_alr(sc);
4063
4064         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4065                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4066
4067 /* disable HW interrupts */
4068                 bnx2x_int_disable(sc);
4069                 bnx2x_release_alr(sc);
4070                 return;
4071         }
4072
4073         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4074         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4075         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4076         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4077         if (!CHIP_IS_E1x(sc)) {
4078                 attn.sig[4] =
4079                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4080         } else {
4081                 attn.sig[4] = 0;
4082         }
4083
4084         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4085                 if (deasserted & (1 << index)) {
4086                         group_mask = &sc->attn_group[index];
4087
4088                         bnx2x_attn_int_deasserted4(sc,
4089                                                  attn.
4090                                                  sig[4] & group_mask->sig[4]);
4091                         bnx2x_attn_int_deasserted3(sc,
4092                                                  attn.
4093                                                  sig[3] & group_mask->sig[3]);
4094                         bnx2x_attn_int_deasserted1(sc,
4095                                                  attn.
4096                                                  sig[1] & group_mask->sig[1]);
4097                         bnx2x_attn_int_deasserted2(sc,
4098                                                  attn.
4099                                                  sig[2] & group_mask->sig[2]);
4100                         bnx2x_attn_int_deasserted0(sc,
4101                                                  attn.
4102                                                  sig[0] & group_mask->sig[0]);
4103                 }
4104         }
4105
4106         bnx2x_release_alr(sc);
4107
4108         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4109                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4110                             COMMAND_REG_ATTN_BITS_CLR);
4111         } else {
4112                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4113         }
4114
4115         val = ~deasserted;
4116         PMD_DRV_LOG(DEBUG,
4117                     "about to mask 0x%08x at %s addr 0x%08x", val,
4118                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4119                     reg_addr);
4120         REG_WR(sc, reg_addr, val);
4121
4122         if (~sc->attn_state & deasserted) {
4123                 PMD_DRV_LOG(ERR, "IGU error");
4124         }
4125
4126         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4127             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4128
4129         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4130
4131         aeu_mask = REG_RD(sc, reg_addr);
4132
4133         aeu_mask |= (deasserted & 0x3ff);
4134
4135         REG_WR(sc, reg_addr, aeu_mask);
4136         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4137
4138         sc->attn_state &= ~deasserted;
4139 }
4140
4141 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4142 {
4143         /* read local copy of bits */
4144         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4145         uint32_t attn_ack =
4146             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4147         uint32_t attn_state = sc->attn_state;
4148
4149         /* look for changed bits */
4150         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4151         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4152
4153         PMD_DRV_LOG(DEBUG,
4154                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4155                     attn_bits, attn_ack, asserted, deasserted);
4156
4157         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4158                 PMD_DRV_LOG(ERR, "BAD attention state");
4159         }
4160
4161         /* handle bits that were raised */
4162         if (asserted) {
4163                 bnx2x_attn_int_asserted(sc, asserted);
4164         }
4165
4166         if (deasserted) {
4167                 bnx2x_attn_int_deasserted(sc, deasserted);
4168         }
4169 }
4170
4171 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4172 {
4173         struct host_sp_status_block *def_sb = sc->def_sb;
4174         uint16_t rc = 0;
4175
4176         mb();                   /* status block is written to by the chip */
4177
4178         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4179                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4180                 rc |= BNX2X_DEF_SB_ATT_IDX;
4181         }
4182
4183         if (sc->def_idx != def_sb->sp_sb.running_index) {
4184                 sc->def_idx = def_sb->sp_sb.running_index;
4185                 rc |= BNX2X_DEF_SB_IDX;
4186         }
4187
4188         mb();
4189
4190         return rc;
4191 }
4192
4193 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4194                                                           uint32_t cid)
4195 {
4196         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4197 }
4198
4199 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4200 {
4201         struct ecore_mcast_ramrod_params rparam;
4202         int rc;
4203
4204         memset(&rparam, 0, sizeof(rparam));
4205
4206         rparam.mcast_obj = &sc->mcast_obj;
4207
4208         /* clear pending state for the last command */
4209         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4210
4211         /* if there are pending mcast commands - send them */
4212         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4213                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4214                 if (rc < 0) {
4215                         PMD_DRV_LOG(INFO,
4216                                     "Failed to send pending mcast commands (%d)",
4217                                     rc);
4218                 }
4219         }
4220 }
4221
4222 static void
4223 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4224 {
4225         unsigned long ramrod_flags = 0;
4226         int rc = 0;
4227         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4228         struct ecore_vlan_mac_obj *vlan_mac_obj;
4229
4230         /* always push next commands out, don't wait here */
4231         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4232
4233         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4234         case ECORE_FILTER_MAC_PENDING:
4235                 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4236                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4237                 break;
4238
4239         case ECORE_FILTER_MCAST_PENDING:
4240                 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4241                 bnx2x_handle_mcast_eqe(sc);
4242                 return;
4243
4244         default:
4245                 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4246                             elem->message.data.eth_event.echo);
4247                 return;
4248         }
4249
4250         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4251
4252         if (rc < 0) {
4253                 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4254         } else if (rc > 0) {
4255                 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4256         }
4257 }
4258
4259 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4260 {
4261         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4262
4263         /* send rx_mode command again if was requested */
4264         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4265                 bnx2x_set_storm_rx_mode(sc);
4266         }
4267 }
4268
4269 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4270 {
4271         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4272         wmb();                  /* keep prod updates ordered */
4273 }
4274
4275 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4276 {
4277         uint16_t hw_cons, sw_cons, sw_prod;
4278         union event_ring_elem *elem;
4279         uint8_t echo;
4280         uint32_t cid;
4281         uint8_t opcode;
4282         int spqe_cnt = 0;
4283         struct ecore_queue_sp_obj *q_obj;
4284         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4285         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4286
4287         hw_cons = le16toh(*sc->eq_cons_sb);
4288
4289         /*
4290          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4291          * when we get to the next-page we need to adjust so the loop
4292          * condition below will be met. The next element is the size of a
4293          * regular element and hence incrementing by 1
4294          */
4295         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4296                 hw_cons++;
4297         }
4298
4299         /*
4300          * This function may never run in parallel with itself for a
4301          * specific sc and no need for a read memory barrier here.
4302          */
4303         sw_cons = sc->eq_cons;
4304         sw_prod = sc->eq_prod;
4305
4306         for (;
4307              sw_cons != hw_cons;
4308              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4309
4310                 elem = &sc->eq[EQ_DESC(sw_cons)];
4311
4312 /* elem CID originates from FW, actually LE */
4313                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4314                 opcode = elem->message.opcode;
4315
4316 /* handle eq element */
4317                 switch (opcode) {
4318                 case EVENT_RING_OPCODE_STAT_QUERY:
4319                         PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4320                                     sc->stats_comp++);
4321                         /* nothing to do with stats comp */
4322                         goto next_spqe;
4323
4324                 case EVENT_RING_OPCODE_CFC_DEL:
4325                         /* handle according to cid range */
4326                         /* we may want to verify here that the sc state is HALTING */
4327                         PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4328                                     cid);
4329                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4330                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4331                                 break;
4332                         }
4333                         goto next_spqe;
4334
4335                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4336                         PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4337                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4338                                 break;
4339                         }
4340                         goto next_spqe;
4341
4342                 case EVENT_RING_OPCODE_START_TRAFFIC:
4343                         PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4344                         if (f_obj->complete_cmd
4345                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4346                                 break;
4347                         }
4348                         goto next_spqe;
4349
4350                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4351                         echo = elem->message.data.function_update_event.echo;
4352                         if (echo == SWITCH_UPDATE) {
4353                                 PMD_DRV_LOG(DEBUG,
4354                                             "got FUNC_SWITCH_UPDATE ramrod");
4355                                 if (f_obj->complete_cmd(sc, f_obj,
4356                                                         ECORE_F_CMD_SWITCH_UPDATE))
4357                                 {
4358                                         break;
4359                                 }
4360                         } else {
4361                                 PMD_DRV_LOG(DEBUG,
4362                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4363                                 f_obj->complete_cmd(sc, f_obj,
4364                                                     ECORE_F_CMD_AFEX_UPDATE);
4365                         }
4366                         goto next_spqe;
4367
4368                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4369                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4370                         if (q_obj->complete_cmd(sc, q_obj,
4371                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4372                                 break;
4373                         }
4374                         goto next_spqe;
4375
4376                 case EVENT_RING_OPCODE_FUNCTION_START:
4377                         PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4378                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4379                                 break;
4380                         }
4381                         goto next_spqe;
4382
4383                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4384                         PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4385                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4386                                 break;
4387                         }
4388                         goto next_spqe;
4389                 }
4390
4391                 switch (opcode | sc->state) {
4392                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4393                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4394                         cid =
4395                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4396                         PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4397                                     cid);
4398                         rss_raw->clear_pending(rss_raw);
4399                         break;
4400
4401                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4402                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4403                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4404                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4405                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4406                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4407                         PMD_DRV_LOG(DEBUG,
4408                                     "got (un)set mac ramrod");
4409                         bnx2x_handle_classification_eqe(sc, elem);
4410                         break;
4411
4412                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4413                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4414                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4415                         PMD_DRV_LOG(DEBUG,
4416                                     "got mcast ramrod");
4417                         bnx2x_handle_mcast_eqe(sc);
4418                         break;
4419
4420                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4421                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4422                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4423                         PMD_DRV_LOG(DEBUG,
4424                                     "got rx_mode ramrod");
4425                         bnx2x_handle_rx_mode_eqe(sc);
4426                         break;
4427
4428                 default:
4429                         /* unknown event log error and continue */
4430                         PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4431                                     elem->message.opcode, sc->state);
4432                 }
4433
4434 next_spqe:
4435                 spqe_cnt++;
4436         }                       /* for */
4437
4438         mb();
4439         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4440
4441         sc->eq_cons = sw_cons;
4442         sc->eq_prod = sw_prod;
4443
4444         /* make sure that above mem writes were issued towards the memory */
4445         wmb();
4446
4447         /* update producer */
4448         bnx2x_update_eq_prod(sc, sc->eq_prod);
4449 }
4450
4451 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4452 {
4453         uint16_t status;
4454         int rc = 0;
4455
4456         /* what work needs to be performed? */
4457         status = bnx2x_update_dsb_idx(sc);
4458
4459         /* HW attentions */
4460         if (status & BNX2X_DEF_SB_ATT_IDX) {
4461                 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4462                 bnx2x_attn_int(sc);
4463                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4464                 rc = 1;
4465         }
4466
4467         /* SP events: STAT_QUERY and others */
4468         if (status & BNX2X_DEF_SB_IDX) {
4469 /* handle EQ completions */
4470                 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4471                 bnx2x_eq_int(sc);
4472                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4473                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4474                 status &= ~BNX2X_DEF_SB_IDX;
4475         }
4476
4477         /* if status is non zero then something went wrong */
4478         if (unlikely(status)) {
4479                 PMD_DRV_LOG(INFO,
4480                             "Got an unknown SP interrupt! (0x%04x)", status);
4481         }
4482
4483         /* ack status block only if something was actually handled */
4484         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4485                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4486
4487         return rc;
4488 }
4489
4490 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4491 {
4492         struct bnx2x_softc *sc = fp->sc;
4493         uint8_t more_rx = FALSE;
4494
4495         /* update the fastpath index */
4496         bnx2x_update_fp_sb_idx(fp);
4497
4498         if (scan_fp) {
4499                 if (bnx2x_has_rx_work(fp)) {
4500                         more_rx = bnx2x_rxeof(sc, fp);
4501                 }
4502
4503                 if (more_rx) {
4504                         /* still more work to do */
4505                         bnx2x_handle_fp_tq(fp, scan_fp);
4506                         return;
4507                 }
4508         }
4509
4510         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4511                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4512 }
4513
4514 /*
4515  * Legacy interrupt entry point.
4516  *
4517  * Verifies that the controller generated the interrupt and
4518  * then calls a separate routine to handle the various
4519  * interrupt causes: link, RX, and TX.
4520  */
4521 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4522 {
4523         struct bnx2x_fastpath *fp;
4524         uint32_t status, mask;
4525         int i, rc = 0;
4526
4527         /*
4528          * 0 for ustorm, 1 for cstorm
4529          * the bits returned from ack_int() are 0-15
4530          * bit 0 = attention status block
4531          * bit 1 = fast path status block
4532          * a mask of 0x2 or more = tx/rx event
4533          * a mask of 1 = slow path event
4534          */
4535
4536         status = bnx2x_ack_int(sc);
4537
4538         /* the interrupt is not for us */
4539         if (unlikely(status == 0)) {
4540                 return 0;
4541         }
4542
4543         PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4544         //bnx2x_dump_status_block(sc);
4545
4546         FOR_EACH_ETH_QUEUE(sc, i) {
4547                 fp = &sc->fp[i];
4548                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4549                 if (status & mask) {
4550                         bnx2x_handle_fp_tq(fp, scan_fp);
4551                         status &= ~mask;
4552                 }
4553         }
4554
4555         if (unlikely(status & 0x1)) {
4556                 rc = bnx2x_handle_sp_tq(sc);
4557                 status &= ~0x1;
4558         }
4559
4560         if (unlikely(status)) {
4561                 PMD_DRV_LOG(WARNING,
4562                             "Unexpected fastpath status (0x%08x)!", status);
4563         }
4564
4565         return rc;
4566 }
4567
4568 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4569 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4570 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4571 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4572 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4573 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4574 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4575 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4576 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4577
4578 static struct
4579 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4580         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4581         .init_hw_cmn = bnx2x_init_hw_common,
4582         .init_hw_port = bnx2x_init_hw_port,
4583         .init_hw_func = bnx2x_init_hw_func,
4584
4585         .reset_hw_cmn = bnx2x_reset_common,
4586         .reset_hw_port = bnx2x_reset_port,
4587         .reset_hw_func = bnx2x_reset_func,
4588
4589         .init_fw = bnx2x_init_firmware,
4590         .release_fw = bnx2x_release_firmware,
4591 };
4592
4593 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4594 {
4595         sc->dmae_ready = 0;
4596
4597         PMD_INIT_FUNC_TRACE();
4598
4599         ecore_init_func_obj(sc,
4600                             &sc->func_obj,
4601                             BNX2X_SP(sc, func_rdata),
4602                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4603                             BNX2X_SP(sc, func_afex_rdata),
4604                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4605                             &bnx2x_func_sp_drv);
4606 }
4607
4608 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4609 {
4610         struct ecore_func_state_params func_params = { NULL };
4611         int rc;
4612
4613         PMD_INIT_FUNC_TRACE();
4614
4615         /* prepare the parameters for function state transitions */
4616         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4617
4618         func_params.f_obj = &sc->func_obj;
4619         func_params.cmd = ECORE_F_CMD_HW_INIT;
4620
4621         func_params.params.hw_init.load_phase = load_code;
4622
4623         /*
4624          * Via a plethora of function pointers, we will eventually reach
4625          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4626          */
4627         rc = ecore_func_state_change(sc, &func_params);
4628
4629         return rc;
4630 }
4631
4632 static void
4633 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4634 {
4635         uint32_t i;
4636
4637         if (!(len % 4) && !(addr % 4)) {
4638                 for (i = 0; i < len; i += 4) {
4639                         REG_WR(sc, (addr + i), fill);
4640                 }
4641         } else {
4642                 for (i = 0; i < len; i++) {
4643                         REG_WR8(sc, (addr + i), fill);
4644                 }
4645         }
4646 }
4647
4648 /* writes FP SP data to FW - data_size in dwords */
4649 static void
4650 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4651                   uint32_t data_size)
4652 {
4653         uint32_t index;
4654
4655         for (index = 0; index < data_size; index++) {
4656                 REG_WR(sc,
4657                        (BAR_CSTRORM_INTMEM +
4658                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4659                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4660         }
4661 }
4662
4663 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4664 {
4665         struct hc_status_block_data_e2 sb_data_e2;
4666         struct hc_status_block_data_e1x sb_data_e1x;
4667         uint32_t *sb_data_p;
4668         uint32_t data_size = 0;
4669
4670         if (!CHIP_IS_E1x(sc)) {
4671                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4672                 sb_data_e2.common.state = SB_DISABLED;
4673                 sb_data_e2.common.p_func.vf_valid = FALSE;
4674                 sb_data_p = (uint32_t *) & sb_data_e2;
4675                 data_size = (sizeof(struct hc_status_block_data_e2) /
4676                              sizeof(uint32_t));
4677         } else {
4678                 memset(&sb_data_e1x, 0,
4679                        sizeof(struct hc_status_block_data_e1x));
4680                 sb_data_e1x.common.state = SB_DISABLED;
4681                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4682                 sb_data_p = (uint32_t *) & sb_data_e1x;
4683                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4684                              sizeof(uint32_t));
4685         }
4686
4687         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4688
4689         bnx2x_fill(sc,
4690                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4691                  CSTORM_STATUS_BLOCK_SIZE);
4692         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4693                  0, CSTORM_SYNC_BLOCK_SIZE);
4694 }
4695
4696 static void
4697 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4698                   struct hc_sp_status_block_data *sp_sb_data)
4699 {
4700         uint32_t i;
4701
4702         for (i = 0;
4703              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4704              i++) {
4705                 REG_WR(sc,
4706                        (BAR_CSTRORM_INTMEM +
4707                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4708                         (i * sizeof(uint32_t))),
4709                        *((uint32_t *) sp_sb_data + i));
4710         }
4711 }
4712
4713 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4714 {
4715         struct hc_sp_status_block_data sp_sb_data;
4716
4717         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4718
4719         sp_sb_data.state = SB_DISABLED;
4720         sp_sb_data.p_func.vf_valid = FALSE;
4721
4722         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4723
4724         bnx2x_fill(sc,
4725                  (BAR_CSTRORM_INTMEM +
4726                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4727                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4728         bnx2x_fill(sc,
4729                  (BAR_CSTRORM_INTMEM +
4730                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4731                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4732 }
4733
4734 static void
4735 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4736                              int igu_seg_id)
4737 {
4738         hc_sm->igu_sb_id = igu_sb_id;
4739         hc_sm->igu_seg_id = igu_seg_id;
4740         hc_sm->timer_value = 0xFF;
4741         hc_sm->time_to_expire = 0xFFFFFFFF;
4742 }
4743
4744 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4745 {
4746         /* zero out state machine indices */
4747
4748         /* rx indices */
4749         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4750
4751         /* tx indices */
4752         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4753         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4754         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4755         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4756
4757         /* map indices */
4758
4759         /* rx indices */
4760         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4761             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4762
4763         /* tx indices */
4764         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4765             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4766         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4767             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4768         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4769             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4770         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4771             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4772 }
4773
4774 static void
4775 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4776             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4777 {
4778         struct hc_status_block_data_e2 sb_data_e2;
4779         struct hc_status_block_data_e1x sb_data_e1x;
4780         struct hc_status_block_sm *hc_sm_p;
4781         uint32_t *sb_data_p;
4782         int igu_seg_id;
4783         int data_size;
4784
4785         if (CHIP_INT_MODE_IS_BC(sc)) {
4786                 igu_seg_id = HC_SEG_ACCESS_NORM;
4787         } else {
4788                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4789         }
4790
4791         bnx2x_zero_fp_sb(sc, fw_sb_id);
4792
4793         if (!CHIP_IS_E1x(sc)) {
4794                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4795                 sb_data_e2.common.state = SB_ENABLED;
4796                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4797                 sb_data_e2.common.p_func.vf_id = vfid;
4798                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4799                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4800                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4801                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4802                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4803                 hc_sm_p = sb_data_e2.common.state_machine;
4804                 sb_data_p = (uint32_t *) & sb_data_e2;
4805                 data_size = (sizeof(struct hc_status_block_data_e2) /
4806                              sizeof(uint32_t));
4807                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4808         } else {
4809                 memset(&sb_data_e1x, 0,
4810                        sizeof(struct hc_status_block_data_e1x));
4811                 sb_data_e1x.common.state = SB_ENABLED;
4812                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4813                 sb_data_e1x.common.p_func.vf_id = 0xff;
4814                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4815                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4816                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4817                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4818                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4819                 hc_sm_p = sb_data_e1x.common.state_machine;
4820                 sb_data_p = (uint32_t *) & sb_data_e1x;
4821                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4822                              sizeof(uint32_t));
4823                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4824         }
4825
4826         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4827         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4828
4829         /* write indices to HW - PCI guarantees endianity of regpairs */
4830         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4831 }
4832
4833 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4834 {
4835         if (CHIP_IS_E1x(fp->sc)) {
4836                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4837         } else {
4838                 return fp->cl_id;
4839         }
4840 }
4841
4842 static uint32_t
4843 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4844 {
4845         uint32_t offset = BAR_USTRORM_INTMEM;
4846
4847         if (IS_VF(sc)) {
4848                 return PXP_VF_ADDR_USDM_QUEUES_START +
4849                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4850                          sizeof(struct ustorm_queue_zone_data));
4851         } else if (!CHIP_IS_E1x(sc)) {
4852                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4853         } else {
4854                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4855         }
4856
4857         return offset;
4858 }
4859
4860 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4861 {
4862         struct bnx2x_fastpath *fp = &sc->fp[idx];
4863         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4864         unsigned long q_type = 0;
4865         int cos;
4866
4867         fp->sc = sc;
4868         fp->index = idx;
4869
4870         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4871         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4872
4873         if (CHIP_IS_E1x(sc))
4874                 fp->cl_id = SC_L_ID(sc) + idx;
4875         else
4876 /* want client ID same as IGU SB ID for non-E1 */
4877                 fp->cl_id = fp->igu_sb_id;
4878         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4879
4880         /* setup sb indices */
4881         if (!CHIP_IS_E1x(sc)) {
4882                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4883                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4884         } else {
4885                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4886                 fp->sb_running_index =
4887                     fp->status_block.e1x_sb->sb.running_index;
4888         }
4889
4890         /* init shortcut */
4891         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4892
4893         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4894
4895         for (cos = 0; cos < sc->max_cos; cos++) {
4896                 cids[cos] = idx;
4897         }
4898         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4899
4900         /* nothing more for a VF to do */
4901         if (IS_VF(sc)) {
4902                 return;
4903         }
4904
4905         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4906                     fp->fw_sb_id, fp->igu_sb_id);
4907
4908         bnx2x_update_fp_sb_idx(fp);
4909
4910         /* Configure Queue State object */
4911         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4912         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4913
4914         ecore_init_queue_obj(sc,
4915                              &sc->sp_objs[idx].q_obj,
4916                              fp->cl_id,
4917                              cids,
4918                              sc->max_cos,
4919                              SC_FUNC(sc),
4920                              BNX2X_SP(sc, q_rdata),
4921                              (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4922                              q_type);
4923
4924         /* configure classification DBs */
4925         ecore_init_mac_obj(sc,
4926                            &sc->sp_objs[idx].mac_obj,
4927                            fp->cl_id,
4928                            idx,
4929                            SC_FUNC(sc),
4930                            BNX2X_SP(sc, mac_rdata),
4931                            (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4932                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4933                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4934 }
4935
4936 static void
4937 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4938                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4939 {
4940         union ustorm_eth_rx_producers rx_prods;
4941         uint32_t i;
4942
4943         /* update producers */
4944         rx_prods.prod.bd_prod = rx_bd_prod;
4945         rx_prods.prod.cqe_prod = rx_cq_prod;
4946         rx_prods.prod.reserved = 0;
4947
4948         /*
4949          * Make sure that the BD and SGE data is updated before updating the
4950          * producers since FW might read the BD/SGE right after the producer
4951          * is updated.
4952          * This is only applicable for weak-ordered memory model archs such
4953          * as IA-64. The following barrier is also mandatory since FW will
4954          * assumes BDs must have buffers.
4955          */
4956         wmb();
4957
4958         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4959                 REG_WR(sc,
4960                        (fp->ustorm_rx_prods_offset + (i * 4)),
4961                        rx_prods.raw_data[i]);
4962         }
4963
4964         wmb();                  /* keep prod updates ordered */
4965 }
4966
4967 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4968 {
4969         struct bnx2x_fastpath *fp;
4970         int i;
4971         struct bnx2x_rx_queue *rxq;
4972
4973         for (i = 0; i < sc->num_queues; i++) {
4974                 fp = &sc->fp[i];
4975                 rxq = sc->rx_queues[fp->index];
4976                 if (!rxq) {
4977                         PMD_RX_LOG(ERR, "RX queue is NULL");
4978                         return;
4979                 }
4980
4981                 rxq->rx_bd_head = 0;
4982                 rxq->rx_bd_tail = rxq->nb_rx_desc;
4983                 rxq->rx_cq_head = 0;
4984                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4985                 *fp->rx_cq_cons_sb = 0;
4986
4987                 /*
4988                  * Activate the BD ring...
4989                  * Warning, this will generate an interrupt (to the TSTORM)
4990                  * so this can only be done after the chip is initialized
4991                  */
4992                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4993
4994                 if (i != 0) {
4995                         continue;
4996                 }
4997         }
4998 }
4999
5000 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5001 {
5002         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5003
5004         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5005         fp->tx_db.data.zero_fill1 = 0;
5006         fp->tx_db.data.prod = 0;
5007
5008         if (!txq) {
5009                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5010                 return;
5011         }
5012
5013         txq->tx_pkt_tail = 0;
5014         txq->tx_pkt_head = 0;
5015         txq->tx_bd_tail = 0;
5016         txq->tx_bd_head = 0;
5017 }
5018
5019 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5020 {
5021         int i;
5022
5023         for (i = 0; i < sc->num_queues; i++) {
5024                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5025         }
5026 }
5027
5028 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5029 {
5030         struct host_sp_status_block *def_sb = sc->def_sb;
5031         phys_addr_t mapping = sc->def_sb_dma.paddr;
5032         int igu_sp_sb_index;
5033         int igu_seg_id;
5034         int port = SC_PORT(sc);
5035         int func = SC_FUNC(sc);
5036         int reg_offset, reg_offset_en5;
5037         uint64_t section;
5038         int index, sindex;
5039         struct hc_sp_status_block_data sp_sb_data;
5040
5041         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5042
5043         if (CHIP_INT_MODE_IS_BC(sc)) {
5044                 igu_sp_sb_index = DEF_SB_IGU_ID;
5045                 igu_seg_id = HC_SEG_ACCESS_DEF;
5046         } else {
5047                 igu_sp_sb_index = sc->igu_dsb_id;
5048                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5049         }
5050
5051         /* attentions */
5052         section = ((uint64_t) mapping +
5053                    offsetof(struct host_sp_status_block, atten_status_block));
5054         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5055         sc->attn_state = 0;
5056
5057         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5058             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5059
5060         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5061             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5062
5063         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5064 /* take care of sig[0]..sig[4] */
5065                 for (sindex = 0; sindex < 4; sindex++) {
5066                         sc->attn_group[index].sig[sindex] =
5067                             REG_RD(sc,
5068                                    (reg_offset + (sindex * 0x4) +
5069                                     (0x10 * index)));
5070                 }
5071
5072                 if (!CHIP_IS_E1x(sc)) {
5073                         /*
5074                          * enable5 is separate from the rest of the registers,
5075                          * and the address skip is 4 and not 16 between the
5076                          * different groups
5077                          */
5078                         sc->attn_group[index].sig[4] =
5079                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5080                 } else {
5081                         sc->attn_group[index].sig[4] = 0;
5082                 }
5083         }
5084
5085         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5086                 reg_offset =
5087                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5088                 REG_WR(sc, reg_offset, U64_LO(section));
5089                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5090         } else if (!CHIP_IS_E1x(sc)) {
5091                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5092                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5093         }
5094
5095         section = ((uint64_t) mapping +
5096                    offsetof(struct host_sp_status_block, sp_sb));
5097
5098         bnx2x_zero_sp_sb(sc);
5099
5100         /* PCI guarantees endianity of regpair */
5101         sp_sb_data.state = SB_ENABLED;
5102         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5103         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5104         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5105         sp_sb_data.igu_seg_id = igu_seg_id;
5106         sp_sb_data.p_func.pf_id = func;
5107         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5108         sp_sb_data.p_func.vf_id = 0xff;
5109
5110         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5111
5112         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5113 }
5114
5115 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5116 {
5117         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5118         sc->spq_prod_idx = 0;
5119         sc->dsb_sp_prod =
5120             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5121         sc->spq_prod_bd = sc->spq;
5122         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5123 }
5124
5125 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5126 {
5127         union event_ring_elem *elem;
5128         int i;
5129
5130         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5131                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5132
5133                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5134                                                          BNX2X_PAGE_SIZE *
5135                                                          (i % NUM_EQ_PAGES)));
5136                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5137                                                          BNX2X_PAGE_SIZE *
5138                                                          (i % NUM_EQ_PAGES)));
5139         }
5140
5141         sc->eq_cons = 0;
5142         sc->eq_prod = NUM_EQ_DESC;
5143         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5144
5145         atomic_store_rel_long(&sc->eq_spq_left,
5146                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5147                                    NUM_EQ_DESC) - 1));
5148 }
5149
5150 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5151 {
5152         int i;
5153
5154         if (IS_MF_SI(sc)) {
5155 /*
5156  * In switch independent mode, the TSTORM needs to accept
5157  * packets that failed classification, since approximate match
5158  * mac addresses aren't written to NIG LLH.
5159  */
5160                 REG_WR8(sc,
5161                         (BAR_TSTRORM_INTMEM +
5162                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5163         } else
5164                 REG_WR8(sc,
5165                         (BAR_TSTRORM_INTMEM +
5166                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5167
5168         /*
5169          * Zero this manually as its initialization is currently missing
5170          * in the initTool.
5171          */
5172         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5173                 REG_WR(sc,
5174                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5175                        0);
5176         }
5177
5178         if (!CHIP_IS_E1x(sc)) {
5179                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5180                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5181                         HC_IGU_NBC_MODE);
5182         }
5183 }
5184
5185 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5186 {
5187         switch (load_code) {
5188         case FW_MSG_CODE_DRV_LOAD_COMMON:
5189         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5190                 bnx2x_init_internal_common(sc);
5191                 /* no break */
5192
5193         case FW_MSG_CODE_DRV_LOAD_PORT:
5194                 /* nothing to do */
5195                 /* no break */
5196
5197         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5198                 /* internal memory per function is initialized inside bnx2x_pf_init */
5199                 break;
5200
5201         default:
5202                 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5203                             load_code);
5204                 break;
5205         }
5206 }
5207
5208 static void
5209 storm_memset_func_cfg(struct bnx2x_softc *sc,
5210                       struct tstorm_eth_function_common_config *tcfg,
5211                       uint16_t abs_fid)
5212 {
5213         uint32_t addr;
5214         size_t size;
5215
5216         addr = (BAR_TSTRORM_INTMEM +
5217                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5218         size = sizeof(struct tstorm_eth_function_common_config);
5219         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5220 }
5221
5222 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5223 {
5224         struct tstorm_eth_function_common_config tcfg = { 0 };
5225
5226         if (CHIP_IS_E1x(sc)) {
5227                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5228         }
5229
5230         /* Enable the function in the FW */
5231         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5232         storm_memset_func_en(sc, p->func_id, 1);
5233
5234         /* spq */
5235         if (p->func_flgs & FUNC_FLG_SPQ) {
5236                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5237                 REG_WR(sc,
5238                        (XSEM_REG_FAST_MEMORY +
5239                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5240         }
5241 }
5242
5243 /*
5244  * Calculates the sum of vn_min_rates.
5245  * It's needed for further normalizing of the min_rates.
5246  * Returns:
5247  *   sum of vn_min_rates.
5248  *     or
5249  *   0 - if all the min_rates are 0.
5250  * In the later case fainess algorithm should be deactivated.
5251  * If all min rates are not zero then those that are zeroes will be set to 1.
5252  */
5253 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5254 {
5255         uint32_t vn_cfg;
5256         uint32_t vn_min_rate;
5257         int all_zero = 1;
5258         int vn;
5259
5260         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5261                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5262                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5263                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5264
5265                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5266                         /* skip hidden VNs */
5267                         vn_min_rate = 0;
5268                 } else if (!vn_min_rate) {
5269                         /* If min rate is zero - set it to 100 */
5270                         vn_min_rate = DEF_MIN_RATE;
5271                 } else {
5272                         all_zero = 0;
5273                 }
5274
5275                 input->vnic_min_rate[vn] = vn_min_rate;
5276         }
5277
5278         /* if ETS or all min rates are zeros - disable fairness */
5279         if (all_zero) {
5280                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5281         } else {
5282                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5283         }
5284 }
5285
5286 static uint16_t
5287 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5288 {
5289         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5290                             FUNC_MF_CFG_MAX_BW_SHIFT);
5291
5292         if (!max_cfg) {
5293                 PMD_DRV_LOG(DEBUG,
5294                             "Max BW configured to 0 - using 100 instead");
5295                 max_cfg = 100;
5296         }
5297
5298         return max_cfg;
5299 }
5300
5301 static void
5302 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5303 {
5304         uint16_t vn_max_rate;
5305         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5306         uint32_t max_cfg;
5307
5308         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5309                 vn_max_rate = 0;
5310         } else {
5311                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5312
5313                 if (IS_MF_SI(sc)) {
5314                         /* max_cfg in percents of linkspeed */
5315                         vn_max_rate =
5316                             ((sc->link_vars.line_speed * max_cfg) / 100);
5317                 } else {        /* SD modes */
5318                         /* max_cfg is absolute in 100Mb units */
5319                         vn_max_rate = (max_cfg * 100);
5320                 }
5321         }
5322
5323         input->vnic_max_rate[vn] = vn_max_rate;
5324 }
5325
5326 static void
5327 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5328 {
5329         struct cmng_init_input input;
5330         int vn;
5331
5332         memset(&input, 0, sizeof(struct cmng_init_input));
5333
5334         input.port_rate = sc->link_vars.line_speed;
5335
5336         if (cmng_type == CMNG_FNS_MINMAX) {
5337 /* read mf conf from shmem */
5338                 if (read_cfg) {
5339                         bnx2x_read_mf_cfg(sc);
5340                 }
5341
5342 /* get VN min rate and enable fairness if not 0 */
5343                 bnx2x_calc_vn_min(sc, &input);
5344
5345 /* get VN max rate */
5346                 if (sc->port.pmf) {
5347                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5348                                 bnx2x_calc_vn_max(sc, vn, &input);
5349                         }
5350                 }
5351
5352 /* always enable rate shaping and fairness */
5353                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5354
5355                 ecore_init_cmng(&input, &sc->cmng);
5356                 return;
5357         }
5358 }
5359
5360 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5361 {
5362         if (CHIP_REV_IS_SLOW(sc)) {
5363                 return CMNG_FNS_NONE;
5364         }
5365
5366         if (IS_MF(sc)) {
5367                 return CMNG_FNS_MINMAX;
5368         }
5369
5370         return CMNG_FNS_NONE;
5371 }
5372
5373 static void
5374 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5375 {
5376         int vn;
5377         int func;
5378         uint32_t addr;
5379         size_t size;
5380
5381         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5382         size = sizeof(struct cmng_struct_per_port);
5383         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5384
5385         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5386                 func = func_by_vn(sc, vn);
5387
5388                 addr = (BAR_XSTRORM_INTMEM +
5389                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5390                 size = sizeof(struct rate_shaping_vars_per_vn);
5391                 ecore_storm_memset_struct(sc, addr, size,
5392                                           (uint32_t *) & cmng->
5393                                           vnic.vnic_max_rate[vn]);
5394
5395                 addr = (BAR_XSTRORM_INTMEM +
5396                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5397                 size = sizeof(struct fairness_vars_per_vn);
5398                 ecore_storm_memset_struct(sc, addr, size,
5399                                           (uint32_t *) & cmng->
5400                                           vnic.vnic_min_rate[vn]);
5401         }
5402 }
5403
5404 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5405 {
5406         struct bnx2x_func_init_params func_init;
5407         struct event_ring_data eq_data;
5408         uint16_t flags;
5409
5410         memset(&eq_data, 0, sizeof(struct event_ring_data));
5411         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5412
5413         if (!CHIP_IS_E1x(sc)) {
5414 /* reset IGU PF statistics: MSIX + ATTN */
5415 /* PF */
5416                 REG_WR(sc,
5417                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5418                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5419                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5420                          4)), 0);
5421 /* ATTN */
5422                 REG_WR(sc,
5423                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5424                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5425                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5426                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5427                          4)), 0);
5428         }
5429
5430         /* function setup flags */
5431         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5432
5433         func_init.func_flgs = flags;
5434         func_init.pf_id = SC_FUNC(sc);
5435         func_init.func_id = SC_FUNC(sc);
5436         func_init.spq_map = sc->spq_dma.paddr;
5437         func_init.spq_prod = sc->spq_prod_idx;
5438
5439         bnx2x_func_init(sc, &func_init);
5440
5441         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5442
5443         /*
5444          * Congestion management values depend on the link rate.
5445          * There is no active link so initial link rate is set to 10Gbps.
5446          * When the link comes up the congestion management values are
5447          * re-calculated according to the actual link rate.
5448          */
5449         sc->link_vars.line_speed = SPEED_10000;
5450         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5451
5452         /* Only the PMF sets the HW */
5453         if (sc->port.pmf) {
5454                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5455         }
5456
5457         /* init Event Queue - PCI bus guarantees correct endainity */
5458         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5459         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5460         eq_data.producer = sc->eq_prod;
5461         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5462         eq_data.sb_id = DEF_SB_ID;
5463         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5464 }
5465
5466 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5467 {
5468         int port = SC_PORT(sc);
5469         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5470         uint32_t val = REG_RD(sc, addr);
5471         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5472             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5473         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5474         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5475
5476         if (msix) {
5477                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5478                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5479                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5480                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5481                 if (single_msix) {
5482                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5483                 }
5484         } else if (msi) {
5485                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5486                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5487                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5488                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5489         } else {
5490                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5491                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5492                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5493                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5494
5495                 REG_WR(sc, addr, val);
5496
5497                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5498         }
5499
5500         REG_WR(sc, addr, val);
5501
5502         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5503         mb();
5504
5505         /* init leading/trailing edge */
5506         if (IS_MF(sc)) {
5507                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5508                 if (sc->port.pmf) {
5509                         /* enable nig and gpio3 attention */
5510                         val |= 0x1100;
5511                 }
5512         } else {
5513                 val = 0xffff;
5514         }
5515
5516         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5517         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5518
5519         /* make sure that interrupts are indeed enabled from here on */
5520         mb();
5521 }
5522
5523 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5524 {
5525         uint32_t val;
5526         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5527             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5528         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5529         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5530
5531         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5532
5533         if (msix) {
5534                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5535                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5536                 if (single_msix) {
5537                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5538                 }
5539         } else if (msi) {
5540                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5541                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5542                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5543         } else {
5544                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5545                 val |= (IGU_PF_CONF_INT_LINE_EN |
5546                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5547         }
5548
5549         /* clean previous status - need to configure igu prior to ack */
5550         if ((!msix) || single_msix) {
5551                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5552                 bnx2x_ack_int(sc);
5553         }
5554
5555         val |= IGU_PF_CONF_FUNC_EN;
5556
5557         PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5558                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5559
5560         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5561
5562         mb();
5563
5564         /* init leading/trailing edge */
5565         if (IS_MF(sc)) {
5566                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5567                 if (sc->port.pmf) {
5568                         /* enable nig and gpio3 attention */
5569                         val |= 0x1100;
5570                 }
5571         } else {
5572                 val = 0xffff;
5573         }
5574
5575         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5576         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5577
5578         /* make sure that interrupts are indeed enabled from here on */
5579         mb();
5580 }
5581
5582 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5583 {
5584         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5585                 bnx2x_hc_int_enable(sc);
5586         } else {
5587                 bnx2x_igu_int_enable(sc);
5588         }
5589 }
5590
5591 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5592 {
5593         int port = SC_PORT(sc);
5594         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5595         uint32_t val = REG_RD(sc, addr);
5596
5597         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5598                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5599                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5600         /* flush all outstanding writes */
5601         mb();
5602
5603         REG_WR(sc, addr, val);
5604         if (REG_RD(sc, addr) != val) {
5605                 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5606         }
5607 }
5608
5609 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5610 {
5611         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5612
5613         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5614                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5615
5616         PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5617
5618         /* flush all outstanding writes */
5619         mb();
5620
5621         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5622         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5623                 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5624         }
5625 }
5626
5627 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5628 {
5629         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5630                 bnx2x_hc_int_disable(sc);
5631         } else {
5632                 bnx2x_igu_int_disable(sc);
5633         }
5634 }
5635
5636 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5637 {
5638         int i;
5639
5640         PMD_INIT_FUNC_TRACE();
5641
5642         for (i = 0; i < sc->num_queues; i++) {
5643                 bnx2x_init_eth_fp(sc, i);
5644         }
5645
5646         rmb();                  /* ensure status block indices were read */
5647
5648         bnx2x_init_rx_rings(sc);
5649         bnx2x_init_tx_rings(sc);
5650
5651         if (IS_VF(sc)) {
5652                 bnx2x_memset_stats(sc);
5653                 return;
5654         }
5655
5656         /* initialize MOD_ABS interrupts */
5657         elink_init_mod_abs_int(sc, &sc->link_vars,
5658                                sc->devinfo.chip_id,
5659                                sc->devinfo.shmem_base,
5660                                sc->devinfo.shmem2_base, SC_PORT(sc));
5661
5662         bnx2x_init_def_sb(sc);
5663         bnx2x_update_dsb_idx(sc);
5664         bnx2x_init_sp_ring(sc);
5665         bnx2x_init_eq_ring(sc);
5666         bnx2x_init_internal(sc, load_code);
5667         bnx2x_pf_init(sc);
5668         bnx2x_stats_init(sc);
5669
5670         /* flush all before enabling interrupts */
5671         mb();
5672
5673         bnx2x_int_enable(sc);
5674
5675         /* check for SPIO5 */
5676         bnx2x_attn_int_deasserted0(sc,
5677                                  REG_RD(sc,
5678                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5679                                          SC_PORT(sc) * 4)) &
5680                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5681 }
5682
5683 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5684 {
5685         /* mcast rules must be added to tx if tx switching is enabled */
5686         ecore_obj_type o_type;
5687         if (sc->flags & BNX2X_TX_SWITCHING)
5688                 o_type = ECORE_OBJ_TYPE_RX_TX;
5689         else
5690                 o_type = ECORE_OBJ_TYPE_RX;
5691
5692         /* RX_MODE controlling object */
5693         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5694
5695         /* multicast configuration controlling object */
5696         ecore_init_mcast_obj(sc,
5697                              &sc->mcast_obj,
5698                              sc->fp[0].cl_id,
5699                              sc->fp[0].index,
5700                              SC_FUNC(sc),
5701                              SC_FUNC(sc),
5702                              BNX2X_SP(sc, mcast_rdata),
5703                              (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5704                              ECORE_FILTER_MCAST_PENDING,
5705                              &sc->sp_state, o_type);
5706
5707         /* Setup CAM credit pools */
5708         ecore_init_mac_credit_pool(sc,
5709                                    &sc->macs_pool,
5710                                    SC_FUNC(sc),
5711                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5712                                    VNICS_PER_PATH(sc));
5713
5714         ecore_init_vlan_credit_pool(sc,
5715                                     &sc->vlans_pool,
5716                                     SC_ABS_FUNC(sc) >> 1,
5717                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5718                                     VNICS_PER_PATH(sc));
5719
5720         /* RSS configuration object */
5721         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5722                                   sc->fp[0].cl_id,
5723                                   sc->fp[0].index,
5724                                   SC_FUNC(sc),
5725                                   SC_FUNC(sc),
5726                                   BNX2X_SP(sc, rss_rdata),
5727                                   (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5728                                   ECORE_FILTER_RSS_CONF_PENDING,
5729                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5730 }
5731
5732 /*
5733  * Initialize the function. This must be called before sending CLIENT_SETUP
5734  * for the first client.
5735  */
5736 static int bnx2x_func_start(struct bnx2x_softc *sc)
5737 {
5738         struct ecore_func_state_params func_params = { NULL };
5739         struct ecore_func_start_params *start_params =
5740             &func_params.params.start;
5741
5742         /* Prepare parameters for function state transitions */
5743         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5744
5745         func_params.f_obj = &sc->func_obj;
5746         func_params.cmd = ECORE_F_CMD_START;
5747
5748         /* Function parameters */
5749         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5750         start_params->sd_vlan_tag = OVLAN(sc);
5751
5752         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5753                 start_params->network_cos_mode = STATIC_COS;
5754         } else {                /* CHIP_IS_E1X */
5755                 start_params->network_cos_mode = FW_WRR;
5756         }
5757
5758         start_params->gre_tunnel_mode = 0;
5759         start_params->gre_tunnel_rss = 0;
5760
5761         return ecore_func_state_change(sc, &func_params);
5762 }
5763
5764 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5765 {
5766         uint16_t pmcsr;
5767
5768         /* If there is no power capability, silently succeed */
5769         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5770                 PMD_DRV_LOG(WARNING, "No power capability");
5771                 return 0;
5772         }
5773
5774         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5775                  2);
5776
5777         switch (state) {
5778         case PCI_PM_D0:
5779                 pci_write_word(sc,
5780                                (sc->devinfo.pcie_pm_cap_reg +
5781                                 PCIR_POWER_STATUS),
5782                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5783
5784                 if (pmcsr & PCIM_PSTAT_DMASK) {
5785                         /* delay required during transition out of D3hot */
5786                         DELAY(20000);
5787                 }
5788
5789                 break;
5790
5791         case PCI_PM_D3hot:
5792                 /* don't shut down the power for emulation and FPGA */
5793                 if (CHIP_REV_IS_SLOW(sc)) {
5794                         return 0;
5795                 }
5796
5797                 pmcsr &= ~PCIM_PSTAT_DMASK;
5798                 pmcsr |= PCIM_PSTAT_D3;
5799
5800                 if (sc->wol) {
5801                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5802                 }
5803
5804                 pci_write_long(sc,
5805                                (sc->devinfo.pcie_pm_cap_reg +
5806                                 PCIR_POWER_STATUS), pmcsr);
5807
5808                 /*
5809                  * No more memory access after this point until device is brought back
5810                  * to D0 state.
5811                  */
5812                 break;
5813
5814         default:
5815                 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5816                             state);
5817                 return -1;
5818         }
5819
5820         return 0;
5821 }
5822
5823 /* return true if succeeded to acquire the lock */
5824 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5825 {
5826         uint32_t lock_status;
5827         uint32_t resource_bit = (1 << resource);
5828         int func = SC_FUNC(sc);
5829         uint32_t hw_lock_control_reg;
5830
5831         /* Validating that the resource is within range */
5832         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5833                 PMD_DRV_LOG(INFO,
5834                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5835                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5836                 return FALSE;
5837         }
5838
5839         if (func <= 5) {
5840                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5841         } else {
5842                 hw_lock_control_reg =
5843                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5844         }
5845
5846         /* try to acquire the lock */
5847         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5848         lock_status = REG_RD(sc, hw_lock_control_reg);
5849         if (lock_status & resource_bit) {
5850                 return TRUE;
5851         }
5852
5853         PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5854
5855         return FALSE;
5856 }
5857
5858 /*
5859  * Get the recovery leader resource id according to the engine this function
5860  * belongs to. Currently only only 2 engines is supported.
5861  */
5862 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5863 {
5864         if (SC_PATH(sc)) {
5865                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5866         } else {
5867                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5868         }
5869 }
5870
5871 /* try to acquire a leader lock for current engine */
5872 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5873 {
5874         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5875 }
5876
5877 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5878 {
5879         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5880 }
5881
5882 /* close gates #2, #3 and #4 */
5883 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5884 {
5885         uint32_t val;
5886
5887         /* gates #2 and #4a are closed/opened */
5888         /* #4 */
5889         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5890         /* #2 */
5891         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5892
5893         /* #3 */
5894         if (CHIP_IS_E1x(sc)) {
5895 /* prevent interrupts from HC on both ports */
5896                 val = REG_RD(sc, HC_REG_CONFIG_1);
5897                 if (close)
5898                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5899                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5900                 else
5901                         REG_WR(sc, HC_REG_CONFIG_1,
5902                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5903
5904                 val = REG_RD(sc, HC_REG_CONFIG_0);
5905                 if (close)
5906                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5907                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5908                 else
5909                         REG_WR(sc, HC_REG_CONFIG_0,
5910                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5911
5912         } else {
5913 /* Prevent incomming interrupts in IGU */
5914                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5915
5916                 if (close)
5917                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5918                                (val & ~(uint32_t)
5919                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5920                 else
5921                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5922                                (val |
5923                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5924         }
5925
5926         wmb();
5927 }
5928
5929 /* poll for pending writes bit, it should get cleared in no more than 1s */
5930 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5931 {
5932         uint32_t cnt = 1000;
5933         uint32_t pend_bits = 0;
5934
5935         do {
5936                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5937
5938                 if (pend_bits == 0) {
5939                         break;
5940                 }
5941
5942                 DELAY(1000);
5943         } while (cnt-- > 0);
5944
5945         if (cnt <= 0) {
5946                 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5947                             pend_bits);
5948                 return -1;
5949         }
5950
5951         return 0;
5952 }
5953
5954 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5955
5956 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5957 {
5958         /* Do some magic... */
5959         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5960         *magic_val = val & SHARED_MF_CLP_MAGIC;
5961         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5962 }
5963
5964 /* restore the value of the 'magic' bit */
5965 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5966 {
5967         /* Restore the 'magic' bit value... */
5968         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5969         MFCFG_WR(sc, shared_mf_config.clp_mb,
5970                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5971 }
5972
5973 /* prepare for MCP reset, takes care of CLP configurations */
5974 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5975 {
5976         uint32_t shmem;
5977         uint32_t validity_offset;
5978
5979         /* set `magic' bit in order to save MF config */
5980         bnx2x_clp_reset_prep(sc, magic_val);
5981
5982         /* get shmem offset */
5983         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5984         validity_offset =
5985             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5986
5987         /* Clear validity map flags */
5988         if (shmem > 0) {
5989                 REG_WR(sc, shmem + validity_offset, 0);
5990         }
5991 }
5992
5993 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
5994 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
5995
5996 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5997 {
5998         /* special handling for emulation and FPGA (10 times longer) */
5999         if (CHIP_REV_IS_SLOW(sc)) {
6000                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6001         } else {
6002                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6003         }
6004 }
6005
6006 /* initialize shmem_base and waits for validity signature to appear */
6007 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6008 {
6009         int cnt = 0;
6010         uint32_t val = 0;
6011
6012         do {
6013                 sc->devinfo.shmem_base =
6014                     sc->link_params.shmem_base =
6015                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6016
6017                 if (sc->devinfo.shmem_base) {
6018                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6019                         if (val & SHR_MEM_VALIDITY_MB)
6020                                 return 0;
6021                 }
6022
6023                 bnx2x_mcp_wait_one(sc);
6024
6025         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6026
6027         PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6028
6029         return -1;
6030 }
6031
6032 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6033 {
6034         int rc = bnx2x_init_shmem(sc);
6035
6036         /* Restore the `magic' bit value */
6037         bnx2x_clp_reset_done(sc, magic_val);
6038
6039         return rc;
6040 }
6041
6042 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6043 {
6044         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6045         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6046         wmb();
6047 }
6048
6049 /*
6050  * Reset the whole chip except for:
6051  *      - PCIE core
6052  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6053  *      - IGU
6054  *      - MISC (including AEU)
6055  *      - GRC
6056  *      - RBCN, RBCP
6057  */
6058 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6059 {
6060         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6061         uint32_t global_bits2, stay_reset2;
6062
6063         /*
6064          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6065          * (per chip) blocks.
6066          */
6067         global_bits2 =
6068             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6069             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6070
6071         /*
6072          * Don't reset the following blocks.
6073          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6074          *            reset, as in 4 port device they might still be owned
6075          *            by the MCP (there is only one leader per path).
6076          */
6077         not_reset_mask1 =
6078             MISC_REGISTERS_RESET_REG_1_RST_HC |
6079             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6080             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6081
6082         not_reset_mask2 =
6083             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6084             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6085             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6086             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6087             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6088             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6089             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6090             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6091             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6092             MISC_REGISTERS_RESET_REG_2_PGLC |
6093             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6094             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6095             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6096             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6097             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6098
6099         /*
6100          * Keep the following blocks in reset:
6101          *  - all xxMACs are handled by the elink code.
6102          */
6103         stay_reset2 =
6104             MISC_REGISTERS_RESET_REG_2_XMAC |
6105             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6106
6107         /* Full reset masks according to the chip */
6108         reset_mask1 = 0xffffffff;
6109
6110         if (CHIP_IS_E1H(sc))
6111                 reset_mask2 = 0x1ffff;
6112         else if (CHIP_IS_E2(sc))
6113                 reset_mask2 = 0xfffff;
6114         else                    /* CHIP_IS_E3 */
6115                 reset_mask2 = 0x3ffffff;
6116
6117         /* Don't reset global blocks unless we need to */
6118         if (!global)
6119                 reset_mask2 &= ~global_bits2;
6120
6121         /*
6122          * In case of attention in the QM, we need to reset PXP
6123          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6124          * because otherwise QM reset would release 'close the gates' shortly
6125          * before resetting the PXP, then the PSWRQ would send a write
6126          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6127          * read the payload data from PSWWR, but PSWWR would not
6128          * respond. The write queue in PGLUE would stuck, dmae commands
6129          * would not return. Therefore it's important to reset the second
6130          * reset register (containing the
6131          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6132          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6133          * bit).
6134          */
6135         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6136                reset_mask2 & (~not_reset_mask2));
6137
6138         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6139                reset_mask1 & (~not_reset_mask1));
6140
6141         mb();
6142         wmb();
6143
6144         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6145                reset_mask2 & (~stay_reset2));
6146
6147         mb();
6148         wmb();
6149
6150         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6151         wmb();
6152 }
6153
6154 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6155 {
6156         int cnt = 1000;
6157         uint32_t val = 0;
6158         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6159         uint32_t tags_63_32 = 0;
6160
6161         /* Empty the Tetris buffer, wait for 1s */
6162         do {
6163                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6164                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6165                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6166                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6167                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6168                 if (CHIP_IS_E3(sc)) {
6169                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6170                 }
6171
6172                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6173                     ((port_is_idle_0 & 0x1) == 0x1) &&
6174                     ((port_is_idle_1 & 0x1) == 0x1) &&
6175                     (pgl_exp_rom2 == 0xffffffff) &&
6176                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6177                         break;
6178                 DELAY(1000);
6179         } while (cnt-- > 0);
6180
6181         if (cnt <= 0) {
6182                 PMD_DRV_LOG(NOTICE,
6183                             "ERROR: Tetris buffer didn't get empty or there "
6184                             "are still outstanding read requests after 1s! "
6185                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6186                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6187                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6188                             pgl_exp_rom2);
6189                 return -1;
6190         }
6191
6192         mb();
6193
6194         /* Close gates #2, #3 and #4 */
6195         bnx2x_set_234_gates(sc, TRUE);
6196
6197         /* Poll for IGU VQs for 57712 and newer chips */
6198         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6199                 return -1;
6200         }
6201
6202         /* clear "unprepared" bit */
6203         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6204         mb();
6205
6206         /* Make sure all is written to the chip before the reset */
6207         wmb();
6208
6209         /*
6210          * Wait for 1ms to empty GLUE and PCI-E core queues,
6211          * PSWHST, GRC and PSWRD Tetris buffer.
6212          */
6213         DELAY(1000);
6214
6215         /* Prepare to chip reset: */
6216         /* MCP */
6217         if (global) {
6218                 bnx2x_reset_mcp_prep(sc, &val);
6219         }
6220
6221         /* PXP */
6222         bnx2x_pxp_prep(sc);
6223         mb();
6224
6225         /* reset the chip */
6226         bnx2x_process_kill_chip_reset(sc, global);
6227         mb();
6228
6229         /* Recover after reset: */
6230         /* MCP */
6231         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6232                 return -1;
6233         }
6234
6235         /* Open the gates #2, #3 and #4 */
6236         bnx2x_set_234_gates(sc, FALSE);
6237
6238         return 0;
6239 }
6240
6241 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6242 {
6243         int rc = 0;
6244         uint8_t global = bnx2x_reset_is_global(sc);
6245         uint32_t load_code;
6246
6247         /*
6248          * If not going to reset MCP, load "fake" driver to reset HW while
6249          * driver is owner of the HW.
6250          */
6251         if (!global && !BNX2X_NOMCP(sc)) {
6252                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6253                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6254                 if (!load_code) {
6255                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6256                         rc = -1;
6257                         goto exit_leader_reset;
6258                 }
6259
6260                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6261                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6262                         PMD_DRV_LOG(NOTICE,
6263                                     "MCP unexpected response, aborting");
6264                         rc = -1;
6265                         goto exit_leader_reset2;
6266                 }
6267
6268                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6269                 if (!load_code) {
6270                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6271                         rc = -1;
6272                         goto exit_leader_reset2;
6273                 }
6274         }
6275
6276         /* try to recover after the failure */
6277         if (bnx2x_process_kill(sc, global)) {
6278                 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6279                             SC_PATH(sc));
6280                 rc = -1;
6281                 goto exit_leader_reset2;
6282         }
6283
6284         /*
6285          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6286          * state.
6287          */
6288         bnx2x_set_reset_done(sc);
6289         if (global) {
6290                 bnx2x_clear_reset_global(sc);
6291         }
6292
6293 exit_leader_reset2:
6294
6295         /* unload "fake driver" if it was loaded */
6296         if (!global &&!BNX2X_NOMCP(sc)) {
6297                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6298                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6299         }
6300
6301 exit_leader_reset:
6302
6303         sc->is_leader = 0;
6304         bnx2x_release_leader_lock(sc);
6305
6306         mb();
6307         return rc;
6308 }
6309
6310 /*
6311  * prepare INIT transition, parameters configured:
6312  *   - HC configuration
6313  *   - Queue's CDU context
6314  */
6315 static void
6316 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6317                    struct ecore_queue_init_params *init_params)
6318 {
6319         uint8_t cos;
6320         int cxt_index, cxt_offset;
6321
6322         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6323         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6324
6325         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6326         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6327
6328         /* HC rate */
6329         init_params->rx.hc_rate =
6330             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6331         init_params->tx.hc_rate =
6332             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6333
6334         /* FW SB ID */
6335         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6336
6337         /* CQ index among the SB indices */
6338         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6339         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6340
6341         /* set maximum number of COSs supported by this queue */
6342         init_params->max_cos = sc->max_cos;
6343
6344         /* set the context pointers queue object */
6345         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6346                 cxt_index = fp->index / ILT_PAGE_CIDS;
6347                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6348                 init_params->cxts[cos] =
6349                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6350         }
6351 }
6352
6353 /* set flags that are common for the Tx-only and not normal connections */
6354 static unsigned long
6355 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6356 {
6357         unsigned long flags = 0;
6358
6359         /* PF driver will always initialize the Queue to an ACTIVE state */
6360         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6361
6362         /*
6363          * tx only connections collect statistics (on the same index as the
6364          * parent connection). The statistics are zeroed when the parent
6365          * connection is initialized.
6366          */
6367
6368         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6369         if (zero_stats) {
6370                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6371         }
6372
6373         /*
6374          * tx only connections can support tx-switching, though their
6375          * CoS-ness doesn't survive the loopback
6376          */
6377         if (sc->flags & BNX2X_TX_SWITCHING) {
6378                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6379         }
6380
6381         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6382
6383         return flags;
6384 }
6385
6386 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6387 {
6388         unsigned long flags = 0;
6389
6390         if (IS_MF_SD(sc)) {
6391                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6392         }
6393
6394         if (leading) {
6395                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6396                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6397         }
6398
6399         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6400
6401         /* merge with common flags */
6402         return flags | bnx2x_get_common_flags(sc, TRUE);
6403 }
6404
6405 static void
6406 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6407                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6408 {
6409         gen_init->stat_id = bnx2x_stats_id(fp);
6410         gen_init->spcl_id = fp->cl_id;
6411         gen_init->mtu = sc->mtu;
6412         gen_init->cos = cos;
6413 }
6414
6415 static void
6416 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6417                  struct rxq_pause_params *pause,
6418                  struct ecore_rxq_setup_params *rxq_init)
6419 {
6420         struct bnx2x_rx_queue *rxq;
6421
6422         rxq = sc->rx_queues[fp->index];
6423         if (!rxq) {
6424                 PMD_RX_LOG(ERR, "RX queue is NULL");
6425                 return;
6426         }
6427         /* pause */
6428         pause->bd_th_lo = BD_TH_LO(sc);
6429         pause->bd_th_hi = BD_TH_HI(sc);
6430
6431         pause->rcq_th_lo = RCQ_TH_LO(sc);
6432         pause->rcq_th_hi = RCQ_TH_HI(sc);
6433
6434         /* validate rings have enough entries to cross high thresholds */
6435         if (sc->dropless_fc &&
6436             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6437                 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6438         }
6439
6440         if (sc->dropless_fc &&
6441             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6442                 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6443         }
6444
6445         pause->pri_map = 1;
6446
6447         /* rxq setup */
6448         rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6449         rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6450         rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6451                                               BNX2X_PAGE_SIZE);
6452
6453         /*
6454          * This should be a maximum number of data bytes that may be
6455          * placed on the BD (not including paddings).
6456          */
6457         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6458
6459         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6460         rxq_init->rss_engine_id = SC_FUNC(sc);
6461         rxq_init->mcast_engine_id = SC_FUNC(sc);
6462
6463         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6464         rxq_init->fw_sb_id = fp->fw_sb_id;
6465
6466         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6467
6468         /*
6469          * configure silent vlan removal
6470          * if multi function mode is afex, then mask default vlan
6471          */
6472         if (IS_MF_AFEX(sc)) {
6473                 rxq_init->silent_removal_value =
6474                     sc->devinfo.mf_info.afex_def_vlan_tag;
6475                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6476         }
6477 }
6478
6479 static void
6480 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6481                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6482 {
6483         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6484
6485         if (!txq) {
6486                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6487                 return;
6488         }
6489         txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6490         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6491         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6492         txq_init->fw_sb_id = fp->fw_sb_id;
6493
6494         /*
6495          * set the TSS leading client id for TX classfication to the
6496          * leading RSS client id
6497          */
6498         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6499 }
6500
6501 /*
6502  * This function performs 2 steps in a queue state machine:
6503  *   1) RESET->INIT
6504  *   2) INIT->SETUP
6505  */
6506 static int
6507 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6508 {
6509         struct ecore_queue_state_params q_params = { NULL };
6510         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6511         int rc;
6512
6513         PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6514
6515         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6516
6517         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6518
6519         /* we want to wait for completion in this context */
6520         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6521
6522         /* prepare the INIT parameters */
6523         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6524
6525         /* Set the command */
6526         q_params.cmd = ECORE_Q_CMD_INIT;
6527
6528         /* Change the state to INIT */
6529         rc = ecore_queue_state_change(sc, &q_params);
6530         if (rc) {
6531                 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6532                 return rc;
6533         }
6534
6535         PMD_DRV_LOG(DEBUG, "init complete");
6536
6537         /* now move the Queue to the SETUP state */
6538         memset(setup_params, 0, sizeof(*setup_params));
6539
6540         /* set Queue flags */
6541         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6542
6543         /* set general SETUP parameters */
6544         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6545                               FIRST_TX_COS_INDEX);
6546
6547         bnx2x_pf_rx_q_prep(sc, fp,
6548                          &setup_params->pause_params,
6549                          &setup_params->rxq_params);
6550
6551         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6552
6553         /* Set the command */
6554         q_params.cmd = ECORE_Q_CMD_SETUP;
6555
6556         /* change the state to SETUP */
6557         rc = ecore_queue_state_change(sc, &q_params);
6558         if (rc) {
6559                 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6560                 return rc;
6561         }
6562
6563         return rc;
6564 }
6565
6566 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6567 {
6568         if (IS_PF(sc))
6569                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6570         else                    /* VF */
6571                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6572 }
6573
6574 static int
6575 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6576                   uint8_t config_hash)
6577 {
6578         struct ecore_config_rss_params params = { NULL };
6579         uint32_t i;
6580
6581         /*
6582          * Although RSS is meaningless when there is a single HW queue we
6583          * still need it enabled in order to have HW Rx hash generated.
6584          */
6585
6586         params.rss_obj = rss_obj;
6587
6588         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6589
6590         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6591
6592         /* RSS configuration */
6593         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6594         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6595         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6596         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6597         if (rss_obj->udp_rss_v4) {
6598                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6599         }
6600         if (rss_obj->udp_rss_v6) {
6601                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6602         }
6603
6604         /* Hash bits */
6605         params.rss_result_mask = MULTI_MASK;
6606
6607         (void)rte_memcpy(params.ind_table, rss_obj->ind_table,
6608                          sizeof(params.ind_table));
6609
6610         if (config_hash) {
6611 /* RSS keys */
6612                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6613                         params.rss_key[i] = (uint32_t) rte_rand();
6614                 }
6615
6616                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6617         }
6618
6619         if (IS_PF(sc))
6620                 return ecore_config_rss(sc, &params);
6621         else
6622                 return bnx2x_vf_config_rss(sc, &params);
6623 }
6624
6625 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6626 {
6627         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6628 }
6629
6630 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6631 {
6632         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6633         uint32_t i;
6634
6635         /*
6636          * Prepare the initial contents of the indirection table if
6637          * RSS is enabled
6638          */
6639         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6640                 sc->rss_conf_obj.ind_table[i] =
6641                     (sc->fp->cl_id + (i % num_eth_queues));
6642         }
6643
6644         if (sc->udp_rss) {
6645                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6646         }
6647
6648         /*
6649          * For 57711 SEARCHER configuration (rss_keys) is
6650          * per-port, so if explicit configuration is needed, do it only
6651          * for a PMF.
6652          *
6653          * For 57712 and newer it's a per-function configuration.
6654          */
6655         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6656 }
6657
6658 static int
6659 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6660                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6661                 unsigned long *ramrod_flags)
6662 {
6663         struct ecore_vlan_mac_ramrod_params ramrod_param;
6664         int rc;
6665
6666         memset(&ramrod_param, 0, sizeof(ramrod_param));
6667
6668         /* fill in general parameters */
6669         ramrod_param.vlan_mac_obj = obj;
6670         ramrod_param.ramrod_flags = *ramrod_flags;
6671
6672         /* fill a user request section if needed */
6673         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6674                 (void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6675                                  ETH_ALEN);
6676
6677                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6678
6679 /* Set the command: ADD or DEL */
6680                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6681                     ECORE_VLAN_MAC_DEL;
6682         }
6683
6684         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6685
6686         if (rc == ECORE_EXISTS) {
6687                 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6688 /* do not treat adding same MAC as error */
6689                 rc = 0;
6690         } else if (rc < 0) {
6691                 PMD_DRV_LOG(ERR,
6692                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6693         }
6694
6695         return rc;
6696 }
6697
6698 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6699 {
6700         unsigned long ramrod_flags = 0;
6701
6702         PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6703
6704         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6705
6706         /* Eth MAC is set on RSS leading client (fp[0]) */
6707         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6708                                &sc->sp_objs->mac_obj,
6709                                set, ECORE_ETH_MAC, &ramrod_flags);
6710 }
6711
6712 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6713 {
6714         uint32_t sel_phy_idx = 0;
6715
6716         if (sc->link_params.num_phys <= 1) {
6717                 return ELINK_INT_PHY;
6718         }
6719
6720         if (sc->link_vars.link_up) {
6721                 sel_phy_idx = ELINK_EXT_PHY1;
6722 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6723                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6724                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6725                      ELINK_SUPPORTED_FIBRE))
6726                         sel_phy_idx = ELINK_EXT_PHY2;
6727         } else {
6728                 switch (elink_phy_selection(&sc->link_params)) {
6729                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6730                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6731                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6732                         sel_phy_idx = ELINK_EXT_PHY1;
6733                         break;
6734                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6735                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6736                         sel_phy_idx = ELINK_EXT_PHY2;
6737                         break;
6738                 }
6739         }
6740
6741         return sel_phy_idx;
6742 }
6743
6744 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6745 {
6746         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6747
6748         /*
6749          * The selected activated PHY is always after swapping (in case PHY
6750          * swapping is enabled). So when swapping is enabled, we need to reverse
6751          * the configuration
6752          */
6753
6754         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6755                 if (sel_phy_idx == ELINK_EXT_PHY1)
6756                         sel_phy_idx = ELINK_EXT_PHY2;
6757                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6758                         sel_phy_idx = ELINK_EXT_PHY1;
6759         }
6760
6761         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6762 }
6763
6764 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6765 {
6766         /*
6767          * Initialize link parameters structure variables
6768          * It is recommended to turn off RX FC for jumbo frames
6769          * for better performance
6770          */
6771         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6772                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6773         } else {
6774                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6775         }
6776 }
6777
6778 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6779 {
6780         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6781         switch (sc->link_vars.ieee_fc &
6782                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6783         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6784         default:
6785                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6786                                                    ADVERTISED_Pause);
6787                 break;
6788
6789         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6790                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6791                                                   ADVERTISED_Pause);
6792                 break;
6793
6794         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6795                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6796                 break;
6797         }
6798 }
6799
6800 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6801 {
6802         uint16_t line_speed = sc->link_vars.line_speed;
6803         if (IS_MF(sc)) {
6804                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6805                                                       sc->devinfo.
6806                                                       mf_info.mf_config[SC_VN
6807                                                                         (sc)]);
6808
6809 /* calculate the current MAX line speed limit for the MF devices */
6810                 if (IS_MF_SI(sc)) {
6811                         line_speed = (line_speed * maxCfg) / 100;
6812                 } else {        /* SD mode */
6813                         uint16_t vn_max_rate = maxCfg * 100;
6814
6815                         if (vn_max_rate < line_speed) {
6816                                 line_speed = vn_max_rate;
6817                         }
6818                 }
6819         }
6820
6821         return line_speed;
6822 }
6823
6824 static void
6825 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6826 {
6827         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6828
6829         memset(data, 0, sizeof(*data));
6830
6831         /* fill the report data with the effective line speed */
6832         data->line_speed = line_speed;
6833
6834         /* Link is down */
6835         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6836                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6837                             &data->link_report_flags);
6838         }
6839
6840         /* Full DUPLEX */
6841         if (sc->link_vars.duplex == DUPLEX_FULL) {
6842                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6843                             &data->link_report_flags);
6844         }
6845
6846         /* Rx Flow Control is ON */
6847         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6848                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6849         }
6850
6851         /* Tx Flow Control is ON */
6852         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6853                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6854         }
6855 }
6856
6857 /* report link status to OS, should be called under phy_lock */
6858 static void bnx2x_link_report(struct bnx2x_softc *sc)
6859 {
6860         struct bnx2x_link_report_data cur_data;
6861
6862         /* reread mf_cfg */
6863         if (IS_PF(sc)) {
6864                 bnx2x_read_mf_cfg(sc);
6865         }
6866
6867         /* Read the current link report info */
6868         bnx2x_fill_report_data(sc, &cur_data);
6869
6870         /* Don't report link down or exactly the same link status twice */
6871         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6872             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6873                           &sc->last_reported_link.link_report_flags) &&
6874              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6875                           &cur_data.link_report_flags))) {
6876                 return;
6877         }
6878
6879         sc->link_cnt++;
6880
6881         /* report new link params and remember the state for the next time */
6882         (void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6883
6884         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6885                          &cur_data.link_report_flags)) {
6886                 PMD_DRV_LOG(INFO, "NIC Link is Down");
6887         } else {
6888                 __rte_unused const char *duplex;
6889                 __rte_unused const char *flow;
6890
6891                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6892                                            &cur_data.link_report_flags)) {
6893                         duplex = "full";
6894                 } else {
6895                         duplex = "half";
6896                 }
6897
6898 /*
6899  * Handle the FC at the end so that only these flags would be
6900  * possibly set. This way we may easily check if there is no FC
6901  * enabled.
6902  */
6903                 if (cur_data.link_report_flags) {
6904                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6905                                          &cur_data.link_report_flags) &&
6906                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6907                                          &cur_data.link_report_flags)) {
6908                                 flow = "ON - receive & transmit";
6909                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6910                                                 &cur_data.link_report_flags) &&
6911                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6912                                                  &cur_data.link_report_flags)) {
6913                                 flow = "ON - receive";
6914                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6915                                                  &cur_data.link_report_flags) &&
6916                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6917                                                 &cur_data.link_report_flags)) {
6918                                 flow = "ON - transmit";
6919                         } else {
6920                                 flow = "none";  /* possible? */
6921                         }
6922                 } else {
6923                         flow = "none";
6924                 }
6925
6926                 PMD_DRV_LOG(INFO,
6927                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6928                             cur_data.line_speed, duplex, flow);
6929         }
6930 }
6931
6932 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6933 {
6934         if (sc->state != BNX2X_STATE_OPEN) {
6935                 return;
6936         }
6937
6938         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6939                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6940         } else {
6941                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6942                                           ELINK_SUPPORTED_10baseT_Full |
6943                                           ELINK_SUPPORTED_100baseT_Half |
6944                                           ELINK_SUPPORTED_100baseT_Full |
6945                                           ELINK_SUPPORTED_1000baseT_Full |
6946                                           ELINK_SUPPORTED_2500baseX_Full |
6947                                           ELINK_SUPPORTED_10000baseT_Full |
6948                                           ELINK_SUPPORTED_TP |
6949                                           ELINK_SUPPORTED_FIBRE |
6950                                           ELINK_SUPPORTED_Autoneg |
6951                                           ELINK_SUPPORTED_Pause |
6952                                           ELINK_SUPPORTED_Asym_Pause);
6953                 sc->port.advertising[0] = sc->port.supported[0];
6954
6955                 sc->link_params.sc = sc;
6956                 sc->link_params.port = SC_PORT(sc);
6957                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6958                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6959                 sc->link_params.req_line_speed[0] = SPEED_10000;
6960                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6961                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6962
6963                 if (CHIP_REV_IS_FPGA(sc)) {
6964                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6965                         sc->link_vars.line_speed = ELINK_SPEED_1000;
6966                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6967                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6968                 } else {
6969                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6970                         sc->link_vars.line_speed = ELINK_SPEED_10000;
6971                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6972                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6973                 }
6974
6975                 sc->link_vars.link_up = 1;
6976
6977                 sc->link_vars.duplex = DUPLEX_FULL;
6978                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6979
6980                 if (IS_PF(sc)) {
6981                         REG_WR(sc,
6982                                NIG_REG_EGRESS_DRAIN0_MODE +
6983                                sc->link_params.port * 4, 0);
6984                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6985                         bnx2x_link_report(sc);
6986                 }
6987         }
6988
6989         if (IS_PF(sc)) {
6990                 if (sc->link_vars.link_up) {
6991                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6992                 } else {
6993                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
6994                 }
6995                 bnx2x_link_report(sc);
6996         } else {
6997                 bnx2x_link_report(sc);
6998                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6999         }
7000 }
7001
7002 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7003 {
7004         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7005 }
7006
7007 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7008 {
7009         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7010 }
7011
7012 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7013 {
7014         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7015         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7016         struct elink_params *lp = &sc->link_params;
7017
7018         bnx2x_set_requested_fc(sc);
7019
7020         if (CHIP_REV_IS_SLOW(sc)) {
7021                 uint32_t bond = CHIP_BOND_ID(sc);
7022                 uint32_t feat = 0;
7023
7024                 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
7025                         feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7026                 } else if (bond & 0x4) {
7027                         if (CHIP_IS_E3(sc)) {
7028                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
7029                         } else {
7030                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
7031                         }
7032                 } else if (bond & 0x8) {
7033                         if (CHIP_IS_E3(sc)) {
7034                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
7035                         } else {
7036                                 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7037                         }
7038                 }
7039
7040 /* disable EMAC for E3 and above */
7041                 if (bond & 0x2) {
7042                         feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
7043                 }
7044
7045                 sc->link_params.feature_config_flags |= feat;
7046         }
7047
7048         if (load_mode == LOAD_DIAG) {
7049                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7050 /* Prefer doing PHY loopback at 10G speed, if possible */
7051                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7052                         if (lp->speed_cap_mask[cfg_idx] &
7053                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7054                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7055                         } else {
7056                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7057                         }
7058                 }
7059         }
7060
7061         if (load_mode == LOAD_LOOPBACK_EXT) {
7062                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7063         }
7064
7065         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7066
7067         bnx2x_calc_fc_adv(sc);
7068
7069         if (sc->link_vars.link_up) {
7070                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7071                 bnx2x_link_report(sc);
7072         }
7073
7074         if (!CHIP_REV_IS_SLOW(sc)) {
7075                 bnx2x_periodic_start(sc);
7076         }
7077
7078         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7079         return rc;
7080 }
7081
7082 /* update flags in shmem */
7083 static void
7084 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7085 {
7086         uint32_t drv_flags;
7087
7088         if (SHMEM2_HAS(sc, drv_flags)) {
7089                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7090                 drv_flags = SHMEM2_RD(sc, drv_flags);
7091
7092                 if (set) {
7093                         drv_flags |= flags;
7094                 } else {
7095                         drv_flags &= ~flags;
7096                 }
7097
7098                 SHMEM2_WR(sc, drv_flags, drv_flags);
7099
7100                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7101         }
7102 }
7103
7104 /* periodic timer callout routine, only runs when the interface is up */
7105 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7106 {
7107         if ((sc->state != BNX2X_STATE_OPEN) ||
7108             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7109                 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7110                             sc->state);
7111                 return;
7112         }
7113         if (!CHIP_REV_IS_SLOW(sc)) {
7114 /*
7115  * This barrier is needed to ensure the ordering between the writing
7116  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7117  * the reading here.
7118  */
7119                 mb();
7120                 if (sc->port.pmf) {
7121                         elink_period_func(&sc->link_params, &sc->link_vars);
7122                 }
7123         }
7124 #ifdef BNX2X_PULSE
7125         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7126                 int mb_idx = SC_FW_MB_IDX(sc);
7127                 uint32_t drv_pulse;
7128                 uint32_t mcp_pulse;
7129
7130                 ++sc->fw_drv_pulse_wr_seq;
7131                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7132
7133                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7134                 bnx2x_drv_pulse(sc);
7135
7136                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7137                              MCP_PULSE_SEQ_MASK);
7138
7139 /*
7140  * The delta between driver pulse and mcp response should
7141  * be 1 (before mcp response) or 0 (after mcp response).
7142  */
7143                 if ((drv_pulse != mcp_pulse) &&
7144                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7145                         /* someone lost a heartbeat... */
7146                         PMD_DRV_LOG(ERR,
7147                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7148                                     drv_pulse, mcp_pulse);
7149                 }
7150         }
7151 #endif
7152 }
7153
7154 /* start the controller */
7155 static __attribute__ ((noinline))
7156 int bnx2x_nic_load(struct bnx2x_softc *sc)
7157 {
7158         uint32_t val;
7159         uint32_t load_code = 0;
7160         int i, rc = 0;
7161
7162         PMD_INIT_FUNC_TRACE();
7163
7164         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7165
7166         if (IS_PF(sc)) {
7167 /* must be called before memory allocation and HW init */
7168                 bnx2x_ilt_set_info(sc);
7169         }
7170
7171         bnx2x_set_fp_rx_buf_size(sc);
7172
7173         if (IS_PF(sc)) {
7174                 if (bnx2x_alloc_mem(sc) != 0) {
7175                         sc->state = BNX2X_STATE_CLOSED;
7176                         rc = -ENOMEM;
7177                         goto bnx2x_nic_load_error0;
7178                 }
7179         }
7180
7181         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7182                 sc->state = BNX2X_STATE_CLOSED;
7183                 rc = -ENOMEM;
7184                 goto bnx2x_nic_load_error0;
7185         }
7186
7187         if (IS_VF(sc)) {
7188                 rc = bnx2x_vf_init(sc);
7189                 if (rc) {
7190                         sc->state = BNX2X_STATE_ERROR;
7191                         goto bnx2x_nic_load_error0;
7192                 }
7193         }
7194
7195         if (IS_PF(sc)) {
7196 /* set pf load just before approaching the MCP */
7197                 bnx2x_set_pf_load(sc);
7198
7199 /* if MCP exists send load request and analyze response */
7200                 if (!BNX2X_NOMCP(sc)) {
7201                         /* attempt to load pf */
7202                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7203                                 sc->state = BNX2X_STATE_CLOSED;
7204                                 rc = -ENXIO;
7205                                 goto bnx2x_nic_load_error1;
7206                         }
7207
7208                         /* what did the MCP say? */
7209                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7210                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7211                                 sc->state = BNX2X_STATE_CLOSED;
7212                                 rc = -ENXIO;
7213                                 goto bnx2x_nic_load_error2;
7214                         }
7215                 } else {
7216                         PMD_DRV_LOG(INFO, "Device has no MCP!");
7217                         load_code = bnx2x_nic_load_no_mcp(sc);
7218                 }
7219
7220 /* mark PMF if applicable */
7221                 bnx2x_nic_load_pmf(sc, load_code);
7222
7223 /* Init Function state controlling object */
7224                 bnx2x_init_func_obj(sc);
7225
7226 /* Initialize HW */
7227                 if (bnx2x_init_hw(sc, load_code) != 0) {
7228                         PMD_DRV_LOG(NOTICE, "HW init failed");
7229                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7230                         sc->state = BNX2X_STATE_CLOSED;
7231                         rc = -ENXIO;
7232                         goto bnx2x_nic_load_error2;
7233                 }
7234         }
7235
7236         bnx2x_nic_init(sc, load_code);
7237
7238         /* Init per-function objects */
7239         if (IS_PF(sc)) {
7240                 bnx2x_init_objs(sc);
7241
7242 /* set AFEX default VLAN tag to an invalid value */
7243                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7244
7245                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7246                 rc = bnx2x_func_start(sc);
7247                 if (rc) {
7248                         PMD_DRV_LOG(NOTICE, "Function start failed!");
7249                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7250                         sc->state = BNX2X_STATE_ERROR;
7251                         goto bnx2x_nic_load_error3;
7252                 }
7253
7254 /* send LOAD_DONE command to MCP */
7255                 if (!BNX2X_NOMCP(sc)) {
7256                         load_code =
7257                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7258                         if (!load_code) {
7259                                 PMD_DRV_LOG(NOTICE,
7260                                             "MCP response failure, aborting");
7261                                 sc->state = BNX2X_STATE_ERROR;
7262                                 rc = -ENXIO;
7263                                 goto bnx2x_nic_load_error3;
7264                         }
7265                 }
7266         }
7267
7268         rc = bnx2x_setup_leading(sc);
7269         if (rc) {
7270                 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7271                 sc->state = BNX2X_STATE_ERROR;
7272                 goto bnx2x_nic_load_error3;
7273         }
7274
7275         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7276                 if (IS_PF(sc))
7277                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7278                 else            /* IS_VF(sc) */
7279                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7280
7281                 if (rc) {
7282                         PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7283                         sc->state = BNX2X_STATE_ERROR;
7284                         goto bnx2x_nic_load_error3;
7285                 }
7286         }
7287
7288         rc = bnx2x_init_rss_pf(sc);
7289         if (rc) {
7290                 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7291                 sc->state = BNX2X_STATE_ERROR;
7292                 goto bnx2x_nic_load_error3;
7293         }
7294
7295         /* now when Clients are configured we are ready to work */
7296         sc->state = BNX2X_STATE_OPEN;
7297
7298         /* Configure a ucast MAC */
7299         if (IS_PF(sc)) {
7300                 rc = bnx2x_set_eth_mac(sc, TRUE);
7301         } else {                /* IS_VF(sc) */
7302                 rc = bnx2x_vf_set_mac(sc, TRUE);
7303         }
7304
7305         if (rc) {
7306                 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7307                 sc->state = BNX2X_STATE_ERROR;
7308                 goto bnx2x_nic_load_error3;
7309         }
7310
7311         if (sc->port.pmf) {
7312                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7313                 if (rc) {
7314                         sc->state = BNX2X_STATE_ERROR;
7315                         goto bnx2x_nic_load_error3;
7316                 }
7317         }
7318
7319         sc->link_params.feature_config_flags &=
7320             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7321
7322         /* start the Tx */
7323         switch (LOAD_OPEN) {
7324         case LOAD_NORMAL:
7325         case LOAD_OPEN:
7326                 break;
7327
7328         case LOAD_DIAG:
7329         case LOAD_LOOPBACK_EXT:
7330                 sc->state = BNX2X_STATE_DIAG;
7331                 break;
7332
7333         default:
7334                 break;
7335         }
7336
7337         if (sc->port.pmf) {
7338                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7339         } else {
7340                 bnx2x_link_status_update(sc);
7341         }
7342
7343         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7344 /* mark driver is loaded in shmem2 */
7345                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7346                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7347                           (val |
7348                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7349                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7350         }
7351
7352         /* start fast path */
7353         /* Initialize Rx filter */
7354         bnx2x_set_rx_mode(sc);
7355
7356         /* wait for all pending SP commands to complete */
7357         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7358                 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7359                 bnx2x_periodic_stop(sc);
7360                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7361                 return -ENXIO;
7362         }
7363
7364         PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7365
7366         return 0;
7367
7368 bnx2x_nic_load_error3:
7369
7370         if (IS_PF(sc)) {
7371                 bnx2x_int_disable_sync(sc, 1);
7372
7373 /* clean out queued objects */
7374                 bnx2x_squeeze_objects(sc);
7375         }
7376
7377 bnx2x_nic_load_error2:
7378
7379         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7380                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7381                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7382         }
7383
7384         sc->port.pmf = 0;
7385
7386 bnx2x_nic_load_error1:
7387
7388         /* clear pf_load status, as it was already set */
7389         if (IS_PF(sc)) {
7390                 bnx2x_clear_pf_load(sc);
7391         }
7392
7393 bnx2x_nic_load_error0:
7394
7395         bnx2x_free_fw_stats_mem(sc);
7396         bnx2x_free_mem(sc);
7397
7398         return rc;
7399 }
7400
7401 /*
7402 * Handles controller initialization.
7403 */
7404 int bnx2x_init(struct bnx2x_softc *sc)
7405 {
7406         int other_engine = SC_PATH(sc) ? 0 : 1;
7407         uint8_t other_load_status, load_status;
7408         uint8_t global = FALSE;
7409         int rc;
7410
7411         /* Check if the driver is still running and bail out if it is. */
7412         if (sc->state != BNX2X_STATE_CLOSED) {
7413                 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7414                 rc = 0;
7415                 goto bnx2x_init_done;
7416         }
7417
7418         bnx2x_set_power_state(sc, PCI_PM_D0);
7419
7420         /*
7421          * If parity occurred during the unload, then attentions and/or
7422          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7423          * loaded on the current engine to complete the recovery. Parity recovery
7424          * is only relevant for PF driver.
7425          */
7426         if (IS_PF(sc)) {
7427                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7428                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7429
7430                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7431                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7432                         do {
7433                                 /*
7434                                  * If there are attentions and they are in global blocks, set
7435                                  * the GLOBAL_RESET bit regardless whether it will be this
7436                                  * function that will complete the recovery or not.
7437                                  */
7438                                 if (global) {
7439                                         bnx2x_set_reset_global(sc);
7440                                 }
7441
7442                                 /*
7443                                  * Only the first function on the current engine should try
7444                                  * to recover in open. In case of attentions in global blocks
7445                                  * only the first in the chip should try to recover.
7446                                  */
7447                                 if ((!load_status
7448                                      && (!global ||!other_load_status))
7449                                     && bnx2x_trylock_leader_lock(sc)
7450                                     && !bnx2x_leader_reset(sc)) {
7451                                         PMD_DRV_LOG(INFO,
7452                                                     "Recovered during init");
7453                                         break;
7454                                 }
7455
7456                                 /* recovery has failed... */
7457                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7458
7459                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7460
7461                                 PMD_DRV_LOG(NOTICE,
7462                                             "Recovery flow hasn't properly "
7463                                             "completed yet, try again later. "
7464                                             "If you still see this message after a "
7465                                             "few retries then power cycle is required.");
7466
7467                                 rc = -ENXIO;
7468                                 goto bnx2x_init_done;
7469                         } while (0);
7470                 }
7471         }
7472
7473         sc->recovery_state = BNX2X_RECOVERY_DONE;
7474
7475         rc = bnx2x_nic_load(sc);
7476
7477 bnx2x_init_done:
7478
7479         if (rc) {
7480                 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7481                             "stack notified driver is NOT running!");
7482         }
7483
7484         return rc;
7485 }
7486
7487 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7488 {
7489         uint32_t val = 0;
7490
7491         /*
7492          * Read the ME register to get the function number. The ME register
7493          * holds the relative-function number and absolute-function number. The
7494          * absolute-function number appears only in E2 and above. Before that
7495          * these bits always contained zero, therefore we cannot blindly use them.
7496          */
7497
7498         val = REG_RD(sc, BAR_ME_REGISTER);
7499
7500         sc->pfunc_rel =
7501             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7502         sc->path_id =
7503             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7504             1;
7505
7506         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7507                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7508         } else {
7509                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7510         }
7511
7512         PMD_DRV_LOG(DEBUG,
7513                     "Relative function %d, Absolute function %d, Path %d",
7514                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7515 }
7516
7517 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7518 {
7519         uint32_t shmem2_size;
7520         uint32_t offset;
7521         uint32_t mf_cfg_offset_value;
7522
7523         /* Non 57712 */
7524         offset = (SHMEM_ADDR(sc, func_mb) +
7525                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7526
7527         /* 57712 plus */
7528         if (sc->devinfo.shmem2_base != 0) {
7529                 shmem2_size = SHMEM2_RD(sc, size);
7530                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7531                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7532                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7533                                 offset = mf_cfg_offset_value;
7534                         }
7535                 }
7536         }
7537
7538         return offset;
7539 }
7540
7541 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7542 {
7543         uint32_t ret;
7544         struct bnx2x_pci_cap *caps;
7545
7546         /* ensure PCIe capability is enabled */
7547         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7548         if (NULL != caps) {
7549                 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7550                             "id=0x%04X type=0x%04X addr=0x%08X",
7551                             caps->id, caps->type, caps->addr);
7552                 pci_read(sc, (caps->addr + reg), &ret, 2);
7553                 return ret;
7554         }
7555
7556         PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7557
7558         return 0;
7559 }
7560
7561 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7562 {
7563         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7564                 PCIM_EXP_STA_TRANSACTION_PND;
7565 }
7566
7567 /*
7568 * Walk the PCI capabiites list for the device to find what features are
7569 * supported. These capabilites may be enabled/disabled by firmware so it's
7570 * best to walk the list rather than make assumptions.
7571 */
7572 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7573 {
7574         PMD_INIT_FUNC_TRACE();
7575
7576         struct bnx2x_pci_cap *caps;
7577         uint16_t link_status;
7578 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7579         int reg = 0;
7580 #endif
7581
7582         /* check if PCI Power Management is enabled */
7583         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7584         if (NULL != caps) {
7585                 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7586                             "id=0x%04X type=0x%04X addr=0x%08X",
7587                             caps->id, caps->type, caps->addr);
7588
7589                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7590                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7591         }
7592
7593         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7594
7595         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7596         sc->devinfo.pcie_link_width =
7597             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7598
7599         PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7600                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7601
7602         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7603
7604         /* check if MSI capability is enabled */
7605         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7606         if (NULL != caps) {
7607                 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7608
7609                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7610                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7611         }
7612
7613         /* check if MSI-X capability is enabled */
7614         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7615         if (NULL != caps) {
7616                 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7617
7618                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7619                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7620         }
7621 }
7622
7623 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7624 {
7625         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7626         uint32_t val;
7627
7628         /* get the outer vlan if we're in switch-dependent mode */
7629
7630         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7631         mf_info->ext_id = (uint16_t) val;
7632
7633         mf_info->multi_vnics_mode = 1;
7634
7635         if (!VALID_OVLAN(mf_info->ext_id)) {
7636                 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7637                 return 1;
7638         }
7639
7640         /* get the capabilities */
7641         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7642             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7643                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7644         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7645                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7646                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7647         } else {
7648                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7649         }
7650
7651         mf_info->vnics_per_port =
7652             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7653
7654         return 0;
7655 }
7656
7657 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7658 {
7659         uint32_t retval = 0;
7660         uint32_t val;
7661
7662         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7663
7664         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7665                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7666                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7667                 }
7668                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7669                         retval |= MF_PROTO_SUPPORT_ISCSI;
7670                 }
7671                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7672                         retval |= MF_PROTO_SUPPORT_FCOE;
7673                 }
7674         }
7675
7676         return retval;
7677 }
7678
7679 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7680 {
7681         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7682         uint32_t val;
7683
7684         /*
7685          * There is no outer vlan if we're in switch-independent mode.
7686          * If the mac is valid then assume multi-function.
7687          */
7688
7689         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7690
7691         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7692
7693         mf_info->mf_protos_supported =
7694             bnx2x_get_shmem_ext_proto_support_flags(sc);
7695
7696         mf_info->vnics_per_port =
7697             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7698
7699         return 0;
7700 }
7701
7702 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7703 {
7704         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7705         uint32_t e1hov_tag;
7706         uint32_t func_config;
7707         uint32_t niv_config;
7708
7709         mf_info->multi_vnics_mode = 1;
7710
7711         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7712         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7713         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7714
7715         mf_info->ext_id =
7716             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7717                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7718
7719         mf_info->default_vlan =
7720             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7721                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7722
7723         mf_info->niv_allowed_priorities =
7724             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7725                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7726
7727         mf_info->niv_default_cos =
7728             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7729                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7730
7731         mf_info->afex_vlan_mode =
7732             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7733              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7734
7735         mf_info->niv_mba_enabled =
7736             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7737              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7738
7739         mf_info->mf_protos_supported =
7740             bnx2x_get_shmem_ext_proto_support_flags(sc);
7741
7742         mf_info->vnics_per_port =
7743             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7744
7745         return 0;
7746 }
7747
7748 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7749 {
7750         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7751         uint32_t mf_cfg1;
7752         uint32_t mf_cfg2;
7753         uint32_t ovlan1;
7754         uint32_t ovlan2;
7755         uint8_t i, j;
7756
7757         /* various MF mode sanity checks... */
7758
7759         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7760                 PMD_DRV_LOG(NOTICE,
7761                             "Enumerated function %d is marked as hidden",
7762                             SC_PORT(sc));
7763                 return 1;
7764         }
7765
7766         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7767                 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7768                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7769                 return 1;
7770         }
7771
7772         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7773 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7774                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7775                         PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7776                                     SC_VN(sc), OVLAN(sc));
7777                         return 1;
7778                 }
7779
7780                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7781                         PMD_DRV_LOG(NOTICE,
7782                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7783                                     mf_info->multi_vnics_mode, OVLAN(sc));
7784                         return 1;
7785                 }
7786
7787 /*
7788  * Verify all functions are either MF or SF mode. If MF, make sure
7789  * sure that all non-hidden functions have a valid ovlan. If SF,
7790  * make sure that all non-hidden functions have an invalid ovlan.
7791  */
7792                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7793                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7794                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7795                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7796                             (((mf_info->multi_vnics_mode)
7797                               && !VALID_OVLAN(ovlan1))
7798                              || ((!mf_info->multi_vnics_mode)
7799                                  && VALID_OVLAN(ovlan1)))) {
7800                                 PMD_DRV_LOG(NOTICE,
7801                                             "mf_mode=SD function %d MF config "
7802                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7803                                             i, mf_info->multi_vnics_mode,
7804                                             ovlan1);
7805                                 return 1;
7806                         }
7807                 }
7808
7809 /* Verify all funcs on the same port each have a different ovlan. */
7810                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7811                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7812                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7813                         /* iterate from the next function on the port to the max func */
7814                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7815                                 mf_cfg2 =
7816                                     MFCFG_RD(sc, func_mf_config[j].config);
7817                                 ovlan2 =
7818                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7819                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7820                                     && VALID_OVLAN(ovlan1)
7821                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7822                                     && VALID_OVLAN(ovlan2)
7823                                     && (ovlan1 == ovlan2)) {
7824                                         PMD_DRV_LOG(NOTICE,
7825                                                     "mf_mode=SD functions %d and %d "
7826                                                     "have the same ovlan (%d)",
7827                                                     i, j, ovlan1);
7828                                         return 1;
7829                                 }
7830                         }
7831                 }
7832         }
7833         /* MULTI_FUNCTION_SD */
7834         return 0;
7835 }
7836
7837 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7838 {
7839         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7840         uint32_t val, mac_upper;
7841         uint8_t i, vnic;
7842
7843         /* initialize mf_info defaults */
7844         mf_info->vnics_per_port = 1;
7845         mf_info->multi_vnics_mode = FALSE;
7846         mf_info->path_has_ovlan = FALSE;
7847         mf_info->mf_mode = SINGLE_FUNCTION;
7848
7849         if (!CHIP_IS_MF_CAP(sc)) {
7850                 return 0;
7851         }
7852
7853         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7854                 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7855                 return 1;
7856         }
7857
7858         /* get the MF mode (switch dependent / independent / single-function) */
7859
7860         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7861
7862         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7863         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7864
7865                 mac_upper =
7866                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7867
7868                 /* check for legal upper mac bytes */
7869                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7870                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7871                 } else {
7872                         PMD_DRV_LOG(NOTICE,
7873                                     "Invalid config for Switch Independent mode");
7874                 }
7875
7876                 break;
7877
7878         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7879         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7880
7881                 /* get outer vlan configuration */
7882                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7883
7884                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7885                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7886                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7887                 } else {
7888                         PMD_DRV_LOG(NOTICE,
7889                                     "Invalid config for Switch Dependent mode");
7890                 }
7891
7892                 break;
7893
7894         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7895
7896                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7897                 return 0;
7898
7899         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7900
7901                 /*
7902                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7903                  * and the MAC address is valid.
7904                  */
7905                 mac_upper =
7906                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7907
7908                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7909                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7910                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7911                 } else {
7912                         PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7913                 }
7914
7915                 break;
7916
7917         default:
7918
7919                 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7920                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7921
7922                 return 1;
7923         }
7924
7925         /* set path mf_mode (which could be different than function mf_mode) */
7926         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7927                 mf_info->path_has_ovlan = TRUE;
7928         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7929 /*
7930  * Decide on path multi vnics mode. If we're not in MF mode and in
7931  * 4-port mode, this is good enough to check vnic-0 of the other port
7932  * on the same path
7933  */
7934                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7935                         uint8_t other_port = !(PORT_ID(sc) & 1);
7936                         uint8_t abs_func_other_port =
7937                             (SC_PATH(sc) + (2 * other_port));
7938
7939                         val =
7940                             MFCFG_RD(sc,
7941                                      func_mf_config
7942                                      [abs_func_other_port].e1hov_tag);
7943
7944                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7945                 }
7946         }
7947
7948         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7949 /* invalid MF config */
7950                 if (SC_VN(sc) >= 1) {
7951                         PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7952                         return 1;
7953                 }
7954
7955                 return 0;
7956         }
7957
7958         /* get the MF configuration */
7959         mf_info->mf_config[SC_VN(sc)] =
7960             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7961
7962         switch (mf_info->mf_mode) {
7963         case MULTI_FUNCTION_SD:
7964
7965                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7966                 break;
7967
7968         case MULTI_FUNCTION_SI:
7969
7970                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7971                 break;
7972
7973         case MULTI_FUNCTION_AFEX:
7974
7975                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7976                 break;
7977
7978         default:
7979
7980                 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7981                             mf_info->mf_mode);
7982                 return 1;
7983         }
7984
7985         /* get the congestion management parameters */
7986
7987         vnic = 0;
7988         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7989 /* get min/max bw */
7990                 val = MFCFG_RD(sc, func_mf_config[i].config);
7991                 mf_info->min_bw[vnic] =
7992                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7993                      FUNC_MF_CFG_MIN_BW_SHIFT);
7994                 mf_info->max_bw[vnic] =
7995                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7996                      FUNC_MF_CFG_MAX_BW_SHIFT);
7997                 vnic++;
7998         }
7999
8000         return bnx2x_check_valid_mf_cfg(sc);
8001 }
8002
8003 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8004 {
8005         int port;
8006         uint32_t mac_hi, mac_lo, val;
8007
8008         PMD_INIT_FUNC_TRACE();
8009
8010         port = SC_PORT(sc);
8011         mac_hi = mac_lo = 0;
8012
8013         sc->link_params.sc = sc;
8014         sc->link_params.port = port;
8015
8016         /* get the hardware config info */
8017         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8018         sc->devinfo.hw_config2 =
8019             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8020
8021         sc->link_params.hw_led_mode =
8022             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8023              SHARED_HW_CFG_LED_MODE_SHIFT);
8024
8025         /* get the port feature config */
8026         sc->port.config =
8027             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8028
8029         /* get the link params */
8030         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8031             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8032             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8033         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8034             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8035             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8036
8037         /* get the lane config */
8038         sc->link_params.lane_config =
8039             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8040
8041         /* get the link config */
8042         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8043         sc->port.link_config[ELINK_INT_PHY] = val;
8044         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8045         sc->port.link_config[ELINK_EXT_PHY1] =
8046             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8047
8048         /* get the override preemphasis flag and enable it or turn it off */
8049         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8050         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8051                 sc->link_params.feature_config_flags |=
8052                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8053         } else {
8054                 sc->link_params.feature_config_flags &=
8055                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8056         }
8057
8058         /* get the initial value of the link params */
8059         sc->link_params.multi_phy_config =
8060             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8061
8062         /* get external phy info */
8063         sc->port.ext_phy_config =
8064             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8065
8066         /* get the multifunction configuration */
8067         bnx2x_get_mf_cfg_info(sc);
8068
8069         /* get the mac address */
8070         if (IS_MF(sc)) {
8071                 mac_hi =
8072                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8073                 mac_lo =
8074                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8075         } else {
8076                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8077                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8078         }
8079
8080         if ((mac_lo == 0) && (mac_hi == 0)) {
8081                 *sc->mac_addr_str = 0;
8082                 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8083         } else {
8084                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8085                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8086                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8087                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8088                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8089                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8090                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8091                          "%02x:%02x:%02x:%02x:%02x:%02x",
8092                          sc->link_params.mac_addr[0],
8093                          sc->link_params.mac_addr[1],
8094                          sc->link_params.mac_addr[2],
8095                          sc->link_params.mac_addr[3],
8096                          sc->link_params.mac_addr[4],
8097                          sc->link_params.mac_addr[5]);
8098                 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8099         }
8100
8101         return 0;
8102 }
8103
8104 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8105 {
8106         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8107         switch (sc->link_params.phy[phy_idx].media_type) {
8108         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8109         case ELINK_ETH_PHY_SFP_1G_FIBER:
8110         case ELINK_ETH_PHY_XFP_FIBER:
8111         case ELINK_ETH_PHY_KR:
8112         case ELINK_ETH_PHY_CX4:
8113                 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8114                 sc->media = IFM_10G_CX4;
8115                 break;
8116         case ELINK_ETH_PHY_DA_TWINAX:
8117                 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8118                 sc->media = IFM_10G_TWINAX;
8119                 break;
8120         case ELINK_ETH_PHY_BASE_T:
8121                 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8122                 sc->media = IFM_10G_T;
8123                 break;
8124         case ELINK_ETH_PHY_NOT_PRESENT:
8125                 PMD_DRV_LOG(INFO, "Media not present.");
8126                 sc->media = 0;
8127                 break;
8128         case ELINK_ETH_PHY_UNSPECIFIED:
8129         default:
8130                 PMD_DRV_LOG(INFO, "Unknown media!");
8131                 sc->media = 0;
8132                 break;
8133         }
8134 }
8135
8136 #define GET_FIELD(value, fname)                     \
8137 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8138 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8139 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8140
8141 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8142 {
8143         int pfid = SC_FUNC(sc);
8144         int igu_sb_id;
8145         uint32_t val;
8146         uint8_t fid, igu_sb_cnt = 0;
8147
8148         sc->igu_base_sb = 0xff;
8149
8150         if (CHIP_INT_MODE_IS_BC(sc)) {
8151                 int vn = SC_VN(sc);
8152                 igu_sb_cnt = sc->igu_sb_cnt;
8153                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8154                                    FP_SB_MAX_E1x);
8155                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8156                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8157                 return 0;
8158         }
8159
8160         /* IGU in normal mode - read CAM */
8161         for (igu_sb_id = 0;
8162              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8163                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8164                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8165                         continue;
8166                 }
8167                 fid = IGU_FID(val);
8168                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8169                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8170                                 continue;
8171                         }
8172                         if (IGU_VEC(val) == 0) {
8173                                 /* default status block */
8174                                 sc->igu_dsb_id = igu_sb_id;
8175                         } else {
8176                                 if (sc->igu_base_sb == 0xff) {
8177                                         sc->igu_base_sb = igu_sb_id;
8178                                 }
8179                                 igu_sb_cnt++;
8180                         }
8181                 }
8182         }
8183
8184         /*
8185          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8186          * that number of CAM entries will not be equal to the value advertised in
8187          * PCI. Driver should use the minimal value of both as the actual status
8188          * block count
8189          */
8190         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8191
8192         if (igu_sb_cnt == 0) {
8193                 PMD_DRV_LOG(ERR, "CAM configuration error");
8194                 return -1;
8195         }
8196
8197         return 0;
8198 }
8199
8200 /*
8201 * Gather various information from the device config space, the device itself,
8202 * shmem, and the user input.
8203 */
8204 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8205 {
8206         uint32_t val;
8207         int rc;
8208
8209         /* get the chip revision (chip metal comes from pci config space) */
8210         sc->devinfo.chip_id = sc->link_params.chip_id =
8211             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8212              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8213              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8214              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8215
8216         /* force 57811 according to MISC register */
8217         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8218                 if (CHIP_IS_57810(sc)) {
8219                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8220                                                (sc->
8221                                                 devinfo.chip_id & 0x0000ffff));
8222                 } else if (CHIP_IS_57810_MF(sc)) {
8223                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8224                                                (sc->
8225                                                 devinfo.chip_id & 0x0000ffff));
8226                 }
8227                 sc->devinfo.chip_id |= 0x1;
8228         }
8229
8230         PMD_DRV_LOG(DEBUG,
8231                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8232                     sc->devinfo.chip_id,
8233                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8234                     ((sc->devinfo.chip_id >> 12) & 0xf),
8235                     ((sc->devinfo.chip_id >> 4) & 0xff),
8236                     ((sc->devinfo.chip_id >> 0) & 0xf));
8237
8238         val = (REG_RD(sc, 0x2874) & 0x55);
8239         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8240                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8241                 PMD_DRV_LOG(DEBUG, "single port device");
8242         }
8243
8244         /* set the doorbell size */
8245         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8246
8247         /* determine whether the device is in 2 port or 4 port mode */
8248         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8249         if (CHIP_IS_E2E3(sc)) {
8250 /*
8251  * Read port4mode_en_ovwr[0]:
8252  *   If 1, four port mode is in port4mode_en_ovwr[1].
8253  *   If 0, four port mode is in port4mode_en[0].
8254  */
8255                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8256                 if (val & 1) {
8257                         val = ((val >> 1) & 1);
8258                 } else {
8259                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8260                 }
8261
8262                 sc->devinfo.chip_port_mode =
8263                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8264
8265                 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8266         }
8267
8268         /* get the function and path info for the device */
8269         bnx2x_get_function_num(sc);
8270
8271         /* get the shared memory base address */
8272         sc->devinfo.shmem_base =
8273             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8274         sc->devinfo.shmem2_base =
8275             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8276                         MISC_REG_GENERIC_CR_0));
8277
8278         if (!sc->devinfo.shmem_base) {
8279 /* this should ONLY prevent upcoming shmem reads */
8280                 PMD_DRV_LOG(INFO, "MCP not active");
8281                 sc->flags |= BNX2X_NO_MCP_FLAG;
8282                 return 0;
8283         }
8284
8285         /* make sure the shared memory contents are valid */
8286         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8287         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8288             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8289                 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8290                             val);
8291                 return 0;
8292         }
8293
8294         /* get the bootcode version */
8295         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8296         snprintf(sc->devinfo.bc_ver_str,
8297                  sizeof(sc->devinfo.bc_ver_str),
8298                  "%d.%d.%d",
8299                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8300                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8301                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8302         PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8303
8304         /* get the bootcode shmem address */
8305         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8306
8307         /* clean indirect addresses as they're not used */
8308         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8309         if (IS_PF(sc)) {
8310                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8311                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8312                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8313                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8314                 if (CHIP_IS_E1x(sc)) {
8315                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8316                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8317                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8318                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8319                 }
8320
8321 /*
8322  * Enable internal target-read (in case we are probed after PF
8323  * FLR). Must be done prior to any BAR read access. Only for
8324  * 57712 and up
8325  */
8326                 if (!CHIP_IS_E1x(sc)) {
8327                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
8328                                1);
8329                 }
8330         }
8331
8332         /* get the nvram size */
8333         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8334         sc->devinfo.flash_size =
8335             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8336
8337         bnx2x_set_power_state(sc, PCI_PM_D0);
8338         /* get various configuration parameters from shmem */
8339         bnx2x_get_shmem_info(sc);
8340
8341         /* initialize IGU parameters */
8342         if (CHIP_IS_E1x(sc)) {
8343                 sc->devinfo.int_block = INT_BLOCK_HC;
8344                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8345                 sc->igu_base_sb = 0;
8346         } else {
8347                 sc->devinfo.int_block = INT_BLOCK_IGU;
8348
8349 /* do not allow device reset during IGU info preocessing */
8350                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8351
8352                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8353
8354                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8355                         int tout = 5000;
8356
8357                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8358                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8359                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8360
8361                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8362                                 tout--;
8363                                 DELAY(1000);
8364                         }
8365
8366                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8367                                 PMD_DRV_LOG(NOTICE,
8368                                             "FORCING IGU Normal Mode failed!!!");
8369                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8370                                 return -1;
8371                         }
8372                 }
8373
8374                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8375                         PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8376                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8377                 } else {
8378                         PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8379                 }
8380
8381                 rc = bnx2x_get_igu_cam_info(sc);
8382
8383                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8384
8385                 if (rc) {
8386                         return rc;
8387                 }
8388         }
8389
8390         /*
8391          * Get base FW non-default (fast path) status block ID. This value is
8392          * used to initialize the fw_sb_id saved on the fp/queue structure to
8393          * determine the id used by the FW.
8394          */
8395         if (CHIP_IS_E1x(sc)) {
8396                 sc->base_fw_ndsb =
8397                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8398         } else {
8399 /*
8400  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8401  * the same queue are indicated on the same IGU SB). So we prefer
8402  * FW and IGU SBs to be the same value.
8403  */
8404                 sc->base_fw_ndsb = sc->igu_base_sb;
8405         }
8406
8407         elink_phy_probe(&sc->link_params);
8408
8409         return 0;
8410 }
8411
8412 static void
8413 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8414 {
8415         uint32_t cfg_size = 0;
8416         uint32_t idx;
8417         uint8_t port = SC_PORT(sc);
8418
8419         /* aggregation of supported attributes of all external phys */
8420         sc->port.supported[0] = 0;
8421         sc->port.supported[1] = 0;
8422
8423         switch (sc->link_params.num_phys) {
8424         case 1:
8425                 sc->port.supported[0] =
8426                     sc->link_params.phy[ELINK_INT_PHY].supported;
8427                 cfg_size = 1;
8428                 break;
8429         case 2:
8430                 sc->port.supported[0] =
8431                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8432                 cfg_size = 1;
8433                 break;
8434         case 3:
8435                 if (sc->link_params.multi_phy_config &
8436                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8437                         sc->port.supported[1] =
8438                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8439                         sc->port.supported[0] =
8440                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8441                 } else {
8442                         sc->port.supported[0] =
8443                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8444                         sc->port.supported[1] =
8445                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8446                 }
8447                 cfg_size = 2;
8448                 break;
8449         }
8450
8451         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8452                 PMD_DRV_LOG(ERR,
8453                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8454                             SHMEM_RD(sc,
8455                                      dev_info.port_hw_config
8456                                      [port].external_phy_config),
8457                             SHMEM_RD(sc,
8458                                      dev_info.port_hw_config
8459                                      [port].external_phy_config2));
8460                 return;
8461         }
8462
8463         if (CHIP_IS_E3(sc))
8464                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8465         else {
8466                 switch (switch_cfg) {
8467                 case ELINK_SWITCH_CFG_1G:
8468                         sc->port.phy_addr =
8469                             REG_RD(sc,
8470                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8471                         break;
8472                 case ELINK_SWITCH_CFG_10G:
8473                         sc->port.phy_addr =
8474                             REG_RD(sc,
8475                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8476                         break;
8477                 default:
8478                         PMD_DRV_LOG(ERR,
8479                                     "Invalid switch config in"
8480                                     "link_config=0x%08x",
8481                                     sc->port.link_config[0]);
8482                         return;
8483                 }
8484         }
8485
8486         PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8487
8488         /* mask what we support according to speed_cap_mask per configuration */
8489         for (idx = 0; idx < cfg_size; idx++) {
8490                 if (!(sc->link_params.speed_cap_mask[idx] &
8491                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8492                         sc->port.supported[idx] &=
8493                             ~ELINK_SUPPORTED_10baseT_Half;
8494                 }
8495
8496                 if (!(sc->link_params.speed_cap_mask[idx] &
8497                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8498                         sc->port.supported[idx] &=
8499                             ~ELINK_SUPPORTED_10baseT_Full;
8500                 }
8501
8502                 if (!(sc->link_params.speed_cap_mask[idx] &
8503                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8504                         sc->port.supported[idx] &=
8505                             ~ELINK_SUPPORTED_100baseT_Half;
8506                 }
8507
8508                 if (!(sc->link_params.speed_cap_mask[idx] &
8509                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8510                         sc->port.supported[idx] &=
8511                             ~ELINK_SUPPORTED_100baseT_Full;
8512                 }
8513
8514                 if (!(sc->link_params.speed_cap_mask[idx] &
8515                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8516                         sc->port.supported[idx] &=
8517                             ~ELINK_SUPPORTED_1000baseT_Full;
8518                 }
8519
8520                 if (!(sc->link_params.speed_cap_mask[idx] &
8521                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8522                         sc->port.supported[idx] &=
8523                             ~ELINK_SUPPORTED_2500baseX_Full;
8524                 }
8525
8526                 if (!(sc->link_params.speed_cap_mask[idx] &
8527                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8528                         sc->port.supported[idx] &=
8529                             ~ELINK_SUPPORTED_10000baseT_Full;
8530                 }
8531
8532                 if (!(sc->link_params.speed_cap_mask[idx] &
8533                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8534                         sc->port.supported[idx] &=
8535                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8536                 }
8537         }
8538
8539         PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8540                     sc->port.supported[0], sc->port.supported[1]);
8541 }
8542
8543 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8544 {
8545         uint32_t link_config;
8546         uint32_t idx;
8547         uint32_t cfg_size = 0;
8548
8549         sc->port.advertising[0] = 0;
8550         sc->port.advertising[1] = 0;
8551
8552         switch (sc->link_params.num_phys) {
8553         case 1:
8554         case 2:
8555                 cfg_size = 1;
8556                 break;
8557         case 3:
8558                 cfg_size = 2;
8559                 break;
8560         }
8561
8562         for (idx = 0; idx < cfg_size; idx++) {
8563                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8564                 link_config = sc->port.link_config[idx];
8565
8566                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8567                 case PORT_FEATURE_LINK_SPEED_AUTO:
8568                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8569                                 sc->link_params.req_line_speed[idx] =
8570                                     ELINK_SPEED_AUTO_NEG;
8571                                 sc->port.advertising[idx] |=
8572                                     sc->port.supported[idx];
8573                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8574                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8575                                         sc->port.advertising[idx] |=
8576                                             (ELINK_SUPPORTED_100baseT_Half |
8577                                              ELINK_SUPPORTED_100baseT_Full);
8578                         } else {
8579                                 /* force 10G, no AN */
8580                                 sc->link_params.req_line_speed[idx] =
8581                                     ELINK_SPEED_10000;
8582                                 sc->port.advertising[idx] |=
8583                                     (ADVERTISED_10000baseT_Full |
8584                                      ADVERTISED_FIBRE);
8585                                 continue;
8586                         }
8587                         break;
8588
8589                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8590                         if (sc->
8591                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8592                         {
8593                                 sc->link_params.req_line_speed[idx] =
8594                                     ELINK_SPEED_10;
8595                                 sc->port.advertising[idx] |=
8596                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8597                         } else {
8598                                 PMD_DRV_LOG(ERR,
8599                                             "Invalid NVRAM config link_config=0x%08x "
8600                                             "speed_cap_mask=0x%08x",
8601                                             link_config,
8602                                             sc->
8603                                             link_params.speed_cap_mask[idx]);
8604                                 return;
8605                         }
8606                         break;
8607
8608                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8609                         if (sc->
8610                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8611                         {
8612                                 sc->link_params.req_line_speed[idx] =
8613                                     ELINK_SPEED_10;
8614                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8615                                 sc->port.advertising[idx] |=
8616                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8617                         } else {
8618                                 PMD_DRV_LOG(ERR,
8619                                             "Invalid NVRAM config link_config=0x%08x "
8620                                             "speed_cap_mask=0x%08x",
8621                                             link_config,
8622                                             sc->
8623                                             link_params.speed_cap_mask[idx]);
8624                                 return;
8625                         }
8626                         break;
8627
8628                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8629                         if (sc->
8630                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8631                         {
8632                                 sc->link_params.req_line_speed[idx] =
8633                                     ELINK_SPEED_100;
8634                                 sc->port.advertising[idx] |=
8635                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8636                         } else {
8637                                 PMD_DRV_LOG(ERR,
8638                                             "Invalid NVRAM config link_config=0x%08x "
8639                                             "speed_cap_mask=0x%08x",
8640                                             link_config,
8641                                             sc->
8642                                             link_params.speed_cap_mask[idx]);
8643                                 return;
8644                         }
8645                         break;
8646
8647                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8648                         if (sc->
8649                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8650                         {
8651                                 sc->link_params.req_line_speed[idx] =
8652                                     ELINK_SPEED_100;
8653                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8654                                 sc->port.advertising[idx] |=
8655                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8656                         } else {
8657                                 PMD_DRV_LOG(ERR,
8658                                             "Invalid NVRAM config link_config=0x%08x "
8659                                             "speed_cap_mask=0x%08x",
8660                                             link_config,
8661                                             sc->
8662                                             link_params.speed_cap_mask[idx]);
8663                                 return;
8664                         }
8665                         break;
8666
8667                 case PORT_FEATURE_LINK_SPEED_1G:
8668                         if (sc->port.supported[idx] &
8669                             ELINK_SUPPORTED_1000baseT_Full) {
8670                                 sc->link_params.req_line_speed[idx] =
8671                                     ELINK_SPEED_1000;
8672                                 sc->port.advertising[idx] |=
8673                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8674                         } else {
8675                                 PMD_DRV_LOG(ERR,
8676                                             "Invalid NVRAM config link_config=0x%08x "
8677                                             "speed_cap_mask=0x%08x",
8678                                             link_config,
8679                                             sc->
8680                                             link_params.speed_cap_mask[idx]);
8681                                 return;
8682                         }
8683                         break;
8684
8685                 case PORT_FEATURE_LINK_SPEED_2_5G:
8686                         if (sc->port.supported[idx] &
8687                             ELINK_SUPPORTED_2500baseX_Full) {
8688                                 sc->link_params.req_line_speed[idx] =
8689                                     ELINK_SPEED_2500;
8690                                 sc->port.advertising[idx] |=
8691                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8692                         } else {
8693                                 PMD_DRV_LOG(ERR,
8694                                             "Invalid NVRAM config link_config=0x%08x "
8695                                             "speed_cap_mask=0x%08x",
8696                                             link_config,
8697                                             sc->
8698                                             link_params.speed_cap_mask[idx]);
8699                                 return;
8700                         }
8701                         break;
8702
8703                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8704                         if (sc->port.supported[idx] &
8705                             ELINK_SUPPORTED_10000baseT_Full) {
8706                                 sc->link_params.req_line_speed[idx] =
8707                                     ELINK_SPEED_10000;
8708                                 sc->port.advertising[idx] |=
8709                                     (ADVERTISED_10000baseT_Full |
8710                                      ADVERTISED_FIBRE);
8711                         } else {
8712                                 PMD_DRV_LOG(ERR,
8713                                             "Invalid NVRAM config link_config=0x%08x "
8714                                             "speed_cap_mask=0x%08x",
8715                                             link_config,
8716                                             sc->
8717                                             link_params.speed_cap_mask[idx]);
8718                                 return;
8719                         }
8720                         break;
8721
8722                 case PORT_FEATURE_LINK_SPEED_20G:
8723                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8724                         break;
8725
8726                 default:
8727                         PMD_DRV_LOG(ERR,
8728                                     "Invalid NVRAM config link_config=0x%08x "
8729                                     "speed_cap_mask=0x%08x", link_config,
8730                                     sc->link_params.speed_cap_mask[idx]);
8731                         sc->link_params.req_line_speed[idx] =
8732                             ELINK_SPEED_AUTO_NEG;
8733                         sc->port.advertising[idx] = sc->port.supported[idx];
8734                         break;
8735                 }
8736
8737                 sc->link_params.req_flow_ctrl[idx] =
8738                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8739
8740                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8741                         if (!
8742                             (sc->
8743                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8744                                 sc->link_params.req_flow_ctrl[idx] =
8745                                     ELINK_FLOW_CTRL_NONE;
8746                         } else {
8747                                 bnx2x_set_requested_fc(sc);
8748                         }
8749                 }
8750         }
8751 }
8752
8753 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8754 {
8755         uint8_t port = SC_PORT(sc);
8756         uint32_t eee_mode;
8757
8758         PMD_INIT_FUNC_TRACE();
8759
8760         /* shmem data already read in bnx2x_get_shmem_info() */
8761
8762         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8763         bnx2x_link_settings_requested(sc);
8764
8765         /* configure link feature according to nvram value */
8766         eee_mode =
8767             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8768               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8769              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8770         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8771                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8772                                             ELINK_EEE_MODE_ENABLE_LPI |
8773                                             ELINK_EEE_MODE_OUTPUT_TIME);
8774         } else {
8775                 sc->link_params.eee_mode = 0;
8776         }
8777
8778         /* get the media type */
8779         bnx2x_media_detect(sc);
8780 }
8781
8782 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8783 {
8784         uint32_t flags = MODE_ASIC | MODE_PORT2;
8785
8786         if (CHIP_IS_E2(sc)) {
8787                 flags |= MODE_E2;
8788         } else if (CHIP_IS_E3(sc)) {
8789                 flags |= MODE_E3;
8790                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8791                         flags |= MODE_E3_A0;
8792                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8793
8794                         flags |= MODE_E3_B0 | MODE_COS3;
8795                 }
8796         }
8797
8798         if (IS_MF(sc)) {
8799                 flags |= MODE_MF;
8800                 switch (sc->devinfo.mf_info.mf_mode) {
8801                 case MULTI_FUNCTION_SD:
8802                         flags |= MODE_MF_SD;
8803                         break;
8804                 case MULTI_FUNCTION_SI:
8805                         flags |= MODE_MF_SI;
8806                         break;
8807                 case MULTI_FUNCTION_AFEX:
8808                         flags |= MODE_MF_AFEX;
8809                         break;
8810                 }
8811         } else {
8812                 flags |= MODE_SF;
8813         }
8814
8815 #if defined(__LITTLE_ENDIAN)
8816         flags |= MODE_LITTLE_ENDIAN;
8817 #else /* __BIG_ENDIAN */
8818         flags |= MODE_BIG_ENDIAN;
8819 #endif
8820
8821         INIT_MODE_FLAGS(sc) = flags;
8822 }
8823
8824 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8825 {
8826         struct bnx2x_fastpath *fp;
8827         char buf[32];
8828         uint32_t i;
8829
8830         if (IS_PF(sc)) {
8831 /************************/
8832 /* DEFAULT STATUS BLOCK */
8833 /************************/
8834
8835                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8836                                   &sc->def_sb_dma, "def_sb",
8837                                   RTE_CACHE_LINE_SIZE) != 0) {
8838                         return -1;
8839                 }
8840
8841                 sc->def_sb =
8842                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8843 /***************/
8844 /* EVENT QUEUE */
8845 /***************/
8846
8847                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8848                                   &sc->eq_dma, "ev_queue",
8849                                   RTE_CACHE_LINE_SIZE) != 0) {
8850                         sc->def_sb = NULL;
8851                         return -1;
8852                 }
8853
8854                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8855
8856 /*************/
8857 /* SLOW PATH */
8858 /*************/
8859
8860                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8861                                   &sc->sp_dma, "sp",
8862                                   RTE_CACHE_LINE_SIZE) != 0) {
8863                         sc->eq = NULL;
8864                         sc->def_sb = NULL;
8865                         return -1;
8866                 }
8867
8868                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8869
8870 /*******************/
8871 /* SLOW PATH QUEUE */
8872 /*******************/
8873
8874                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8875                                   &sc->spq_dma, "sp_queue",
8876                                   RTE_CACHE_LINE_SIZE) != 0) {
8877                         sc->sp = NULL;
8878                         sc->eq = NULL;
8879                         sc->def_sb = NULL;
8880                         return -1;
8881                 }
8882
8883                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8884
8885 /***************************/
8886 /* FW DECOMPRESSION BUFFER */
8887 /***************************/
8888
8889                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8890                                   "fw_dec_buf", RTE_CACHE_LINE_SIZE) != 0) {
8891                         sc->spq = NULL;
8892                         sc->sp = NULL;
8893                         sc->eq = NULL;
8894                         sc->def_sb = NULL;
8895                         return -1;
8896                 }
8897
8898                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8899         }
8900
8901         /*************/
8902         /* FASTPATHS */
8903         /*************/
8904
8905         /* allocate DMA memory for each fastpath structure */
8906         for (i = 0; i < sc->num_queues; i++) {
8907                 fp = &sc->fp[i];
8908                 fp->sc = sc;
8909                 fp->index = i;
8910
8911 /*******************/
8912 /* FP STATUS BLOCK */
8913 /*******************/
8914
8915                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8916                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8917                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8918                         PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8919                         return -1;
8920                 } else {
8921                         if (CHIP_IS_E2E3(sc)) {
8922                                 fp->status_block.e2_sb =
8923                                     (struct host_hc_status_block_e2 *)
8924                                     fp->sb_dma.vaddr;
8925                         } else {
8926                                 fp->status_block.e1x_sb =
8927                                     (struct host_hc_status_block_e1x *)
8928                                     fp->sb_dma.vaddr;
8929                         }
8930                 }
8931         }
8932
8933         return 0;
8934 }
8935
8936 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8937 {
8938         struct bnx2x_fastpath *fp;
8939         int i;
8940
8941         for (i = 0; i < sc->num_queues; i++) {
8942                 fp = &sc->fp[i];
8943
8944 /*******************/
8945 /* FP STATUS BLOCK */
8946 /*******************/
8947
8948                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8949         }
8950
8951         /***************************/
8952         /* FW DECOMPRESSION BUFFER */
8953         /***************************/
8954
8955         sc->gz_buf = NULL;
8956
8957         /*******************/
8958         /* SLOW PATH QUEUE */
8959         /*******************/
8960
8961         sc->spq = NULL;
8962
8963         /*************/
8964         /* SLOW PATH */
8965         /*************/
8966
8967         sc->sp = NULL;
8968
8969         /***************/
8970         /* EVENT QUEUE */
8971         /***************/
8972
8973         sc->eq = NULL;
8974
8975         /************************/
8976         /* DEFAULT STATUS BLOCK */
8977         /************************/
8978
8979         sc->def_sb = NULL;
8980
8981 }
8982
8983 /*
8984 * Previous driver DMAE transaction may have occurred when pre-boot stage
8985 * ended and boot began. This would invalidate the addresses of the
8986 * transaction, resulting in was-error bit set in the PCI causing all
8987 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8988 * the interrupt which detected this from the pglueb and the was-done bit
8989 */
8990 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8991 {
8992         uint32_t val;
8993
8994         if (!CHIP_IS_E1x(sc)) {
8995                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8996                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8997                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8998                                1 << SC_FUNC(sc));
8999                 }
9000         }
9001 }
9002
9003 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9004 {
9005         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9006                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9007         if (!rc) {
9008                 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9009                 return -1;
9010         }
9011
9012         return 0;
9013 }
9014
9015 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9016 {
9017         struct bnx2x_prev_list_node *tmp;
9018
9019         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9020                 if ((sc->pcie_bus == tmp->bus) &&
9021                     (sc->pcie_device == tmp->slot) &&
9022                     (SC_PATH(sc) == tmp->path)) {
9023                         return tmp;
9024                 }
9025         }
9026
9027         return NULL;
9028 }
9029
9030 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9031 {
9032         struct bnx2x_prev_list_node *tmp;
9033         int rc = FALSE;
9034
9035         rte_spinlock_lock(&bnx2x_prev_mtx);
9036
9037         tmp = bnx2x_prev_path_get_entry(sc);
9038         if (tmp) {
9039                 if (tmp->aer) {
9040                         PMD_DRV_LOG(DEBUG,
9041                                     "Path %d/%d/%d was marked by AER",
9042                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9043                 } else {
9044                         rc = TRUE;
9045                         PMD_DRV_LOG(DEBUG,
9046                                     "Path %d/%d/%d was already cleaned from previous drivers",
9047                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9048                 }
9049         }
9050
9051         rte_spinlock_unlock(&bnx2x_prev_mtx);
9052
9053         return rc;
9054 }
9055
9056 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9057 {
9058         struct bnx2x_prev_list_node *tmp;
9059
9060         rte_spinlock_lock(&bnx2x_prev_mtx);
9061
9062         /* Check whether the entry for this path already exists */
9063         tmp = bnx2x_prev_path_get_entry(sc);
9064         if (tmp) {
9065                 if (!tmp->aer) {
9066                         PMD_DRV_LOG(DEBUG,
9067                                     "Re-marking AER in path %d/%d/%d",
9068                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9069                 } else {
9070                         PMD_DRV_LOG(DEBUG,
9071                                     "Removing AER indication from path %d/%d/%d",
9072                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9073                         tmp->aer = 0;
9074                 }
9075
9076                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9077                 return 0;
9078         }
9079
9080         rte_spinlock_unlock(&bnx2x_prev_mtx);
9081
9082         /* Create an entry for this path and add it */
9083         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9084                          RTE_CACHE_LINE_SIZE);
9085         if (!tmp) {
9086                 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9087                 return -1;
9088         }
9089
9090         tmp->bus = sc->pcie_bus;
9091         tmp->slot = sc->pcie_device;
9092         tmp->path = SC_PATH(sc);
9093         tmp->aer = 0;
9094         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9095
9096         rte_spinlock_lock(&bnx2x_prev_mtx);
9097
9098         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9099
9100         rte_spinlock_unlock(&bnx2x_prev_mtx);
9101
9102         return 0;
9103 }
9104
9105 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9106 {
9107         int i;
9108
9109         /* only E2 and onwards support FLR */
9110         if (CHIP_IS_E1x(sc)) {
9111                 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9112                 return -1;
9113         }
9114
9115         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9116         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9117                 PMD_DRV_LOG(WARNING,
9118                             "FLR not supported by BC_VER: 0x%08x",
9119                             sc->devinfo.bc_ver);
9120                 return -1;
9121         }
9122
9123         /* Wait for Transaction Pending bit clean */
9124         for (i = 0; i < 4; i++) {
9125                 if (i) {
9126                         DELAY(((1 << (i - 1)) * 100) * 1000);
9127                 }
9128
9129                 if (!bnx2x_is_pcie_pending(sc)) {
9130                         goto clear;
9131                 }
9132         }
9133
9134         PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9135                     "proceeding with reset anyway");
9136
9137 clear:
9138         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9139
9140         return 0;
9141 }
9142
9143 struct bnx2x_mac_vals {
9144         uint32_t xmac_addr;
9145         uint32_t xmac_val;
9146         uint32_t emac_addr;
9147         uint32_t emac_val;
9148         uint32_t umac_addr;
9149         uint32_t umac_val;
9150         uint32_t bmac_addr;
9151         uint32_t bmac_val[2];
9152 };
9153
9154 static void
9155 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9156 {
9157         uint32_t val, base_addr, offset, mask, reset_reg;
9158         uint8_t mac_stopped = FALSE;
9159         uint8_t port = SC_PORT(sc);
9160         uint32_t wb_data[2];
9161
9162         /* reset addresses as they also mark which values were changed */
9163         vals->bmac_addr = 0;
9164         vals->umac_addr = 0;
9165         vals->xmac_addr = 0;
9166         vals->emac_addr = 0;
9167
9168         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9169
9170         if (!CHIP_IS_E3(sc)) {
9171                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9172                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9173                 if ((mask & reset_reg) && val) {
9174                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9175                             : NIG_REG_INGRESS_BMAC0_MEM;
9176                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9177                             : BIGMAC_REGISTER_BMAC_CONTROL;
9178
9179                         /*
9180                          * use rd/wr since we cannot use dmae. This is safe
9181                          * since MCP won't access the bus due to the request
9182                          * to unload, and no function on the path can be
9183                          * loaded at this time.
9184                          */
9185                         wb_data[0] = REG_RD(sc, base_addr + offset);
9186                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9187                         vals->bmac_addr = base_addr + offset;
9188                         vals->bmac_val[0] = wb_data[0];
9189                         vals->bmac_val[1] = wb_data[1];
9190                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9191                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9192                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9193                 }
9194
9195                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9196                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9197                 REG_WR(sc, vals->emac_addr, 0);
9198                 mac_stopped = TRUE;
9199         } else {
9200                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9201                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9202                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9203                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9204                                val & ~(1 << 1));
9205                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9206                                val | (1 << 1));
9207                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9208                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9209                         REG_WR(sc, vals->xmac_addr, 0);
9210                         mac_stopped = TRUE;
9211                 }
9212
9213                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9214                 if (mask & reset_reg) {
9215                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9216                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9217                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9218                         REG_WR(sc, vals->umac_addr, 0);
9219                         mac_stopped = TRUE;
9220                 }
9221         }
9222
9223         if (mac_stopped) {
9224                 DELAY(20000);
9225         }
9226 }
9227
9228 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9229 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9230 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9231 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9232
9233 static void
9234 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9235 {
9236         uint16_t rcq, bd;
9237         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9238
9239         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9240         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9241
9242         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9243         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9244 }
9245
9246 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9247 {
9248         uint32_t reset_reg, tmp_reg = 0, rc;
9249         uint8_t prev_undi = FALSE;
9250         struct bnx2x_mac_vals mac_vals;
9251         uint32_t timer_count = 1000;
9252         uint32_t prev_brb;
9253
9254         /*
9255          * It is possible a previous function received 'common' answer,
9256          * but hasn't loaded yet, therefore creating a scenario of
9257          * multiple functions receiving 'common' on the same path.
9258          */
9259         memset(&mac_vals, 0, sizeof(mac_vals));
9260
9261         if (bnx2x_prev_is_path_marked(sc)) {
9262                 return bnx2x_prev_mcp_done(sc);
9263         }
9264
9265         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9266
9267         /* Reset should be performed after BRB is emptied */
9268         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9269                 /* Close the MAC Rx to prevent BRB from filling up */
9270                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9271
9272                 /* close LLH filters towards the BRB */
9273                 elink_set_rx_filter(&sc->link_params, 0);
9274
9275                 /*
9276                  * Check if the UNDI driver was previously loaded.
9277                  * UNDI driver initializes CID offset for normal bell to 0x7
9278                  */
9279                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9280                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9281                         if (tmp_reg == 0x7) {
9282                                 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9283                                 prev_undi = TRUE;
9284                                 /* clear the UNDI indication */
9285                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9286                                 /* clear possible idle check errors */
9287                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9288                         }
9289                 }
9290
9291                 /* wait until BRB is empty */
9292                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9293                 while (timer_count) {
9294                         prev_brb = tmp_reg;
9295
9296                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9297                         if (!tmp_reg) {
9298                                 break;
9299                         }
9300
9301                         PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9302
9303                         /* reset timer as long as BRB actually gets emptied */
9304                         if (prev_brb > tmp_reg) {
9305                                 timer_count = 1000;
9306                         } else {
9307                                 timer_count--;
9308                         }
9309
9310                         /* If UNDI resides in memory, manually increment it */
9311                         if (prev_undi) {
9312                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9313                         }
9314
9315                         DELAY(10);
9316                 }
9317
9318                 if (!timer_count) {
9319                         PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9320                 }
9321         }
9322
9323         /* No packets are in the pipeline, path is ready for reset */
9324         bnx2x_reset_common(sc);
9325
9326         if (mac_vals.xmac_addr) {
9327                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9328         }
9329         if (mac_vals.umac_addr) {
9330                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9331         }
9332         if (mac_vals.emac_addr) {
9333                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9334         }
9335         if (mac_vals.bmac_addr) {
9336                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9337                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9338         }
9339
9340         rc = bnx2x_prev_mark_path(sc, prev_undi);
9341         if (rc) {
9342                 bnx2x_prev_mcp_done(sc);
9343                 return rc;
9344         }
9345
9346         return bnx2x_prev_mcp_done(sc);
9347 }
9348
9349 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9350 {
9351         int rc;
9352
9353         /* Test if previous unload process was already finished for this path */
9354         if (bnx2x_prev_is_path_marked(sc)) {
9355                 return bnx2x_prev_mcp_done(sc);
9356         }
9357
9358         /*
9359          * If function has FLR capabilities, and existing FW version matches
9360          * the one required, then FLR will be sufficient to clean any residue
9361          * left by previous driver
9362          */
9363         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9364         if (!rc) {
9365                 /* fw version is good */
9366                 rc = bnx2x_do_flr(sc);
9367         }
9368
9369         if (!rc) {
9370                 /* FLR was performed */
9371                 return 0;
9372         }
9373
9374         PMD_DRV_LOG(INFO, "Could not FLR");
9375
9376         /* Close the MCP request, return failure */
9377         rc = bnx2x_prev_mcp_done(sc);
9378         if (!rc) {
9379                 rc = BNX2X_PREV_WAIT_NEEDED;
9380         }
9381
9382         return rc;
9383 }
9384
9385 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9386 {
9387         int time_counter = 10;
9388         uint32_t fw, hw_lock_reg, hw_lock_val;
9389         uint32_t rc = 0;
9390
9391         /*
9392          * Clear HW from errors which may have resulted from an interrupted
9393          * DMAE transaction.
9394          */
9395         bnx2x_prev_interrupted_dmae(sc);
9396
9397         /* Release previously held locks */
9398         if (SC_FUNC(sc) <= 5)
9399                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9400         else
9401                 hw_lock_reg =
9402                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9403
9404         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9405         if (hw_lock_val) {
9406                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9407                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9408                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9409                 }
9410                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9411         }
9412
9413         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9414                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9415         }
9416
9417         do {
9418                 /* Lock MCP using an unload request */
9419                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9420                 if (!fw) {
9421                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9422                         rc = -1;
9423                         break;
9424                 }
9425
9426                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9427                         rc = bnx2x_prev_unload_common(sc);
9428                         break;
9429                 }
9430
9431                 /* non-common reply from MCP might require looping */
9432                 rc = bnx2x_prev_unload_uncommon(sc);
9433                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9434                         break;
9435                 }
9436
9437                 DELAY(20000);
9438         } while (--time_counter);
9439
9440         if (!time_counter || rc) {
9441                 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9442                 rc = -1;
9443         }
9444
9445         return rc;
9446 }
9447
9448 static void
9449 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9450 {
9451         if (!CHIP_IS_E1x(sc)) {
9452                 sc->dcb_state = dcb_on;
9453                 sc->dcbx_enabled = dcbx_enabled;
9454         } else {
9455                 sc->dcb_state = FALSE;
9456                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9457         }
9458         PMD_DRV_LOG(DEBUG,
9459                     "DCB state [%s:%s]",
9460                     dcb_on ? "ON" : "OFF",
9461                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9462                     (dcbx_enabled ==
9463                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9464                     : (dcbx_enabled ==
9465                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9466                     "on-chip with negotiation" : "invalid");
9467 }
9468
9469 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9470 {
9471         int cid_count = BNX2X_L2_MAX_CID(sc);
9472
9473         if (CNIC_SUPPORT(sc)) {
9474                 cid_count += CNIC_CID_MAX;
9475         }
9476
9477         return roundup(cid_count, QM_CID_ROUND);
9478 }
9479
9480 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9481 {
9482         int pri, cos;
9483
9484         uint32_t pri_map = 0;
9485
9486         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9487                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9488                 if (cos < sc->max_cos) {
9489                         sc->prio_to_cos[pri] = cos;
9490                 } else {
9491                         PMD_DRV_LOG(WARNING,
9492                                     "Invalid COS %d for priority %d "
9493                                     "(max COS is %d), setting to 0", cos, pri,
9494                                     (sc->max_cos - 1));
9495                         sc->prio_to_cos[pri] = 0;
9496                 }
9497         }
9498 }
9499
9500 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9501 {
9502         struct {
9503                 uint8_t id;
9504                 uint8_t next;
9505         } pci_cap;
9506         uint16_t status;
9507         struct bnx2x_pci_cap *cap;
9508
9509         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9510                                          RTE_CACHE_LINE_SIZE);
9511         if (!cap) {
9512                 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9513                 return -ENOMEM;
9514         }
9515
9516 #ifndef __FreeBSD__
9517         pci_read(sc, PCI_STATUS, &status, 2);
9518         if (!(status & PCI_STATUS_CAP_LIST)) {
9519 #else
9520         pci_read(sc, PCIR_STATUS, &status, 2);
9521         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9522 #endif
9523                 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9524                 return -1;
9525         }
9526
9527 #ifndef __FreeBSD__
9528         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9529 #else
9530         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9531 #endif
9532         while (pci_cap.next) {
9533                 cap->addr = pci_cap.next & ~3;
9534                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9535                 if (pci_cap.id == 0xff)
9536                         break;
9537                 cap->id = pci_cap.id;
9538                 cap->type = BNX2X_PCI_CAP;
9539                 cap->next = rte_zmalloc("pci_cap",
9540                                         sizeof(struct bnx2x_pci_cap),
9541                                         RTE_CACHE_LINE_SIZE);
9542                 if (!cap->next) {
9543                         PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9544                         return -ENOMEM;
9545                 }
9546                 cap = cap->next;
9547         }
9548
9549         return 0;
9550 }
9551
9552 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9553 {
9554         if (IS_VF(sc)) {
9555                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9556                                         sc->igu_sb_cnt);
9557                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9558                                         sc->igu_sb_cnt);
9559         } else {
9560                 sc->max_tx_queues = 128;
9561                 sc->max_rx_queues = 128;
9562         }
9563 }
9564
9565 #define FW_HEADER_LEN 104
9566 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9567 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9568
9569 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9570 {
9571         const char *fwname;
9572         int f;
9573         struct stat st;
9574
9575         fwname = sc->devinfo.device_id == BNX2X_DEV_ID_57711
9576                 ? FW_NAME_57711 : FW_NAME_57810;
9577         f = open(fwname, O_RDONLY);
9578         if (f < 0) {
9579                 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9580                 return;
9581         }
9582
9583         if (fstat(f, &st) < 0) {
9584                 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9585                 close(f);
9586                 return;
9587         }
9588
9589         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9590         if (!sc->firmware) {
9591                 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9592                 close(f);
9593                 return;
9594         }
9595
9596         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9597                 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9598                 close(f);
9599                 return;
9600         }
9601         close(f);
9602
9603         sc->fw_len = st.st_size;
9604         if (sc->fw_len < FW_HEADER_LEN) {
9605                 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9606                 return;
9607         }
9608         PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9609 }
9610
9611 static void
9612 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9613 {
9614         uint32_t *src = (uint32_t *) data;
9615         uint32_t i, j, tmp;
9616
9617         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9618                 tmp = rte_be_to_cpu_32(src[j]);
9619                 dst[i].op = (tmp >> 24) & 0xFF;
9620                 dst[i].offset = tmp & 0xFFFFFF;
9621                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9622         }
9623 }
9624
9625 static void
9626 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9627 {
9628         uint16_t *src = (uint16_t *) data;
9629         uint32_t i;
9630
9631         for (i = 0; i < len / 2; ++i)
9632                 dst[i] = rte_be_to_cpu_16(src[i]);
9633 }
9634
9635 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9636 {
9637         uint32_t *src = (uint32_t *) data;
9638         uint32_t i;
9639
9640         for (i = 0; i < len / 4; ++i)
9641                 dst[i] = rte_be_to_cpu_32(src[i]);
9642 }
9643
9644 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9645 {
9646         uint32_t *src = (uint32_t *) data;
9647         uint32_t i, j, tmp;
9648
9649         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9650                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9651                 tmp = rte_be_to_cpu_32(src[j]);
9652                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9653                 dst[i].m2 = tmp & 0xFFFF;
9654                 ++j;
9655                 tmp = rte_be_to_cpu_32(src[j]);
9656                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9657                 dst[i].size = tmp & 0xFFFF;
9658         }
9659 }
9660
9661 /*
9662 * Device attach function.
9663 *
9664 * Allocates device resources, performs secondary chip identification, and
9665 * initializes driver instance variables. This function is called from driver
9666 * load after a successful probe.
9667 *
9668 * Returns:
9669 *   0 = Success, >0 = Failure
9670 */
9671 int bnx2x_attach(struct bnx2x_softc *sc)
9672 {
9673         int rc;
9674
9675         PMD_DRV_LOG(DEBUG, "Starting attach...");
9676
9677         rc = bnx2x_pci_get_caps(sc);
9678         if (rc) {
9679                 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9680                 return rc;
9681         }
9682
9683         sc->state = BNX2X_STATE_CLOSED;
9684
9685         /* Init RTE stuff */
9686         bnx2x_init_rte(sc);
9687
9688         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9689
9690         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9691
9692         /* get PCI capabilites */
9693         bnx2x_probe_pci_caps(sc);
9694
9695         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9696                 uint32_t val;
9697                 pci_read(sc,
9698                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9699                          2);
9700                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9701         } else {
9702                 sc->igu_sb_cnt = 1;
9703         }
9704
9705         if (IS_PF(sc)) {
9706 /* get device info and set params */
9707                 if (bnx2x_get_device_info(sc) != 0) {
9708                         PMD_DRV_LOG(NOTICE, "getting device info");
9709                         return -ENXIO;
9710                 }
9711
9712 /* get phy settings from shmem and 'and' against admin settings */
9713                 bnx2x_get_phy_info(sc);
9714         } else {
9715 /* Left mac of VF unfilled, PF should set it for VF */
9716                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9717         }
9718
9719         sc->wol = 0;
9720
9721         /* set the default MTU (changed via ifconfig) */
9722         sc->mtu = ETHER_MTU;
9723
9724         bnx2x_set_modes_bitmap(sc);
9725
9726         /* need to reset chip if UNDI was active */
9727         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9728 /* init fw_seq */
9729                 sc->fw_seq =
9730                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9731                      DRV_MSG_SEQ_NUMBER_MASK);
9732                 bnx2x_prev_unload(sc);
9733         }
9734
9735         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9736
9737         /* calculate qm_cid_count */
9738         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9739
9740         sc->max_cos = 1;
9741         bnx2x_init_multi_cos(sc);
9742
9743         return 0;
9744 }
9745
9746 static void
9747 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9748                uint16_t index, uint8_t op, uint8_t update)
9749 {
9750         uint32_t igu_addr = sc->igu_base_addr;
9751         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9752         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9753 }
9754
9755 static void
9756 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9757            uint16_t index, uint8_t op, uint8_t update)
9758 {
9759         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9760                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9761         else {
9762                 uint8_t segment;
9763                 if (CHIP_INT_MODE_IS_BC(sc)) {
9764                         segment = storm;
9765                 } else if (igu_sb_id != sc->igu_dsb_id) {
9766                         segment = IGU_SEG_ACCESS_DEF;
9767                 } else if (storm == ATTENTION_ID) {
9768                         segment = IGU_SEG_ACCESS_ATTN;
9769                 } else {
9770                         segment = IGU_SEG_ACCESS_DEF;
9771                 }
9772                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9773         }
9774 }
9775
9776 static void
9777 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9778                      uint8_t is_pf)
9779 {
9780         uint32_t data, ctl, cnt = 100;
9781         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9782         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9783         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9784             (idu_sb_id / 32) * 4;
9785         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9786         uint32_t func_encode = func |
9787             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9788         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9789
9790         /* Not supported in BC mode */
9791         if (CHIP_INT_MODE_IS_BC(sc)) {
9792                 return;
9793         }
9794
9795         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9796                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9797                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9798
9799         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9800                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9801                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9802
9803         REG_WR(sc, igu_addr_data, data);
9804
9805         mb();
9806
9807         PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9808                     ctl, igu_addr_ctl);
9809         REG_WR(sc, igu_addr_ctl, ctl);
9810
9811         mb();
9812
9813         /* wait for clean up to finish */
9814         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9815                 DELAY(20000);
9816         }
9817
9818         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9819                 PMD_DRV_LOG(DEBUG,
9820                             "Unable to finish IGU cleanup: "
9821                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9822                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9823         }
9824 }
9825
9826 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9827 {
9828         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9829 }
9830
9831 /*******************/
9832 /* ECORE CALLBACKS */
9833 /*******************/
9834
9835 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9836 {
9837         uint32_t val = 0x1400;
9838
9839         PMD_INIT_FUNC_TRACE();
9840
9841         /* reset_common */
9842         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9843                0xd3ffff7f);
9844
9845         if (CHIP_IS_E3(sc)) {
9846                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9847                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9848         }
9849
9850         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9851 }
9852
9853 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9854 {
9855         uint32_t shmem_base[2];
9856         uint32_t shmem2_base[2];
9857
9858         /* Avoid common init in case MFW supports LFA */
9859         if (SHMEM2_RD(sc, size) >
9860             (uint32_t) offsetof(struct shmem2_region,
9861                                 lfa_host_addr[SC_PORT(sc)])) {
9862                 return;
9863         }
9864
9865         shmem_base[0] = sc->devinfo.shmem_base;
9866         shmem2_base[0] = sc->devinfo.shmem2_base;
9867
9868         if (!CHIP_IS_E1x(sc)) {
9869                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9870                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9871         }
9872
9873         elink_common_init_phy(sc, shmem_base, shmem2_base,
9874                               sc->devinfo.chip_id, 0);
9875 }
9876
9877 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9878 {
9879         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9880
9881         val &= ~IGU_PF_CONF_FUNC_EN;
9882
9883         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9884         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9885         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9886 }
9887
9888 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9889 {
9890         uint16_t devctl;
9891         int r_order, w_order;
9892
9893         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9894
9895         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9896         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9897
9898         ecore_init_pxp_arb(sc, r_order, w_order);
9899 }
9900
9901 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9902 {
9903         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9904         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9905         return base + (SC_ABS_FUNC(sc)) * stride;
9906 }
9907
9908 /*
9909  * Called only on E1H or E2.
9910  * When pretending to be PF, the pretend value is the function number 0..7.
9911  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9912  * combination.
9913  */
9914 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9915 {
9916         uint32_t pretend_reg;
9917
9918         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9919                 return -1;
9920
9921         /* get my own pretend register */
9922         pretend_reg = bnx2x_get_pretend_reg(sc);
9923         REG_WR(sc, pretend_reg, pretend_func_val);
9924         REG_RD(sc, pretend_reg);
9925         return 0;
9926 }
9927
9928 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9929 {
9930         int is_required;
9931         uint32_t val;
9932         int port;
9933
9934         is_required = 0;
9935         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9936                SHARED_HW_CFG_FAN_FAILURE_MASK);
9937
9938         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9939                 is_required = 1;
9940         }
9941         /*
9942          * The fan failure mechanism is usually related to the PHY type since
9943          * the power consumption of the board is affected by the PHY. Currently,
9944          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9945          */
9946         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9947                 for (port = PORT_0; port < PORT_MAX; port++) {
9948                         is_required |= elink_fan_failure_det_req(sc,
9949                                                                  sc->
9950                                                                  devinfo.shmem_base,
9951                                                                  sc->
9952                                                                  devinfo.shmem2_base,
9953                                                                  port);
9954                 }
9955         }
9956
9957         if (is_required == 0) {
9958                 return;
9959         }
9960
9961         /* Fan failure is indicated by SPIO 5 */
9962         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9963
9964         /* set to active low mode */
9965         val = REG_RD(sc, MISC_REG_SPIO_INT);
9966         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9967         REG_WR(sc, MISC_REG_SPIO_INT, val);
9968
9969         /* enable interrupt to signal the IGU */
9970         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9971         val |= MISC_SPIO_SPIO5;
9972         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9973 }
9974
9975 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9976 {
9977         uint32_t val;
9978
9979         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9980         if (!CHIP_IS_E1x(sc)) {
9981                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9982         } else {
9983                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9984         }
9985         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9986         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9987         /*
9988          * mask read length error interrupts in brb for parser
9989          * (parsing unit and 'checksum and crc' unit)
9990          * these errors are legal (PU reads fixed length and CAC can cause
9991          * read length error on truncated packets)
9992          */
9993         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9994         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9995         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9996         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9997         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9998         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9999         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10000         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10001         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10002         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10003         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10004         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10005         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10006         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10007         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10008         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10009         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10010         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10011         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10012
10013         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10014                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10015                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10016         if (!CHIP_IS_E1x(sc)) {
10017                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10018                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10019         }
10020         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10021
10022         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10023         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10024         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10025         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10026
10027         if (!CHIP_IS_E1x(sc)) {
10028 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10029                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10030         }
10031
10032         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10033         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10034         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10035         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10036 }
10037
10038 /**
10039  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10040  *
10041  * @sc:     driver handle
10042  */
10043 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10044 {
10045         uint8_t abs_func_id;
10046         uint32_t val;
10047
10048         PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10049
10050         /*
10051          * take the RESET lock to protect undi_unload flow from accessing
10052          * registers while we are resetting the chip
10053          */
10054         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10055
10056         bnx2x_reset_common(sc);
10057
10058         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10059
10060         val = 0xfffc;
10061         if (CHIP_IS_E3(sc)) {
10062                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10063                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10064         }
10065
10066         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10067
10068         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10069
10070         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10071
10072         if (!CHIP_IS_E1x(sc)) {
10073 /*
10074  * 4-port mode or 2-port mode we need to turn off master-enable for
10075  * everyone. After that we turn it back on for self. So, we disregard
10076  * multi-function, and always disable all functions on the given path,
10077  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10078  */
10079                 for (abs_func_id = SC_PATH(sc);
10080                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10081                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10082                                 REG_WR(sc,
10083                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10084                                        1);
10085                                 continue;
10086                         }
10087
10088                         bnx2x_pretend_func(sc, abs_func_id);
10089
10090                         /* clear pf enable */
10091                         bnx2x_pf_disable(sc);
10092
10093                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10094                 }
10095         }
10096
10097         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10098
10099         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10100         bnx2x_init_pxp(sc);
10101
10102 #ifdef __BIG_ENDIAN
10103         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10104         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10105         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10106         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10107         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10108         /* make sure this value is 0 */
10109         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10110
10111         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10112         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10113         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10114         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10115         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10116 #endif
10117
10118         ecore_ilt_init_page_size(sc, INITOP_SET);
10119
10120         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10121                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10122         }
10123
10124         /* let the HW do it's magic... */
10125         DELAY(100000);
10126
10127         /* finish PXP init */
10128
10129         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10130         if (val != 1) {
10131                 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10132                 return -1;
10133         }
10134         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10135         if (val != 1) {
10136                 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10137                 return -1;
10138         }
10139
10140         /*
10141          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10142          * entries with value "0" and valid bit on. This needs to be done by the
10143          * first PF that is loaded in a path (i.e. common phase)
10144          */
10145         if (!CHIP_IS_E1x(sc)) {
10146 /*
10147  * In E2 there is a bug in the timers block that can cause function 6 / 7
10148  * (i.e. vnic3) to start even if it is marked as "scan-off".
10149  * This occurs when a different function (func2,3) is being marked
10150  * as "scan-off". Real-life scenario for example: if a driver is being
10151  * load-unloaded while func6,7 are down. This will cause the timer to access
10152  * the ilt, translate to a logical address and send a request to read/write.
10153  * Since the ilt for the function that is down is not valid, this will cause
10154  * a translation error which is unrecoverable.
10155  * The Workaround is intended to make sure that when this happens nothing
10156  * fatal will occur. The workaround:
10157  *  1.  First PF driver which loads on a path will:
10158  *      a.  After taking the chip out of reset, by using pretend,
10159  *          it will write "0" to the following registers of
10160  *          the other vnics.
10161  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10162  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10163  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10164  *          And for itself it will write '1' to
10165  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10166  *          dmae-operations (writing to pram for example.)
10167  *          note: can be done for only function 6,7 but cleaner this
10168  *            way.
10169  *      b.  Write zero+valid to the entire ILT.
10170  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10171  *          VNIC3 (of that port). The range allocated will be the
10172  *          entire ILT. This is needed to prevent  ILT range error.
10173  *  2.  Any PF driver load flow:
10174  *      a.  ILT update with the physical addresses of the allocated
10175  *          logical pages.
10176  *      b.  Wait 20msec. - note that this timeout is needed to make
10177  *          sure there are no requests in one of the PXP internal
10178  *          queues with "old" ILT addresses.
10179  *      c.  PF enable in the PGLC.
10180  *      d.  Clear the was_error of the PF in the PGLC. (could have
10181  *          occurred while driver was down)
10182  *      e.  PF enable in the CFC (WEAK + STRONG)
10183  *      f.  Timers scan enable
10184  *  3.  PF driver unload flow:
10185  *      a.  Clear the Timers scan_en.
10186  *      b.  Polling for scan_on=0 for that PF.
10187  *      c.  Clear the PF enable bit in the PXP.
10188  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10189  *      e.  Write zero+valid to all ILT entries (The valid bit must
10190  *          stay set)
10191  *      f.  If this is VNIC 3 of a port then also init
10192  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10193  *          to the last enrty in the ILT.
10194  *
10195  *      Notes:
10196  *      Currently the PF error in the PGLC is non recoverable.
10197  *      In the future the there will be a recovery routine for this error.
10198  *      Currently attention is masked.
10199  *      Having an MCP lock on the load/unload process does not guarantee that
10200  *      there is no Timer disable during Func6/7 enable. This is because the
10201  *      Timers scan is currently being cleared by the MCP on FLR.
10202  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10203  *      there is error before clearing it. But the flow above is simpler and
10204  *      more general.
10205  *      All ILT entries are written by zero+valid and not just PF6/7
10206  *      ILT entries since in the future the ILT entries allocation for
10207  *      PF-s might be dynamic.
10208  */
10209                 struct ilt_client_info ilt_cli;
10210                 struct ecore_ilt ilt;
10211
10212                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10213                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10214
10215 /* initialize dummy TM client */
10216                 ilt_cli.start = 0;
10217                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10218                 ilt_cli.client_num = ILT_CLIENT_TM;
10219
10220 /*
10221  * Step 1: set zeroes to all ilt page entries with valid bit on
10222  * Step 2: set the timers first/last ilt entry to point
10223  * to the entire range to prevent ILT range error for 3rd/4th
10224  * vnic (this code assumes existence of the vnic)
10225  *
10226  * both steps performed by call to ecore_ilt_client_init_op()
10227  * with dummy TM client
10228  *
10229  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10230  * and his brother are split registers
10231  */
10232
10233                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10234                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10235                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10236
10237                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10238                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10239                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10240         }
10241
10242         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10243         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10244
10245         if (!CHIP_IS_E1x(sc)) {
10246                 int factor = 0;
10247
10248                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10249                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10250
10251 /* let the HW do it's magic... */
10252                 do {
10253                         DELAY(200000);
10254                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10255                 } while (factor-- && (val != 1));
10256
10257                 if (val != 1) {
10258                         PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10259                         return -1;
10260                 }
10261         }
10262
10263         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10264
10265         /* clean the DMAE memory */
10266         sc->dmae_ready = 1;
10267         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10268
10269         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10270
10271         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10272
10273         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10274
10275         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10276
10277         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10278         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10279         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10280         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10281
10282         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10283
10284         /* QM queues pointers table */
10285         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10286
10287         /* soft reset pulse */
10288         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10289         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10290
10291         if (CNIC_SUPPORT(sc))
10292                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10293
10294         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10295         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10296
10297         if (!CHIP_REV_IS_SLOW(sc)) {
10298 /* enable hw interrupt from doorbell Q */
10299                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10300         }
10301
10302         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10303
10304         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10305         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10306         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10307
10308         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10309                 if (IS_MF_AFEX(sc)) {
10310                         /*
10311                          * configure that AFEX and VLAN headers must be
10312                          * received in AFEX mode
10313                          */
10314                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10315                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10316                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10317                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10318                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10319                 } else {
10320                         /*
10321                          * Bit-map indicating which L2 hdrs may appear
10322                          * after the basic Ethernet header
10323                          */
10324                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10325                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10326                 }
10327         }
10328
10329         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10330         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10331         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10332         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10333
10334         if (!CHIP_IS_E1x(sc)) {
10335 /* reset VFC memories */
10336                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10337                        VFC_MEMORIES_RST_REG_CAM_RST |
10338                        VFC_MEMORIES_RST_REG_RAM_RST);
10339                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10340                        VFC_MEMORIES_RST_REG_CAM_RST |
10341                        VFC_MEMORIES_RST_REG_RAM_RST);
10342
10343                 DELAY(20000);
10344         }
10345
10346         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10347         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10348         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10349         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10350
10351         /* sync semi rtc */
10352         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10353         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10354
10355         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10356         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10357         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10358
10359         if (!CHIP_IS_E1x(sc)) {
10360                 if (IS_MF_AFEX(sc)) {
10361                         /*
10362                          * configure that AFEX and VLAN headers must be
10363                          * sent in AFEX mode
10364                          */
10365                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10366                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10367                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10368                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10369                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10370                 } else {
10371                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10372                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10373                 }
10374         }
10375
10376         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10377
10378         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10379
10380         if (CNIC_SUPPORT(sc)) {
10381                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10382                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10383                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10384                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10385                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10386                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10387                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10388                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10389                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10390                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10391         }
10392         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10393
10394         if (sizeof(union cdu_context) != 1024) {
10395 /* we currently assume that a context is 1024 bytes */
10396                 PMD_DRV_LOG(NOTICE,
10397                             "please adjust the size of cdu_context(%ld)",
10398                             (long)sizeof(union cdu_context));
10399         }
10400
10401         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10402         val = (4 << 24) + (0 << 12) + 1024;
10403         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10404
10405         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10406
10407         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10408         /* enable context validation interrupt from CFC */
10409         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10410
10411         /* set the thresholds to prevent CFC/CDU race */
10412         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10413         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10414
10415         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10416                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10417         }
10418
10419         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10420         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10421
10422         /* Reset PCIE errors for debug */
10423         REG_WR(sc, 0x2814, 0xffffffff);
10424         REG_WR(sc, 0x3820, 0xffffffff);
10425
10426         if (!CHIP_IS_E1x(sc)) {
10427                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10428                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10429                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10430                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10431                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10432                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10433                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10434                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10435                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10436                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10437                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10438         }
10439
10440         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10441
10442         /* in E3 this done in per-port section */
10443         if (!CHIP_IS_E3(sc))
10444                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10445
10446         if (CHIP_IS_E1H(sc)) {
10447 /* not applicable for E2 (and above ...) */
10448                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10449         }
10450
10451         if (CHIP_REV_IS_SLOW(sc)) {
10452                 DELAY(200000);
10453         }
10454
10455         /* finish CFC init */
10456         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10457         if (val != 1) {
10458                 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10459                 return -1;
10460         }
10461         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10462         if (val != 1) {
10463                 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10464                 return -1;
10465         }
10466         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10467         if (val != 1) {
10468                 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10469                 return -1;
10470         }
10471         REG_WR(sc, CFC_REG_DEBUG0, 0);
10472
10473         bnx2x_setup_fan_failure_detection(sc);
10474
10475         /* clear PXP2 attentions */
10476         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10477
10478         bnx2x_enable_blocks_attention(sc);
10479
10480         if (!CHIP_REV_IS_SLOW(sc)) {
10481                 ecore_enable_blocks_parity(sc);
10482         }
10483
10484         if (!BNX2X_NOMCP(sc)) {
10485                 if (CHIP_IS_E1x(sc)) {
10486                         bnx2x_common_init_phy(sc);
10487                 }
10488         }
10489
10490         return 0;
10491 }
10492
10493 /**
10494  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10495  *
10496  * @sc:     driver handle
10497  */
10498 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10499 {
10500         int rc = bnx2x_init_hw_common(sc);
10501
10502         if (rc) {
10503                 return rc;
10504         }
10505
10506         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10507         if (!BNX2X_NOMCP(sc)) {
10508                 bnx2x_common_init_phy(sc);
10509         }
10510
10511         return 0;
10512 }
10513
10514 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10515 {
10516         int port = SC_PORT(sc);
10517         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10518         uint32_t low, high;
10519         uint32_t val;
10520
10521         PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10522
10523         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10524
10525         ecore_init_block(sc, BLOCK_MISC, init_phase);
10526         ecore_init_block(sc, BLOCK_PXP, init_phase);
10527         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10528
10529         /*
10530          * Timers bug workaround: disables the pf_master bit in pglue at
10531          * common phase, we need to enable it here before any dmae access are
10532          * attempted. Therefore we manually added the enable-master to the
10533          * port phase (it also happens in the function phase)
10534          */
10535         if (!CHIP_IS_E1x(sc)) {
10536                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10537         }
10538
10539         ecore_init_block(sc, BLOCK_ATC, init_phase);
10540         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10541         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10542         ecore_init_block(sc, BLOCK_QM, init_phase);
10543
10544         ecore_init_block(sc, BLOCK_TCM, init_phase);
10545         ecore_init_block(sc, BLOCK_UCM, init_phase);
10546         ecore_init_block(sc, BLOCK_CCM, init_phase);
10547         ecore_init_block(sc, BLOCK_XCM, init_phase);
10548
10549         /* QM cid (connection) count */
10550         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10551
10552         if (CNIC_SUPPORT(sc)) {
10553                 ecore_init_block(sc, BLOCK_TM, init_phase);
10554                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10555                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10556         }
10557
10558         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10559
10560         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10561
10562         if (CHIP_IS_E1H(sc)) {
10563                 if (IS_MF(sc)) {
10564                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10565                 } else if (sc->mtu > 4096) {
10566                         if (BNX2X_ONE_PORT(sc)) {
10567                                 low = 160;
10568                         } else {
10569                                 val = sc->mtu;
10570                                 /* (24*1024 + val*4)/256 */
10571                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10572                         }
10573                 } else {
10574                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10575                 }
10576                 high = (low + 56);      /* 14*1024/256 */
10577                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10578                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10579         }
10580
10581         if (CHIP_IS_MODE_4_PORT(sc)) {
10582                 REG_WR(sc, SC_PORT(sc) ?
10583                        BRB1_REG_MAC_GUARANTIED_1 :
10584                        BRB1_REG_MAC_GUARANTIED_0, 40);
10585         }
10586
10587         ecore_init_block(sc, BLOCK_PRS, init_phase);
10588         if (CHIP_IS_E3B0(sc)) {
10589                 if (IS_MF_AFEX(sc)) {
10590                         /* configure headers for AFEX mode */
10591                         if (SC_PORT(sc)) {
10592                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10593                                        0xE);
10594                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10595                                        0x6);
10596                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10597                         } else {
10598                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10599                                        0xE);
10600                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10601                                        0x6);
10602                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10603                         }
10604                 } else {
10605                         /* Ovlan exists only if we are in multi-function +
10606                          * switch-dependent mode, in switch-independent there
10607                          * is no ovlan headers
10608                          */
10609                         REG_WR(sc, SC_PORT(sc) ?
10610                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10611                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10612                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10613                 }
10614         }
10615
10616         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10617         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10618         ecore_init_block(sc, BLOCK_USDM, init_phase);
10619         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10620
10621         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10622         ecore_init_block(sc, BLOCK_USEM, init_phase);
10623         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10624         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10625
10626         ecore_init_block(sc, BLOCK_UPB, init_phase);
10627         ecore_init_block(sc, BLOCK_XPB, init_phase);
10628
10629         ecore_init_block(sc, BLOCK_PBF, init_phase);
10630
10631         if (CHIP_IS_E1x(sc)) {
10632 /* configure PBF to work without PAUSE mtu 9000 */
10633                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10634
10635 /* update threshold */
10636                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10637 /* update init credit */
10638                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10639                        (9040 / 16) + 553 - 22);
10640
10641 /* probe changes */
10642                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10643                 DELAY(50);
10644                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10645         }
10646
10647         if (CNIC_SUPPORT(sc)) {
10648                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10649         }
10650
10651         ecore_init_block(sc, BLOCK_CDU, init_phase);
10652         ecore_init_block(sc, BLOCK_CFC, init_phase);
10653         ecore_init_block(sc, BLOCK_HC, init_phase);
10654         ecore_init_block(sc, BLOCK_IGU, init_phase);
10655         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10656         /* init aeu_mask_attn_func_0/1:
10657          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10658          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10659          *             bits 4-7 are used for "per vn group attention" */
10660         val = IS_MF(sc) ? 0xF7 : 0x7;
10661         val |= 0x10;
10662         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10663
10664         ecore_init_block(sc, BLOCK_NIG, init_phase);
10665
10666         if (!CHIP_IS_E1x(sc)) {
10667 /* Bit-map indicating which L2 hdrs may appear after the
10668  * basic Ethernet header
10669  */
10670                 if (IS_MF_AFEX(sc)) {
10671                         REG_WR(sc, SC_PORT(sc) ?
10672                                NIG_REG_P1_HDRS_AFTER_BASIC :
10673                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10674                 } else {
10675                         REG_WR(sc, SC_PORT(sc) ?
10676                                NIG_REG_P1_HDRS_AFTER_BASIC :
10677                                NIG_REG_P0_HDRS_AFTER_BASIC,
10678                                IS_MF_SD(sc) ? 7 : 6);
10679                 }
10680
10681                 if (CHIP_IS_E3(sc)) {
10682                         REG_WR(sc, SC_PORT(sc) ?
10683                                NIG_REG_LLH1_MF_MODE :
10684                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10685                 }
10686         }
10687         if (!CHIP_IS_E3(sc)) {
10688                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10689         }
10690
10691         /* 0x2 disable mf_ov, 0x1 enable */
10692         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10693                (IS_MF_SD(sc) ? 0x1 : 0x2));
10694
10695         if (!CHIP_IS_E1x(sc)) {
10696                 val = 0;
10697                 switch (sc->devinfo.mf_info.mf_mode) {
10698                 case MULTI_FUNCTION_SD:
10699                         val = 1;
10700                         break;
10701                 case MULTI_FUNCTION_SI:
10702                 case MULTI_FUNCTION_AFEX:
10703                         val = 2;
10704                         break;
10705                 }
10706
10707                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10708                             NIG_REG_LLH0_CLS_TYPE), val);
10709         }
10710         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10711         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10712         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10713
10714         /* If SPIO5 is set to generate interrupts, enable it for this port */
10715         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10716         if (val & MISC_SPIO_SPIO5) {
10717                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10718                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10719                 val = REG_RD(sc, reg_addr);
10720                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10721                 REG_WR(sc, reg_addr, val);
10722         }
10723
10724         return 0;
10725 }
10726
10727 static uint32_t
10728 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10729                        uint32_t expected, uint32_t poll_count)
10730 {
10731         uint32_t cur_cnt = poll_count;
10732         uint32_t val;
10733
10734         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10735                 DELAY(FLR_WAIT_INTERVAL);
10736         }
10737
10738         return val;
10739 }
10740
10741 static int
10742 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10743                               __rte_unused const char *msg, uint32_t poll_cnt)
10744 {
10745         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10746
10747         if (val != 0) {
10748                 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10749                 return -1;
10750         }
10751
10752         return 0;
10753 }
10754
10755 /* Common routines with VF FLR cleanup */
10756 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10757 {
10758         /* adjust polling timeout */
10759         if (CHIP_REV_IS_EMUL(sc)) {
10760                 return FLR_POLL_CNT * 2000;
10761         }
10762
10763         if (CHIP_REV_IS_FPGA(sc)) {
10764                 return FLR_POLL_CNT * 120;
10765         }
10766
10767         return FLR_POLL_CNT;
10768 }
10769
10770 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10771 {
10772         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10773         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10774                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10775                                           "CFC PF usage counter timed out",
10776                                           poll_cnt)) {
10777                 return -1;
10778         }
10779
10780         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10781         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10782                                           DORQ_REG_PF_USAGE_CNT,
10783                                           "DQ PF usage counter timed out",
10784                                           poll_cnt)) {
10785                 return -1;
10786         }
10787
10788         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10789         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10790                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10791                                           "QM PF usage counter timed out",
10792                                           poll_cnt)) {
10793                 return -1;
10794         }
10795
10796         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10797         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10798                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10799                                           "Timers VNIC usage counter timed out",
10800                                           poll_cnt)) {
10801                 return -1;
10802         }
10803
10804         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10805                                           TM_REG_LIN0_NUM_SCANS +
10806                                           4 * SC_PORT(sc),
10807                                           "Timers NUM_SCANS usage counter timed out",
10808                                           poll_cnt)) {
10809                 return -1;
10810         }
10811
10812         /* Wait DMAE PF usage counter to zero */
10813         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10814                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10815                                           "DMAE dommand register timed out",
10816                                           poll_cnt)) {
10817                 return -1;
10818         }
10819
10820         return 0;
10821 }
10822
10823 #define OP_GEN_PARAM(param)                                            \
10824         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10825 #define OP_GEN_TYPE(type)                                           \
10826         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10827 #define OP_GEN_AGG_VECT(index)                                             \
10828         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10829
10830 static int
10831 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10832                      uint32_t poll_cnt)
10833 {
10834         uint32_t op_gen_command = 0;
10835         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10836                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10837         int ret = 0;
10838
10839         if (REG_RD(sc, comp_addr)) {
10840                 PMD_DRV_LOG(NOTICE,
10841                             "Cleanup complete was not 0 before sending");
10842                 return -1;
10843         }
10844
10845         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10846         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10847         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10848         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10849
10850         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10851
10852         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10853                 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10854                 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10855                             (REG_RD(sc, comp_addr)));
10856                 rte_panic("FLR cleanup failed");
10857                 return -1;
10858         }
10859
10860         /* Zero completion for nxt FLR */
10861         REG_WR(sc, comp_addr, 0);
10862
10863         return ret;
10864 }
10865
10866 static void
10867 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10868                        uint32_t poll_count)
10869 {
10870         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10871         uint32_t cur_cnt = poll_count;
10872
10873         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10874         crd = crd_start = REG_RD(sc, regs->crd);
10875         init_crd = REG_RD(sc, regs->init_crd);
10876
10877         while ((crd != init_crd) &&
10878                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10879                 (init_crd - crd_start))) {
10880                 if (cur_cnt--) {
10881                         DELAY(FLR_WAIT_INTERVAL);
10882                         crd = REG_RD(sc, regs->crd);
10883                         crd_freed = REG_RD(sc, regs->crd_freed);
10884                 } else {
10885                         break;
10886                 }
10887         }
10888 }
10889
10890 static void
10891 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10892                        uint32_t poll_count)
10893 {
10894         uint32_t occup, to_free, freed, freed_start;
10895         uint32_t cur_cnt = poll_count;
10896
10897         occup = to_free = REG_RD(sc, regs->lines_occup);
10898         freed = freed_start = REG_RD(sc, regs->lines_freed);
10899
10900         while (occup &&
10901                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10902                 to_free)) {
10903                 if (cur_cnt--) {
10904                         DELAY(FLR_WAIT_INTERVAL);
10905                         occup = REG_RD(sc, regs->lines_occup);
10906                         freed = REG_RD(sc, regs->lines_freed);
10907                 } else {
10908                         break;
10909                 }
10910         }
10911 }
10912
10913 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10914 {
10915         struct pbf_pN_cmd_regs cmd_regs[] = {
10916                 {0, (CHIP_IS_E3B0(sc)) ?
10917                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10918                  (CHIP_IS_E3B0(sc)) ?
10919                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10920                 {1, (CHIP_IS_E3B0(sc)) ?
10921                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10922                  (CHIP_IS_E3B0(sc)) ?
10923                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10924                 {4, (CHIP_IS_E3B0(sc)) ?
10925                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10926                  (CHIP_IS_E3B0(sc)) ?
10927                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10928                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10929         };
10930
10931         struct pbf_pN_buf_regs buf_regs[] = {
10932                 {0, (CHIP_IS_E3B0(sc)) ?
10933                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10934                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10935                  (CHIP_IS_E3B0(sc)) ?
10936                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10937                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10938                 {1, (CHIP_IS_E3B0(sc)) ?
10939                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10940                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10941                  (CHIP_IS_E3B0(sc)) ?
10942                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10943                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10944                 {4, (CHIP_IS_E3B0(sc)) ?
10945                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10946                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10947                  (CHIP_IS_E3B0(sc)) ?
10948                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10949                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10950         };
10951
10952         uint32_t i;
10953
10954         /* Verify the command queues are flushed P0, P1, P4 */
10955         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10956                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10957         }
10958
10959         /* Verify the transmission buffers are flushed P0, P1, P4 */
10960         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10961                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10962         }
10963 }
10964
10965 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10966 {
10967         __rte_unused uint32_t val;
10968
10969         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10970         PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10971
10972         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10973         PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10974
10975         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10976         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10977
10978         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10979         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10980
10981         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10982         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10983
10984         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10985         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10986
10987         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10988         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10989
10990         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10991         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10992                     val);
10993 }
10994
10995 /**
10996  *      bnx2x_pf_flr_clnup
10997  *      a. re-enable target read on the PF
10998  *      b. poll cfc per function usgae counter
10999  *      c. poll the qm perfunction usage counter
11000  *      d. poll the tm per function usage counter
11001  *      e. poll the tm per function scan-done indication
11002  *      f. clear the dmae channel associated wit hthe PF
11003  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11004  *      h. call the common flr cleanup code with -1 (pf indication)
11005  */
11006 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11007 {
11008         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11009
11010         /* Re-enable PF target read access */
11011         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11012
11013         /* Poll HW usage counters */
11014         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11015                 return -1;
11016         }
11017
11018         /* Zero the igu 'trailing edge' and 'leading edge' */
11019
11020         /* Send the FW cleanup command */
11021         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11022                 return -1;
11023         }
11024
11025         /* ATC cleanup */
11026
11027         /* Verify TX hw is flushed */
11028         bnx2x_tx_hw_flushed(sc, poll_cnt);
11029
11030         /* Wait 100ms (not adjusted according to platform) */
11031         DELAY(100000);
11032
11033         /* Verify no pending pci transactions */
11034         if (bnx2x_is_pcie_pending(sc)) {
11035                 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11036         }
11037
11038         /* Debug */
11039         bnx2x_hw_enable_status(sc);
11040
11041         /*
11042          * Master enable - Due to WB DMAE writes performed before this
11043          * register is re-initialized as part of the regular function init
11044          */
11045         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11046
11047         return 0;
11048 }
11049
11050 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11051 {
11052         int port = SC_PORT(sc);
11053         int func = SC_FUNC(sc);
11054         int init_phase = PHASE_PF0 + func;
11055         struct ecore_ilt *ilt = sc->ilt;
11056         uint16_t cdu_ilt_start;
11057         uint32_t addr, val;
11058         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11059         int main_mem_width, rc;
11060         uint32_t i;
11061
11062         PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11063
11064         /* FLR cleanup */
11065         if (!CHIP_IS_E1x(sc)) {
11066                 rc = bnx2x_pf_flr_clnup(sc);
11067                 if (rc) {
11068                         PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11069                         return rc;
11070                 }
11071         }
11072
11073         /* set MSI reconfigure capability */
11074         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11075                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11076                 val = REG_RD(sc, addr);
11077                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11078                 REG_WR(sc, addr, val);
11079         }
11080
11081         ecore_init_block(sc, BLOCK_PXP, init_phase);
11082         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11083
11084         ilt = sc->ilt;
11085         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11086
11087         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11088                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11089                 ilt->lines[cdu_ilt_start + i].page_mapping =
11090                     (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11091                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11092         }
11093         ecore_ilt_init_op(sc, INITOP_SET);
11094
11095         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11096
11097         if (!CHIP_IS_E1x(sc)) {
11098                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11099
11100 /* Turn on a single ISR mode in IGU if driver is going to use
11101  * INT#x or MSI
11102  */
11103                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11104                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11105                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11106                 }
11107
11108 /*
11109  * Timers workaround bug: function init part.
11110  * Need to wait 20msec after initializing ILT,
11111  * needed to make sure there are no requests in
11112  * one of the PXP internal queues with "old" ILT addresses
11113  */
11114                 DELAY(20000);
11115
11116 /*
11117  * Master enable - Due to WB DMAE writes performed before this
11118  * register is re-initialized as part of the regular function
11119  * init
11120  */
11121                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11122 /* Enable the function in IGU */
11123                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11124         }
11125
11126         sc->dmae_ready = 1;
11127
11128         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11129
11130         if (!CHIP_IS_E1x(sc))
11131                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11132
11133         ecore_init_block(sc, BLOCK_ATC, init_phase);
11134         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11135         ecore_init_block(sc, BLOCK_NIG, init_phase);
11136         ecore_init_block(sc, BLOCK_SRC, init_phase);
11137         ecore_init_block(sc, BLOCK_MISC, init_phase);
11138         ecore_init_block(sc, BLOCK_TCM, init_phase);
11139         ecore_init_block(sc, BLOCK_UCM, init_phase);
11140         ecore_init_block(sc, BLOCK_CCM, init_phase);
11141         ecore_init_block(sc, BLOCK_XCM, init_phase);
11142         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11143         ecore_init_block(sc, BLOCK_USEM, init_phase);
11144         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11145         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11146
11147         if (!CHIP_IS_E1x(sc))
11148                 REG_WR(sc, QM_REG_PF_EN, 1);
11149
11150         if (!CHIP_IS_E1x(sc)) {
11151                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11152                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11153                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11154                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11155         }
11156         ecore_init_block(sc, BLOCK_QM, init_phase);
11157
11158         ecore_init_block(sc, BLOCK_TM, init_phase);
11159         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11160
11161         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11162         ecore_init_block(sc, BLOCK_PRS, init_phase);
11163         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11164         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11165         ecore_init_block(sc, BLOCK_USDM, init_phase);
11166         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11167         ecore_init_block(sc, BLOCK_UPB, init_phase);
11168         ecore_init_block(sc, BLOCK_XPB, init_phase);
11169         ecore_init_block(sc, BLOCK_PBF, init_phase);
11170         if (!CHIP_IS_E1x(sc))
11171                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11172
11173         ecore_init_block(sc, BLOCK_CDU, init_phase);
11174
11175         ecore_init_block(sc, BLOCK_CFC, init_phase);
11176
11177         if (!CHIP_IS_E1x(sc))
11178                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11179
11180         if (IS_MF(sc)) {
11181                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11182                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11183         }
11184
11185         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11186
11187         /* HC init per function */
11188         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11189                 if (CHIP_IS_E1H(sc)) {
11190                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11191
11192                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11193                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11194                 }
11195                 ecore_init_block(sc, BLOCK_HC, init_phase);
11196
11197         } else {
11198                 uint32_t num_segs, sb_idx, prod_offset;
11199
11200                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11201
11202                 if (!CHIP_IS_E1x(sc)) {
11203                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11204                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11205                 }
11206
11207                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11208
11209                 if (!CHIP_IS_E1x(sc)) {
11210                         int dsb_idx = 0;
11211         /**
11212          * Producer memory:
11213          * E2 mode: address 0-135 match to the mapping memory;
11214          * 136 - PF0 default prod; 137 - PF1 default prod;
11215          * 138 - PF2 default prod; 139 - PF3 default prod;
11216          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11217          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11218          * 144-147 reserved.
11219          *
11220          * E1.5 mode - In backward compatible mode;
11221          * for non default SB; each even line in the memory
11222          * holds the U producer and each odd line hold
11223          * the C producer. The first 128 producers are for
11224          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11225          * producers are for the DSB for each PF.
11226          * Each PF has five segments: (the order inside each
11227          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11228          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11229          * 144-147 attn prods;
11230          */
11231                         /* non-default-status-blocks */
11232                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11233                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11234                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11235                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11236                                     num_segs;
11237
11238                                 for (i = 0; i < num_segs; i++) {
11239                                         addr = IGU_REG_PROD_CONS_MEMORY +
11240                                             (prod_offset + i) * 4;
11241                                         REG_WR(sc, addr, 0);
11242                                 }
11243                                 /* send consumer update with value 0 */
11244                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11245                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11246                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11247                         }
11248
11249                         /* default-status-blocks */
11250                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11251                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11252
11253                         if (CHIP_IS_MODE_4_PORT(sc))
11254                                 dsb_idx = SC_FUNC(sc);
11255                         else
11256                                 dsb_idx = SC_VN(sc);
11257
11258                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11259                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11260                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11261
11262                         /*
11263                          * igu prods come in chunks of E1HVN_MAX (4) -
11264                          * does not matters what is the current chip mode
11265                          */
11266                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11267                                 addr = IGU_REG_PROD_CONS_MEMORY +
11268                                     (prod_offset + i) * 4;
11269                                 REG_WR(sc, addr, 0);
11270                         }
11271                         /* send consumer update with 0 */
11272                         if (CHIP_INT_MODE_IS_BC(sc)) {
11273                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11274                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11275                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11276                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11277                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11278                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11279                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11280                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11281                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11282                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11283                         } else {
11284                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11285                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11286                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11287                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11288                         }
11289                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11290
11291                         /* !!! these should become driver const once
11292                            rf-tool supports split-68 const */
11293                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11294                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11295                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11296                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11297                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11298                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11299                 }
11300         }
11301
11302         /* Reset PCIE errors for debug */
11303         REG_WR(sc, 0x2114, 0xffffffff);
11304         REG_WR(sc, 0x2120, 0xffffffff);
11305
11306         if (CHIP_IS_E1x(sc)) {
11307                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11308                 main_mem_base = HC_REG_MAIN_MEMORY +
11309                     SC_PORT(sc) * (main_mem_size * 4);
11310                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11311                 main_mem_width = 8;
11312
11313                 val = REG_RD(sc, main_mem_prty_clr);
11314                 if (val) {
11315                         PMD_DRV_LOG(DEBUG,
11316                                     "Parity errors in HC block during function init (0x%x)!",
11317                                     val);
11318                 }
11319
11320 /* Clear "false" parity errors in MSI-X table */
11321                 for (i = main_mem_base;
11322                      i < main_mem_base + main_mem_size * 4;
11323                      i += main_mem_width) {
11324                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11325                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11326                                        i, main_mem_width / 4);
11327                 }
11328 /* Clear HC parity attention */
11329                 REG_RD(sc, main_mem_prty_clr);
11330         }
11331
11332         /* Enable STORMs SP logging */
11333         REG_WR8(sc, BAR_USTRORM_INTMEM +
11334                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11335         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11336                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11337         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11338                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11339         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11340                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11341
11342         elink_phy_probe(&sc->link_params);
11343
11344         return 0;
11345 }
11346
11347 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11348 {
11349         if (!BNX2X_NOMCP(sc)) {
11350                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11351         } else {
11352                 if (!CHIP_REV_IS_SLOW(sc)) {
11353                         PMD_DRV_LOG(WARNING,
11354                                     "Bootcode is missing - cannot reset link");
11355                 }
11356         }
11357 }
11358
11359 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11360 {
11361         int port = SC_PORT(sc);
11362         uint32_t val;
11363
11364         /* reset physical Link */
11365         bnx2x_link_reset(sc);
11366
11367         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11368
11369         /* Do not rcv packets to BRB */
11370         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11371         /* Do not direct rcv packets that are not for MCP to the BRB */
11372         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11373                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11374
11375         /* Configure AEU */
11376         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11377
11378         DELAY(100000);
11379
11380         /* Check for BRB port occupancy */
11381         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11382         if (val) {
11383                 PMD_DRV_LOG(DEBUG,
11384                             "BRB1 is not empty, %d blocks are occupied", val);
11385         }
11386 }
11387
11388 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11389 {
11390         int reg;
11391         uint32_t wb_write[2];
11392
11393         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11394
11395         wb_write[0] = ONCHIP_ADDR1(addr);
11396         wb_write[1] = ONCHIP_ADDR2(addr);
11397         REG_WR_DMAE(sc, reg, wb_write, 2);
11398 }
11399
11400 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11401 {
11402         uint32_t i, base = FUNC_ILT_BASE(func);
11403         for (i = base; i < base + ILT_PER_FUNC; i++) {
11404                 bnx2x_ilt_wr(sc, i, 0);
11405         }
11406 }
11407
11408 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11409 {
11410         struct bnx2x_fastpath *fp;
11411         int port = SC_PORT(sc);
11412         int func = SC_FUNC(sc);
11413         int i;
11414
11415         /* Disable the function in the FW */
11416         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11417         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11418         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11419         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11420
11421         /* FP SBs */
11422         FOR_EACH_ETH_QUEUE(sc, i) {
11423                 fp = &sc->fp[i];
11424                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11425                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11426                         SB_DISABLED);
11427         }
11428
11429         /* SP SB */
11430         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11431                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11432
11433         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11434                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11435                        0);
11436         }
11437
11438         /* Configure IGU */
11439         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11440                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11441                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11442         } else {
11443                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11444                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11445         }
11446
11447         if (CNIC_LOADED(sc)) {
11448 /* Disable Timer scan */
11449                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11450 /*
11451  * Wait for at least 10ms and up to 2 second for the timers
11452  * scan to complete
11453  */
11454                 for (i = 0; i < 200; i++) {
11455                         DELAY(10000);
11456                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11457                                 break;
11458                 }
11459         }
11460
11461         /* Clear ILT */
11462         bnx2x_clear_func_ilt(sc, func);
11463
11464         /*
11465          * Timers workaround bug for E2: if this is vnic-3,
11466          * we need to set the entire ilt range for this timers.
11467          */
11468         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11469                 struct ilt_client_info ilt_cli;
11470 /* use dummy TM client */
11471                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11472                 ilt_cli.start = 0;
11473                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11474                 ilt_cli.client_num = ILT_CLIENT_TM;
11475
11476                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11477         }
11478
11479         /* this assumes that reset_port() called before reset_func() */
11480         if (!CHIP_IS_E1x(sc)) {
11481                 bnx2x_pf_disable(sc);
11482         }
11483
11484         sc->dmae_ready = 0;
11485 }
11486
11487 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11488 {
11489         rte_free(sc->init_ops);
11490         rte_free(sc->init_ops_offsets);
11491         rte_free(sc->init_data);
11492         rte_free(sc->iro_array);
11493 }
11494
11495 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11496 {
11497         uint32_t len, i;
11498         uint8_t *p = sc->firmware;
11499         uint32_t off[24];
11500
11501         for (i = 0; i < 24; ++i)
11502                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11503
11504         len = off[0];
11505         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11506         if (!sc->init_ops)
11507                 goto alloc_failed;
11508         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11509
11510         len = off[2];
11511         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11512         if (!sc->init_ops_offsets)
11513                 goto alloc_failed;
11514         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11515
11516         len = off[4];
11517         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11518         if (!sc->init_data)
11519                 goto alloc_failed;
11520         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11521
11522         sc->tsem_int_table_data = p + off[7];
11523         sc->tsem_pram_data = p + off[9];
11524         sc->usem_int_table_data = p + off[11];
11525         sc->usem_pram_data = p + off[13];
11526         sc->csem_int_table_data = p + off[15];
11527         sc->csem_pram_data = p + off[17];
11528         sc->xsem_int_table_data = p + off[19];
11529         sc->xsem_pram_data = p + off[21];
11530
11531         len = off[22];
11532         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11533         if (!sc->iro_array)
11534                 goto alloc_failed;
11535         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11536
11537         return 0;
11538
11539 alloc_failed:
11540         bnx2x_release_firmware(sc);
11541         return -1;
11542 }
11543
11544 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11545 {
11546 #define MIN_PREFIX_SIZE (10)
11547
11548         int n = MIN_PREFIX_SIZE;
11549         uint16_t xlen;
11550
11551         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11552             len <= MIN_PREFIX_SIZE) {
11553                 return -1;
11554         }
11555
11556         /* optional extra fields are present */
11557         if (zbuf[3] & 0x4) {
11558                 xlen = zbuf[13];
11559                 xlen <<= 8;
11560                 xlen += zbuf[12];
11561
11562                 n += xlen;
11563         }
11564         /* file name is present */
11565         if (zbuf[3] & 0x8) {
11566                 while ((zbuf[n++] != 0) && (n < len)) ;
11567         }
11568
11569         return n;
11570 }
11571
11572 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11573 {
11574         int ret;
11575         int data_begin = cut_gzip_prefix(zbuf, len);
11576
11577         PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11578
11579         if (data_begin <= 0) {
11580                 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11581                 return -1;
11582         }
11583
11584         memset(&zlib_stream, 0, sizeof(zlib_stream));
11585         zlib_stream.next_in = zbuf + data_begin;
11586         zlib_stream.avail_in = len - data_begin;
11587         zlib_stream.next_out = sc->gz_buf;
11588         zlib_stream.avail_out = FW_BUF_SIZE;
11589
11590         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11591         if (ret != Z_OK) {
11592                 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11593                 return ret;
11594         }
11595
11596         ret = inflate(&zlib_stream, Z_FINISH);
11597         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11598                 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11599                             zlib_stream.msg);
11600         }
11601
11602         sc->gz_outlen = zlib_stream.total_out;
11603         if (sc->gz_outlen & 0x3) {
11604                 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11605                             sc->gz_outlen);
11606         }
11607         sc->gz_outlen >>= 2;
11608
11609         inflateEnd(&zlib_stream);
11610
11611         if (ret == Z_STREAM_END)
11612                 return 0;
11613
11614         return ret;
11615 }
11616
11617 static void
11618 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11619                           uint32_t addr, uint32_t len)
11620 {
11621         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11622 }
11623
11624 void
11625 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11626                           uint32_t * data)
11627 {
11628         uint8_t i;
11629         for (i = 0; i < size / 4; i++) {
11630                 REG_WR(sc, addr + (i * 4), data[i]);
11631         }
11632 }
11633
11634 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11635 {
11636         uint32_t phy_type_idx = ext_phy_type >> 8;
11637         static const char *types[] =
11638             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11639                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11640                 "BNX2X-8727",
11641                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11642         };
11643
11644         if (phy_type_idx < 12)
11645                 return types[phy_type_idx];
11646         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11647                 return types[12];
11648         else
11649                 return types[13];
11650 }
11651
11652 static const char *get_state(uint32_t state)
11653 {
11654         uint32_t state_idx = state >> 12;
11655         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11656                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11657                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11658                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11659                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11660         };
11661
11662         if (state_idx <= 0xF)
11663                 return states[state_idx];
11664         else
11665                 return states[0x10];
11666 }
11667
11668 static const char *get_recovery_state(uint32_t state)
11669 {
11670         static const char *states[] = { "NONE", "DONE", "INIT",
11671                 "WAIT", "FAILED", "NIC_LOADING"
11672         };
11673         return states[state];
11674 }
11675
11676 static const char *get_rx_mode(uint32_t mode)
11677 {
11678         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11679                 "PROMISC", "MAX_MULTICAST", "ERROR"
11680         };
11681
11682         if (mode < 0x4)
11683                 return modes[mode];
11684         else if (BNX2X_MAX_MULTICAST == mode)
11685                 return modes[4];
11686         else
11687                 return modes[5];
11688 }
11689
11690 #define BNX2X_INFO_STR_MAX 256
11691 static const char *get_bnx2x_flags(uint32_t flags)
11692 {
11693         int i;
11694         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11695                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11696                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11697                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11698         };
11699         static char flag_str[BNX2X_INFO_STR_MAX];
11700         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11701
11702         for (i = 0; i < 5; i++)
11703                 if (flags & (1 << i)) {
11704                         strcat(flag_str, flag[i]);
11705                         flags ^= (1 << i);
11706                 }
11707         if (flags) {
11708                 static char unknown[BNX2X_INFO_STR_MAX];
11709                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11710                 strcat(flag_str, unknown);
11711         }
11712         return flag_str;
11713 }
11714
11715 /*
11716  * Prints useful adapter info.
11717  */
11718 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11719 {
11720         int i = 0;
11721         __rte_unused uint32_t ext_phy_type;
11722
11723         PMD_INIT_FUNC_TRACE();
11724         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11725                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11726                                                               sc->
11727                                                               devinfo.shmem_base
11728                                                               + offsetof(struct
11729                                                                          shmem_region,
11730                                                                          dev_info.port_hw_config
11731                                                                          [0].external_phy_config)));
11732         else
11733                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11734                                                                 sc->
11735                                                                 devinfo.shmem_base
11736                                                                 +
11737                                                                 offsetof(struct
11738                                                                          shmem_region,
11739                                                                          dev_info.port_hw_config
11740                                                                          [0].external_phy_config)));
11741
11742         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11743         /* Hardware chip info. */
11744         PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11745         PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11746                      (CHIP_METAL(sc) >> 4));
11747
11748         /* Bus info. */
11749         PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11750         switch (sc->devinfo.pcie_link_speed) {
11751         case 1:
11752                 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11753                 break;
11754         case 2:
11755                 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11756                 break;
11757         case 4:
11758                 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11759                 break;
11760         default:
11761                 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11762         }
11763
11764         /* Device features. */
11765         PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11766
11767         /* Miscellaneous flags. */
11768         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11769                 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11770                 i++;
11771         }
11772
11773         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11774                 if (i > 0)
11775                         PMD_INIT_LOG(DEBUG, "|");
11776                 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11777                 i++;
11778         }
11779
11780         if (IS_PF(sc)) {
11781                 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11782                 switch (sc->sp->rss_rdata.rss_mode) {
11783                 case ETH_RSS_MODE_DISABLED:
11784                         PMD_INIT_LOG(DEBUG, "%19s", "None");
11785                         break;
11786                 case ETH_RSS_MODE_REGULAR:
11787                         PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11788                         break;
11789                 default:
11790                         PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11791                         break;
11792                 }
11793         }
11794
11795         /* RTE and Driver versions */
11796         PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11797                      rte_version());
11798         PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11799                      bnx2x_pmd_version());
11800
11801         /* Firmware versions and device features. */
11802         PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11803                      "Firmware",
11804                      BNX2X_5710_FW_MAJOR_VERSION,
11805                      BNX2X_5710_FW_MINOR_VERSION,
11806                      BNX2X_5710_FW_REVISION_VERSION);
11807         PMD_INIT_LOG(DEBUG, "%12s : %s",
11808                      "Bootcode", sc->devinfo.bc_ver_str);
11809
11810         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11811         PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11812         PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11813         PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11814                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11815         PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11816         PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11817         PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11818         PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11819         PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11820                         sc->link_params.mac_addr[0],
11821                         sc->link_params.mac_addr[1],
11822                         sc->link_params.mac_addr[2],
11823                         sc->link_params.mac_addr[3],
11824                         sc->link_params.mac_addr[4],
11825                         sc->link_params.mac_addr[5]);
11826         PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11827         PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11828         if (sc->recovery_state)
11829                 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11830                              get_recovery_state(sc->recovery_state));
11831         PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11832                      sc->cq_spq_left, sc->eq_spq_left);
11833         PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11834         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11835 }