drivers/net/bnx2x/bnx2x.c

   1 /*-
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015 QLogic Corporation.
  10  * All rights reserved.
  11  * www.qlogic.com
  12  *
  13  * See LICENSE.bnx2x_pmd for copyright and licensing details.
  14  */
  15
  16 #define BNX2X_DRIVER_VERSION "1.78.18"
  17
  18 #include "bnx2x.h"
  19 #include "bnx2x_vfpf.h"
  20 #include "ecore_sp.h"
  21 #include "ecore_init.h"
  22 #include "ecore_init_ops.h"
  23
  24 #include "rte_version.h"
  25
  26 #include <sys/types.h>
  27 #include <sys/stat.h>
  28 #include <fcntl.h>
  29 #include <zlib.h>
  30
  31 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  32 #define BNX2X_PMD_VERSION_MAJOR 1
  33 #define BNX2X_PMD_VERSION_MINOR 0
  34 #define BNX2X_PMD_VERSION_REVISION 5
  35 #define BNX2X_PMD_VERSION_PATCH 1
  36
  37 #ifdef RTE_LIBRTE_BNX2X_DEBUG
  38 static inline const char *
  39 bnx2x_pmd_version(void)
  40 {
  41         static char version[32];
  42
  43         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  44                         BNX2X_PMD_VER_PREFIX,
  45                         BNX2X_DRIVER_VERSION,
  46                         BNX2X_PMD_VERSION_MAJOR,
  47                         BNX2X_PMD_VERSION_MINOR,
  48                         BNX2X_PMD_VERSION_REVISION,
  49                         BNX2X_PMD_VERSION_PATCH);
  50
  51         return version;
  52 }
  53 #endif
  54
  55 static z_stream zlib_stream;
  56
  57 #define EVL_VLID_MASK 0x0FFF
  58
  59 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  60 #define BNX2X_DEF_SB_IDX     0x0002
  61
  62 /*
  63  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  64  * function HW initialization.
  65  */
  66 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  67 #define FLR_WAIT_INTERVAL 50    /* usecs */
  68 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  69
  70 struct pbf_pN_buf_regs {
  71         int pN;
  72         uint32_t init_crd;
  73         uint32_t crd;
  74         uint32_t crd_freed;
  75 };
  76
  77 struct pbf_pN_cmd_regs {
  78         int pN;
  79         uint32_t lines_occup;
  80         uint32_t lines_freed;
  81 };
  82
  83 /* resources needed for unloading a previously loaded device */
  84
  85 #define BNX2X_PREV_WAIT_NEEDED 1
  86 rte_spinlock_t bnx2x_prev_mtx;
  87 struct bnx2x_prev_list_node {
  88         LIST_ENTRY(bnx2x_prev_list_node) node;
  89         uint8_t bus;
  90         uint8_t slot;
  91         uint8_t path;
  92         uint8_t aer;
  93         uint8_t undi;
  94 };
  95
  96 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  97         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  98
  99 static int load_count[2][3] = { { 0 } };
 100         /* per-path: 0-common, 1-port0, 2-port1 */
 101
 102 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 103                                 uint8_t cmng_type);
 104 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 105 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 106                               uint8_t port);
 107 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 108 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 109 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 110 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 111 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 112                                      uint8_t print);
 113 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 114 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 115 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 116 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 117                                  struct bnx2x_fastpath *fp,
 118                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 119 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
 120 static void bnx2x_link_report(struct bnx2x_softc *sc);
 121 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 122 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 123 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 124 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 125 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 126 static __rte_noinline
 127 int bnx2x_nic_load(struct bnx2x_softc *sc);
 128
 129 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 130 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 131 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 132                          uint8_t storm, uint16_t index, uint8_t op,
 133                          uint8_t update);
 134
 135 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 136 {
 137         int res;
 138
 139         mb();
 140         res = ((*addr) & (1UL << nr)) != 0;
 141         mb();
 142         return res;
 143 }
 144
 145 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 146 {
 147         __sync_fetch_and_or(addr, (1UL << nr));
 148 }
 149
 150 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 151 {
 152         __sync_fetch_and_and(addr, ~(1UL << nr));
 153 }
 154
 155 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 156 {
 157         unsigned long mask = (1UL << nr);
 158         return __sync_fetch_and_and(addr, ~mask) & mask;
 159 }
 160
 161 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 162 {
 163         return __sync_val_compare_and_swap(addr, old, new);
 164 }
 165
 166 int
 167 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 168               const char *msg, uint32_t align)
 169 {
 170         char mz_name[RTE_MEMZONE_NAMESIZE];
 171         const struct rte_memzone *z;
 172
 173         dma->sc = sc;
 174         if (IS_PF(sc))
 175                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 176                         rte_get_timer_cycles());
 177         else
 178                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 179                         rte_get_timer_cycles());
 180
 181         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 182         z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
 183                                         SOCKET_ID_ANY,
 184                                         0, align);
 185         if (z == NULL) {
 186                 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
 187                 return -ENOMEM;
 188         }
 189         dma->paddr = (uint64_t) z->iova;
 190         dma->vaddr = z->addr;
 191
 192         PMD_DRV_LOG(DEBUG, sc,
 193                     "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 194
 195         return 0;
 196 }
 197
 198 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 199 {
 200         uint32_t lock_status;
 201         uint32_t resource_bit = (1 << resource);
 202         int func = SC_FUNC(sc);
 203         uint32_t hw_lock_control_reg;
 204         int cnt;
 205
 206 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 207         if (resource)
 208                 PMD_INIT_FUNC_TRACE(sc);
 209 #else
 210         PMD_INIT_FUNC_TRACE(sc);
 211 #endif
 212
 213         /* validate the resource is within range */
 214         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 215                 PMD_DRV_LOG(NOTICE, sc,
 216                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 217                             resource);
 218                 return -1;
 219         }
 220
 221         if (func <= 5) {
 222                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 223         } else {
 224                 hw_lock_control_reg =
 225                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 226         }
 227
 228         /* validate the resource is not already taken */
 229         lock_status = REG_RD(sc, hw_lock_control_reg);
 230         if (lock_status & resource_bit) {
 231                 PMD_DRV_LOG(NOTICE, sc,
 232                             "resource in use (status 0x%x bit 0x%x)",
 233                             lock_status, resource_bit);
 234                 return -1;
 235         }
 236
 237         /* try every 5ms for 5 seconds */
 238         for (cnt = 0; cnt < 1000; cnt++) {
 239                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 240                 lock_status = REG_RD(sc, hw_lock_control_reg);
 241                 if (lock_status & resource_bit) {
 242                         return 0;
 243                 }
 244                 DELAY(5000);
 245         }
 246
 247         PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
 248                     resource, resource_bit);
 249         return -1;
 250 }
 251
 252 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 253 {
 254         uint32_t lock_status;
 255         uint32_t resource_bit = (1 << resource);
 256         int func = SC_FUNC(sc);
 257         uint32_t hw_lock_control_reg;
 258
 259 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
 260         if (resource)
 261                 PMD_INIT_FUNC_TRACE(sc);
 262 #else
 263         PMD_INIT_FUNC_TRACE(sc);
 264 #endif
 265
 266         /* validate the resource is within range */
 267         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 268                 PMD_DRV_LOG(NOTICE, sc,
 269                             "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
 270                             " resource_bit 0x%x", resource, resource_bit);
 271                 return -1;
 272         }
 273
 274         if (func <= 5) {
 275                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 276         } else {
 277                 hw_lock_control_reg =
 278                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 279         }
 280
 281         /* validate the resource is currently taken */
 282         lock_status = REG_RD(sc, hw_lock_control_reg);
 283         if (!(lock_status & resource_bit)) {
 284                 PMD_DRV_LOG(NOTICE, sc,
 285                             "resource not in use (status 0x%x bit 0x%x)",
 286                             lock_status, resource_bit);
 287                 return -1;
 288         }
 289
 290         REG_WR(sc, hw_lock_control_reg, resource_bit);
 291         return 0;
 292 }
 293
 294 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
 295 {
 296         BNX2X_PHY_LOCK(sc);
 297         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 298 }
 299
 300 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
 301 {
 302         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
 303         BNX2X_PHY_UNLOCK(sc);
 304 }
 305
 306 /* copy command into DMAE command memory and set DMAE command Go */
 307 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 308 {
 309         uint32_t cmd_offset;
 310         uint32_t i;
 311
 312         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 313         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 314                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 315         }
 316
 317         REG_WR(sc, dmae_reg_go_c[idx], 1);
 318 }
 319
 320 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 321 {
 322         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 323                           DMAE_COMMAND_C_TYPE_ENABLE);
 324 }
 325
 326 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 327 {
 328         return opcode & ~DMAE_COMMAND_SRC_RESET;
 329 }
 330
 331 uint32_t
 332 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 333                 uint8_t with_comp, uint8_t comp_type)
 334 {
 335         uint32_t opcode = 0;
 336
 337         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 338                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 339
 340         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 341
 342         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 343
 344         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 345                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 346
 347         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 348
 349 #ifdef __BIG_ENDIAN
 350         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 351 #else
 352         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 353 #endif
 354
 355         if (with_comp) {
 356                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 357         }
 358
 359         return opcode;
 360 }
 361
 362 static void
 363 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 364                         uint8_t src_type, uint8_t dst_type)
 365 {
 366         memset(dmae, 0, sizeof(struct dmae_command));
 367
 368         /* set the opcode */
 369         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 370                                        TRUE, DMAE_COMP_PCI);
 371
 372         /* fill in the completion parameters */
 373         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 374         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 375         dmae->comp_val = DMAE_COMP_VAL;
 376 }
 377
 378 /* issue a DMAE command over the init channel and wait for completion */
 379 static int
 380 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 381 {
 382         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 383         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 384
 385         /* reset completion */
 386         *wb_comp = 0;
 387
 388         /* post the command on the channel used for initializations */
 389         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 390
 391         /* wait for completion */
 392         DELAY(500);
 393
 394         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 395                 if (!timeout ||
 396                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 397                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 398                         PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
 399                         return DMAE_TIMEOUT;
 400                 }
 401
 402                 timeout--;
 403                 DELAY(50);
 404         }
 405
 406         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 407                 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
 408                 return DMAE_PCI_ERROR;
 409         }
 410
 411         return 0;
 412 }
 413
 414 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 415 {
 416         struct dmae_command dmae;
 417         uint32_t *data;
 418         uint32_t i;
 419         int rc;
 420
 421         if (!sc->dmae_ready) {
 422                 data = BNX2X_SP(sc, wb_data[0]);
 423
 424                 for (i = 0; i < len32; i++) {
 425                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 426                 }
 427
 428                 return;
 429         }
 430
 431         /* set opcode and fixed command fields */
 432         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 433
 434         /* fill in addresses and len */
 435         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 436         dmae.src_addr_hi = 0;
 437         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 438         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 439         dmae.len = len32;
 440
 441         /* issue the command and wait for completion */
 442         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 443                 rte_panic("DMAE failed (%d)", rc);
 444         };
 445 }
 446
 447 void
 448 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 449                uint32_t len32)
 450 {
 451         struct dmae_command dmae;
 452         int rc;
 453
 454         if (!sc->dmae_ready) {
 455                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 456                 return;
 457         }
 458
 459         /* set opcode and fixed command fields */
 460         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 461
 462         /* fill in addresses and len */
 463         dmae.src_addr_lo = U64_LO(dma_addr);
 464         dmae.src_addr_hi = U64_HI(dma_addr);
 465         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 466         dmae.dst_addr_hi = 0;
 467         dmae.len = len32;
 468
 469         /* issue the command and wait for completion */
 470         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 471                 rte_panic("DMAE failed (%d)", rc);
 472         }
 473 }
 474
 475 static void
 476 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 477                         uint32_t addr, uint32_t len)
 478 {
 479         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 480         uint32_t offset = 0;
 481
 482         while (len > dmae_wr_max) {
 483                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 484                                (addr + offset), /* dst GRC address */
 485                                dmae_wr_max);
 486                 offset += (dmae_wr_max * 4);
 487                 len -= dmae_wr_max;
 488         }
 489
 490         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 491                        (addr + offset), /* dst GRC address */
 492                        len);
 493 }
 494
 495 void
 496 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 497                        uint32_t cid)
 498 {
 499         /* ustorm cxt validation */
 500         cxt->ustorm_ag_context.cdu_usage =
 501             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 502                                    CDU_REGION_NUMBER_UCM_AG,
 503                                    ETH_CONNECTION_TYPE);
 504         /* xcontext validation */
 505         cxt->xstorm_ag_context.cdu_reserved =
 506             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 507                                    CDU_REGION_NUMBER_XCM_AG,
 508                                    ETH_CONNECTION_TYPE);
 509 }
 510
 511 static void
 512 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 513                             uint8_t sb_index, uint8_t ticks)
 514 {
 515         uint32_t addr =
 516             (BAR_CSTRORM_INTMEM +
 517              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 518
 519         REG_WR8(sc, addr, ticks);
 520 }
 521
 522 static void
 523 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 524                             uint8_t sb_index, uint8_t disable)
 525 {
 526         uint32_t enable_flag =
 527             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 528         uint32_t addr =
 529             (BAR_CSTRORM_INTMEM +
 530              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 531         uint8_t flags;
 532
 533         /* clear and set */
 534         flags = REG_RD8(sc, addr);
 535         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 536         flags |= enable_flag;
 537         REG_WR8(sc, addr, flags);
 538 }
 539
 540 void
 541 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 542                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 543 {
 544         uint8_t ticks = (usec / 4);
 545
 546         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 547
 548         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 549         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 550 }
 551
 552 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 553 {
 554         return REG_RD(sc, reg_addr);
 555 }
 556
 557 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 558 {
 559         REG_WR(sc, reg_addr, val);
 560 }
 561
 562 void
 563 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 564                    __rte_unused const elink_log_id_t elink_log_id, ...)
 565 {
 566         PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
 567 }
 568
 569 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 570 {
 571         uint32_t spio_reg;
 572
 573         /* Only 2 SPIOs are configurable */
 574         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 575                 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
 576                 return -1;
 577         }
 578
 579         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 580
 581         /* read SPIO and mask except the float bits */
 582         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 583
 584         switch (mode) {
 585         case MISC_SPIO_OUTPUT_LOW:
 586                 /* clear FLOAT and set CLR */
 587                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 588                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 589                 break;
 590
 591         case MISC_SPIO_OUTPUT_HIGH:
 592                 /* clear FLOAT and set SET */
 593                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 594                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 595                 break;
 596
 597         case MISC_SPIO_INPUT_HI_Z:
 598                 /* set FLOAT */
 599                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 600                 break;
 601
 602         default:
 603                 break;
 604         }
 605
 606         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 607         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 608
 609         return 0;
 610 }
 611
 612 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 613 {
 614         /* The GPIO should be swapped if swap register is set and active */
 615         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 616                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 617         int gpio_shift = gpio_num;
 618         if (gpio_port)
 619                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 620
 621         uint32_t gpio_mask = (1 << gpio_shift);
 622         uint32_t gpio_reg;
 623
 624         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 625                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 626                 return -1;
 627         }
 628
 629         /* read GPIO value */
 630         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 631
 632         /* get the requested pin value */
 633         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 634 }
 635
 636 static int
 637 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 638 {
 639         /* The GPIO should be swapped if swap register is set and active */
 640         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 641                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 642         int gpio_shift = gpio_num;
 643         if (gpio_port)
 644                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 645
 646         uint32_t gpio_mask = (1 << gpio_shift);
 647         uint32_t gpio_reg;
 648
 649         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 650                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 651                 return -1;
 652         }
 653
 654         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 655
 656         /* read GPIO and mask except the float bits */
 657         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 658
 659         switch (mode) {
 660         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 661                 /* clear FLOAT and set CLR */
 662                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 663                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 664                 break;
 665
 666         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 667                 /* clear FLOAT and set SET */
 668                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 669                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 670                 break;
 671
 672         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 673                 /* set FLOAT */
 674                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 675                 break;
 676
 677         default:
 678                 break;
 679         }
 680
 681         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 682         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 683
 684         return 0;
 685 }
 686
 687 static int
 688 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 689 {
 690         uint32_t gpio_reg;
 691
 692         /* any port swapping should be handled by caller */
 693
 694         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 695
 696         /* read GPIO and mask except the float bits */
 697         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 698         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 699         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 700         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 701
 702         switch (mode) {
 703         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 704                 /* set CLR */
 705                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 706                 break;
 707
 708         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 709                 /* set SET */
 710                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 711                 break;
 712
 713         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 714                 /* set FLOAT */
 715                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 716                 break;
 717
 718         default:
 719                 PMD_DRV_LOG(NOTICE, sc,
 720                             "Invalid GPIO mode assignment %d", mode);
 721                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 722                 return -1;
 723         }
 724
 725         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 726         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 727
 728         return 0;
 729 }
 730
 731 static int
 732 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 733                    uint8_t port)
 734 {
 735         /* The GPIO should be swapped if swap register is set and active */
 736         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 737                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 738         int gpio_shift = gpio_num;
 739         if (gpio_port)
 740                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 741
 742         uint32_t gpio_mask = (1 << gpio_shift);
 743         uint32_t gpio_reg;
 744
 745         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 746                 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
 747                 return -1;
 748         }
 749
 750         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 751
 752         /* read GPIO int */
 753         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 754
 755         switch (mode) {
 756         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 757                 /* clear SET and set CLR */
 758                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 759                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 760                 break;
 761
 762         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 763                 /* clear CLR and set SET */
 764                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 765                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 766                 break;
 767
 768         default:
 769                 break;
 770         }
 771
 772         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 773         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 774
 775         return 0;
 776 }
 777
 778 uint32_t
 779 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 780 {
 781         return bnx2x_gpio_read(sc, gpio_num, port);
 782 }
 783
 784 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 785                             uint8_t port)
 786 {
 787         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 788 }
 789
 790 uint8_t
 791 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 792                          uint8_t mode /* 0=low 1=high */ )
 793 {
 794         return bnx2x_gpio_mult_write(sc, pins, mode);
 795 }
 796
 797 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 798                                 uint8_t port)
 799 {
 800         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 801 }
 802
 803 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 804 {
 805         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 806                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 807 }
 808
 809 /* send the MCP a request, block until there is a reply */
 810 uint32_t
 811 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 812 {
 813         int mb_idx = SC_FW_MB_IDX(sc);
 814         uint32_t seq;
 815         uint32_t rc = 0;
 816         uint32_t cnt = 1;
 817         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 818
 819         seq = ++sc->fw_seq;
 820         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 821         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 822
 823         PMD_DRV_LOG(DEBUG, sc,
 824                     "wrote command 0x%08x to FW MB param 0x%08x",
 825                     (command | seq), param);
 826
 827         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 828         do {
 829                 DELAY(delay * 1000);
 830                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 831         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 832
 833         /* is this a reply to our command? */
 834         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 835                 rc &= FW_MSG_CODE_MASK;
 836         } else {
 837                 /* Ruh-roh! */
 838                 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
 839                 rc = 0;
 840         }
 841
 842         return rc;
 843 }
 844
 845 static uint32_t
 846 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 847 {
 848         return elink_cb_fw_command(sc, command, param);
 849 }
 850
 851 static void
 852 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 853                            rte_iova_t mapping)
 854 {
 855         REG_WR(sc, addr, U64_LO(mapping));
 856         REG_WR(sc, (addr + 4), U64_HI(mapping));
 857 }
 858
 859 static void
 860 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 861                       uint16_t abs_fid)
 862 {
 863         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 864                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 865         __storm_memset_dma_mapping(sc, addr, mapping);
 866 }
 867
 868 static void
 869 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 870 {
 871         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 872                 pf_id);
 873         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 874                 pf_id);
 875         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 876                 pf_id);
 877         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 878                 pf_id);
 879 }
 880
 881 static void
 882 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 883 {
 884         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 885                 enable);
 886         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 887                 enable);
 888         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 889                 enable);
 890         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 891                 enable);
 892 }
 893
 894 static void
 895 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 896                      uint16_t pfid)
 897 {
 898         uint32_t addr;
 899         size_t size;
 900
 901         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 902         size = sizeof(struct event_ring_data);
 903         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 904 }
 905
 906 static void
 907 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 908 {
 909         uint32_t addr = (BAR_CSTRORM_INTMEM +
 910                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 911         REG_WR16(sc, addr, eq_prod);
 912 }
 913
 914 /*
 915  * Post a slowpath command.
 916  *
 917  * A slowpath command is used to propagate a configuration change through
 918  * the controller in a controlled manner, allowing each STORM processor and
 919  * other H/W blocks to phase in the change.  The commands sent on the
 920  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 921  * completion of the ramrod will occur in different ways.  Here's a
 922  * breakdown of ramrods and how they complete:
 923  *
 924  * RAMROD_CMD_ID_ETH_PORT_SETUP
 925  *   Used to setup the leading connection on a port.  Completes on the
 926  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 927  *
 928  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 929  *   Used to setup an additional connection on a port.  Completes on the
 930  *   RCQ of the multi-queue/RSS connection being initialized.
 931  *
 932  * RAMROD_CMD_ID_ETH_STAT_QUERY
 933  *   Used to force the storm processors to update the statistics database
 934  *   in host memory.  This ramrod is send on the leading connection CID and
 935  *   completes as an index increment of the CSTORM on the default status
 936  *   block.
 937  *
 938  * RAMROD_CMD_ID_ETH_UPDATE
 939  *   Used to update the state of the leading connection, usually to udpate
 940  *   the RSS indirection table.  Completes on the RCQ of the leading
 941  *   connection. (Not currently used under FreeBSD until OS support becomes
 942  *   available.)
 943  *
 944  * RAMROD_CMD_ID_ETH_HALT
 945  *   Used when tearing down a connection prior to driver unload.  Completes
 946  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 947  *   use this on the leading connection.
 948  *
 949  * RAMROD_CMD_ID_ETH_SET_MAC
 950  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 951  *   the RCQ of the leading connection.
 952  *
 953  * RAMROD_CMD_ID_ETH_CFC_DEL
 954  *   Used when tearing down a conneciton prior to driver unload.  Completes
 955  *   on the RCQ of the leading connection (since the current connection
 956  *   has been completely removed from controller memory).
 957  *
 958  * RAMROD_CMD_ID_ETH_PORT_DEL
 959  *   Used to tear down the leading connection prior to driver unload,
 960  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 961  *   default status block.
 962  *
 963  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 964  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 965  *   RSS connection that is being offloaded.  (Not currently used under
 966  *   FreeBSD.)
 967  *
 968  * There can only be one command pending per function.
 969  *
 970  * Returns:
 971  *   0 = Success, !0 = Failure.
 972  */
 973
 974 /* must be called under the spq lock */
 975 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 976 {
 977         struct eth_spe *next_spe = sc->spq_prod_bd;
 978
 979         if (sc->spq_prod_bd == sc->spq_last_bd) {
 980                 /* wrap back to the first eth_spq */
 981                 sc->spq_prod_bd = sc->spq;
 982                 sc->spq_prod_idx = 0;
 983         } else {
 984                 sc->spq_prod_bd++;
 985                 sc->spq_prod_idx++;
 986         }
 987
 988         return next_spe;
 989 }
 990
 991 /* must be called under the spq lock */
 992 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 993 {
 994         int func = SC_FUNC(sc);
 995
 996         /*
 997          * Make sure that BD data is updated before writing the producer.
 998          * BD data is written to the memory, the producer is read from the
 999          * memory, thus we need a full memory barrier to ensure the ordering.
1000          */
1001         mb();
1002
1003         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1004                  sc->spq_prod_idx);
1005
1006         mb();
1007 }
1008
1009 /**
1010  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1011  *
1012  * @cmd:      command to check
1013  * @cmd_type: command type
1014  */
1015 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1016 {
1017         if ((cmd_type == NONE_CONNECTION_TYPE) ||
1018             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1019             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1020             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1021             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1022             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1023             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1024                 return TRUE;
1025         } else {
1026                 return FALSE;
1027         }
1028 }
1029
1030 /**
1031  * bnx2x_sp_post - place a single command on an SP ring
1032  *
1033  * @sc:         driver handle
1034  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1035  * @cid:        SW CID the command is related to
1036  * @data_hi:    command private data address (high 32 bits)
1037  * @data_lo:    command private data address (low 32 bits)
1038  * @cmd_type:   command type (e.g. NONE, ETH)
1039  *
1040  * SP data is handled as if it's always an address pair, thus data fields are
1041  * not swapped to little endian in upper functions. Instead this function swaps
1042  * data as if it's two uint32 fields.
1043  */
1044 int
1045 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1046             uint32_t data_lo, int cmd_type)
1047 {
1048         struct eth_spe *spe;
1049         uint16_t type;
1050         int common;
1051
1052         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1053
1054         if (common) {
1055                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1056                         PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1057                         return -1;
1058                 }
1059         } else {
1060                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1061                         PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1062                         return -1;
1063                 }
1064         }
1065
1066         spe = bnx2x_sp_get_next(sc);
1067
1068         /* CID needs port number to be encoded int it */
1069         spe->hdr.conn_and_cmd_data =
1070             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1071
1072         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1073
1074         /* TBD: Check if it works for VFs */
1075         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1076                  SPE_HDR_FUNCTION_ID);
1077
1078         spe->hdr.type = htole16(type);
1079
1080         spe->data.update_data_addr.hi = htole32(data_hi);
1081         spe->data.update_data_addr.lo = htole32(data_lo);
1082
1083         /*
1084          * It's ok if the actual decrement is issued towards the memory
1085          * somewhere between the lock and unlock. Thus no more explict
1086          * memory barrier is needed.
1087          */
1088         if (common) {
1089                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1090         } else {
1091                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1092         }
1093
1094         PMD_DRV_LOG(DEBUG, sc,
1095                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1096                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1097                     sc->spq_prod_idx,
1098                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1099                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1100                                 (uint8_t *) sc->spq_prod_bd -
1101                                 (uint8_t *) sc->spq), command, common,
1102                     HW_CID(sc, cid), data_hi, data_lo, type,
1103                     atomic_load_acq_long(&sc->cq_spq_left),
1104                     atomic_load_acq_long(&sc->eq_spq_left));
1105
1106         bnx2x_sp_prod_update(sc);
1107
1108         return 0;
1109 }
1110
1111 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1112 {
1113         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1114                  sc->fw_drv_pulse_wr_seq);
1115 }
1116
1117 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1118 {
1119         uint16_t hw_cons;
1120         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1121
1122         if (unlikely(!txq)) {
1123                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1124                 return 0;
1125         }
1126
1127         mb();                   /* status block fields can change */
1128         hw_cons = le16toh(*fp->tx_cons_sb);
1129         return hw_cons != txq->tx_pkt_head;
1130 }
1131
1132 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1133 {
1134         /* expand this for multi-cos if ever supported */
1135         return bnx2x_tx_queue_has_work(fp);
1136 }
1137
1138 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1139 {
1140         uint16_t rx_cq_cons_sb;
1141         struct bnx2x_rx_queue *rxq;
1142         rxq = fp->sc->rx_queues[fp->index];
1143         if (unlikely(!rxq)) {
1144                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1145                 return 0;
1146         }
1147
1148         mb();                   /* status block fields can change */
1149         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1150         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1151                      MAX_RCQ_ENTRIES(rxq)))
1152                 rx_cq_cons_sb++;
1153         return rxq->rx_cq_head != rx_cq_cons_sb;
1154 }
1155
1156 static void
1157 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1158              union eth_rx_cqe *rr_cqe)
1159 {
1160 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1161         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1162 #endif
1163         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1164         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1165         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1166
1167         PMD_DRV_LOG(DEBUG, sc,
1168                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1169                     fp->index, cid, command, sc->state,
1170                     rr_cqe->ramrod_cqe.ramrod_type);
1171
1172         switch (command) {
1173         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1174                 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1175                 drv_cmd = ECORE_Q_CMD_UPDATE;
1176                 break;
1177
1178         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1179                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1180                 drv_cmd = ECORE_Q_CMD_SETUP;
1181                 break;
1182
1183         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1184                 PMD_DRV_LOG(DEBUG, sc,
1185                             "got MULTI[%d] tx-only setup ramrod", cid);
1186                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1187                 break;
1188
1189         case (RAMROD_CMD_ID_ETH_HALT):
1190                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1191                 drv_cmd = ECORE_Q_CMD_HALT;
1192                 break;
1193
1194         case (RAMROD_CMD_ID_ETH_TERMINATE):
1195                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1196                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1197                 break;
1198
1199         case (RAMROD_CMD_ID_ETH_EMPTY):
1200                 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1201                 drv_cmd = ECORE_Q_CMD_EMPTY;
1202                 break;
1203
1204         default:
1205                 PMD_DRV_LOG(DEBUG, sc,
1206                             "ERROR: unexpected MC reply (%d)"
1207                             "on fp[%d]", command, fp->index);
1208                 return;
1209         }
1210
1211         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1212             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1213                 /*
1214                  * q_obj->complete_cmd() failure means that this was
1215                  * an unexpected completion.
1216                  *
1217                  * In this case we don't want to increase the sc->spq_left
1218                  * because apparently we haven't sent this command the first
1219                  * place.
1220                  */
1221                 // rte_panic("Unexpected SP completion");
1222                 return;
1223         }
1224
1225         atomic_add_acq_long(&sc->cq_spq_left, 1);
1226
1227         PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1228                     atomic_load_acq_long(&sc->cq_spq_left));
1229 }
1230
1231 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1232 {
1233         struct bnx2x_rx_queue *rxq;
1234         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1235         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1236
1237         rxq = sc->rx_queues[fp->index];
1238         if (!rxq) {
1239                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1240                 return 0;
1241         }
1242
1243         /* CQ "next element" is of the size of the regular element */
1244         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1245         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1246                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1247                 hw_cq_cons++;
1248         }
1249
1250         bd_cons = rxq->rx_bd_head;
1251         bd_prod = rxq->rx_bd_tail;
1252         bd_prod_fw = bd_prod;
1253         sw_cq_cons = rxq->rx_cq_head;
1254         sw_cq_prod = rxq->rx_cq_tail;
1255
1256         /*
1257          * Memory barrier necessary as speculative reads of the rx
1258          * buffer can be ahead of the index in the status block
1259          */
1260         rmb();
1261
1262         while (sw_cq_cons != hw_cq_cons) {
1263                 union eth_rx_cqe *cqe;
1264                 struct eth_fast_path_rx_cqe *cqe_fp;
1265                 uint8_t cqe_fp_flags;
1266                 enum eth_rx_cqe_type cqe_fp_type;
1267
1268                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1269                 bd_prod = RX_BD(bd_prod, rxq);
1270                 bd_cons = RX_BD(bd_cons, rxq);
1271
1272                 cqe = &rxq->cq_ring[comp_ring_cons];
1273                 cqe_fp = &cqe->fast_path_cqe;
1274                 cqe_fp_flags = cqe_fp->type_error_flags;
1275                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1276
1277                 /* is this a slowpath msg? */
1278                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1279                         bnx2x_sp_event(sc, fp, cqe);
1280                         goto next_cqe;
1281                 }
1282
1283                 /* is this an error packet? */
1284                 if (unlikely(cqe_fp_flags &
1285                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1286                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1287                                    cqe_fp_flags, sw_cq_cons);
1288                         goto next_rx;
1289                 }
1290
1291                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1292
1293 next_rx:
1294                 bd_cons = NEXT_RX_BD(bd_cons);
1295                 bd_prod = NEXT_RX_BD(bd_prod);
1296                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1297
1298 next_cqe:
1299                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1300                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1301
1302         }                       /* while work to do */
1303
1304         rxq->rx_bd_head = bd_cons;
1305         rxq->rx_bd_tail = bd_prod_fw;
1306         rxq->rx_cq_head = sw_cq_cons;
1307         rxq->rx_cq_tail = sw_cq_prod;
1308
1309         /* Update producers */
1310         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1311
1312         return sw_cq_cons != hw_cq_cons;
1313 }
1314
1315 static uint16_t
1316 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1317                 uint16_t pkt_idx, uint16_t bd_idx)
1318 {
1319         struct eth_tx_start_bd *tx_start_bd =
1320             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1321         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1322         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1323
1324         if (likely(tx_mbuf != NULL)) {
1325                 rte_pktmbuf_free_seg(tx_mbuf);
1326         } else {
1327                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1328                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1329         }
1330
1331         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1332         txq->nb_tx_avail += nbd;
1333
1334         while (nbd--)
1335                 bd_idx = NEXT_TX_BD(bd_idx);
1336
1337         return bd_idx;
1338 }
1339
1340 /* processes transmit completions */
1341 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1342 {
1343         uint16_t bd_cons, hw_cons, sw_cons;
1344         __rte_unused uint16_t tx_bd_avail;
1345
1346         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1347
1348         if (unlikely(!txq)) {
1349                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1350                 return 0;
1351         }
1352
1353         bd_cons = txq->tx_bd_head;
1354         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1355         sw_cons = txq->tx_pkt_head;
1356
1357         while (sw_cons != hw_cons) {
1358                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1359                 sw_cons++;
1360         }
1361
1362         txq->tx_pkt_head = sw_cons;
1363         txq->tx_bd_head = bd_cons;
1364
1365         tx_bd_avail = txq->nb_tx_avail;
1366
1367         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1368                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1369                    fp->index, tx_bd_avail, hw_cons,
1370                    txq->tx_pkt_head, txq->tx_pkt_tail,
1371                    txq->tx_bd_head, txq->tx_bd_tail);
1372         return TRUE;
1373 }
1374
1375 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1376 {
1377         struct bnx2x_fastpath *fp;
1378         int i, count;
1379
1380         /* wait until all TX fastpath tasks have completed */
1381         for (i = 0; i < sc->num_queues; i++) {
1382                 fp = &sc->fp[i];
1383
1384                 count = 1000;
1385
1386                 while (bnx2x_has_tx_work(fp)) {
1387                         bnx2x_txeof(sc, fp);
1388
1389                         if (count == 0) {
1390                                 PMD_TX_LOG(ERR,
1391                                            "Timeout waiting for fp[%d] "
1392                                            "transmits to complete!", i);
1393                                 rte_panic("tx drain failure");
1394                                 return;
1395                         }
1396
1397                         count--;
1398                         DELAY(1000);
1399                         rmb();
1400                 }
1401         }
1402
1403         return;
1404 }
1405
1406 static int
1407 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1408                  int mac_type, uint8_t wait_for_comp)
1409 {
1410         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1411         int rc;
1412
1413         /* wait for completion of requested */
1414         if (wait_for_comp) {
1415                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1416         }
1417
1418         /* Set the mac type of addresses we want to clear */
1419         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1420
1421         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1422         if (rc < 0)
1423                 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1424
1425         return rc;
1426 }
1427
1428 static int
1429 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1430                         unsigned long *rx_accept_flags,
1431                         unsigned long *tx_accept_flags)
1432 {
1433         /* Clear the flags first */
1434         *rx_accept_flags = 0;
1435         *tx_accept_flags = 0;
1436
1437         switch (rx_mode) {
1438         case BNX2X_RX_MODE_NONE:
1439                 /*
1440                  * 'drop all' supersedes any accept flags that may have been
1441                  * passed to the function.
1442                  */
1443                 break;
1444
1445         case BNX2X_RX_MODE_NORMAL:
1446                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1447                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1448                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1449
1450                 /* internal switching mode */
1451                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1452                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1453                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1454
1455                 break;
1456
1457         case BNX2X_RX_MODE_ALLMULTI:
1458                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1459                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1460                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1461
1462                 /* internal switching mode */
1463                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1464                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1465                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1466
1467                 break;
1468
1469         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1470         case BNX2X_RX_MODE_PROMISC:
1471                 /*
1472                  * According to deffinition of SI mode, iface in promisc mode
1473                  * should receive matched and unmatched (in resolution of port)
1474                  * unicast packets.
1475                  */
1476                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1477                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1478                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1479                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1480
1481                 /* internal switching mode */
1482                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1483                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1484
1485                 if (IS_MF_SI(sc)) {
1486                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1487                 } else {
1488                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1489                 }
1490
1491                 break;
1492
1493         default:
1494                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1495                 return -1;
1496         }
1497
1498         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1499         if (rx_mode != BNX2X_RX_MODE_NONE) {
1500                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1501                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1502         }
1503
1504         return 0;
1505 }
1506
1507 static int
1508 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1509                   unsigned long rx_mode_flags,
1510                   unsigned long rx_accept_flags,
1511                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1512 {
1513         struct ecore_rx_mode_ramrod_params ramrod_param;
1514         int rc;
1515
1516         memset(&ramrod_param, 0, sizeof(ramrod_param));
1517
1518         /* Prepare ramrod parameters */
1519         ramrod_param.cid = 0;
1520         ramrod_param.cl_id = cl_id;
1521         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1522         ramrod_param.func_id = SC_FUNC(sc);
1523
1524         ramrod_param.pstate = &sc->sp_state;
1525         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1526
1527         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1528         ramrod_param.rdata_mapping =
1529             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1530             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1531
1532         ramrod_param.ramrod_flags = ramrod_flags;
1533         ramrod_param.rx_mode_flags = rx_mode_flags;
1534
1535         ramrod_param.rx_accept_flags = rx_accept_flags;
1536         ramrod_param.tx_accept_flags = tx_accept_flags;
1537
1538         rc = ecore_config_rx_mode(sc, &ramrod_param);
1539         if (rc < 0) {
1540                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1541                 return rc;
1542         }
1543
1544         return 0;
1545 }
1546
1547 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1548 {
1549         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1550         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1551         int rc;
1552
1553         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1554                                    &tx_accept_flags);
1555         if (rc) {
1556                 return rc;
1557         }
1558
1559         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1560         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1561         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1562
1563         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1564                                  rx_accept_flags, tx_accept_flags,
1565                                  ramrod_flags);
1566 }
1567
1568 /* returns the "mcp load_code" according to global load_count array */
1569 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1570 {
1571         int path = SC_PATH(sc);
1572         int port = SC_PORT(sc);
1573
1574         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1575                     path, load_count[path][0], load_count[path][1],
1576                     load_count[path][2]);
1577
1578         load_count[path][0]++;
1579         load_count[path][1 + port]++;
1580         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1581                     path, load_count[path][0], load_count[path][1],
1582                     load_count[path][2]);
1583         if (load_count[path][0] == 1)
1584                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1585         else if (load_count[path][1 + port] == 1)
1586                 return FW_MSG_CODE_DRV_LOAD_PORT;
1587         else
1588                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1589 }
1590
1591 /* returns the "mcp load_code" according to global load_count array */
1592 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1593 {
1594         int port = SC_PORT(sc);
1595         int path = SC_PATH(sc);
1596
1597         PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d]      %d, %d, %d",
1598                     path, load_count[path][0], load_count[path][1],
1599                     load_count[path][2]);
1600         load_count[path][0]--;
1601         load_count[path][1 + port]--;
1602         PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d]  %d, %d, %d",
1603                     path, load_count[path][0], load_count[path][1],
1604                     load_count[path][2]);
1605         if (load_count[path][0] == 0) {
1606                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1607         } else if (load_count[path][1 + port] == 0) {
1608                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1609         } else {
1610                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1611         }
1612 }
1613
1614 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1615 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1616 {
1617         uint32_t reset_code = 0;
1618
1619         /* Select the UNLOAD request mode */
1620         if (unload_mode == UNLOAD_NORMAL) {
1621                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1622         } else {
1623                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1624         }
1625
1626         /* Send the request to the MCP */
1627         if (!BNX2X_NOMCP(sc)) {
1628                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1629         } else {
1630                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1631         }
1632
1633         return reset_code;
1634 }
1635
1636 /* send UNLOAD_DONE command to the MCP */
1637 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1638 {
1639         uint32_t reset_param =
1640             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1641
1642         /* Report UNLOAD_DONE to MCP */
1643         if (!BNX2X_NOMCP(sc)) {
1644                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1645         }
1646 }
1647
1648 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1649 {
1650         int tout = 50;
1651
1652         if (!sc->port.pmf) {
1653                 return 0;
1654         }
1655
1656         /*
1657          * (assumption: No Attention from MCP at this stage)
1658          * PMF probably in the middle of TX disable/enable transaction
1659          * 1. Sync IRS for default SB
1660          * 2. Sync SP queue - this guarantees us that attention handling started
1661          * 3. Wait, that TX disable/enable transaction completes
1662          *
1663          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1664          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1665          * received completion for the transaction the state is TX_STOPPED.
1666          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1667          * transaction.
1668          */
1669
1670         while (ecore_func_get_state(sc, &sc->func_obj) !=
1671                ECORE_F_STATE_STARTED && tout--) {
1672                 DELAY(20000);
1673         }
1674
1675         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1676                 /*
1677                  * Failed to complete the transaction in a "good way"
1678                  * Force both transactions with CLR bit.
1679                  */
1680                 struct ecore_func_state_params func_params = { NULL };
1681
1682                 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1683                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1684
1685                 func_params.f_obj = &sc->func_obj;
1686                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1687
1688                 /* STARTED-->TX_STOPPED */
1689                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1690                 ecore_func_state_change(sc, &func_params);
1691
1692                 /* TX_STOPPED-->STARTED */
1693                 func_params.cmd = ECORE_F_CMD_TX_START;
1694                 return ecore_func_state_change(sc, &func_params);
1695         }
1696
1697         return 0;
1698 }
1699
1700 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1701 {
1702         struct bnx2x_fastpath *fp = &sc->fp[index];
1703         struct ecore_queue_state_params q_params = { NULL };
1704         int rc;
1705
1706         PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1707
1708         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1709         /* We want to wait for completion in this context */
1710         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1711
1712         /* Stop the primary connection: */
1713
1714         /* ...halt the connection */
1715         q_params.cmd = ECORE_Q_CMD_HALT;
1716         rc = ecore_queue_state_change(sc, &q_params);
1717         if (rc) {
1718                 return rc;
1719         }
1720
1721         /* ...terminate the connection */
1722         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1723         memset(&q_params.params.terminate, 0,
1724                sizeof(q_params.params.terminate));
1725         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1726         rc = ecore_queue_state_change(sc, &q_params);
1727         if (rc) {
1728                 return rc;
1729         }
1730
1731         /* ...delete cfc entry */
1732         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1733         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1734         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1735         return ecore_queue_state_change(sc, &q_params);
1736 }
1737
1738 /* wait for the outstanding SP commands */
1739 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1740 {
1741         unsigned long tmp;
1742         int tout = 5000;        /* wait for 5 secs tops */
1743
1744         while (tout--) {
1745                 mb();
1746                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1747                         return TRUE;
1748                 }
1749
1750                 DELAY(1000);
1751         }
1752
1753         mb();
1754
1755         tmp = atomic_load_acq_long(&sc->sp_state);
1756         if (tmp & mask) {
1757                 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1758                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1759                 return FALSE;
1760         }
1761
1762         return FALSE;
1763 }
1764
1765 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1766 {
1767         struct ecore_func_state_params func_params = { NULL };
1768         int rc;
1769
1770         /* prepare parameters for function state transitions */
1771         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1772         func_params.f_obj = &sc->func_obj;
1773         func_params.cmd = ECORE_F_CMD_STOP;
1774
1775         /*
1776          * Try to stop the function the 'good way'. If it fails (in case
1777          * of a parity error during bnx2x_chip_cleanup()) and we are
1778          * not in a debug mode, perform a state transaction in order to
1779          * enable further HW_RESET transaction.
1780          */
1781         rc = ecore_func_state_change(sc, &func_params);
1782         if (rc) {
1783                 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1784                             "Running a dry transaction");
1785                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1786                 return ecore_func_state_change(sc, &func_params);
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1793 {
1794         struct ecore_func_state_params func_params = { NULL };
1795
1796         /* Prepare parameters for function state transitions */
1797         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1798
1799         func_params.f_obj = &sc->func_obj;
1800         func_params.cmd = ECORE_F_CMD_HW_RESET;
1801
1802         func_params.params.hw_init.load_phase = load_code;
1803
1804         return ecore_func_state_change(sc, &func_params);
1805 }
1806
1807 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1808 {
1809         if (disable_hw) {
1810                 /* prevent the HW from sending interrupts */
1811                 bnx2x_int_disable(sc);
1812         }
1813 }
1814
1815 static void
1816 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1817 {
1818         int port = SC_PORT(sc);
1819         struct ecore_mcast_ramrod_params rparam = { NULL };
1820         uint32_t reset_code;
1821         int i, rc = 0;
1822
1823         bnx2x_drain_tx_queues(sc);
1824
1825         /* give HW time to discard old tx messages */
1826         DELAY(1000);
1827
1828         /* Clean all ETH MACs */
1829         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1830                               FALSE);
1831         if (rc < 0) {
1832                 PMD_DRV_LOG(NOTICE, sc,
1833                             "Failed to delete all ETH MACs (%d)", rc);
1834         }
1835
1836         /* Clean up UC list  */
1837         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1838                               TRUE);
1839         if (rc < 0) {
1840                 PMD_DRV_LOG(NOTICE, sc,
1841                             "Failed to delete UC MACs list (%d)", rc);
1842         }
1843
1844         /* Disable LLH */
1845         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1846
1847         /* Set "drop all" to stop Rx */
1848
1849         /*
1850          * We need to take the if_maddr_lock() here in order to prevent
1851          * a race between the completion code and this code.
1852          */
1853
1854         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1855                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1856         } else {
1857                 bnx2x_set_storm_rx_mode(sc);
1858         }
1859
1860         /* Clean up multicast configuration */
1861         rparam.mcast_obj = &sc->mcast_obj;
1862         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1863         if (rc < 0) {
1864                 PMD_DRV_LOG(NOTICE, sc,
1865                             "Failed to send DEL MCAST command (%d)", rc);
1866         }
1867
1868         /*
1869          * Send the UNLOAD_REQUEST to the MCP. This will return if
1870          * this function should perform FUNCTION, PORT, or COMMON HW
1871          * reset.
1872          */
1873         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1874
1875         /*
1876          * (assumption: No Attention from MCP at this stage)
1877          * PMF probably in the middle of TX disable/enable transaction
1878          */
1879         rc = bnx2x_func_wait_started(sc);
1880         if (rc) {
1881                 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1882         }
1883
1884         /*
1885          * Close multi and leading connections
1886          * Completions for ramrods are collected in a synchronous way
1887          */
1888         for (i = 0; i < sc->num_queues; i++) {
1889                 if (bnx2x_stop_queue(sc, i)) {
1890                         goto unload_error;
1891                 }
1892         }
1893
1894         /*
1895          * If SP settings didn't get completed so far - something
1896          * very wrong has happen.
1897          */
1898         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1899                 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1900         }
1901
1902 unload_error:
1903
1904         rc = bnx2x_func_stop(sc);
1905         if (rc) {
1906                 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1907         }
1908
1909         /* disable HW interrupts */
1910         bnx2x_int_disable_sync(sc, TRUE);
1911
1912         /* Reset the chip */
1913         rc = bnx2x_reset_hw(sc, reset_code);
1914         if (rc) {
1915                 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1916         }
1917
1918         /* Report UNLOAD_DONE to MCP */
1919         bnx2x_send_unload_done(sc, keep_link);
1920 }
1921
1922 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1923 {
1924         uint32_t val;
1925
1926         PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1927
1928         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1929         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1930                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1931         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1932 }
1933
1934 /*
1935  * Cleans the object that have internal lists without sending
1936  * ramrods. Should be run when interrutps are disabled.
1937  */
1938 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1939 {
1940         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1941         struct ecore_mcast_ramrod_params rparam = { NULL };
1942         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1943         int rc;
1944
1945         /* Cleanup MACs' object first... */
1946
1947         /* Wait for completion of requested */
1948         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1949         /* Perform a dry cleanup */
1950         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1951
1952         /* Clean ETH primary MAC */
1953         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1954         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1955                                  &ramrod_flags);
1956         if (rc != 0) {
1957                 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1958         }
1959
1960         /* Cleanup UC list */
1961         vlan_mac_flags = 0;
1962         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1963         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1964         if (rc != 0) {
1965                 PMD_DRV_LOG(NOTICE, sc,
1966                             "Failed to clean UC list MACs (%d)", rc);
1967         }
1968
1969         /* Now clean mcast object... */
1970
1971         rparam.mcast_obj = &sc->mcast_obj;
1972         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1973
1974         /* Add a DEL command... */
1975         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1976         if (rc < 0) {
1977                 PMD_DRV_LOG(NOTICE, sc,
1978                             "Failed to send DEL MCAST command (%d)", rc);
1979         }
1980
1981         /* now wait until all pending commands are cleared */
1982
1983         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1984         while (rc != 0) {
1985                 if (rc < 0) {
1986                         PMD_DRV_LOG(NOTICE, sc,
1987                                     "Failed to clean MCAST object (%d)", rc);
1988                         return;
1989                 }
1990
1991                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1992         }
1993 }
1994
1995 /* stop the controller */
1996 __rte_noinline
1997 int
1998 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1999 {
2000         uint8_t global = FALSE;
2001         uint32_t val;
2002
2003         PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2004
2005         /* mark driver as unloaded in shmem2 */
2006         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2007                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2008                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2009                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2010         }
2011
2012         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2013             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2014                 /*
2015                  * We can get here if the driver has been unloaded
2016                  * during parity error recovery and is either waiting for a
2017                  * leader to complete or for other functions to unload and
2018                  * then ifconfig down has been issued. In this case we want to
2019                  * unload and let other functions to complete a recovery
2020                  * process.
2021                  */
2022                 sc->recovery_state = BNX2X_RECOVERY_DONE;
2023                 sc->is_leader = 0;
2024                 bnx2x_release_leader_lock(sc);
2025                 mb();
2026
2027                 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2028                 return -1;
2029         }
2030
2031         /*
2032          * Nothing to do during unload if previous bnx2x_nic_load()
2033          * did not completed successfully - all resourses are released.
2034          */
2035         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2036                 return 0;
2037         }
2038
2039         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2040         mb();
2041
2042         sc->rx_mode = BNX2X_RX_MODE_NONE;
2043         bnx2x_set_rx_mode(sc);
2044         mb();
2045
2046         if (IS_PF(sc)) {
2047                 /* set ALWAYS_ALIVE bit in shmem */
2048                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2049
2050                 bnx2x_drv_pulse(sc);
2051
2052                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2053                 bnx2x_save_statistics(sc);
2054         }
2055
2056         /* wait till consumers catch up with producers in all queues */
2057         bnx2x_drain_tx_queues(sc);
2058
2059         /* if VF indicate to PF this function is going down (PF will delete sp
2060          * elements and clear initializations
2061          */
2062         if (IS_VF(sc)) {
2063                 bnx2x_vf_unload(sc);
2064         } else if (unload_mode != UNLOAD_RECOVERY) {
2065                 /* if this is a normal/close unload need to clean up chip */
2066                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2067         } else {
2068                 /* Send the UNLOAD_REQUEST to the MCP */
2069                 bnx2x_send_unload_req(sc, unload_mode);
2070
2071                 /*
2072                  * Prevent transactions to host from the functions on the
2073                  * engine that doesn't reset global blocks in case of global
2074                  * attention once gloabl blocks are reset and gates are opened
2075                  * (the engine which leader will perform the recovery
2076                  * last).
2077                  */
2078                 if (!CHIP_IS_E1x(sc)) {
2079                         bnx2x_pf_disable(sc);
2080                 }
2081
2082                 /* disable HW interrupts */
2083                 bnx2x_int_disable_sync(sc, TRUE);
2084
2085                 /* Report UNLOAD_DONE to MCP */
2086                 bnx2x_send_unload_done(sc, FALSE);
2087         }
2088
2089         /*
2090          * At this stage no more interrupts will arrive so we may safely clean
2091          * the queue'able objects here in case they failed to get cleaned so far.
2092          */
2093         if (IS_PF(sc)) {
2094                 bnx2x_squeeze_objects(sc);
2095         }
2096
2097         /* There should be no more pending SP commands at this stage */
2098         sc->sp_state = 0;
2099
2100         sc->port.pmf = 0;
2101
2102         if (IS_PF(sc)) {
2103                 bnx2x_free_mem(sc);
2104         }
2105
2106         bnx2x_free_fw_stats_mem(sc);
2107
2108         sc->state = BNX2X_STATE_CLOSED;
2109
2110         /*
2111          * Check if there are pending parity attentions. If there are - set
2112          * RECOVERY_IN_PROGRESS.
2113          */
2114         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2115                 bnx2x_set_reset_in_progress(sc);
2116
2117                 /* Set RESET_IS_GLOBAL if needed */
2118                 if (global) {
2119                         bnx2x_set_reset_global(sc);
2120                 }
2121         }
2122
2123         /*
2124          * The last driver must disable a "close the gate" if there is no
2125          * parity attention or "process kill" pending.
2126          */
2127         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2128             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2129                 bnx2x_disable_close_the_gate(sc);
2130         }
2131
2132         PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2133
2134         return 0;
2135 }
2136
2137 /*
2138  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2139  * visible to the controller.
2140  *
2141  * If an mbuf is submitted to this routine and cannot be given to the
2142  * controller (e.g. it has too many fragments) then the function may free
2143  * the mbuf and return to the caller.
2144  *
2145  * Returns:
2146  *     int: Number of TX BDs used for the mbuf
2147  *
2148  *   Note the side effect that an mbuf may be freed if it causes a problem.
2149  */
2150 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2151 {
2152         struct eth_tx_start_bd *tx_start_bd;
2153         uint16_t bd_prod, pkt_prod;
2154         struct bnx2x_softc *sc;
2155         uint32_t nbds = 0;
2156
2157         sc = txq->sc;
2158         bd_prod = txq->tx_bd_tail;
2159         pkt_prod = txq->tx_pkt_tail;
2160
2161         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2162
2163         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2164
2165         tx_start_bd->addr =
2166             rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2167         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2168         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2169         tx_start_bd->general_data =
2170             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2171
2172         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2173
2174         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2175                 tx_start_bd->vlan_or_ethertype =
2176                     rte_cpu_to_le_16(m0->vlan_tci);
2177                 tx_start_bd->bd_flags.as_bitfield |=
2178                     (X_ETH_OUTBAND_VLAN <<
2179                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2180         } else {
2181                 if (IS_PF(sc))
2182                         tx_start_bd->vlan_or_ethertype =
2183                             rte_cpu_to_le_16(pkt_prod);
2184                 else {
2185                         struct ether_hdr *eh =
2186                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2187
2188                         tx_start_bd->vlan_or_ethertype =
2189                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2190                 }
2191         }
2192
2193         bd_prod = NEXT_TX_BD(bd_prod);
2194         if (IS_VF(sc)) {
2195                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2196                 const struct ether_hdr *eh =
2197                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2198                 uint8_t mac_type = UNICAST_ADDRESS;
2199
2200                 tx_parse_bd =
2201                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2202                 if (is_multicast_ether_addr(&eh->d_addr)) {
2203                         if (is_broadcast_ether_addr(&eh->d_addr))
2204                                 mac_type = BROADCAST_ADDRESS;
2205                         else
2206                                 mac_type = MULTICAST_ADDRESS;
2207                 }
2208                 tx_parse_bd->parsing_data =
2209                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2210
2211                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2212                            &eh->d_addr.addr_bytes[0], 2);
2213                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2214                            &eh->d_addr.addr_bytes[2], 2);
2215                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2216                            &eh->d_addr.addr_bytes[4], 2);
2217                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2218                            &eh->s_addr.addr_bytes[0], 2);
2219                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2220                            &eh->s_addr.addr_bytes[2], 2);
2221                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2222                            &eh->s_addr.addr_bytes[4], 2);
2223
2224                 tx_parse_bd->data.mac_addr.dst_hi =
2225                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2226                 tx_parse_bd->data.mac_addr.dst_mid =
2227                     rte_cpu_to_be_16(tx_parse_bd->data.
2228                                      mac_addr.dst_mid);
2229                 tx_parse_bd->data.mac_addr.dst_lo =
2230                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2231                 tx_parse_bd->data.mac_addr.src_hi =
2232                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2233                 tx_parse_bd->data.mac_addr.src_mid =
2234                     rte_cpu_to_be_16(tx_parse_bd->data.
2235                                      mac_addr.src_mid);
2236                 tx_parse_bd->data.mac_addr.src_lo =
2237                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2238
2239                 PMD_TX_LOG(DEBUG,
2240                            "PBD dst %x %x %x src %x %x %x p_data %x",
2241                            tx_parse_bd->data.mac_addr.dst_hi,
2242                            tx_parse_bd->data.mac_addr.dst_mid,
2243                            tx_parse_bd->data.mac_addr.dst_lo,
2244                            tx_parse_bd->data.mac_addr.src_hi,
2245                            tx_parse_bd->data.mac_addr.src_mid,
2246                            tx_parse_bd->data.mac_addr.src_lo,
2247                            tx_parse_bd->parsing_data);
2248         }
2249
2250         PMD_TX_LOG(DEBUG,
2251                    "start bd: nbytes %d flags %x vlan %x",
2252                    tx_start_bd->nbytes,
2253                    tx_start_bd->bd_flags.as_bitfield,
2254                    tx_start_bd->vlan_or_ethertype);
2255
2256         bd_prod = NEXT_TX_BD(bd_prod);
2257         pkt_prod++;
2258
2259         if (TX_IDX(bd_prod) < 2)
2260                 nbds++;
2261
2262         txq->nb_tx_avail -= 2;
2263         txq->tx_bd_tail = bd_prod;
2264         txq->tx_pkt_tail = pkt_prod;
2265
2266         return nbds + 2;
2267 }
2268
2269 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2270 {
2271         return L2_ILT_LINES(sc);
2272 }
2273
2274 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2275 {
2276         struct ilt_client_info *ilt_client;
2277         struct ecore_ilt *ilt = sc->ilt;
2278         uint16_t line = 0;
2279
2280         PMD_INIT_FUNC_TRACE(sc);
2281
2282         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2283
2284         /* CDU */
2285         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2286         ilt_client->client_num = ILT_CLIENT_CDU;
2287         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2288         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2289         ilt_client->start = line;
2290         line += bnx2x_cid_ilt_lines(sc);
2291
2292         if (CNIC_SUPPORT(sc)) {
2293                 line += CNIC_ILT_LINES;
2294         }
2295
2296         ilt_client->end = (line - 1);
2297
2298         /* QM */
2299         if (QM_INIT(sc->qm_cid_count)) {
2300                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2301                 ilt_client->client_num = ILT_CLIENT_QM;
2302                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2303                 ilt_client->flags = 0;
2304                 ilt_client->start = line;
2305
2306                 /* 4 bytes for each cid */
2307                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2308                                      QM_ILT_PAGE_SZ);
2309
2310                 ilt_client->end = (line - 1);
2311         }
2312
2313         if (CNIC_SUPPORT(sc)) {
2314                 /* SRC */
2315                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2316                 ilt_client->client_num = ILT_CLIENT_SRC;
2317                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2318                 ilt_client->flags = 0;
2319                 ilt_client->start = line;
2320                 line += SRC_ILT_LINES;
2321                 ilt_client->end = (line - 1);
2322
2323                 /* TM */
2324                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2325                 ilt_client->client_num = ILT_CLIENT_TM;
2326                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2327                 ilt_client->flags = 0;
2328                 ilt_client->start = line;
2329                 line += TM_ILT_LINES;
2330                 ilt_client->end = (line - 1);
2331         }
2332
2333         assert((line <= ILT_MAX_LINES));
2334 }
2335
2336 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2337 {
2338         int i;
2339
2340         for (i = 0; i < sc->num_queues; i++) {
2341                 /* get the Rx buffer size for RX frames */
2342                 sc->fp[i].rx_buf_size =
2343                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2344         }
2345 }
2346
2347 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2348 {
2349
2350         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2351
2352         return sc->ilt == NULL;
2353 }
2354
2355 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2356 {
2357         sc->ilt->lines = rte_calloc("",
2358                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2359                                     RTE_CACHE_LINE_SIZE);
2360         return sc->ilt->lines == NULL;
2361 }
2362
2363 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2364 {
2365         rte_free(sc->ilt);
2366         sc->ilt = NULL;
2367 }
2368
2369 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2370 {
2371         if (sc->ilt->lines != NULL) {
2372                 rte_free(sc->ilt->lines);
2373                 sc->ilt->lines = NULL;
2374         }
2375 }
2376
2377 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2378 {
2379         uint32_t i;
2380
2381         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2382                 sc->context[i].vcxt = NULL;
2383                 sc->context[i].size = 0;
2384         }
2385
2386         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2387
2388         bnx2x_free_ilt_lines_mem(sc);
2389 }
2390
2391 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2392 {
2393         int context_size;
2394         int allocated;
2395         int i;
2396         char cdu_name[RTE_MEMZONE_NAMESIZE];
2397
2398         /*
2399          * Allocate memory for CDU context:
2400          * This memory is allocated separately and not in the generic ILT
2401          * functions because CDU differs in few aspects:
2402          * 1. There can be multiple entities allocating memory for context -
2403          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2404          * its own ILT lines.
2405          * 2. Since CDU page-size is not a single 4KB page (which is the case
2406          * for the other ILT clients), to be efficient we want to support
2407          * allocation of sub-page-size in the last entry.
2408          * 3. Context pointers are used by the driver to pass to FW / update
2409          * the context (for the other ILT clients the pointers are used just to
2410          * free the memory during unload).
2411          */
2412         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2413         for (i = 0, allocated = 0; allocated < context_size; i++) {
2414                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2415                                           (context_size - allocated));
2416
2417                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2418                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2419                                   &sc->context[i].vcxt_dma,
2420                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2421                         bnx2x_free_mem(sc);
2422                         return -1;
2423                 }
2424
2425                 sc->context[i].vcxt =
2426                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2427
2428                 allocated += sc->context[i].size;
2429         }
2430
2431         bnx2x_alloc_ilt_lines_mem(sc);
2432
2433         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2434                 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2435                 bnx2x_free_mem(sc);
2436                 return -1;
2437         }
2438
2439         return 0;
2440 }
2441
2442 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2443 {
2444         sc->fw_stats_num = 0;
2445
2446         sc->fw_stats_req_size = 0;
2447         sc->fw_stats_req = NULL;
2448         sc->fw_stats_req_mapping = 0;
2449
2450         sc->fw_stats_data_size = 0;
2451         sc->fw_stats_data = NULL;
2452         sc->fw_stats_data_mapping = 0;
2453 }
2454
2455 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2456 {
2457         uint8_t num_queue_stats;
2458         int num_groups, vf_headroom = 0;
2459
2460         /* number of queues for statistics is number of eth queues */
2461         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2462
2463         /*
2464          * Total number of FW statistics requests =
2465          *   1 for port stats + 1 for PF stats + num of queues
2466          */
2467         sc->fw_stats_num = (2 + num_queue_stats);
2468
2469         /*
2470          * Request is built from stats_query_header and an array of
2471          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2472          * rules. The real number or requests is configured in the
2473          * stats_query_header.
2474          */
2475         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2476         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2477                 num_groups++;
2478
2479         sc->fw_stats_req_size =
2480             (sizeof(struct stats_query_header) +
2481              (num_groups * sizeof(struct stats_query_cmd_group)));
2482
2483         /*
2484          * Data for statistics requests + stats_counter.
2485          * stats_counter holds per-STORM counters that are incremented when
2486          * STORM has finished with the current request. Memory for FCoE
2487          * offloaded statistics are counted anyway, even if they will not be sent.
2488          * VF stats are not accounted for here as the data of VF stats is stored
2489          * in memory allocated by the VF, not here.
2490          */
2491         sc->fw_stats_data_size =
2492             (sizeof(struct stats_counter) +
2493              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2494              /* sizeof(struct fcoe_statistics_params) + */
2495              (sizeof(struct per_queue_stats) * num_queue_stats));
2496
2497         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2498                           &sc->fw_stats_dma, "fw_stats",
2499                           RTE_CACHE_LINE_SIZE) != 0) {
2500                 bnx2x_free_fw_stats_mem(sc);
2501                 return -1;
2502         }
2503
2504         /* set up the shortcuts */
2505
2506         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2507         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2508
2509         sc->fw_stats_data =
2510             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2511                                          sc->fw_stats_req_size);
2512         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2513                                      sc->fw_stats_req_size);
2514
2515         return 0;
2516 }
2517
2518 /*
2519  * Bits map:
2520  * 0-7  - Engine0 load counter.
2521  * 8-15 - Engine1 load counter.
2522  * 16   - Engine0 RESET_IN_PROGRESS bit.
2523  * 17   - Engine1 RESET_IN_PROGRESS bit.
2524  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2525  *        function on the engine
2526  * 19   - Engine1 ONE_IS_LOADED.
2527  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2528  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2529  *        for just the one belonging to its engine).
2530  */
2531 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2532 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2533 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2534 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2535 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2536 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2537 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2538 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2539
2540 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2541 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2542 {
2543         uint32_t val;
2544         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2545         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2546         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2547         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2548 }
2549
2550 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2551 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2552 {
2553         uint32_t val;
2554         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2555         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2556         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2557         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2558 }
2559
2560 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2561 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2562 {
2563         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2564 }
2565
2566 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2567 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2568 {
2569         uint32_t val;
2570         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2571             BNX2X_PATH0_RST_IN_PROG_BIT;
2572
2573         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2574
2575         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2576         /* Clear the bit */
2577         val &= ~bit;
2578         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2579
2580         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2581 }
2582
2583 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2584 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2585 {
2586         uint32_t val;
2587         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2588             BNX2X_PATH0_RST_IN_PROG_BIT;
2589
2590         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2591
2592         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2593         /* Set the bit */
2594         val |= bit;
2595         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2596
2597         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2598 }
2599
2600 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2601 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2602 {
2603         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2604         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2605             BNX2X_PATH0_RST_IN_PROG_BIT;
2606
2607         /* return false if bit is set */
2608         return (val & bit) ? FALSE : TRUE;
2609 }
2610
2611 /* get the load status for an engine, should be run under rtnl lock */
2612 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2613 {
2614         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2615             BNX2X_PATH0_LOAD_CNT_MASK;
2616         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2617             BNX2X_PATH0_LOAD_CNT_SHIFT;
2618         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2619
2620         val = ((val & mask) >> shift);
2621
2622         return val != 0;
2623 }
2624
2625 /* set pf load mark */
2626 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2627 {
2628         uint32_t val;
2629         uint32_t val1;
2630         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2631             BNX2X_PATH0_LOAD_CNT_MASK;
2632         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2633             BNX2X_PATH0_LOAD_CNT_SHIFT;
2634
2635         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2636
2637         PMD_INIT_FUNC_TRACE(sc);
2638
2639         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2640
2641         /* get the current counter value */
2642         val1 = ((val & mask) >> shift);
2643
2644         /* set bit of this PF */
2645         val1 |= (1 << SC_ABS_FUNC(sc));
2646
2647         /* clear the old value */
2648         val &= ~mask;
2649
2650         /* set the new one */
2651         val |= ((val1 << shift) & mask);
2652
2653         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2654
2655         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2656 }
2657
2658 /* clear pf load mark */
2659 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2660 {
2661         uint32_t val1, val;
2662         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2663             BNX2X_PATH0_LOAD_CNT_MASK;
2664         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2665             BNX2X_PATH0_LOAD_CNT_SHIFT;
2666
2667         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2668         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2669
2670         /* get the current counter value */
2671         val1 = (val & mask) >> shift;
2672
2673         /* clear bit of that PF */
2674         val1 &= ~(1 << SC_ABS_FUNC(sc));
2675
2676         /* clear the old value */
2677         val &= ~mask;
2678
2679         /* set the new one */
2680         val |= ((val1 << shift) & mask);
2681
2682         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2683         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2684         return val1 != 0;
2685 }
2686
2687 /* send load requrest to mcp and analyze response */
2688 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2689 {
2690         PMD_INIT_FUNC_TRACE(sc);
2691
2692         /* init fw_seq */
2693         sc->fw_seq =
2694             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2695              DRV_MSG_SEQ_NUMBER_MASK);
2696
2697         PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2698
2699 #ifdef BNX2X_PULSE
2700         /* get the current FW pulse sequence */
2701         sc->fw_drv_pulse_wr_seq =
2702             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2703              DRV_PULSE_SEQ_MASK);
2704 #else
2705         /* set ALWAYS_ALIVE bit in shmem */
2706         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2707         bnx2x_drv_pulse(sc);
2708 #endif
2709
2710         /* load request */
2711         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2712                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2713
2714         /* if the MCP fails to respond we must abort */
2715         if (!(*load_code)) {
2716                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2717                 return -1;
2718         }
2719
2720         /* if MCP refused then must abort */
2721         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2722                 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2723                 return -1;
2724         }
2725
2726         return 0;
2727 }
2728
2729 /*
2730  * Check whether another PF has already loaded FW to chip. In virtualized
2731  * environments a pf from anoth VM may have already initialized the device
2732  * including loading FW.
2733  */
2734 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2735 {
2736         uint32_t my_fw, loaded_fw;
2737
2738         /* is another pf loaded on this engine? */
2739         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2740             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2741                 /* build my FW version dword */
2742                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2743                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2744                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2745                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2746
2747                 /* read loaded FW from chip */
2748                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2749                 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2750                             loaded_fw, my_fw);
2751
2752                 /* abort nic load if version mismatch */
2753                 if (my_fw != loaded_fw) {
2754                         PMD_DRV_LOG(NOTICE, sc,
2755                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2756                                     loaded_fw, my_fw);
2757                         return -1;
2758                 }
2759         }
2760
2761         return 0;
2762 }
2763
2764 /* mark PMF if applicable */
2765 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2766 {
2767         uint32_t ncsi_oem_data_addr;
2768
2769         PMD_INIT_FUNC_TRACE(sc);
2770
2771         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2772             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2773             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2774                 /*
2775                  * Barrier here for ordering between the writing to sc->port.pmf here
2776                  * and reading it from the periodic task.
2777                  */
2778                 sc->port.pmf = 1;
2779                 mb();
2780         } else {
2781                 sc->port.pmf = 0;
2782         }
2783
2784         PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2785
2786         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2787                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2788                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2789                         if (ncsi_oem_data_addr) {
2790                                 REG_WR(sc,
2791                                        (ncsi_oem_data_addr +
2792                                         offsetof(struct glob_ncsi_oem_data,
2793                                                  driver_version)), 0);
2794                         }
2795                 }
2796         }
2797 }
2798
2799 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2800 {
2801         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2802         int abs_func;
2803         int vn;
2804
2805         if (BNX2X_NOMCP(sc)) {
2806                 return;         /* what should be the default bvalue in this case */
2807         }
2808
2809         /*
2810          * The formula for computing the absolute function number is...
2811          * For 2 port configuration (4 functions per port):
2812          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2813          * For 4 port configuration (2 functions per port):
2814          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2815          */
2816         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2817                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2818                 if (abs_func >= E1H_FUNC_MAX) {
2819                         break;
2820                 }
2821                 sc->devinfo.mf_info.mf_config[vn] =
2822                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2823         }
2824
2825         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2826             FUNC_MF_CFG_FUNC_DISABLED) {
2827                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2828                 sc->flags |= BNX2X_MF_FUNC_DIS;
2829         } else {
2830                 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2831                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2832         }
2833 }
2834
2835 /* acquire split MCP access lock register */
2836 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2837 {
2838         uint32_t j, val;
2839
2840         for (j = 0; j < 1000; j++) {
2841                 val = (1UL << 31);
2842                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2843                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2844                 if (val & (1L << 31))
2845                         break;
2846
2847                 DELAY(5000);
2848         }
2849
2850         if (!(val & (1L << 31))) {
2851                 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2852                 return -1;
2853         }
2854
2855         return 0;
2856 }
2857
2858 /* release split MCP access lock register */
2859 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2860 {
2861         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2862 }
2863
2864 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2865 {
2866         int port = SC_PORT(sc);
2867         uint32_t ext_phy_config;
2868
2869         /* mark the failure */
2870         ext_phy_config =
2871             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2872
2873         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2874         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2875         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2876                  ext_phy_config);
2877
2878         /* log the failure */
2879         PMD_DRV_LOG(INFO, sc,
2880                     "Fan Failure has caused the driver to shutdown "
2881                     "the card to prevent permanent damage. "
2882                     "Please contact OEM Support for assistance");
2883
2884         rte_panic("Schedule task to handle fan failure");
2885 }
2886
2887 /* this function is called upon a link interrupt */
2888 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2889 {
2890         uint32_t pause_enabled = 0;
2891         struct host_port_stats *pstats;
2892         int cmng_fns;
2893
2894         /* Make sure that we are synced with the current statistics */
2895         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2896
2897         elink_link_update(&sc->link_params, &sc->link_vars);
2898
2899         if (sc->link_vars.link_up) {
2900
2901                 /* dropless flow control */
2902                 if (sc->dropless_fc) {
2903                         pause_enabled = 0;
2904
2905                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2906                                 pause_enabled = 1;
2907                         }
2908
2909                         REG_WR(sc,
2910                                (BAR_USTRORM_INTMEM +
2911                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2912                                pause_enabled);
2913                 }
2914
2915                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2916                         pstats = BNX2X_SP(sc, port_stats);
2917                         /* reset old mac stats */
2918                         memset(&(pstats->mac_stx[0]), 0,
2919                                sizeof(struct mac_stx));
2920                 }
2921
2922                 if (sc->state == BNX2X_STATE_OPEN) {
2923                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2924                 }
2925         }
2926
2927         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2928                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2929
2930                 if (cmng_fns != CMNG_FNS_NONE) {
2931                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2932                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2933                 }
2934         }
2935
2936         bnx2x_link_report_locked(sc);
2937
2938         if (IS_MF(sc)) {
2939                 bnx2x_link_sync_notify(sc);
2940         }
2941 }
2942
2943 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2944 {
2945         int port = SC_PORT(sc);
2946         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2947             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2948         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2949             NIG_REG_MASK_INTERRUPT_PORT0;
2950         uint32_t aeu_mask;
2951         uint32_t nig_mask = 0;
2952         uint32_t reg_addr;
2953         uint32_t igu_acked;
2954         uint32_t cnt;
2955
2956         if (sc->attn_state & asserted) {
2957                 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2958         }
2959
2960         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2961
2962         aeu_mask = REG_RD(sc, aeu_addr);
2963
2964         aeu_mask &= ~(asserted & 0x3ff);
2965
2966         REG_WR(sc, aeu_addr, aeu_mask);
2967
2968         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2969
2970         sc->attn_state |= asserted;
2971
2972         if (asserted & ATTN_HARD_WIRED_MASK) {
2973                 if (asserted & ATTN_NIG_FOR_FUNC) {
2974
2975                         bnx2x_acquire_phy_lock(sc);
2976                         /* save nig interrupt mask */
2977                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2978
2979                         /* If nig_mask is not set, no need to call the update function */
2980                         if (nig_mask) {
2981                                 REG_WR(sc, nig_int_mask_addr, 0);
2982
2983                                 bnx2x_link_attn(sc);
2984                         }
2985
2986                         /* handle unicore attn? */
2987                 }
2988
2989                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2990                         PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
2991                 }
2992
2993                 if (asserted & GPIO_2_FUNC) {
2994                         PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
2995                 }
2996
2997                 if (asserted & GPIO_3_FUNC) {
2998                         PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
2999                 }
3000
3001                 if (asserted & GPIO_4_FUNC) {
3002                         PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3003                 }
3004
3005                 if (port == 0) {
3006                         if (asserted & ATTN_GENERAL_ATTN_1) {
3007                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3008                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3009                         }
3010                         if (asserted & ATTN_GENERAL_ATTN_2) {
3011                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3012                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3013                         }
3014                         if (asserted & ATTN_GENERAL_ATTN_3) {
3015                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3016                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3017                         }
3018                 } else {
3019                         if (asserted & ATTN_GENERAL_ATTN_4) {
3020                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3021                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3022                         }
3023                         if (asserted & ATTN_GENERAL_ATTN_5) {
3024                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3025                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3026                         }
3027                         if (asserted & ATTN_GENERAL_ATTN_6) {
3028                                 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3029                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3030                         }
3031                 }
3032         }
3033         /* hardwired */
3034         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3035                 reg_addr =
3036                     (HC_REG_COMMAND_REG + port * 32 +
3037                      COMMAND_REG_ATTN_BITS_SET);
3038         } else {
3039                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3040         }
3041
3042         PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3043                     asserted,
3044                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3045                     reg_addr);
3046         REG_WR(sc, reg_addr, asserted);
3047
3048         /* now set back the mask */
3049         if (asserted & ATTN_NIG_FOR_FUNC) {
3050                 /*
3051                  * Verify that IGU ack through BAR was written before restoring
3052                  * NIG mask. This loop should exit after 2-3 iterations max.
3053                  */
3054                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3055                         cnt = 0;
3056
3057                         do {
3058                                 igu_acked =
3059                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3060                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3061                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3062
3063                         if (!igu_acked) {
3064                                 PMD_DRV_LOG(ERR, sc,
3065                                             "Failed to verify IGU ack on time");
3066                         }
3067
3068                         mb();
3069                 }
3070
3071                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3072
3073                 bnx2x_release_phy_lock(sc);
3074         }
3075 }
3076
3077 static void
3078 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3079                      __rte_unused const char *blk)
3080 {
3081         PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3082 }
3083
3084 static int
3085 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3086                               uint8_t print)
3087 {
3088         uint32_t cur_bit = 0;
3089         int i = 0;
3090
3091         for (i = 0; sig; i++) {
3092                 cur_bit = ((uint32_t) 0x1 << i);
3093                 if (sig & cur_bit) {
3094                         switch (cur_bit) {
3095                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3096                                 if (print)
3097                                         bnx2x_print_next_block(sc, par_num++,
3098                                                              "BRB");
3099                                 break;
3100                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3101                                 if (print)
3102                                         bnx2x_print_next_block(sc, par_num++,
3103                                                              "PARSER");
3104                                 break;
3105                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3106                                 if (print)
3107                                         bnx2x_print_next_block(sc, par_num++,
3108                                                              "TSDM");
3109                                 break;
3110                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3111                                 if (print)
3112                                         bnx2x_print_next_block(sc, par_num++,
3113                                                              "SEARCHER");
3114                                 break;
3115                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3116                                 if (print)
3117                                         bnx2x_print_next_block(sc, par_num++,
3118                                                              "TCM");
3119                                 break;
3120                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3121                                 if (print)
3122                                         bnx2x_print_next_block(sc, par_num++,
3123                                                              "TSEMI");
3124                                 break;
3125                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3126                                 if (print)
3127                                         bnx2x_print_next_block(sc, par_num++,
3128                                                              "XPB");
3129                                 break;
3130                         }
3131
3132                         /* Clear the bit */
3133                         sig &= ~cur_bit;
3134                 }
3135         }
3136
3137         return par_num;
3138 }
3139
3140 static int
3141 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3142                               uint8_t * global, uint8_t print)
3143 {
3144         int i = 0;
3145         uint32_t cur_bit = 0;
3146         for (i = 0; sig; i++) {
3147                 cur_bit = ((uint32_t) 0x1 << i);
3148                 if (sig & cur_bit) {
3149                         switch (cur_bit) {
3150                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3151                                 if (print)
3152                                         bnx2x_print_next_block(sc, par_num++,
3153                                                              "PBF");
3154                                 break;
3155                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3156                                 if (print)
3157                                         bnx2x_print_next_block(sc, par_num++,
3158                                                              "QM");
3159                                 break;
3160                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3161                                 if (print)
3162                                         bnx2x_print_next_block(sc, par_num++,
3163                                                              "TM");
3164                                 break;
3165                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3166                                 if (print)
3167                                         bnx2x_print_next_block(sc, par_num++,
3168                                                              "XSDM");
3169                                 break;
3170                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3171                                 if (print)
3172                                         bnx2x_print_next_block(sc, par_num++,
3173                                                              "XCM");
3174                                 break;
3175                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3176                                 if (print)
3177                                         bnx2x_print_next_block(sc, par_num++,
3178                                                              "XSEMI");
3179                                 break;
3180                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3181                                 if (print)
3182                                         bnx2x_print_next_block(sc, par_num++,
3183                                                              "DOORBELLQ");
3184                                 break;
3185                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3186                                 if (print)
3187                                         bnx2x_print_next_block(sc, par_num++,
3188                                                              "NIG");
3189                                 break;
3190                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3191                                 if (print)
3192                                         bnx2x_print_next_block(sc, par_num++,
3193                                                              "VAUX PCI CORE");
3194                                 *global = TRUE;
3195                                 break;
3196                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3197                                 if (print)
3198                                         bnx2x_print_next_block(sc, par_num++,
3199                                                              "DEBUG");
3200                                 break;
3201                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3202                                 if (print)
3203                                         bnx2x_print_next_block(sc, par_num++,
3204                                                              "USDM");
3205                                 break;
3206                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3207                                 if (print)
3208                                         bnx2x_print_next_block(sc, par_num++,
3209                                                              "UCM");
3210                                 break;
3211                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3212                                 if (print)
3213                                         bnx2x_print_next_block(sc, par_num++,
3214                                                              "USEMI");
3215                                 break;
3216                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3217                                 if (print)
3218                                         bnx2x_print_next_block(sc, par_num++,
3219                                                              "UPB");
3220                                 break;
3221                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3222                                 if (print)
3223                                         bnx2x_print_next_block(sc, par_num++,
3224                                                              "CSDM");
3225                                 break;
3226                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3227                                 if (print)
3228                                         bnx2x_print_next_block(sc, par_num++,
3229                                                              "CCM");
3230                                 break;
3231                         }
3232
3233                         /* Clear the bit */
3234                         sig &= ~cur_bit;
3235                 }
3236         }
3237
3238         return par_num;
3239 }
3240
3241 static int
3242 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3243                               uint8_t print)
3244 {
3245         uint32_t cur_bit = 0;
3246         int i = 0;
3247
3248         for (i = 0; sig; i++) {
3249                 cur_bit = ((uint32_t) 0x1 << i);
3250                 if (sig & cur_bit) {
3251                         switch (cur_bit) {
3252                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3253                                 if (print)
3254                                         bnx2x_print_next_block(sc, par_num++,
3255                                                              "CSEMI");
3256                                 break;
3257                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3258                                 if (print)
3259                                         bnx2x_print_next_block(sc, par_num++,
3260                                                              "PXP");
3261                                 break;
3262                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3263                                 if (print)
3264                                         bnx2x_print_next_block(sc, par_num++,
3265                                                              "PXPPCICLOCKCLIENT");
3266                                 break;
3267                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3268                                 if (print)
3269                                         bnx2x_print_next_block(sc, par_num++,
3270                                                              "CFC");
3271                                 break;
3272                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3273                                 if (print)
3274                                         bnx2x_print_next_block(sc, par_num++,
3275                                                              "CDU");
3276                                 break;
3277                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3278                                 if (print)
3279                                         bnx2x_print_next_block(sc, par_num++,
3280                                                              "DMAE");
3281                                 break;
3282                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3283                                 if (print)
3284                                         bnx2x_print_next_block(sc, par_num++,
3285                                                              "IGU");
3286                                 break;
3287                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3288                                 if (print)
3289                                         bnx2x_print_next_block(sc, par_num++,
3290                                                              "MISC");
3291                                 break;
3292                         }
3293
3294                         /* Clear the bit */
3295                         sig &= ~cur_bit;
3296                 }
3297         }
3298
3299         return par_num;
3300 }
3301
3302 static int
3303 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3304                               uint8_t * global, uint8_t print)
3305 {
3306         uint32_t cur_bit = 0;
3307         int i = 0;
3308
3309         for (i = 0; sig; i++) {
3310                 cur_bit = ((uint32_t) 0x1 << i);
3311                 if (sig & cur_bit) {
3312                         switch (cur_bit) {
3313                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3314                                 if (print)
3315                                         bnx2x_print_next_block(sc, par_num++,
3316                                                              "MCP ROM");
3317                                 *global = TRUE;
3318                                 break;
3319                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3320                                 if (print)
3321                                         bnx2x_print_next_block(sc, par_num++,
3322                                                              "MCP UMP RX");
3323                                 *global = TRUE;
3324                                 break;
3325                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3326                                 if (print)
3327                                         bnx2x_print_next_block(sc, par_num++,
3328                                                              "MCP UMP TX");
3329                                 *global = TRUE;
3330                                 break;
3331                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3332                                 if (print)
3333                                         bnx2x_print_next_block(sc, par_num++,
3334                                                              "MCP SCPAD");
3335                                 *global = TRUE;
3336                                 break;
3337                         }
3338
3339                         /* Clear the bit */
3340                         sig &= ~cur_bit;
3341                 }
3342         }
3343
3344         return par_num;
3345 }
3346
3347 static int
3348 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3349                               uint8_t print)
3350 {
3351         uint32_t cur_bit = 0;
3352         int i = 0;
3353
3354         for (i = 0; sig; i++) {
3355                 cur_bit = ((uint32_t) 0x1 << i);
3356                 if (sig & cur_bit) {
3357                         switch (cur_bit) {
3358                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3359                                 if (print)
3360                                         bnx2x_print_next_block(sc, par_num++,
3361                                                              "PGLUE_B");
3362                                 break;
3363                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3364                                 if (print)
3365                                         bnx2x_print_next_block(sc, par_num++,
3366                                                              "ATC");
3367                                 break;
3368                         }
3369
3370                         /* Clear the bit */
3371                         sig &= ~cur_bit;
3372                 }
3373         }
3374
3375         return par_num;
3376 }
3377
3378 static uint8_t
3379 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3380                 uint32_t * sig)
3381 {
3382         int par_num = 0;
3383
3384         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3385             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3386             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3387             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3388             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3389                 PMD_DRV_LOG(ERR, sc,
3390                             "Parity error: HW block parity attention:"
3391                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3392                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3393                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3394                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3395                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3396                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3397
3398                 if (print)
3399                         PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3400
3401                 par_num =
3402                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3403                                                   HW_PRTY_ASSERT_SET_0,
3404                                                   par_num, print);
3405                 par_num =
3406                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3407                                                   HW_PRTY_ASSERT_SET_1,
3408                                                   par_num, global, print);
3409                 par_num =
3410                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3411                                                   HW_PRTY_ASSERT_SET_2,
3412                                                   par_num, print);
3413                 par_num =
3414                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3415                                                   HW_PRTY_ASSERT_SET_3,
3416                                                   par_num, global, print);
3417                 par_num =
3418                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3419                                                   HW_PRTY_ASSERT_SET_4,
3420                                                   par_num, print);
3421
3422                 if (print)
3423                         PMD_DRV_LOG(INFO, sc, "");
3424
3425                 return TRUE;
3426         }
3427
3428         return FALSE;
3429 }
3430
3431 static uint8_t
3432 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3433 {
3434         struct attn_route attn = { {0} };
3435         int port = SC_PORT(sc);
3436
3437         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3438         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3439         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3440         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3441
3442         if (!CHIP_IS_E1x(sc))
3443                 attn.sig[4] =
3444                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3445
3446         return bnx2x_parity_attn(sc, global, print, attn.sig);
3447 }
3448
3449 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3450 {
3451         uint32_t val;
3452
3453         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3454                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3455                 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3456                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3457                         PMD_DRV_LOG(INFO, sc,
3458                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3459                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3460                         PMD_DRV_LOG(INFO, sc,
3461                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3462                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3463                         PMD_DRV_LOG(INFO, sc,
3464                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3465                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3466                         PMD_DRV_LOG(INFO, sc,
3467                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3468                 if (val &
3469                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3470                         PMD_DRV_LOG(INFO, sc,
3471                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3472                 if (val &
3473                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3474                         PMD_DRV_LOG(INFO, sc,
3475                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3476                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3477                         PMD_DRV_LOG(INFO, sc,
3478                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3479                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3480                         PMD_DRV_LOG(INFO, sc,
3481                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3482                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3483                         PMD_DRV_LOG(INFO, sc,
3484                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3485         }
3486
3487         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3488                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3489                 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3490                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3491                         PMD_DRV_LOG(INFO, sc,
3492                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3493                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3494                         PMD_DRV_LOG(INFO, sc,
3495                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3496                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3497                         PMD_DRV_LOG(INFO, sc,
3498                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3499                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3500                         PMD_DRV_LOG(INFO, sc,
3501                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3502                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3503                         PMD_DRV_LOG(INFO, sc,
3504                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3505                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3506                         PMD_DRV_LOG(INFO, sc,
3507                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3508         }
3509
3510         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3511                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3512                 PMD_DRV_LOG(INFO, sc,
3513                             "ERROR: FATAL parity attention set4 0x%08x",
3514                             (uint32_t) (attn &
3515                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3516                                          |
3517                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3518         }
3519 }
3520
3521 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3522 {
3523         int port = SC_PORT(sc);
3524
3525         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3526 }
3527
3528 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3529 {
3530         int port = SC_PORT(sc);
3531
3532         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3533 }
3534
3535 /*
3536  * called due to MCP event (on pmf):
3537  *   reread new bandwidth configuration
3538  *   configure FW
3539  *   notify others function about the change
3540  */
3541 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3542 {
3543         if (sc->link_vars.link_up) {
3544                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3545                 bnx2x_link_sync_notify(sc);
3546         }
3547
3548         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3549 }
3550
3551 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3552 {
3553         bnx2x_config_mf_bw(sc);
3554         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3555 }
3556
3557 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3558 {
3559         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3560 }
3561
3562 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3563
3564 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3565 {
3566         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3567
3568         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3569                 ETH_STAT_INFO_VERSION_LEN);
3570
3571         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3572                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3573                                               ether_stat->mac_local + MAC_PAD,
3574                                               MAC_PAD, ETH_ALEN);
3575
3576         ether_stat->mtu_size = sc->mtu;
3577
3578         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3579         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3580
3581         ether_stat->txq_size = sc->tx_ring_size;
3582         ether_stat->rxq_size = sc->rx_ring_size;
3583 }
3584
3585 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3586 {
3587         enum drv_info_opcode op_code;
3588         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3589
3590         /* if drv_info version supported by MFW doesn't match - send NACK */
3591         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3592                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3593                 return;
3594         }
3595
3596         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3597                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3598
3599         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3600
3601         switch (op_code) {
3602         case ETH_STATS_OPCODE:
3603                 bnx2x_drv_info_ether_stat(sc);
3604                 break;
3605         case FCOE_STATS_OPCODE:
3606         case ISCSI_STATS_OPCODE:
3607         default:
3608                 /* if op code isn't supported - send NACK */
3609                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3610                 return;
3611         }
3612
3613         /*
3614          * If we got drv_info attn from MFW then these fields are defined in
3615          * shmem2 for sure
3616          */
3617         SHMEM2_WR(sc, drv_info_host_addr_lo,
3618                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3619         SHMEM2_WR(sc, drv_info_host_addr_hi,
3620                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3621
3622         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3623 }
3624
3625 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3626 {
3627         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3628 /*
3629  * This is the only place besides the function initialization
3630  * where the sc->flags can change so it is done without any
3631  * locks
3632  */
3633                 if (sc->devinfo.
3634                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3635                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3636                         sc->flags |= BNX2X_MF_FUNC_DIS;
3637                         bnx2x_e1h_disable(sc);
3638                 } else {
3639                         PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3640                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3641                         bnx2x_e1h_enable(sc);
3642                 }
3643                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3644         }
3645
3646         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3647                 bnx2x_config_mf_bw(sc);
3648                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3649         }
3650
3651         /* Report results to MCP */
3652         if (dcc_event)
3653                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3654         else
3655                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3656 }
3657
3658 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3659 {
3660         int port = SC_PORT(sc);
3661         uint32_t val;
3662
3663         sc->port.pmf = 1;
3664
3665         /*
3666          * We need the mb() to ensure the ordering between the writing to
3667          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3668          */
3669         mb();
3670
3671         /* enable nig attention */
3672         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3673         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3674                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3675                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3676         } else if (!CHIP_IS_E1x(sc)) {
3677                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3678                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3679         }
3680
3681         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3682 }
3683
3684 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3685 {
3686         char last_idx;
3687         int i, rc = 0;
3688         __rte_unused uint32_t row0, row1, row2, row3;
3689
3690         /* XSTORM */
3691         last_idx =
3692             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3693         if (last_idx)
3694                 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3695
3696         /* print the asserts */
3697         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3698
3699                 row0 =
3700                     REG_RD(sc,
3701                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3702                 row1 =
3703                     REG_RD(sc,
3704                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3705                            4);
3706                 row2 =
3707                     REG_RD(sc,
3708                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3709                            8);
3710                 row3 =
3711                     REG_RD(sc,
3712                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3713                            12);
3714
3715                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3716                         PMD_DRV_LOG(ERR, sc,
3717                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3718                                     i, row3, row2, row1, row0);
3719                         rc++;
3720                 } else {
3721                         break;
3722                 }
3723         }
3724
3725         /* TSTORM */
3726         last_idx =
3727             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3728         if (last_idx) {
3729                 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3730         }
3731
3732         /* print the asserts */
3733         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3734
3735                 row0 =
3736                     REG_RD(sc,
3737                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3738                 row1 =
3739                     REG_RD(sc,
3740                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3741                            4);
3742                 row2 =
3743                     REG_RD(sc,
3744                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3745                            8);
3746                 row3 =
3747                     REG_RD(sc,
3748                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3749                            12);
3750
3751                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3752                         PMD_DRV_LOG(ERR, sc,
3753                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3754                                     i, row3, row2, row1, row0);
3755                         rc++;
3756                 } else {
3757                         break;
3758                 }
3759         }
3760
3761         /* CSTORM */
3762         last_idx =
3763             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3764         if (last_idx) {
3765                 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3766         }
3767
3768         /* print the asserts */
3769         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3770
3771                 row0 =
3772                     REG_RD(sc,
3773                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3774                 row1 =
3775                     REG_RD(sc,
3776                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3777                            4);
3778                 row2 =
3779                     REG_RD(sc,
3780                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3781                            8);
3782                 row3 =
3783                     REG_RD(sc,
3784                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3785                            12);
3786
3787                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3788                         PMD_DRV_LOG(ERR, sc,
3789                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3790                                     i, row3, row2, row1, row0);
3791                         rc++;
3792                 } else {
3793                         break;
3794                 }
3795         }
3796
3797         /* USTORM */
3798         last_idx =
3799             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3800         if (last_idx) {
3801                 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3802         }
3803
3804         /* print the asserts */
3805         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3806
3807                 row0 =
3808                     REG_RD(sc,
3809                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3810                 row1 =
3811                     REG_RD(sc,
3812                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3813                            4);
3814                 row2 =
3815                     REG_RD(sc,
3816                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3817                            8);
3818                 row3 =
3819                     REG_RD(sc,
3820                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3821                            12);
3822
3823                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3824                         PMD_DRV_LOG(ERR, sc,
3825                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3826                                     i, row3, row2, row1, row0);
3827                         rc++;
3828                 } else {
3829                         break;
3830                 }
3831         }
3832
3833         return rc;
3834 }
3835
3836 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3837 {
3838         int func = SC_FUNC(sc);
3839         uint32_t val;
3840
3841         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3842
3843                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3844
3845                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3846                         bnx2x_read_mf_cfg(sc);
3847                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3848                             MFCFG_RD(sc,
3849                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3850                         val =
3851                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3852
3853                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3854                                 bnx2x_dcc_event(sc,
3855                                               (val &
3856                                                DRV_STATUS_DCC_EVENT_MASK));
3857
3858                         if (val & DRV_STATUS_SET_MF_BW)
3859                                 bnx2x_set_mf_bw(sc);
3860
3861                         if (val & DRV_STATUS_DRV_INFO_REQ)
3862                                 bnx2x_handle_drv_info_req(sc);
3863
3864                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3865                                 bnx2x_pmf_update(sc);
3866
3867                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3868                                 bnx2x_handle_eee_event(sc);
3869
3870                         if (sc->link_vars.periodic_flags &
3871                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3872                                 /* sync with link */
3873                                 bnx2x_acquire_phy_lock(sc);
3874                                 sc->link_vars.periodic_flags &=
3875                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3876                                 bnx2x_release_phy_lock(sc);
3877                                 if (IS_MF(sc)) {
3878                                         bnx2x_link_sync_notify(sc);
3879                                 }
3880                                 bnx2x_link_report(sc);
3881                         }
3882
3883                         /*
3884                          * Always call it here: bnx2x_link_report() will
3885                          * prevent the link indication duplication.
3886                          */
3887                         bnx2x_link_status_update(sc);
3888
3889                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3890
3891                         PMD_DRV_LOG(ERR, sc, "MC assert!");
3892                         bnx2x_mc_assert(sc);
3893                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3894                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3895                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3896                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3897                         rte_panic("MC assert!");
3898
3899                 } else if (attn & BNX2X_MCP_ASSERT) {
3900
3901                         PMD_DRV_LOG(ERR, sc, "MCP assert!");
3902                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3903
3904                 } else {
3905                         PMD_DRV_LOG(ERR, sc,
3906                                     "Unknown HW assert! (attn 0x%08x)", attn);
3907                 }
3908         }
3909
3910         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3911                 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3912                 if (attn & BNX2X_GRC_TIMEOUT) {
3913                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3914                         PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3915                 }
3916                 if (attn & BNX2X_GRC_RSV) {
3917                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3918                         PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3919                 }
3920                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3921         }
3922 }
3923
3924 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3925 {
3926         int port = SC_PORT(sc);
3927         int reg_offset;
3928         uint32_t val0, mask0, val1, mask1;
3929         uint32_t val;
3930
3931         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3932                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3933                 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3934 /* CFC error attention */
3935                 if (val & 0x2) {
3936                         PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3937                 }
3938         }
3939
3940         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3941                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3942                 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3943 /* RQ_USDMDP_FIFO_OVERFLOW */
3944                 if (val & 0x18000) {
3945                         PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3946                 }
3947
3948                 if (!CHIP_IS_E1x(sc)) {
3949                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3950                         PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3951                 }
3952         }
3953 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3954 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3955
3956         if (attn & AEU_PXP2_HW_INT_BIT) {
3957 /*  CQ47854 workaround do not panic on
3958  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3959  */
3960                 if (!CHIP_IS_E1x(sc)) {
3961                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3962                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3963                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3964                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3965                         /*
3966                          * If the only PXP2_EOP_ERROR_BIT is set in
3967                          * STS0 and STS1 - clear it
3968                          *
3969                          * probably we lose additional attentions between
3970                          * STS0 and STS_CLR0, in this case user will not
3971                          * be notified about them
3972                          */
3973                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3974                             !(val1 & mask1))
3975                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3976
3977                         /* print the register, since no one can restore it */
3978                         PMD_DRV_LOG(ERR, sc,
3979                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3980
3981                         /*
3982                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3983                          * then notify
3984                          */
3985                         if (val0 & PXP2_EOP_ERROR_BIT) {
3986                                 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
3987
3988                                 /*
3989                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3990                                  * set then clear attention from PXP2 block without panic
3991                                  */
3992                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3993                                     ((val1 & mask1) == 0))
3994                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3995                         }
3996                 }
3997         }
3998
3999         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4000                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4001                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4002
4003                 val = REG_RD(sc, reg_offset);
4004                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4005                 REG_WR(sc, reg_offset, val);
4006
4007                 PMD_DRV_LOG(ERR, sc,
4008                             "FATAL HW block attention set2 0x%x",
4009                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4010                 rte_panic("HW block attention set2");
4011         }
4012 }
4013
4014 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4015 {
4016         int port = SC_PORT(sc);
4017         int reg_offset;
4018         uint32_t val;
4019
4020         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4021                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4022                 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4023 /* DORQ discard attention */
4024                 if (val & 0x2) {
4025                         PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4026                 }
4027         }
4028
4029         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4030                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4031                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4032
4033                 val = REG_RD(sc, reg_offset);
4034                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4035                 REG_WR(sc, reg_offset, val);
4036
4037                 PMD_DRV_LOG(ERR, sc,
4038                             "FATAL HW block attention set1 0x%08x",
4039                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4040                 rte_panic("HW block attention set1");
4041         }
4042 }
4043
4044 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4045 {
4046         int port = SC_PORT(sc);
4047         int reg_offset;
4048         uint32_t val;
4049
4050         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4051             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4052
4053         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4054                 val = REG_RD(sc, reg_offset);
4055                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4056                 REG_WR(sc, reg_offset, val);
4057
4058                 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4059
4060 /* Fan failure attention */
4061                 elink_hw_reset_phy(&sc->link_params);
4062                 bnx2x_fan_failure(sc);
4063         }
4064
4065         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4066                 bnx2x_acquire_phy_lock(sc);
4067                 elink_handle_module_detect_int(&sc->link_params);
4068                 bnx2x_release_phy_lock(sc);
4069         }
4070
4071         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4072                 val = REG_RD(sc, reg_offset);
4073                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4074                 REG_WR(sc, reg_offset, val);
4075
4076                 rte_panic("FATAL HW block attention set0 0x%lx",
4077                           (attn & HW_INTERRUT_ASSERT_SET_0));
4078         }
4079 }
4080
4081 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4082 {
4083         struct attn_route attn;
4084         struct attn_route *group_mask;
4085         int port = SC_PORT(sc);
4086         int index;
4087         uint32_t reg_addr;
4088         uint32_t val;
4089         uint32_t aeu_mask;
4090         uint8_t global = FALSE;
4091
4092         /*
4093          * Need to take HW lock because MCP or other port might also
4094          * try to handle this event.
4095          */
4096         bnx2x_acquire_alr(sc);
4097
4098         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4099                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4100
4101 /* disable HW interrupts */
4102                 bnx2x_int_disable(sc);
4103                 bnx2x_release_alr(sc);
4104                 return;
4105         }
4106
4107         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4108         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4109         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4110         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4111         if (!CHIP_IS_E1x(sc)) {
4112                 attn.sig[4] =
4113                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4114         } else {
4115                 attn.sig[4] = 0;
4116         }
4117
4118         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4119                 if (deasserted & (1 << index)) {
4120                         group_mask = &sc->attn_group[index];
4121
4122                         bnx2x_attn_int_deasserted4(sc,
4123                                                  attn.
4124                                                  sig[4] & group_mask->sig[4]);
4125                         bnx2x_attn_int_deasserted3(sc,
4126                                                  attn.
4127                                                  sig[3] & group_mask->sig[3]);
4128                         bnx2x_attn_int_deasserted1(sc,
4129                                                  attn.
4130                                                  sig[1] & group_mask->sig[1]);
4131                         bnx2x_attn_int_deasserted2(sc,
4132                                                  attn.
4133                                                  sig[2] & group_mask->sig[2]);
4134                         bnx2x_attn_int_deasserted0(sc,
4135                                                  attn.
4136                                                  sig[0] & group_mask->sig[0]);
4137                 }
4138         }
4139
4140         bnx2x_release_alr(sc);
4141
4142         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4143                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4144                             COMMAND_REG_ATTN_BITS_CLR);
4145         } else {
4146                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4147         }
4148
4149         val = ~deasserted;
4150         PMD_DRV_LOG(DEBUG, sc,
4151                     "about to mask 0x%08x at %s addr 0x%08x", val,
4152                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4153                     reg_addr);
4154         REG_WR(sc, reg_addr, val);
4155
4156         if (~sc->attn_state & deasserted) {
4157                 PMD_DRV_LOG(ERR, sc, "IGU error");
4158         }
4159
4160         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4161             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4162
4163         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4164
4165         aeu_mask = REG_RD(sc, reg_addr);
4166
4167         aeu_mask |= (deasserted & 0x3ff);
4168
4169         REG_WR(sc, reg_addr, aeu_mask);
4170         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4171
4172         sc->attn_state &= ~deasserted;
4173 }
4174
4175 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4176 {
4177         /* read local copy of bits */
4178         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4179         uint32_t attn_ack =
4180             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4181         uint32_t attn_state = sc->attn_state;
4182
4183         /* look for changed bits */
4184         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4185         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4186
4187         PMD_DRV_LOG(DEBUG, sc,
4188                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4189                     attn_bits, attn_ack, asserted, deasserted);
4190
4191         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4192                 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4193         }
4194
4195         /* handle bits that were raised */
4196         if (asserted) {
4197                 bnx2x_attn_int_asserted(sc, asserted);
4198         }
4199
4200         if (deasserted) {
4201                 bnx2x_attn_int_deasserted(sc, deasserted);
4202         }
4203 }
4204
4205 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4206 {
4207         struct host_sp_status_block *def_sb = sc->def_sb;
4208         uint16_t rc = 0;
4209
4210         mb();                   /* status block is written to by the chip */
4211
4212         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4213                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4214                 rc |= BNX2X_DEF_SB_ATT_IDX;
4215         }
4216
4217         if (sc->def_idx != def_sb->sp_sb.running_index) {
4218                 sc->def_idx = def_sb->sp_sb.running_index;
4219                 rc |= BNX2X_DEF_SB_IDX;
4220         }
4221
4222         mb();
4223
4224         return rc;
4225 }
4226
4227 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4228                                                           uint32_t cid)
4229 {
4230         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4231 }
4232
4233 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4234 {
4235         struct ecore_mcast_ramrod_params rparam;
4236         int rc;
4237
4238         memset(&rparam, 0, sizeof(rparam));
4239
4240         rparam.mcast_obj = &sc->mcast_obj;
4241
4242         /* clear pending state for the last command */
4243         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4244
4245         /* if there are pending mcast commands - send them */
4246         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4247                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4248                 if (rc < 0) {
4249                         PMD_DRV_LOG(INFO, sc,
4250                                     "Failed to send pending mcast commands (%d)",
4251                                     rc);
4252                 }
4253         }
4254 }
4255
4256 static void
4257 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4258 {
4259         unsigned long ramrod_flags = 0;
4260         int rc = 0;
4261         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4262         struct ecore_vlan_mac_obj *vlan_mac_obj;
4263
4264         /* always push next commands out, don't wait here */
4265         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4266
4267         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4268         case ECORE_FILTER_MAC_PENDING:
4269                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4270                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4271                 break;
4272
4273         case ECORE_FILTER_MCAST_PENDING:
4274                 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4275                 bnx2x_handle_mcast_eqe(sc);
4276                 return;
4277
4278         default:
4279                 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4280                             elem->message.data.eth_event.echo);
4281                 return;
4282         }
4283
4284         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4285
4286         if (rc < 0) {
4287                 PMD_DRV_LOG(NOTICE, sc,
4288                             "Failed to schedule new commands (%d)", rc);
4289         } else if (rc > 0) {
4290                 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4291         }
4292 }
4293
4294 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4295 {
4296         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4297
4298         /* send rx_mode command again if was requested */
4299         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4300                 bnx2x_set_storm_rx_mode(sc);
4301         }
4302 }
4303
4304 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4305 {
4306         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4307         wmb();                  /* keep prod updates ordered */
4308 }
4309
4310 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4311 {
4312         uint16_t hw_cons, sw_cons, sw_prod;
4313         union event_ring_elem *elem;
4314         uint8_t echo;
4315         uint32_t cid;
4316         uint8_t opcode;
4317         int spqe_cnt = 0;
4318         struct ecore_queue_sp_obj *q_obj;
4319         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4320         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4321
4322         hw_cons = le16toh(*sc->eq_cons_sb);
4323
4324         /*
4325          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4326          * when we get to the next-page we need to adjust so the loop
4327          * condition below will be met. The next element is the size of a
4328          * regular element and hence incrementing by 1
4329          */
4330         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4331                 hw_cons++;
4332         }
4333
4334         /*
4335          * This function may never run in parallel with itself for a
4336          * specific sc and no need for a read memory barrier here.
4337          */
4338         sw_cons = sc->eq_cons;
4339         sw_prod = sc->eq_prod;
4340
4341         for (;
4342              sw_cons != hw_cons;
4343              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4344
4345                 elem = &sc->eq[EQ_DESC(sw_cons)];
4346
4347 /* elem CID originates from FW, actually LE */
4348                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4349                 opcode = elem->message.opcode;
4350
4351 /* handle eq element */
4352                 switch (opcode) {
4353                 case EVENT_RING_OPCODE_STAT_QUERY:
4354                         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4355                                     sc->stats_comp++);
4356                         /* nothing to do with stats comp */
4357                         goto next_spqe;
4358
4359                 case EVENT_RING_OPCODE_CFC_DEL:
4360                         /* handle according to cid range */
4361                         /* we may want to verify here that the sc state is HALTING */
4362                         PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4363                                     cid);
4364                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4365                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4366                                 break;
4367                         }
4368                         goto next_spqe;
4369
4370                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4371                         PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4372                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4373                                 break;
4374                         }
4375                         goto next_spqe;
4376
4377                 case EVENT_RING_OPCODE_START_TRAFFIC:
4378                         PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4379                         if (f_obj->complete_cmd
4380                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4381                                 break;
4382                         }
4383                         goto next_spqe;
4384
4385                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4386                         echo = elem->message.data.function_update_event.echo;
4387                         if (echo == SWITCH_UPDATE) {
4388                                 PMD_DRV_LOG(DEBUG, sc,
4389                                             "got FUNC_SWITCH_UPDATE ramrod");
4390                                 if (f_obj->complete_cmd(sc, f_obj,
4391                                                         ECORE_F_CMD_SWITCH_UPDATE))
4392                                 {
4393                                         break;
4394                                 }
4395                         } else {
4396                                 PMD_DRV_LOG(DEBUG, sc,
4397                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4398                                 f_obj->complete_cmd(sc, f_obj,
4399                                                     ECORE_F_CMD_AFEX_UPDATE);
4400                         }
4401                         goto next_spqe;
4402
4403                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4404                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4405                         if (q_obj->complete_cmd(sc, q_obj,
4406                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4407                                 break;
4408                         }
4409                         goto next_spqe;
4410
4411                 case EVENT_RING_OPCODE_FUNCTION_START:
4412                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4413                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4414                                 break;
4415                         }
4416                         goto next_spqe;
4417
4418                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4419                         PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4420                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4421                                 break;
4422                         }
4423                         goto next_spqe;
4424                 }
4425
4426                 switch (opcode | sc->state) {
4427                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4428                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4429                         cid =
4430                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4431                         PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4432                                     cid);
4433                         rss_raw->clear_pending(rss_raw);
4434                         break;
4435
4436                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4437                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4438                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4439                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4440                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4441                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4442                         PMD_DRV_LOG(DEBUG, sc,
4443                                     "got (un)set mac ramrod");
4444                         bnx2x_handle_classification_eqe(sc, elem);
4445                         break;
4446
4447                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4448                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4449                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4450                         PMD_DRV_LOG(DEBUG, sc,
4451                                     "got mcast ramrod");
4452                         bnx2x_handle_mcast_eqe(sc);
4453                         break;
4454
4455                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4456                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4457                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4458                         PMD_DRV_LOG(DEBUG, sc,
4459                                     "got rx_mode ramrod");
4460                         bnx2x_handle_rx_mode_eqe(sc);
4461                         break;
4462
4463                 default:
4464                         /* unknown event log error and continue */
4465                         PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4466                                     elem->message.opcode, sc->state);
4467                 }
4468
4469 next_spqe:
4470                 spqe_cnt++;
4471         }                       /* for */
4472
4473         mb();
4474         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4475
4476         sc->eq_cons = sw_cons;
4477         sc->eq_prod = sw_prod;
4478
4479         /* make sure that above mem writes were issued towards the memory */
4480         wmb();
4481
4482         /* update producer */
4483         bnx2x_update_eq_prod(sc, sc->eq_prod);
4484 }
4485
4486 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4487 {
4488         uint16_t status;
4489         int rc = 0;
4490
4491         PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4492
4493         /* what work needs to be performed? */
4494         status = bnx2x_update_dsb_idx(sc);
4495
4496         PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4497
4498         /* HW attentions */
4499         if (status & BNX2X_DEF_SB_ATT_IDX) {
4500                 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4501                 bnx2x_attn_int(sc);
4502                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4503                 rc = 1;
4504         }
4505
4506         /* SP events: STAT_QUERY and others */
4507         if (status & BNX2X_DEF_SB_IDX) {
4508 /* handle EQ completions */
4509                 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4510                 bnx2x_eq_int(sc);
4511                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4512                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4513                 status &= ~BNX2X_DEF_SB_IDX;
4514         }
4515
4516         /* if status is non zero then something went wrong */
4517         if (unlikely(status)) {
4518                 PMD_DRV_LOG(INFO, sc,
4519                             "Got an unknown SP interrupt! (0x%04x)", status);
4520         }
4521
4522         /* ack status block only if something was actually handled */
4523         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4524                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4525
4526         return rc;
4527 }
4528
4529 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4530 {
4531         struct bnx2x_softc *sc = fp->sc;
4532         uint8_t more_rx = FALSE;
4533
4534         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4535                                "---> FP TASK QUEUE (%d) <--", fp->index);
4536
4537         /* update the fastpath index */
4538         bnx2x_update_fp_sb_idx(fp);
4539
4540         if (scan_fp) {
4541                 if (bnx2x_has_rx_work(fp)) {
4542                         more_rx = bnx2x_rxeof(sc, fp);
4543                 }
4544
4545                 if (more_rx) {
4546                         /* still more work to do */
4547                         bnx2x_handle_fp_tq(fp, scan_fp);
4548                         return;
4549                 }
4550         }
4551
4552         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4553                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4554 }
4555
4556 /*
4557  * Legacy interrupt entry point.
4558  *
4559  * Verifies that the controller generated the interrupt and
4560  * then calls a separate routine to handle the various
4561  * interrupt causes: link, RX, and TX.
4562  */
4563 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4564 {
4565         struct bnx2x_fastpath *fp;
4566         uint32_t status, mask;
4567         int i, rc = 0;
4568
4569         /*
4570          * 0 for ustorm, 1 for cstorm
4571          * the bits returned from ack_int() are 0-15
4572          * bit 0 = attention status block
4573          * bit 1 = fast path status block
4574          * a mask of 0x2 or more = tx/rx event
4575          * a mask of 1 = slow path event
4576          */
4577
4578         status = bnx2x_ack_int(sc);
4579
4580         /* the interrupt is not for us */
4581         if (unlikely(status == 0)) {
4582                 return 0;
4583         }
4584
4585         PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4586         //bnx2x_dump_status_block(sc);
4587
4588         FOR_EACH_ETH_QUEUE(sc, i) {
4589                 fp = &sc->fp[i];
4590                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4591                 if (status & mask) {
4592                 /* acknowledge and disable further fastpath interrupts */
4593                         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4594                                      0, IGU_INT_DISABLE, 0);
4595                         bnx2x_handle_fp_tq(fp, scan_fp);
4596                         status &= ~mask;
4597                 }
4598         }
4599
4600         if (unlikely(status & 0x1)) {
4601                 /* acknowledge and disable further slowpath interrupts */
4602                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4603                              0, IGU_INT_DISABLE, 0);
4604                 rc = bnx2x_handle_sp_tq(sc);
4605                 status &= ~0x1;
4606         }
4607
4608         if (unlikely(status)) {
4609                 PMD_DRV_LOG(WARNING, sc,
4610                             "Unexpected fastpath status (0x%08x)!", status);
4611         }
4612
4613         return rc;
4614 }
4615
4616 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4617 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4618 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4619 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4620 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4621 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4622 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4623 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4624 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4625
4626 static struct
4627 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4628         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4629         .init_hw_cmn = bnx2x_init_hw_common,
4630         .init_hw_port = bnx2x_init_hw_port,
4631         .init_hw_func = bnx2x_init_hw_func,
4632
4633         .reset_hw_cmn = bnx2x_reset_common,
4634         .reset_hw_port = bnx2x_reset_port,
4635         .reset_hw_func = bnx2x_reset_func,
4636
4637         .init_fw = bnx2x_init_firmware,
4638         .release_fw = bnx2x_release_firmware,
4639 };
4640
4641 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4642 {
4643         sc->dmae_ready = 0;
4644
4645         PMD_INIT_FUNC_TRACE(sc);
4646
4647         ecore_init_func_obj(sc,
4648                             &sc->func_obj,
4649                             BNX2X_SP(sc, func_rdata),
4650                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4651                             BNX2X_SP(sc, func_afex_rdata),
4652                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4653                             &bnx2x_func_sp_drv);
4654 }
4655
4656 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4657 {
4658         struct ecore_func_state_params func_params = { NULL };
4659         int rc;
4660
4661         PMD_INIT_FUNC_TRACE(sc);
4662
4663         /* prepare the parameters for function state transitions */
4664         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4665
4666         func_params.f_obj = &sc->func_obj;
4667         func_params.cmd = ECORE_F_CMD_HW_INIT;
4668
4669         func_params.params.hw_init.load_phase = load_code;
4670
4671         /*
4672          * Via a plethora of function pointers, we will eventually reach
4673          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4674          */
4675         rc = ecore_func_state_change(sc, &func_params);
4676
4677         return rc;
4678 }
4679
4680 static void
4681 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4682 {
4683         uint32_t i;
4684
4685         if (!(len % 4) && !(addr % 4)) {
4686                 for (i = 0; i < len; i += 4) {
4687                         REG_WR(sc, (addr + i), fill);
4688                 }
4689         } else {
4690                 for (i = 0; i < len; i++) {
4691                         REG_WR8(sc, (addr + i), fill);
4692                 }
4693         }
4694 }
4695
4696 /* writes FP SP data to FW - data_size in dwords */
4697 static void
4698 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4699                   uint32_t data_size)
4700 {
4701         uint32_t index;
4702
4703         for (index = 0; index < data_size; index++) {
4704                 REG_WR(sc,
4705                        (BAR_CSTRORM_INTMEM +
4706                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4707                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4708         }
4709 }
4710
4711 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4712 {
4713         struct hc_status_block_data_e2 sb_data_e2;
4714         struct hc_status_block_data_e1x sb_data_e1x;
4715         uint32_t *sb_data_p;
4716         uint32_t data_size = 0;
4717
4718         if (!CHIP_IS_E1x(sc)) {
4719                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4720                 sb_data_e2.common.state = SB_DISABLED;
4721                 sb_data_e2.common.p_func.vf_valid = FALSE;
4722                 sb_data_p = (uint32_t *) & sb_data_e2;
4723                 data_size = (sizeof(struct hc_status_block_data_e2) /
4724                              sizeof(uint32_t));
4725         } else {
4726                 memset(&sb_data_e1x, 0,
4727                        sizeof(struct hc_status_block_data_e1x));
4728                 sb_data_e1x.common.state = SB_DISABLED;
4729                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4730                 sb_data_p = (uint32_t *) & sb_data_e1x;
4731                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4732                              sizeof(uint32_t));
4733         }
4734
4735         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4736
4737         bnx2x_fill(sc,
4738                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4739                  CSTORM_STATUS_BLOCK_SIZE);
4740         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4741                  0, CSTORM_SYNC_BLOCK_SIZE);
4742 }
4743
4744 static void
4745 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4746                   struct hc_sp_status_block_data *sp_sb_data)
4747 {
4748         uint32_t i;
4749
4750         for (i = 0;
4751              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4752              i++) {
4753                 REG_WR(sc,
4754                        (BAR_CSTRORM_INTMEM +
4755                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4756                         (i * sizeof(uint32_t))),
4757                        *((uint32_t *) sp_sb_data + i));
4758         }
4759 }
4760
4761 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4762 {
4763         struct hc_sp_status_block_data sp_sb_data;
4764
4765         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4766
4767         sp_sb_data.state = SB_DISABLED;
4768         sp_sb_data.p_func.vf_valid = FALSE;
4769
4770         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4771
4772         bnx2x_fill(sc,
4773                  (BAR_CSTRORM_INTMEM +
4774                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4775                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4776         bnx2x_fill(sc,
4777                  (BAR_CSTRORM_INTMEM +
4778                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4779                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4780 }
4781
4782 static void
4783 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4784                              int igu_seg_id)
4785 {
4786         hc_sm->igu_sb_id = igu_sb_id;
4787         hc_sm->igu_seg_id = igu_seg_id;
4788         hc_sm->timer_value = 0xFF;
4789         hc_sm->time_to_expire = 0xFFFFFFFF;
4790 }
4791
4792 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4793 {
4794         /* zero out state machine indices */
4795
4796         /* rx indices */
4797         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4798
4799         /* tx indices */
4800         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4801         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4802         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4803         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4804
4805         /* map indices */
4806
4807         /* rx indices */
4808         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4809             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4810
4811         /* tx indices */
4812         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4813             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4814         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4815             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4816         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4817             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4818         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4819             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4820 }
4821
4822 static void
4823 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4824             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4825 {
4826         struct hc_status_block_data_e2 sb_data_e2;
4827         struct hc_status_block_data_e1x sb_data_e1x;
4828         struct hc_status_block_sm *hc_sm_p;
4829         uint32_t *sb_data_p;
4830         int igu_seg_id;
4831         int data_size;
4832
4833         if (CHIP_INT_MODE_IS_BC(sc)) {
4834                 igu_seg_id = HC_SEG_ACCESS_NORM;
4835         } else {
4836                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4837         }
4838
4839         bnx2x_zero_fp_sb(sc, fw_sb_id);
4840
4841         if (!CHIP_IS_E1x(sc)) {
4842                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4843                 sb_data_e2.common.state = SB_ENABLED;
4844                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4845                 sb_data_e2.common.p_func.vf_id = vfid;
4846                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4847                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4848                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4849                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4850                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4851                 hc_sm_p = sb_data_e2.common.state_machine;
4852                 sb_data_p = (uint32_t *) & sb_data_e2;
4853                 data_size = (sizeof(struct hc_status_block_data_e2) /
4854                              sizeof(uint32_t));
4855                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4856         } else {
4857                 memset(&sb_data_e1x, 0,
4858                        sizeof(struct hc_status_block_data_e1x));
4859                 sb_data_e1x.common.state = SB_ENABLED;
4860                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4861                 sb_data_e1x.common.p_func.vf_id = 0xff;
4862                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4863                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4864                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4865                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4866                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4867                 hc_sm_p = sb_data_e1x.common.state_machine;
4868                 sb_data_p = (uint32_t *) & sb_data_e1x;
4869                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4870                              sizeof(uint32_t));
4871                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4872         }
4873
4874         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4875         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4876
4877         /* write indices to HW - PCI guarantees endianity of regpairs */
4878         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4879 }
4880
4881 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4882 {
4883         if (CHIP_IS_E1x(fp->sc)) {
4884                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4885         } else {
4886                 return fp->cl_id;
4887         }
4888 }
4889
4890 static uint32_t
4891 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4892 {
4893         uint32_t offset = BAR_USTRORM_INTMEM;
4894
4895         if (IS_VF(sc)) {
4896                 return PXP_VF_ADDR_USDM_QUEUES_START +
4897                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4898                          sizeof(struct ustorm_queue_zone_data));
4899         } else if (!CHIP_IS_E1x(sc)) {
4900                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4901         } else {
4902                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4903         }
4904
4905         return offset;
4906 }
4907
4908 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4909 {
4910         struct bnx2x_fastpath *fp = &sc->fp[idx];
4911         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4912         unsigned long q_type = 0;
4913         int cos;
4914
4915         fp->sc = sc;
4916         fp->index = idx;
4917
4918         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4919         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4920
4921         if (CHIP_IS_E1x(sc))
4922                 fp->cl_id = SC_L_ID(sc) + idx;
4923         else
4924 /* want client ID same as IGU SB ID for non-E1 */
4925                 fp->cl_id = fp->igu_sb_id;
4926         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4927
4928         /* setup sb indices */
4929         if (!CHIP_IS_E1x(sc)) {
4930                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4931                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4932         } else {
4933                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4934                 fp->sb_running_index =
4935                     fp->status_block.e1x_sb->sb.running_index;
4936         }
4937
4938         /* init shortcut */
4939         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4940
4941         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4942
4943         for (cos = 0; cos < sc->max_cos; cos++) {
4944                 cids[cos] = idx;
4945         }
4946         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4947
4948         /* nothing more for a VF to do */
4949         if (IS_VF(sc)) {
4950                 return;
4951         }
4952
4953         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4954                     fp->fw_sb_id, fp->igu_sb_id);
4955
4956         bnx2x_update_fp_sb_idx(fp);
4957
4958         /* Configure Queue State object */
4959         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4960         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4961
4962         ecore_init_queue_obj(sc,
4963                              &sc->sp_objs[idx].q_obj,
4964                              fp->cl_id,
4965                              cids,
4966                              sc->max_cos,
4967                              SC_FUNC(sc),
4968                              BNX2X_SP(sc, q_rdata),
4969                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4970                              q_type);
4971
4972         /* configure classification DBs */
4973         ecore_init_mac_obj(sc,
4974                            &sc->sp_objs[idx].mac_obj,
4975                            fp->cl_id,
4976                            idx,
4977                            SC_FUNC(sc),
4978                            BNX2X_SP(sc, mac_rdata),
4979                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4980                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4981                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4982 }
4983
4984 static void
4985 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4986                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4987 {
4988         union ustorm_eth_rx_producers rx_prods;
4989         uint32_t i;
4990
4991         /* update producers */
4992         rx_prods.prod.bd_prod = rx_bd_prod;
4993         rx_prods.prod.cqe_prod = rx_cq_prod;
4994         rx_prods.prod.reserved = 0;
4995
4996         /*
4997          * Make sure that the BD and SGE data is updated before updating the
4998          * producers since FW might read the BD/SGE right after the producer
4999          * is updated.
5000          * This is only applicable for weak-ordered memory model archs such
5001          * as IA-64. The following barrier is also mandatory since FW will
5002          * assumes BDs must have buffers.
5003          */
5004         wmb();
5005
5006         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5007                 REG_WR(sc,
5008                        (fp->ustorm_rx_prods_offset + (i * 4)),
5009                        rx_prods.raw_data[i]);
5010         }
5011
5012         wmb();                  /* keep prod updates ordered */
5013 }
5014
5015 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5016 {
5017         struct bnx2x_fastpath *fp;
5018         int i;
5019         struct bnx2x_rx_queue *rxq;
5020
5021         for (i = 0; i < sc->num_queues; i++) {
5022                 fp = &sc->fp[i];
5023                 rxq = sc->rx_queues[fp->index];
5024                 if (!rxq) {
5025                         PMD_RX_LOG(ERR, "RX queue is NULL");
5026                         return;
5027                 }
5028
5029                 rxq->rx_bd_head = 0;
5030                 rxq->rx_bd_tail = rxq->nb_rx_desc;
5031                 rxq->rx_cq_head = 0;
5032                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5033                 *fp->rx_cq_cons_sb = 0;
5034
5035                 /*
5036                  * Activate the BD ring...
5037                  * Warning, this will generate an interrupt (to the TSTORM)
5038                  * so this can only be done after the chip is initialized
5039                  */
5040                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5041
5042                 if (i != 0) {
5043                         continue;
5044                 }
5045         }
5046 }
5047
5048 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5049 {
5050         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5051
5052         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5053         fp->tx_db.data.zero_fill1 = 0;
5054         fp->tx_db.data.prod = 0;
5055
5056         if (!txq) {
5057                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5058                 return;
5059         }
5060
5061         txq->tx_pkt_tail = 0;
5062         txq->tx_pkt_head = 0;
5063         txq->tx_bd_tail = 0;
5064         txq->tx_bd_head = 0;
5065 }
5066
5067 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5068 {
5069         int i;
5070
5071         for (i = 0; i < sc->num_queues; i++) {
5072                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5073         }
5074 }
5075
5076 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5077 {
5078         struct host_sp_status_block *def_sb = sc->def_sb;
5079         rte_iova_t mapping = sc->def_sb_dma.paddr;
5080         int igu_sp_sb_index;
5081         int igu_seg_id;
5082         int port = SC_PORT(sc);
5083         int func = SC_FUNC(sc);
5084         int reg_offset, reg_offset_en5;
5085         uint64_t section;
5086         int index, sindex;
5087         struct hc_sp_status_block_data sp_sb_data;
5088
5089         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5090
5091         if (CHIP_INT_MODE_IS_BC(sc)) {
5092                 igu_sp_sb_index = DEF_SB_IGU_ID;
5093                 igu_seg_id = HC_SEG_ACCESS_DEF;
5094         } else {
5095                 igu_sp_sb_index = sc->igu_dsb_id;
5096                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5097         }
5098
5099         /* attentions */
5100         section = ((uint64_t) mapping +
5101                    offsetof(struct host_sp_status_block, atten_status_block));
5102         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5103         sc->attn_state = 0;
5104
5105         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5106             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5107
5108         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5109             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5110
5111         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5112 /* take care of sig[0]..sig[4] */
5113                 for (sindex = 0; sindex < 4; sindex++) {
5114                         sc->attn_group[index].sig[sindex] =
5115                             REG_RD(sc,
5116                                    (reg_offset + (sindex * 0x4) +
5117                                     (0x10 * index)));
5118                 }
5119
5120                 if (!CHIP_IS_E1x(sc)) {
5121                         /*
5122                          * enable5 is separate from the rest of the registers,
5123                          * and the address skip is 4 and not 16 between the
5124                          * different groups
5125                          */
5126                         sc->attn_group[index].sig[4] =
5127                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5128                 } else {
5129                         sc->attn_group[index].sig[4] = 0;
5130                 }
5131         }
5132
5133         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5134                 reg_offset =
5135                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5136                 REG_WR(sc, reg_offset, U64_LO(section));
5137                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5138         } else if (!CHIP_IS_E1x(sc)) {
5139                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5140                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5141         }
5142
5143         section = ((uint64_t) mapping +
5144                    offsetof(struct host_sp_status_block, sp_sb));
5145
5146         bnx2x_zero_sp_sb(sc);
5147
5148         /* PCI guarantees endianity of regpair */
5149         sp_sb_data.state = SB_ENABLED;
5150         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5151         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5152         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5153         sp_sb_data.igu_seg_id = igu_seg_id;
5154         sp_sb_data.p_func.pf_id = func;
5155         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5156         sp_sb_data.p_func.vf_id = 0xff;
5157
5158         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5159
5160         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5161 }
5162
5163 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5164 {
5165         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5166         sc->spq_prod_idx = 0;
5167         sc->dsb_sp_prod =
5168             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5169         sc->spq_prod_bd = sc->spq;
5170         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5171 }
5172
5173 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5174 {
5175         union event_ring_elem *elem;
5176         int i;
5177
5178         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5179                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5180
5181                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5182                                                          BNX2X_PAGE_SIZE *
5183                                                          (i % NUM_EQ_PAGES)));
5184                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5185                                                          BNX2X_PAGE_SIZE *
5186                                                          (i % NUM_EQ_PAGES)));
5187         }
5188
5189         sc->eq_cons = 0;
5190         sc->eq_prod = NUM_EQ_DESC;
5191         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5192
5193         atomic_store_rel_long(&sc->eq_spq_left,
5194                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5195                                    NUM_EQ_DESC) - 1));
5196 }
5197
5198 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5199 {
5200         int i;
5201
5202         if (IS_MF_SI(sc)) {
5203 /*
5204  * In switch independent mode, the TSTORM needs to accept
5205  * packets that failed classification, since approximate match
5206  * mac addresses aren't written to NIG LLH.
5207  */
5208                 REG_WR8(sc,
5209                         (BAR_TSTRORM_INTMEM +
5210                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5211         } else
5212                 REG_WR8(sc,
5213                         (BAR_TSTRORM_INTMEM +
5214                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5215
5216         /*
5217          * Zero this manually as its initialization is currently missing
5218          * in the initTool.
5219          */
5220         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5221                 REG_WR(sc,
5222                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5223                        0);
5224         }
5225
5226         if (!CHIP_IS_E1x(sc)) {
5227                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5228                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5229                         HC_IGU_NBC_MODE);
5230         }
5231 }
5232
5233 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5234 {
5235         switch (load_code) {
5236         case FW_MSG_CODE_DRV_LOAD_COMMON:
5237         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5238                 bnx2x_init_internal_common(sc);
5239                 /* no break */
5240
5241         case FW_MSG_CODE_DRV_LOAD_PORT:
5242                 /* nothing to do */
5243                 /* no break */
5244
5245         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5246                 /* internal memory per function is initialized inside bnx2x_pf_init */
5247                 break;
5248
5249         default:
5250                 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5251                             load_code);
5252                 break;
5253         }
5254 }
5255
5256 static void
5257 storm_memset_func_cfg(struct bnx2x_softc *sc,
5258                       struct tstorm_eth_function_common_config *tcfg,
5259                       uint16_t abs_fid)
5260 {
5261         uint32_t addr;
5262         size_t size;
5263
5264         addr = (BAR_TSTRORM_INTMEM +
5265                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5266         size = sizeof(struct tstorm_eth_function_common_config);
5267         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5268 }
5269
5270 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5271 {
5272         struct tstorm_eth_function_common_config tcfg = { 0 };
5273
5274         if (CHIP_IS_E1x(sc)) {
5275                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5276         }
5277
5278         /* Enable the function in the FW */
5279         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5280         storm_memset_func_en(sc, p->func_id, 1);
5281
5282         /* spq */
5283         if (p->func_flgs & FUNC_FLG_SPQ) {
5284                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5285                 REG_WR(sc,
5286                        (XSEM_REG_FAST_MEMORY +
5287                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5288         }
5289 }
5290
5291 /*
5292  * Calculates the sum of vn_min_rates.
5293  * It's needed for further normalizing of the min_rates.
5294  * Returns:
5295  *   sum of vn_min_rates.
5296  *     or
5297  *   0 - if all the min_rates are 0.
5298  * In the later case fainess algorithm should be deactivated.
5299  * If all min rates are not zero then those that are zeroes will be set to 1.
5300  */
5301 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5302 {
5303         uint32_t vn_cfg;
5304         uint32_t vn_min_rate;
5305         int all_zero = 1;
5306         int vn;
5307
5308         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5309                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5310                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5311                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5312
5313                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5314                         /* skip hidden VNs */
5315                         vn_min_rate = 0;
5316                 } else if (!vn_min_rate) {
5317                         /* If min rate is zero - set it to 100 */
5318                         vn_min_rate = DEF_MIN_RATE;
5319                 } else {
5320                         all_zero = 0;
5321                 }
5322
5323                 input->vnic_min_rate[vn] = vn_min_rate;
5324         }
5325
5326         /* if ETS or all min rates are zeros - disable fairness */
5327         if (all_zero) {
5328                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5329         } else {
5330                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5331         }
5332 }
5333
5334 static uint16_t
5335 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5336 {
5337         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5338                             FUNC_MF_CFG_MAX_BW_SHIFT);
5339
5340         if (!max_cfg) {
5341                 PMD_DRV_LOG(DEBUG, sc,
5342                             "Max BW configured to 0 - using 100 instead");
5343                 max_cfg = 100;
5344         }
5345
5346         return max_cfg;
5347 }
5348
5349 static void
5350 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5351 {
5352         uint16_t vn_max_rate;
5353         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5354         uint32_t max_cfg;
5355
5356         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5357                 vn_max_rate = 0;
5358         } else {
5359                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5360
5361                 if (IS_MF_SI(sc)) {
5362                         /* max_cfg in percents of linkspeed */
5363                         vn_max_rate =
5364                             ((sc->link_vars.line_speed * max_cfg) / 100);
5365                 } else {        /* SD modes */
5366                         /* max_cfg is absolute in 100Mb units */
5367                         vn_max_rate = (max_cfg * 100);
5368                 }
5369         }
5370
5371         input->vnic_max_rate[vn] = vn_max_rate;
5372 }
5373
5374 static void
5375 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5376 {
5377         struct cmng_init_input input;
5378         int vn;
5379
5380         memset(&input, 0, sizeof(struct cmng_init_input));
5381
5382         input.port_rate = sc->link_vars.line_speed;
5383
5384         if (cmng_type == CMNG_FNS_MINMAX) {
5385 /* read mf conf from shmem */
5386                 if (read_cfg) {
5387                         bnx2x_read_mf_cfg(sc);
5388                 }
5389
5390 /* get VN min rate and enable fairness if not 0 */
5391                 bnx2x_calc_vn_min(sc, &input);
5392
5393 /* get VN max rate */
5394                 if (sc->port.pmf) {
5395                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5396                                 bnx2x_calc_vn_max(sc, vn, &input);
5397                         }
5398                 }
5399
5400 /* always enable rate shaping and fairness */
5401                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5402
5403                 ecore_init_cmng(&input, &sc->cmng);
5404                 return;
5405         }
5406 }
5407
5408 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5409 {
5410         if (CHIP_REV_IS_SLOW(sc)) {
5411                 return CMNG_FNS_NONE;
5412         }
5413
5414         if (IS_MF(sc)) {
5415                 return CMNG_FNS_MINMAX;
5416         }
5417
5418         return CMNG_FNS_NONE;
5419 }
5420
5421 static void
5422 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5423 {
5424         int vn;
5425         int func;
5426         uint32_t addr;
5427         size_t size;
5428
5429         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5430         size = sizeof(struct cmng_struct_per_port);
5431         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5432
5433         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5434                 func = func_by_vn(sc, vn);
5435
5436                 addr = (BAR_XSTRORM_INTMEM +
5437                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5438                 size = sizeof(struct rate_shaping_vars_per_vn);
5439                 ecore_storm_memset_struct(sc, addr, size,
5440                                           (uint32_t *) & cmng->
5441                                           vnic.vnic_max_rate[vn]);
5442
5443                 addr = (BAR_XSTRORM_INTMEM +
5444                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5445                 size = sizeof(struct fairness_vars_per_vn);
5446                 ecore_storm_memset_struct(sc, addr, size,
5447                                           (uint32_t *) & cmng->
5448                                           vnic.vnic_min_rate[vn]);
5449         }
5450 }
5451
5452 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5453 {
5454         struct bnx2x_func_init_params func_init;
5455         struct event_ring_data eq_data;
5456         uint16_t flags;
5457
5458         memset(&eq_data, 0, sizeof(struct event_ring_data));
5459         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5460
5461         if (!CHIP_IS_E1x(sc)) {
5462 /* reset IGU PF statistics: MSIX + ATTN */
5463 /* PF */
5464                 REG_WR(sc,
5465                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5466                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5467                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5468                          4)), 0);
5469 /* ATTN */
5470                 REG_WR(sc,
5471                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5472                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5473                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5474                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5475                          4)), 0);
5476         }
5477
5478         /* function setup flags */
5479         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5480
5481         func_init.func_flgs = flags;
5482         func_init.pf_id = SC_FUNC(sc);
5483         func_init.func_id = SC_FUNC(sc);
5484         func_init.spq_map = sc->spq_dma.paddr;
5485         func_init.spq_prod = sc->spq_prod_idx;
5486
5487         bnx2x_func_init(sc, &func_init);
5488
5489         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5490
5491         /*
5492          * Congestion management values depend on the link rate.
5493          * There is no active link so initial link rate is set to 10Gbps.
5494          * When the link comes up the congestion management values are
5495          * re-calculated according to the actual link rate.
5496          */
5497         sc->link_vars.line_speed = SPEED_10000;
5498         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5499
5500         /* Only the PMF sets the HW */
5501         if (sc->port.pmf) {
5502                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5503         }
5504
5505         /* init Event Queue - PCI bus guarantees correct endainity */
5506         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5507         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5508         eq_data.producer = sc->eq_prod;
5509         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5510         eq_data.sb_id = DEF_SB_ID;
5511         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5512 }
5513
5514 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5515 {
5516         int port = SC_PORT(sc);
5517         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5518         uint32_t val = REG_RD(sc, addr);
5519         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5520             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5521         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5522         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5523
5524         if (msix) {
5525                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5526                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5527                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5528                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5529                 if (single_msix) {
5530                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5531                 }
5532         } else if (msi) {
5533                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5534                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5535                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5536                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5537         } else {
5538                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5539                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5540                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5541                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5542
5543                 REG_WR(sc, addr, val);
5544
5545                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5546         }
5547
5548         REG_WR(sc, addr, val);
5549
5550         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5551         mb();
5552
5553         /* init leading/trailing edge */
5554         if (IS_MF(sc)) {
5555                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5556                 if (sc->port.pmf) {
5557                         /* enable nig and gpio3 attention */
5558                         val |= 0x1100;
5559                 }
5560         } else {
5561                 val = 0xffff;
5562         }
5563
5564         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5565         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5566
5567         /* make sure that interrupts are indeed enabled from here on */
5568         mb();
5569 }
5570
5571 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5572 {
5573         uint32_t val;
5574         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5575             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5576         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5577         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5578
5579         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5580
5581         if (msix) {
5582                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5583                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5584                 if (single_msix) {
5585                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5586                 }
5587         } else if (msi) {
5588                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5589                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5590                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5591         } else {
5592                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5593                 val |= (IGU_PF_CONF_INT_LINE_EN |
5594                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5595         }
5596
5597         /* clean previous status - need to configure igu prior to ack */
5598         if ((!msix) || single_msix) {
5599                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5600                 bnx2x_ack_int(sc);
5601         }
5602
5603         val |= IGU_PF_CONF_FUNC_EN;
5604
5605         PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5606                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5607
5608         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5609
5610         mb();
5611
5612         /* init leading/trailing edge */
5613         if (IS_MF(sc)) {
5614                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5615                 if (sc->port.pmf) {
5616                         /* enable nig and gpio3 attention */
5617                         val |= 0x1100;
5618                 }
5619         } else {
5620                 val = 0xffff;
5621         }
5622
5623         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5624         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5625
5626         /* make sure that interrupts are indeed enabled from here on */
5627         mb();
5628 }
5629
5630 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5631 {
5632         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5633                 bnx2x_hc_int_enable(sc);
5634         } else {
5635                 bnx2x_igu_int_enable(sc);
5636         }
5637 }
5638
5639 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5640 {
5641         int port = SC_PORT(sc);
5642         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5643         uint32_t val = REG_RD(sc, addr);
5644
5645         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5646                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5647                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5648         /* flush all outstanding writes */
5649         mb();
5650
5651         REG_WR(sc, addr, val);
5652         if (REG_RD(sc, addr) != val) {
5653                 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5654         }
5655 }
5656
5657 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5658 {
5659         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5660
5661         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5662                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5663
5664         PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5665
5666         /* flush all outstanding writes */
5667         mb();
5668
5669         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5670         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5671                 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5672         }
5673 }
5674
5675 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5676 {
5677         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5678                 bnx2x_hc_int_disable(sc);
5679         } else {
5680                 bnx2x_igu_int_disable(sc);
5681         }
5682 }
5683
5684 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5685 {
5686         int i;
5687
5688         PMD_INIT_FUNC_TRACE(sc);
5689
5690         for (i = 0; i < sc->num_queues; i++) {
5691                 bnx2x_init_eth_fp(sc, i);
5692         }
5693
5694         rmb();                  /* ensure status block indices were read */
5695
5696         bnx2x_init_rx_rings(sc);
5697         bnx2x_init_tx_rings(sc);
5698
5699         if (IS_VF(sc)) {
5700                 bnx2x_memset_stats(sc);
5701                 return;
5702         }
5703
5704         /* initialize MOD_ABS interrupts */
5705         elink_init_mod_abs_int(sc, &sc->link_vars,
5706                                sc->devinfo.chip_id,
5707                                sc->devinfo.shmem_base,
5708                                sc->devinfo.shmem2_base, SC_PORT(sc));
5709
5710         bnx2x_init_def_sb(sc);
5711         bnx2x_update_dsb_idx(sc);
5712         bnx2x_init_sp_ring(sc);
5713         bnx2x_init_eq_ring(sc);
5714         bnx2x_init_internal(sc, load_code);
5715         bnx2x_pf_init(sc);
5716         bnx2x_stats_init(sc);
5717
5718         /* flush all before enabling interrupts */
5719         mb();
5720
5721         bnx2x_int_enable(sc);
5722
5723         /* check for SPIO5 */
5724         bnx2x_attn_int_deasserted0(sc,
5725                                  REG_RD(sc,
5726                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5727                                          SC_PORT(sc) * 4)) &
5728                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5729 }
5730
5731 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5732 {
5733         /* mcast rules must be added to tx if tx switching is enabled */
5734         ecore_obj_type o_type;
5735         if (sc->flags & BNX2X_TX_SWITCHING)
5736                 o_type = ECORE_OBJ_TYPE_RX_TX;
5737         else
5738                 o_type = ECORE_OBJ_TYPE_RX;
5739
5740         /* RX_MODE controlling object */
5741         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5742
5743         /* multicast configuration controlling object */
5744         ecore_init_mcast_obj(sc,
5745                              &sc->mcast_obj,
5746                              sc->fp[0].cl_id,
5747                              sc->fp[0].index,
5748                              SC_FUNC(sc),
5749                              SC_FUNC(sc),
5750                              BNX2X_SP(sc, mcast_rdata),
5751                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5752                              ECORE_FILTER_MCAST_PENDING,
5753                              &sc->sp_state, o_type);
5754
5755         /* Setup CAM credit pools */
5756         ecore_init_mac_credit_pool(sc,
5757                                    &sc->macs_pool,
5758                                    SC_FUNC(sc),
5759                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5760                                    VNICS_PER_PATH(sc));
5761
5762         ecore_init_vlan_credit_pool(sc,
5763                                     &sc->vlans_pool,
5764                                     SC_ABS_FUNC(sc) >> 1,
5765                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5766                                     VNICS_PER_PATH(sc));
5767
5768         /* RSS configuration object */
5769         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5770                                   sc->fp[0].cl_id,
5771                                   sc->fp[0].index,
5772                                   SC_FUNC(sc),
5773                                   SC_FUNC(sc),
5774                                   BNX2X_SP(sc, rss_rdata),
5775                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5776                                   ECORE_FILTER_RSS_CONF_PENDING,
5777                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5778 }
5779
5780 /*
5781  * Initialize the function. This must be called before sending CLIENT_SETUP
5782  * for the first client.
5783  */
5784 static int bnx2x_func_start(struct bnx2x_softc *sc)
5785 {
5786         struct ecore_func_state_params func_params = { NULL };
5787         struct ecore_func_start_params *start_params =
5788             &func_params.params.start;
5789
5790         /* Prepare parameters for function state transitions */
5791         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5792
5793         func_params.f_obj = &sc->func_obj;
5794         func_params.cmd = ECORE_F_CMD_START;
5795
5796         /* Function parameters */
5797         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5798         start_params->sd_vlan_tag = OVLAN(sc);
5799
5800         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5801                 start_params->network_cos_mode = STATIC_COS;
5802         } else {                /* CHIP_IS_E1X */
5803                 start_params->network_cos_mode = FW_WRR;
5804         }
5805
5806         start_params->gre_tunnel_mode = 0;
5807         start_params->gre_tunnel_rss = 0;
5808
5809         return ecore_func_state_change(sc, &func_params);
5810 }
5811
5812 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5813 {
5814         uint16_t pmcsr;
5815
5816         /* If there is no power capability, silently succeed */
5817         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5818                 PMD_DRV_LOG(WARNING, sc, "No power capability");
5819                 return 0;
5820         }
5821
5822         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5823                  2);
5824
5825         switch (state) {
5826         case PCI_PM_D0:
5827                 pci_write_word(sc,
5828                                (sc->devinfo.pcie_pm_cap_reg +
5829                                 PCIR_POWER_STATUS),
5830                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5831
5832                 if (pmcsr & PCIM_PSTAT_DMASK) {
5833                         /* delay required during transition out of D3hot */
5834                         DELAY(20000);
5835                 }
5836
5837                 break;
5838
5839         case PCI_PM_D3hot:
5840                 /* don't shut down the power for emulation and FPGA */
5841                 if (CHIP_REV_IS_SLOW(sc)) {
5842                         return 0;
5843                 }
5844
5845                 pmcsr &= ~PCIM_PSTAT_DMASK;
5846                 pmcsr |= PCIM_PSTAT_D3;
5847
5848                 if (sc->wol) {
5849                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5850                 }
5851
5852                 pci_write_long(sc,
5853                                (sc->devinfo.pcie_pm_cap_reg +
5854                                 PCIR_POWER_STATUS), pmcsr);
5855
5856                 /*
5857                  * No more memory access after this point until device is brought back
5858                  * to D0 state.
5859                  */
5860                 break;
5861
5862         default:
5863                 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5864                             state);
5865                 return -1;
5866         }
5867
5868         return 0;
5869 }
5870
5871 /* return true if succeeded to acquire the lock */
5872 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5873 {
5874         uint32_t lock_status;
5875         uint32_t resource_bit = (1 << resource);
5876         int func = SC_FUNC(sc);
5877         uint32_t hw_lock_control_reg;
5878
5879         /* Validating that the resource is within range */
5880         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5881                 PMD_DRV_LOG(INFO, sc,
5882                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5883                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5884                 return FALSE;
5885         }
5886
5887         if (func <= 5) {
5888                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5889         } else {
5890                 hw_lock_control_reg =
5891                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5892         }
5893
5894         /* try to acquire the lock */
5895         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5896         lock_status = REG_RD(sc, hw_lock_control_reg);
5897         if (lock_status & resource_bit) {
5898                 return TRUE;
5899         }
5900
5901         PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5902
5903         return FALSE;
5904 }
5905
5906 /*
5907  * Get the recovery leader resource id according to the engine this function
5908  * belongs to. Currently only only 2 engines is supported.
5909  */
5910 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5911 {
5912         if (SC_PATH(sc)) {
5913                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5914         } else {
5915                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5916         }
5917 }
5918
5919 /* try to acquire a leader lock for current engine */
5920 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5921 {
5922         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5923 }
5924
5925 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5926 {
5927         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5928 }
5929
5930 /* close gates #2, #3 and #4 */
5931 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5932 {
5933         uint32_t val;
5934
5935         /* gates #2 and #4a are closed/opened */
5936         /* #4 */
5937         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5938         /* #2 */
5939         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5940
5941         /* #3 */
5942         if (CHIP_IS_E1x(sc)) {
5943 /* prevent interrupts from HC on both ports */
5944                 val = REG_RD(sc, HC_REG_CONFIG_1);
5945                 if (close)
5946                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5947                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5948                 else
5949                         REG_WR(sc, HC_REG_CONFIG_1,
5950                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5951
5952                 val = REG_RD(sc, HC_REG_CONFIG_0);
5953                 if (close)
5954                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5955                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5956                 else
5957                         REG_WR(sc, HC_REG_CONFIG_0,
5958                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5959
5960         } else {
5961 /* Prevent incoming interrupts in IGU */
5962                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5963
5964                 if (close)
5965                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5966                                (val & ~(uint32_t)
5967                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5968                 else
5969                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5970                                (val |
5971                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5972         }
5973
5974         wmb();
5975 }
5976
5977 /* poll for pending writes bit, it should get cleared in no more than 1s */
5978 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5979 {
5980         uint32_t cnt = 1000;
5981         uint32_t pend_bits = 0;
5982
5983         do {
5984                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5985
5986                 if (pend_bits == 0) {
5987                         break;
5988                 }
5989
5990                 DELAY(1000);
5991         } while (cnt-- > 0);
5992
5993         if (cnt <= 0) {
5994                 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
5995                             pend_bits);
5996                 return -1;
5997         }
5998
5999         return 0;
6000 }
6001
6002 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
6003
6004 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6005 {
6006         /* Do some magic... */
6007         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6008         *magic_val = val & SHARED_MF_CLP_MAGIC;
6009         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6010 }
6011
6012 /* restore the value of the 'magic' bit */
6013 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6014 {
6015         /* Restore the 'magic' bit value... */
6016         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6017         MFCFG_WR(sc, shared_mf_config.clp_mb,
6018                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6019 }
6020
6021 /* prepare for MCP reset, takes care of CLP configurations */
6022 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6023 {
6024         uint32_t shmem;
6025         uint32_t validity_offset;
6026
6027         /* set `magic' bit in order to save MF config */
6028         bnx2x_clp_reset_prep(sc, magic_val);
6029
6030         /* get shmem offset */
6031         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6032         validity_offset =
6033             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6034
6035         /* Clear validity map flags */
6036         if (shmem > 0) {
6037                 REG_WR(sc, shmem + validity_offset, 0);
6038         }
6039 }
6040
6041 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
6042 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
6043
6044 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6045 {
6046         /* special handling for emulation and FPGA (10 times longer) */
6047         if (CHIP_REV_IS_SLOW(sc)) {
6048                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6049         } else {
6050                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6051         }
6052 }
6053
6054 /* initialize shmem_base and waits for validity signature to appear */
6055 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6056 {
6057         int cnt = 0;
6058         uint32_t val = 0;
6059
6060         do {
6061                 sc->devinfo.shmem_base =
6062                     sc->link_params.shmem_base =
6063                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6064
6065                 if (sc->devinfo.shmem_base) {
6066                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6067                         if (val & SHR_MEM_VALIDITY_MB)
6068                                 return 0;
6069                 }
6070
6071                 bnx2x_mcp_wait_one(sc);
6072
6073         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6074
6075         PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6076
6077         return -1;
6078 }
6079
6080 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6081 {
6082         int rc = bnx2x_init_shmem(sc);
6083
6084         /* Restore the `magic' bit value */
6085         bnx2x_clp_reset_done(sc, magic_val);
6086
6087         return rc;
6088 }
6089
6090 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6091 {
6092         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6093         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6094         wmb();
6095 }
6096
6097 /*
6098  * Reset the whole chip except for:
6099  *      - PCIE core
6100  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6101  *      - IGU
6102  *      - MISC (including AEU)
6103  *      - GRC
6104  *      - RBCN, RBCP
6105  */
6106 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6107 {
6108         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6109         uint32_t global_bits2, stay_reset2;
6110
6111         /*
6112          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6113          * (per chip) blocks.
6114          */
6115         global_bits2 =
6116             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6117             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6118
6119         /*
6120          * Don't reset the following blocks.
6121          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6122          *            reset, as in 4 port device they might still be owned
6123          *            by the MCP (there is only one leader per path).
6124          */
6125         not_reset_mask1 =
6126             MISC_REGISTERS_RESET_REG_1_RST_HC |
6127             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6128             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6129
6130         not_reset_mask2 =
6131             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6132             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6133             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6134             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6135             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6136             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6137             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6138             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6139             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6140             MISC_REGISTERS_RESET_REG_2_PGLC |
6141             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6142             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6143             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6144             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6145             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6146
6147         /*
6148          * Keep the following blocks in reset:
6149          *  - all xxMACs are handled by the elink code.
6150          */
6151         stay_reset2 =
6152             MISC_REGISTERS_RESET_REG_2_XMAC |
6153             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6154
6155         /* Full reset masks according to the chip */
6156         reset_mask1 = 0xffffffff;
6157
6158         if (CHIP_IS_E1H(sc))
6159                 reset_mask2 = 0x1ffff;
6160         else if (CHIP_IS_E2(sc))
6161                 reset_mask2 = 0xfffff;
6162         else                    /* CHIP_IS_E3 */
6163                 reset_mask2 = 0x3ffffff;
6164
6165         /* Don't reset global blocks unless we need to */
6166         if (!global)
6167                 reset_mask2 &= ~global_bits2;
6168
6169         /*
6170          * In case of attention in the QM, we need to reset PXP
6171          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6172          * because otherwise QM reset would release 'close the gates' shortly
6173          * before resetting the PXP, then the PSWRQ would send a write
6174          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6175          * read the payload data from PSWWR, but PSWWR would not
6176          * respond. The write queue in PGLUE would stuck, dmae commands
6177          * would not return. Therefore it's important to reset the second
6178          * reset register (containing the
6179          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6180          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6181          * bit).
6182          */
6183         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6184                reset_mask2 & (~not_reset_mask2));
6185
6186         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6187                reset_mask1 & (~not_reset_mask1));
6188
6189         mb();
6190         wmb();
6191
6192         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6193                reset_mask2 & (~stay_reset2));
6194
6195         mb();
6196         wmb();
6197
6198         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6199         wmb();
6200 }
6201
6202 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6203 {
6204         int cnt = 1000;
6205         uint32_t val = 0;
6206         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6207         uint32_t tags_63_32 = 0;
6208
6209         /* Empty the Tetris buffer, wait for 1s */
6210         do {
6211                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6212                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6213                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6214                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6215                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6216                 if (CHIP_IS_E3(sc)) {
6217                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6218                 }
6219
6220                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6221                     ((port_is_idle_0 & 0x1) == 0x1) &&
6222                     ((port_is_idle_1 & 0x1) == 0x1) &&
6223                     (pgl_exp_rom2 == 0xffffffff) &&
6224                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6225                         break;
6226                 DELAY(1000);
6227         } while (cnt-- > 0);
6228
6229         if (cnt <= 0) {
6230                 PMD_DRV_LOG(NOTICE, sc,
6231                             "ERROR: Tetris buffer didn't get empty or there "
6232                             "are still outstanding read requests after 1s! "
6233                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6234                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6235                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6236                             pgl_exp_rom2);
6237                 return -1;
6238         }
6239
6240         mb();
6241
6242         /* Close gates #2, #3 and #4 */
6243         bnx2x_set_234_gates(sc, TRUE);
6244
6245         /* Poll for IGU VQs for 57712 and newer chips */
6246         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6247                 return -1;
6248         }
6249
6250         /* clear "unprepared" bit */
6251         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6252         mb();
6253
6254         /* Make sure all is written to the chip before the reset */
6255         wmb();
6256
6257         /*
6258          * Wait for 1ms to empty GLUE and PCI-E core queues,
6259          * PSWHST, GRC and PSWRD Tetris buffer.
6260          */
6261         DELAY(1000);
6262
6263         /* Prepare to chip reset: */
6264         /* MCP */
6265         if (global) {
6266                 bnx2x_reset_mcp_prep(sc, &val);
6267         }
6268
6269         /* PXP */
6270         bnx2x_pxp_prep(sc);
6271         mb();
6272
6273         /* reset the chip */
6274         bnx2x_process_kill_chip_reset(sc, global);
6275         mb();
6276
6277         /* Recover after reset: */
6278         /* MCP */
6279         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6280                 return -1;
6281         }
6282
6283         /* Open the gates #2, #3 and #4 */
6284         bnx2x_set_234_gates(sc, FALSE);
6285
6286         return 0;
6287 }
6288
6289 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6290 {
6291         int rc = 0;
6292         uint8_t global = bnx2x_reset_is_global(sc);
6293         uint32_t load_code;
6294
6295         /*
6296          * If not going to reset MCP, load "fake" driver to reset HW while
6297          * driver is owner of the HW.
6298          */
6299         if (!global && !BNX2X_NOMCP(sc)) {
6300                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6301                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6302                 if (!load_code) {
6303                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6304                         rc = -1;
6305                         goto exit_leader_reset;
6306                 }
6307
6308                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6309                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6310                         PMD_DRV_LOG(NOTICE, sc,
6311                                     "MCP unexpected response, aborting");
6312                         rc = -1;
6313                         goto exit_leader_reset2;
6314                 }
6315
6316                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6317                 if (!load_code) {
6318                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6319                         rc = -1;
6320                         goto exit_leader_reset2;
6321                 }
6322         }
6323
6324         /* try to recover after the failure */
6325         if (bnx2x_process_kill(sc, global)) {
6326                 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6327                             SC_PATH(sc));
6328                 rc = -1;
6329                 goto exit_leader_reset2;
6330         }
6331
6332         /*
6333          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6334          * state.
6335          */
6336         bnx2x_set_reset_done(sc);
6337         if (global) {
6338                 bnx2x_clear_reset_global(sc);
6339         }
6340
6341 exit_leader_reset2:
6342
6343         /* unload "fake driver" if it was loaded */
6344         if (!global &&!BNX2X_NOMCP(sc)) {
6345                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6346                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6347         }
6348
6349 exit_leader_reset:
6350
6351         sc->is_leader = 0;
6352         bnx2x_release_leader_lock(sc);
6353
6354         mb();
6355         return rc;
6356 }
6357
6358 /*
6359  * prepare INIT transition, parameters configured:
6360  *   - HC configuration
6361  *   - Queue's CDU context
6362  */
6363 static void
6364 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6365                    struct ecore_queue_init_params *init_params)
6366 {
6367         uint8_t cos;
6368         int cxt_index, cxt_offset;
6369
6370         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6371         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6372
6373         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6374         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6375
6376         /* HC rate */
6377         init_params->rx.hc_rate =
6378             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6379         init_params->tx.hc_rate =
6380             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6381
6382         /* FW SB ID */
6383         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6384
6385         /* CQ index among the SB indices */
6386         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6387         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6388
6389         /* set maximum number of COSs supported by this queue */
6390         init_params->max_cos = sc->max_cos;
6391
6392         /* set the context pointers queue object */
6393         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6394                 cxt_index = fp->index / ILT_PAGE_CIDS;
6395                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6396                 init_params->cxts[cos] =
6397                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6398         }
6399 }
6400
6401 /* set flags that are common for the Tx-only and not normal connections */
6402 static unsigned long
6403 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6404 {
6405         unsigned long flags = 0;
6406
6407         /* PF driver will always initialize the Queue to an ACTIVE state */
6408         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6409
6410         /*
6411          * tx only connections collect statistics (on the same index as the
6412          * parent connection). The statistics are zeroed when the parent
6413          * connection is initialized.
6414          */
6415
6416         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6417         if (zero_stats) {
6418                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6419         }
6420
6421         /*
6422          * tx only connections can support tx-switching, though their
6423          * CoS-ness doesn't survive the loopback
6424          */
6425         if (sc->flags & BNX2X_TX_SWITCHING) {
6426                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6427         }
6428
6429         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6430
6431         return flags;
6432 }
6433
6434 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6435 {
6436         unsigned long flags = 0;
6437
6438         if (IS_MF_SD(sc)) {
6439                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6440         }
6441
6442         if (leading) {
6443                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6444                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6445         }
6446
6447         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6448
6449         /* merge with common flags */
6450         return flags | bnx2x_get_common_flags(sc, TRUE);
6451 }
6452
6453 static void
6454 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6455                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6456 {
6457         gen_init->stat_id = bnx2x_stats_id(fp);
6458         gen_init->spcl_id = fp->cl_id;
6459         gen_init->mtu = sc->mtu;
6460         gen_init->cos = cos;
6461 }
6462
6463 static void
6464 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6465                  struct rxq_pause_params *pause,
6466                  struct ecore_rxq_setup_params *rxq_init)
6467 {
6468         struct bnx2x_rx_queue *rxq;
6469
6470         rxq = sc->rx_queues[fp->index];
6471         if (!rxq) {
6472                 PMD_RX_LOG(ERR, "RX queue is NULL");
6473                 return;
6474         }
6475         /* pause */
6476         pause->bd_th_lo = BD_TH_LO(sc);
6477         pause->bd_th_hi = BD_TH_HI(sc);
6478
6479         pause->rcq_th_lo = RCQ_TH_LO(sc);
6480         pause->rcq_th_hi = RCQ_TH_HI(sc);
6481
6482         /* validate rings have enough entries to cross high thresholds */
6483         if (sc->dropless_fc &&
6484             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6485                 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6486         }
6487
6488         if (sc->dropless_fc &&
6489             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6490                 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6491         }
6492
6493         pause->pri_map = 1;
6494
6495         /* rxq setup */
6496         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6497         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6498         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6499                                               BNX2X_PAGE_SIZE);
6500
6501         /*
6502          * This should be a maximum number of data bytes that may be
6503          * placed on the BD (not including paddings).
6504          */
6505         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6506
6507         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6508         rxq_init->rss_engine_id = SC_FUNC(sc);
6509         rxq_init->mcast_engine_id = SC_FUNC(sc);
6510
6511         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6512         rxq_init->fw_sb_id = fp->fw_sb_id;
6513
6514         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6515
6516         /*
6517          * configure silent vlan removal
6518          * if multi function mode is afex, then mask default vlan
6519          */
6520         if (IS_MF_AFEX(sc)) {
6521                 rxq_init->silent_removal_value =
6522                     sc->devinfo.mf_info.afex_def_vlan_tag;
6523                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6524         }
6525 }
6526
6527 static void
6528 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6529                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6530 {
6531         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6532
6533         if (!txq) {
6534                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6535                 return;
6536         }
6537         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6538         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6539         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6540         txq_init->fw_sb_id = fp->fw_sb_id;
6541
6542         /*
6543          * set the TSS leading client id for TX classfication to the
6544          * leading RSS client id
6545          */
6546         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6547 }
6548
6549 /*
6550  * This function performs 2 steps in a queue state machine:
6551  *   1) RESET->INIT
6552  *   2) INIT->SETUP
6553  */
6554 static int
6555 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6556 {
6557         struct ecore_queue_state_params q_params = { NULL };
6558         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6559         int rc;
6560
6561         PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6562
6563         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6564
6565         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6566
6567         /* we want to wait for completion in this context */
6568         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6569
6570         /* prepare the INIT parameters */
6571         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6572
6573         /* Set the command */
6574         q_params.cmd = ECORE_Q_CMD_INIT;
6575
6576         /* Change the state to INIT */
6577         rc = ecore_queue_state_change(sc, &q_params);
6578         if (rc) {
6579                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6580                 return rc;
6581         }
6582
6583         PMD_DRV_LOG(DEBUG, sc, "init complete");
6584
6585         /* now move the Queue to the SETUP state */
6586         memset(setup_params, 0, sizeof(*setup_params));
6587
6588         /* set Queue flags */
6589         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6590
6591         /* set general SETUP parameters */
6592         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6593                               FIRST_TX_COS_INDEX);
6594
6595         bnx2x_pf_rx_q_prep(sc, fp,
6596                          &setup_params->pause_params,
6597                          &setup_params->rxq_params);
6598
6599         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6600
6601         /* Set the command */
6602         q_params.cmd = ECORE_Q_CMD_SETUP;
6603
6604         /* change the state to SETUP */
6605         rc = ecore_queue_state_change(sc, &q_params);
6606         if (rc) {
6607                 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6608                 return rc;
6609         }
6610
6611         return rc;
6612 }
6613
6614 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6615 {
6616         if (IS_PF(sc))
6617                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6618         else                    /* VF */
6619                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6620 }
6621
6622 static int
6623 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6624                   uint8_t config_hash)
6625 {
6626         struct ecore_config_rss_params params = { NULL };
6627         uint32_t i;
6628
6629         /*
6630          * Although RSS is meaningless when there is a single HW queue we
6631          * still need it enabled in order to have HW Rx hash generated.
6632          */
6633
6634         params.rss_obj = rss_obj;
6635
6636         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6637
6638         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6639
6640         /* RSS configuration */
6641         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6642         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6643         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6644         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6645         if (rss_obj->udp_rss_v4) {
6646                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6647         }
6648         if (rss_obj->udp_rss_v6) {
6649                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6650         }
6651
6652         /* Hash bits */
6653         params.rss_result_mask = MULTI_MASK;
6654
6655         rte_memcpy(params.ind_table, rss_obj->ind_table,
6656                          sizeof(params.ind_table));
6657
6658         if (config_hash) {
6659 /* RSS keys */
6660                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6661                         params.rss_key[i] = (uint32_t) rte_rand();
6662                 }
6663
6664                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6665         }
6666
6667         if (IS_PF(sc))
6668                 return ecore_config_rss(sc, &params);
6669         else
6670                 return bnx2x_vf_config_rss(sc, &params);
6671 }
6672
6673 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6674 {
6675         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6676 }
6677
6678 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6679 {
6680         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6681         uint32_t i;
6682
6683         /*
6684          * Prepare the initial contents of the indirection table if
6685          * RSS is enabled
6686          */
6687         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6688                 sc->rss_conf_obj.ind_table[i] =
6689                     (sc->fp->cl_id + (i % num_eth_queues));
6690         }
6691
6692         if (sc->udp_rss) {
6693                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6694         }
6695
6696         /*
6697          * For 57711 SEARCHER configuration (rss_keys) is
6698          * per-port, so if explicit configuration is needed, do it only
6699          * for a PMF.
6700          *
6701          * For 57712 and newer it's a per-function configuration.
6702          */
6703         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6704 }
6705
6706 static int
6707 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6708                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6709                 unsigned long *ramrod_flags)
6710 {
6711         struct ecore_vlan_mac_ramrod_params ramrod_param;
6712         int rc;
6713
6714         memset(&ramrod_param, 0, sizeof(ramrod_param));
6715
6716         /* fill in general parameters */
6717         ramrod_param.vlan_mac_obj = obj;
6718         ramrod_param.ramrod_flags = *ramrod_flags;
6719
6720         /* fill a user request section if needed */
6721         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6722                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6723                                  ETH_ALEN);
6724
6725                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6726
6727 /* Set the command: ADD or DEL */
6728                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6729                     ECORE_VLAN_MAC_DEL;
6730         }
6731
6732         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6733
6734         if (rc == ECORE_EXISTS) {
6735                 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6736 /* do not treat adding same MAC as error */
6737                 rc = 0;
6738         } else if (rc < 0) {
6739                 PMD_DRV_LOG(ERR, sc,
6740                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6741         }
6742
6743         return rc;
6744 }
6745
6746 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6747 {
6748         unsigned long ramrod_flags = 0;
6749
6750         PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6751
6752         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6753
6754         /* Eth MAC is set on RSS leading client (fp[0]) */
6755         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6756                                &sc->sp_objs->mac_obj,
6757                                set, ECORE_ETH_MAC, &ramrod_flags);
6758 }
6759
6760 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6761 {
6762         uint32_t sel_phy_idx = 0;
6763
6764         if (sc->link_params.num_phys <= 1) {
6765                 return ELINK_INT_PHY;
6766         }
6767
6768         if (sc->link_vars.link_up) {
6769                 sel_phy_idx = ELINK_EXT_PHY1;
6770 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6771                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6772                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6773                      ELINK_SUPPORTED_FIBRE))
6774                         sel_phy_idx = ELINK_EXT_PHY2;
6775         } else {
6776                 switch (elink_phy_selection(&sc->link_params)) {
6777                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6778                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6779                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6780                         sel_phy_idx = ELINK_EXT_PHY1;
6781                         break;
6782                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6783                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6784                         sel_phy_idx = ELINK_EXT_PHY2;
6785                         break;
6786                 }
6787         }
6788
6789         return sel_phy_idx;
6790 }
6791
6792 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6793 {
6794         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6795
6796         /*
6797          * The selected activated PHY is always after swapping (in case PHY
6798          * swapping is enabled). So when swapping is enabled, we need to reverse
6799          * the configuration
6800          */
6801
6802         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6803                 if (sel_phy_idx == ELINK_EXT_PHY1)
6804                         sel_phy_idx = ELINK_EXT_PHY2;
6805                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6806                         sel_phy_idx = ELINK_EXT_PHY1;
6807         }
6808
6809         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6810 }
6811
6812 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6813 {
6814         /*
6815          * Initialize link parameters structure variables
6816          * It is recommended to turn off RX FC for jumbo frames
6817          * for better performance
6818          */
6819         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6820                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6821         } else {
6822                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6823         }
6824 }
6825
6826 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6827 {
6828         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6829         switch (sc->link_vars.ieee_fc &
6830                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6831         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6832         default:
6833                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6834                                                    ADVERTISED_Pause);
6835                 break;
6836
6837         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6838                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6839                                                   ADVERTISED_Pause);
6840                 break;
6841
6842         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6843                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6844                 break;
6845         }
6846 }
6847
6848 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6849 {
6850         uint16_t line_speed = sc->link_vars.line_speed;
6851         if (IS_MF(sc)) {
6852                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6853                                                       sc->devinfo.
6854                                                       mf_info.mf_config[SC_VN
6855                                                                         (sc)]);
6856
6857 /* calculate the current MAX line speed limit for the MF devices */
6858                 if (IS_MF_SI(sc)) {
6859                         line_speed = (line_speed * maxCfg) / 100;
6860                 } else {        /* SD mode */
6861                         uint16_t vn_max_rate = maxCfg * 100;
6862
6863                         if (vn_max_rate < line_speed) {
6864                                 line_speed = vn_max_rate;
6865                         }
6866                 }
6867         }
6868
6869         return line_speed;
6870 }
6871
6872 static void
6873 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6874 {
6875         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6876
6877         memset(data, 0, sizeof(*data));
6878
6879         /* fill the report data with the effective line speed */
6880         data->line_speed = line_speed;
6881
6882         /* Link is down */
6883         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6884                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6885                             &data->link_report_flags);
6886         }
6887
6888         /* Full DUPLEX */
6889         if (sc->link_vars.duplex == DUPLEX_FULL) {
6890                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6891                             &data->link_report_flags);
6892         }
6893
6894         /* Rx Flow Control is ON */
6895         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6896                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6897         }
6898
6899         /* Tx Flow Control is ON */
6900         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6901                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6902         }
6903 }
6904
6905 /* report link status to OS, should be called under phy_lock */
6906 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6907 {
6908         struct bnx2x_link_report_data cur_data;
6909
6910         /* reread mf_cfg */
6911         if (IS_PF(sc)) {
6912                 bnx2x_read_mf_cfg(sc);
6913         }
6914
6915         /* Read the current link report info */
6916         bnx2x_fill_report_data(sc, &cur_data);
6917
6918         /* Don't report link down or exactly the same link status twice */
6919         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6920             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6921                           &sc->last_reported_link.link_report_flags) &&
6922              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6923                           &cur_data.link_report_flags))) {
6924                 return;
6925         }
6926
6927         PMD_DRV_LOG(INFO, sc, "Change in link status : cur_data = %lx, last_reported_link = %lx\n",
6928                     cur_data.link_report_flags,
6929                     sc->last_reported_link.link_report_flags);
6930
6931         sc->link_cnt++;
6932
6933         PMD_DRV_LOG(INFO, sc, "link status change count = %x\n", sc->link_cnt);
6934         /* report new link params and remember the state for the next time */
6935         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6936
6937         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6938                          &cur_data.link_report_flags)) {
6939                 PMD_DRV_LOG(INFO, sc, "NIC Link is Down");
6940         } else {
6941                 __rte_unused const char *duplex;
6942                 __rte_unused const char *flow;
6943
6944                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6945                                            &cur_data.link_report_flags)) {
6946                         duplex = "full";
6947                 } else {
6948                         duplex = "half";
6949                 }
6950
6951 /*
6952  * Handle the FC at the end so that only these flags would be
6953  * possibly set. This way we may easily check if there is no FC
6954  * enabled.
6955  */
6956                 if (cur_data.link_report_flags) {
6957                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6958                                          &cur_data.link_report_flags) &&
6959                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6960                                          &cur_data.link_report_flags)) {
6961                                 flow = "ON - receive & transmit";
6962                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6963                                                 &cur_data.link_report_flags) &&
6964                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6965                                                  &cur_data.link_report_flags)) {
6966                                 flow = "ON - receive";
6967                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6968                                                  &cur_data.link_report_flags) &&
6969                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6970                                                 &cur_data.link_report_flags)) {
6971                                 flow = "ON - transmit";
6972                         } else {
6973                                 flow = "none";  /* possible? */
6974                         }
6975                 } else {
6976                         flow = "none";
6977                 }
6978
6979                 PMD_DRV_LOG(INFO, sc,
6980                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6981                             cur_data.line_speed, duplex, flow);
6982         }
6983 }
6984
6985 static void
6986 bnx2x_link_report(struct bnx2x_softc *sc)
6987 {
6988         bnx2x_acquire_phy_lock(sc);
6989         bnx2x_link_report_locked(sc);
6990         bnx2x_release_phy_lock(sc);
6991 }
6992
6993 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6994 {
6995         if (sc->state != BNX2X_STATE_OPEN) {
6996                 return;
6997         }
6998
6999         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7000                 elink_link_status_update(&sc->link_params, &sc->link_vars);
7001         } else {
7002                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7003                                           ELINK_SUPPORTED_10baseT_Full |
7004                                           ELINK_SUPPORTED_100baseT_Half |
7005                                           ELINK_SUPPORTED_100baseT_Full |
7006                                           ELINK_SUPPORTED_1000baseT_Full |
7007                                           ELINK_SUPPORTED_2500baseX_Full |
7008                                           ELINK_SUPPORTED_10000baseT_Full |
7009                                           ELINK_SUPPORTED_TP |
7010                                           ELINK_SUPPORTED_FIBRE |
7011                                           ELINK_SUPPORTED_Autoneg |
7012                                           ELINK_SUPPORTED_Pause |
7013                                           ELINK_SUPPORTED_Asym_Pause);
7014                 sc->port.advertising[0] = sc->port.supported[0];
7015
7016                 sc->link_params.sc = sc;
7017                 sc->link_params.port = SC_PORT(sc);
7018                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7019                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7020                 sc->link_params.req_line_speed[0] = SPEED_10000;
7021                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7022                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7023
7024                 if (CHIP_REV_IS_FPGA(sc)) {
7025                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7026                         sc->link_vars.line_speed = ELINK_SPEED_1000;
7027                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7028                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7029                 } else {
7030                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7031                         sc->link_vars.line_speed = ELINK_SPEED_10000;
7032                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7033                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7034                 }
7035
7036                 sc->link_vars.link_up = 1;
7037
7038                 sc->link_vars.duplex = DUPLEX_FULL;
7039                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7040
7041                 if (IS_PF(sc)) {
7042                         REG_WR(sc,
7043                                NIG_REG_EGRESS_DRAIN0_MODE +
7044                                sc->link_params.port * 4, 0);
7045                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7046                         bnx2x_link_report(sc);
7047                 }
7048         }
7049
7050         if (IS_PF(sc)) {
7051                 if (sc->link_vars.link_up) {
7052                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7053                 } else {
7054                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7055                 }
7056                 bnx2x_link_report(sc);
7057         } else {
7058                 bnx2x_link_report_locked(sc);
7059                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7060         }
7061 }
7062
7063 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7064 {
7065         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7066         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7067         struct elink_params *lp = &sc->link_params;
7068
7069         bnx2x_set_requested_fc(sc);
7070
7071         bnx2x_acquire_phy_lock(sc);
7072
7073         if (load_mode == LOAD_DIAG) {
7074                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7075 /* Prefer doing PHY loopback at 10G speed, if possible */
7076                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7077                         if (lp->speed_cap_mask[cfg_idx] &
7078                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7079                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7080                         } else {
7081                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7082                         }
7083                 }
7084         }
7085
7086         if (load_mode == LOAD_LOOPBACK_EXT) {
7087                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7088         }
7089
7090         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7091
7092         bnx2x_release_phy_lock(sc);
7093
7094         bnx2x_calc_fc_adv(sc);
7095
7096         if (sc->link_vars.link_up) {
7097                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7098                 bnx2x_link_report(sc);
7099         }
7100
7101         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7102         return rc;
7103 }
7104
7105 /* update flags in shmem */
7106 static void
7107 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7108 {
7109         uint32_t drv_flags;
7110
7111         if (SHMEM2_HAS(sc, drv_flags)) {
7112                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7113                 drv_flags = SHMEM2_RD(sc, drv_flags);
7114
7115                 if (set) {
7116                         drv_flags |= flags;
7117                 } else {
7118                         drv_flags &= ~flags;
7119                 }
7120
7121                 SHMEM2_WR(sc, drv_flags, drv_flags);
7122
7123                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7124         }
7125 }
7126
7127 /* periodic timer callout routine, only runs when the interface is up */
7128 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7129 {
7130         if ((sc->state != BNX2X_STATE_OPEN) ||
7131             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7132                 PMD_DRV_LOG(INFO, sc, "periodic callout exit (state=0x%x)",
7133                             sc->state);
7134                 return;
7135         }
7136         if (!CHIP_REV_IS_SLOW(sc)) {
7137 /*
7138  * This barrier is needed to ensure the ordering between the writing
7139  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7140  * the reading here.
7141  */
7142                 mb();
7143                 if (sc->port.pmf) {
7144                         bnx2x_acquire_phy_lock(sc);
7145                         elink_period_func(&sc->link_params, &sc->link_vars);
7146                         bnx2x_release_phy_lock(sc);
7147                 }
7148         }
7149 #ifdef BNX2X_PULSE
7150         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7151                 int mb_idx = SC_FW_MB_IDX(sc);
7152                 uint32_t drv_pulse;
7153                 uint32_t mcp_pulse;
7154
7155                 ++sc->fw_drv_pulse_wr_seq;
7156                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7157
7158                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7159                 bnx2x_drv_pulse(sc);
7160
7161                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7162                              MCP_PULSE_SEQ_MASK);
7163
7164 /*
7165  * The delta between driver pulse and mcp response should
7166  * be 1 (before mcp response) or 0 (after mcp response).
7167  */
7168                 if ((drv_pulse != mcp_pulse) &&
7169                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7170                         /* someone lost a heartbeat... */
7171                         PMD_DRV_LOG(ERR, sc,
7172                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7173                                     drv_pulse, mcp_pulse);
7174                 }
7175         }
7176 #endif
7177 }
7178
7179 /* start the controller */
7180 static __rte_noinline
7181 int bnx2x_nic_load(struct bnx2x_softc *sc)
7182 {
7183         uint32_t val;
7184         uint32_t load_code = 0;
7185         int i, rc = 0;
7186
7187         PMD_INIT_FUNC_TRACE(sc);
7188
7189         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7190
7191         if (IS_PF(sc)) {
7192 /* must be called before memory allocation and HW init */
7193                 bnx2x_ilt_set_info(sc);
7194         }
7195
7196         bnx2x_set_fp_rx_buf_size(sc);
7197
7198         if (IS_PF(sc)) {
7199                 if (bnx2x_alloc_mem(sc) != 0) {
7200                         sc->state = BNX2X_STATE_CLOSED;
7201                         rc = -ENOMEM;
7202                         goto bnx2x_nic_load_error0;
7203                 }
7204         }
7205
7206         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7207                 sc->state = BNX2X_STATE_CLOSED;
7208                 rc = -ENOMEM;
7209                 goto bnx2x_nic_load_error0;
7210         }
7211
7212         if (IS_VF(sc)) {
7213                 rc = bnx2x_vf_init(sc);
7214                 if (rc) {
7215                         sc->state = BNX2X_STATE_ERROR;
7216                         goto bnx2x_nic_load_error0;
7217                 }
7218         }
7219
7220         if (IS_PF(sc)) {
7221 /* set pf load just before approaching the MCP */
7222                 bnx2x_set_pf_load(sc);
7223
7224 /* if MCP exists send load request and analyze response */
7225                 if (!BNX2X_NOMCP(sc)) {
7226                         /* attempt to load pf */
7227                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7228                                 sc->state = BNX2X_STATE_CLOSED;
7229                                 rc = -ENXIO;
7230                                 goto bnx2x_nic_load_error1;
7231                         }
7232
7233                         /* what did the MCP say? */
7234                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7235                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7236                                 sc->state = BNX2X_STATE_CLOSED;
7237                                 rc = -ENXIO;
7238                                 goto bnx2x_nic_load_error2;
7239                         }
7240                 } else {
7241                         PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7242                         load_code = bnx2x_nic_load_no_mcp(sc);
7243                 }
7244
7245 /* mark PMF if applicable */
7246                 bnx2x_nic_load_pmf(sc, load_code);
7247
7248 /* Init Function state controlling object */
7249                 bnx2x_init_func_obj(sc);
7250
7251 /* Initialize HW */
7252                 if (bnx2x_init_hw(sc, load_code) != 0) {
7253                         PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7254                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7255                         sc->state = BNX2X_STATE_CLOSED;
7256                         rc = -ENXIO;
7257                         goto bnx2x_nic_load_error2;
7258                 }
7259         }
7260
7261         bnx2x_nic_init(sc, load_code);
7262
7263         /* Init per-function objects */
7264         if (IS_PF(sc)) {
7265                 bnx2x_init_objs(sc);
7266
7267 /* set AFEX default VLAN tag to an invalid value */
7268                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7269
7270                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7271                 rc = bnx2x_func_start(sc);
7272                 if (rc) {
7273                         PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7274                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7275                         sc->state = BNX2X_STATE_ERROR;
7276                         goto bnx2x_nic_load_error3;
7277                 }
7278
7279 /* send LOAD_DONE command to MCP */
7280                 if (!BNX2X_NOMCP(sc)) {
7281                         load_code =
7282                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7283                         if (!load_code) {
7284                                 PMD_DRV_LOG(NOTICE, sc,
7285                                             "MCP response failure, aborting");
7286                                 sc->state = BNX2X_STATE_ERROR;
7287                                 rc = -ENXIO;
7288                                 goto bnx2x_nic_load_error3;
7289                         }
7290                 }
7291         }
7292
7293         rc = bnx2x_setup_leading(sc);
7294         if (rc) {
7295                 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7296                 sc->state = BNX2X_STATE_ERROR;
7297                 goto bnx2x_nic_load_error3;
7298         }
7299
7300         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7301                 if (IS_PF(sc))
7302                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7303                 else            /* IS_VF(sc) */
7304                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7305
7306                 if (rc) {
7307                         PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7308                         sc->state = BNX2X_STATE_ERROR;
7309                         goto bnx2x_nic_load_error3;
7310                 }
7311         }
7312
7313         rc = bnx2x_init_rss_pf(sc);
7314         if (rc) {
7315                 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7316                 sc->state = BNX2X_STATE_ERROR;
7317                 goto bnx2x_nic_load_error3;
7318         }
7319
7320         /* now when Clients are configured we are ready to work */
7321         sc->state = BNX2X_STATE_OPEN;
7322
7323         /* Configure a ucast MAC */
7324         if (IS_PF(sc)) {
7325                 rc = bnx2x_set_eth_mac(sc, TRUE);
7326         } else {                /* IS_VF(sc) */
7327                 rc = bnx2x_vf_set_mac(sc, TRUE);
7328         }
7329
7330         if (rc) {
7331                 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7332                 sc->state = BNX2X_STATE_ERROR;
7333                 goto bnx2x_nic_load_error3;
7334         }
7335
7336         if (sc->port.pmf) {
7337                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7338                 if (rc) {
7339                         sc->state = BNX2X_STATE_ERROR;
7340                         goto bnx2x_nic_load_error3;
7341                 }
7342         }
7343
7344         sc->link_params.feature_config_flags &=
7345             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7346
7347         /* start the Tx */
7348         switch (LOAD_OPEN) {
7349         case LOAD_NORMAL:
7350         case LOAD_OPEN:
7351                 break;
7352
7353         case LOAD_DIAG:
7354         case LOAD_LOOPBACK_EXT:
7355                 sc->state = BNX2X_STATE_DIAG;
7356                 break;
7357
7358         default:
7359                 break;
7360         }
7361
7362         if (sc->port.pmf) {
7363                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7364         } else {
7365                 bnx2x_link_status_update(sc);
7366         }
7367
7368         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7369 /* mark driver is loaded in shmem2 */
7370                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7371                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7372                           (val |
7373                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7374                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7375         }
7376
7377         /* start fast path */
7378         /* Initialize Rx filter */
7379         bnx2x_set_rx_mode(sc);
7380
7381         /* wait for all pending SP commands to complete */
7382         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7383                 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7384                 bnx2x_periodic_stop(sc);
7385                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7386                 return -ENXIO;
7387         }
7388
7389         PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7390
7391         return 0;
7392
7393 bnx2x_nic_load_error3:
7394
7395         if (IS_PF(sc)) {
7396                 bnx2x_int_disable_sync(sc, 1);
7397
7398 /* clean out queued objects */
7399                 bnx2x_squeeze_objects(sc);
7400         }
7401
7402 bnx2x_nic_load_error2:
7403
7404         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7405                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7406                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7407         }
7408
7409         sc->port.pmf = 0;
7410
7411 bnx2x_nic_load_error1:
7412
7413         /* clear pf_load status, as it was already set */
7414         if (IS_PF(sc)) {
7415                 bnx2x_clear_pf_load(sc);
7416         }
7417
7418 bnx2x_nic_load_error0:
7419
7420         bnx2x_free_fw_stats_mem(sc);
7421         bnx2x_free_mem(sc);
7422
7423         return rc;
7424 }
7425
7426 /*
7427 * Handles controller initialization.
7428 */
7429 int bnx2x_init(struct bnx2x_softc *sc)
7430 {
7431         int other_engine = SC_PATH(sc) ? 0 : 1;
7432         uint8_t other_load_status, load_status;
7433         uint8_t global = FALSE;
7434         int rc;
7435
7436         /* Check if the driver is still running and bail out if it is. */
7437         if (sc->state != BNX2X_STATE_CLOSED) {
7438                 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7439                 rc = 0;
7440                 goto bnx2x_init_done;
7441         }
7442
7443         bnx2x_set_power_state(sc, PCI_PM_D0);
7444
7445         /*
7446          * If parity occurred during the unload, then attentions and/or
7447          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7448          * loaded on the current engine to complete the recovery. Parity recovery
7449          * is only relevant for PF driver.
7450          */
7451         if (IS_PF(sc)) {
7452                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7453                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7454
7455                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7456                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7457                         do {
7458                                 /*
7459                                  * If there are attentions and they are in global blocks, set
7460                                  * the GLOBAL_RESET bit regardless whether it will be this
7461                                  * function that will complete the recovery or not.
7462                                  */
7463                                 if (global) {
7464                                         bnx2x_set_reset_global(sc);
7465                                 }
7466
7467                                 /*
7468                                  * Only the first function on the current engine should try
7469                                  * to recover in open. In case of attentions in global blocks
7470                                  * only the first in the chip should try to recover.
7471                                  */
7472                                 if ((!load_status
7473                                      && (!global ||!other_load_status))
7474                                     && bnx2x_trylock_leader_lock(sc)
7475                                     && !bnx2x_leader_reset(sc)) {
7476                                         PMD_DRV_LOG(INFO, sc,
7477                                                     "Recovered during init");
7478                                         break;
7479                                 }
7480
7481                                 /* recovery has failed... */
7482                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7483
7484                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7485
7486                                 PMD_DRV_LOG(NOTICE, sc,
7487                                             "Recovery flow hasn't properly "
7488                                             "completed yet, try again later. "
7489                                             "If you still see this message after a "
7490                                             "few retries then power cycle is required.");
7491
7492                                 rc = -ENXIO;
7493                                 goto bnx2x_init_done;
7494                         } while (0);
7495                 }
7496         }
7497
7498         sc->recovery_state = BNX2X_RECOVERY_DONE;
7499
7500         rc = bnx2x_nic_load(sc);
7501
7502 bnx2x_init_done:
7503
7504         if (rc) {
7505                 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7506                             "stack notified driver is NOT running!");
7507         }
7508
7509         return rc;
7510 }
7511
7512 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7513 {
7514         uint32_t val = 0;
7515
7516         /*
7517          * Read the ME register to get the function number. The ME register
7518          * holds the relative-function number and absolute-function number. The
7519          * absolute-function number appears only in E2 and above. Before that
7520          * these bits always contained zero, therefore we cannot blindly use them.
7521          */
7522
7523         val = REG_RD(sc, BAR_ME_REGISTER);
7524
7525         sc->pfunc_rel =
7526             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7527         sc->path_id =
7528             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7529             1;
7530
7531         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7532                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7533         } else {
7534                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7535         }
7536
7537         PMD_DRV_LOG(DEBUG, sc,
7538                     "Relative function %d, Absolute function %d, Path %d",
7539                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7540 }
7541
7542 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7543 {
7544         uint32_t shmem2_size;
7545         uint32_t offset;
7546         uint32_t mf_cfg_offset_value;
7547
7548         /* Non 57712 */
7549         offset = (SHMEM_ADDR(sc, func_mb) +
7550                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7551
7552         /* 57712 plus */
7553         if (sc->devinfo.shmem2_base != 0) {
7554                 shmem2_size = SHMEM2_RD(sc, size);
7555                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7556                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7557                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7558                                 offset = mf_cfg_offset_value;
7559                         }
7560                 }
7561         }
7562
7563         return offset;
7564 }
7565
7566 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7567 {
7568         uint32_t ret;
7569         struct bnx2x_pci_cap *caps;
7570
7571         /* ensure PCIe capability is enabled */
7572         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7573         if (NULL != caps) {
7574                 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7575                             "id=0x%04X type=0x%04X addr=0x%08X",
7576                             caps->id, caps->type, caps->addr);
7577                 pci_read(sc, (caps->addr + reg), &ret, 2);
7578                 return ret;
7579         }
7580
7581         PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7582
7583         return 0;
7584 }
7585
7586 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7587 {
7588         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7589                 PCIM_EXP_STA_TRANSACTION_PND;
7590 }
7591
7592 /*
7593 * Walk the PCI capabiites list for the device to find what features are
7594 * supported. These capabilites may be enabled/disabled by firmware so it's
7595 * best to walk the list rather than make assumptions.
7596 */
7597 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7598 {
7599         PMD_INIT_FUNC_TRACE(sc);
7600
7601         struct bnx2x_pci_cap *caps;
7602         uint16_t link_status;
7603 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7604         int reg = 0;
7605 #endif
7606
7607         /* check if PCI Power Management is enabled */
7608         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7609         if (NULL != caps) {
7610                 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7611                             "id=0x%04X type=0x%04X addr=0x%08X",
7612                             caps->id, caps->type, caps->addr);
7613
7614                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7615                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7616         }
7617
7618         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7619
7620         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7621         sc->devinfo.pcie_link_width =
7622             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7623
7624         PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7625                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7626
7627         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7628
7629         /* check if MSI capability is enabled */
7630         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7631         if (NULL != caps) {
7632                 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7633
7634                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7635                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7636         }
7637
7638         /* check if MSI-X capability is enabled */
7639         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7640         if (NULL != caps) {
7641                 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7642
7643                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7644                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7645         }
7646 }
7647
7648 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7649 {
7650         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7651         uint32_t val;
7652
7653         /* get the outer vlan if we're in switch-dependent mode */
7654
7655         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7656         mf_info->ext_id = (uint16_t) val;
7657
7658         mf_info->multi_vnics_mode = 1;
7659
7660         if (!VALID_OVLAN(mf_info->ext_id)) {
7661                 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7662                 return 1;
7663         }
7664
7665         /* get the capabilities */
7666         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7667             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7668                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7669         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7670                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7671                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7672         } else {
7673                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7674         }
7675
7676         mf_info->vnics_per_port =
7677             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7678
7679         return 0;
7680 }
7681
7682 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7683 {
7684         uint32_t retval = 0;
7685         uint32_t val;
7686
7687         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7688
7689         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7690                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7691                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7692                 }
7693                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7694                         retval |= MF_PROTO_SUPPORT_ISCSI;
7695                 }
7696                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7697                         retval |= MF_PROTO_SUPPORT_FCOE;
7698                 }
7699         }
7700
7701         return retval;
7702 }
7703
7704 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7705 {
7706         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7707         uint32_t val;
7708
7709         /*
7710          * There is no outer vlan if we're in switch-independent mode.
7711          * If the mac is valid then assume multi-function.
7712          */
7713
7714         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7715
7716         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7717
7718         mf_info->mf_protos_supported =
7719             bnx2x_get_shmem_ext_proto_support_flags(sc);
7720
7721         mf_info->vnics_per_port =
7722             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7723
7724         return 0;
7725 }
7726
7727 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7728 {
7729         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7730         uint32_t e1hov_tag;
7731         uint32_t func_config;
7732         uint32_t niv_config;
7733
7734         mf_info->multi_vnics_mode = 1;
7735
7736         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7737         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7738         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7739
7740         mf_info->ext_id =
7741             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7742                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7743
7744         mf_info->default_vlan =
7745             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7746                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7747
7748         mf_info->niv_allowed_priorities =
7749             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7750                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7751
7752         mf_info->niv_default_cos =
7753             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7754                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7755
7756         mf_info->afex_vlan_mode =
7757             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7758              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7759
7760         mf_info->niv_mba_enabled =
7761             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7762              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7763
7764         mf_info->mf_protos_supported =
7765             bnx2x_get_shmem_ext_proto_support_flags(sc);
7766
7767         mf_info->vnics_per_port =
7768             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7769
7770         return 0;
7771 }
7772
7773 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7774 {
7775         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7776         uint32_t mf_cfg1;
7777         uint32_t mf_cfg2;
7778         uint32_t ovlan1;
7779         uint32_t ovlan2;
7780         uint8_t i, j;
7781
7782         /* various MF mode sanity checks... */
7783
7784         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7785                 PMD_DRV_LOG(NOTICE, sc,
7786                             "Enumerated function %d is marked as hidden",
7787                             SC_PORT(sc));
7788                 return 1;
7789         }
7790
7791         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7792                 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7793                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7794                 return 1;
7795         }
7796
7797         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7798 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7799                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7800                         PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7801                                     SC_VN(sc), OVLAN(sc));
7802                         return 1;
7803                 }
7804
7805                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7806                         PMD_DRV_LOG(NOTICE, sc,
7807                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7808                                     mf_info->multi_vnics_mode, OVLAN(sc));
7809                         return 1;
7810                 }
7811
7812 /*
7813  * Verify all functions are either MF or SF mode. If MF, make sure
7814  * sure that all non-hidden functions have a valid ovlan. If SF,
7815  * make sure that all non-hidden functions have an invalid ovlan.
7816  */
7817                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7818                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7819                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7820                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7821                             (((mf_info->multi_vnics_mode)
7822                               && !VALID_OVLAN(ovlan1))
7823                              || ((!mf_info->multi_vnics_mode)
7824                                  && VALID_OVLAN(ovlan1)))) {
7825                                 PMD_DRV_LOG(NOTICE, sc,
7826                                             "mf_mode=SD function %d MF config "
7827                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7828                                             i, mf_info->multi_vnics_mode,
7829                                             ovlan1);
7830                                 return 1;
7831                         }
7832                 }
7833
7834 /* Verify all funcs on the same port each have a different ovlan. */
7835                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7836                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7837                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7838                         /* iterate from the next function on the port to the max func */
7839                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7840                                 mf_cfg2 =
7841                                     MFCFG_RD(sc, func_mf_config[j].config);
7842                                 ovlan2 =
7843                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7844                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7845                                     && VALID_OVLAN(ovlan1)
7846                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7847                                     && VALID_OVLAN(ovlan2)
7848                                     && (ovlan1 == ovlan2)) {
7849                                         PMD_DRV_LOG(NOTICE, sc,
7850                                                     "mf_mode=SD functions %d and %d "
7851                                                     "have the same ovlan (%d)",
7852                                                     i, j, ovlan1);
7853                                         return 1;
7854                                 }
7855                         }
7856                 }
7857         }
7858         /* MULTI_FUNCTION_SD */
7859         return 0;
7860 }
7861
7862 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7863 {
7864         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7865         uint32_t val, mac_upper;
7866         uint8_t i, vnic;
7867
7868         /* initialize mf_info defaults */
7869         mf_info->vnics_per_port = 1;
7870         mf_info->multi_vnics_mode = FALSE;
7871         mf_info->path_has_ovlan = FALSE;
7872         mf_info->mf_mode = SINGLE_FUNCTION;
7873
7874         if (!CHIP_IS_MF_CAP(sc)) {
7875                 return 0;
7876         }
7877
7878         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7879                 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7880                 return 1;
7881         }
7882
7883         /* get the MF mode (switch dependent / independent / single-function) */
7884
7885         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7886
7887         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7888         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7889
7890                 mac_upper =
7891                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7892
7893                 /* check for legal upper mac bytes */
7894                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7895                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7896                 } else {
7897                         PMD_DRV_LOG(NOTICE, sc,
7898                                     "Invalid config for Switch Independent mode");
7899                 }
7900
7901                 break;
7902
7903         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7904         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7905
7906                 /* get outer vlan configuration */
7907                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7908
7909                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7910                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7911                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7912                 } else {
7913                         PMD_DRV_LOG(NOTICE, sc,
7914                                     "Invalid config for Switch Dependent mode");
7915                 }
7916
7917                 break;
7918
7919         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7920
7921                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7922                 return 0;
7923
7924         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7925
7926                 /*
7927                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7928                  * and the MAC address is valid.
7929                  */
7930                 mac_upper =
7931                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7932
7933                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7934                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7935                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7936                 } else {
7937                         PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7938                 }
7939
7940                 break;
7941
7942         default:
7943
7944                 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7945                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7946
7947                 return 1;
7948         }
7949
7950         /* set path mf_mode (which could be different than function mf_mode) */
7951         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7952                 mf_info->path_has_ovlan = TRUE;
7953         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7954 /*
7955  * Decide on path multi vnics mode. If we're not in MF mode and in
7956  * 4-port mode, this is good enough to check vnic-0 of the other port
7957  * on the same path
7958  */
7959                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7960                         uint8_t other_port = !(PORT_ID(sc) & 1);
7961                         uint8_t abs_func_other_port =
7962                             (SC_PATH(sc) + (2 * other_port));
7963
7964                         val =
7965                             MFCFG_RD(sc,
7966                                      func_mf_config
7967                                      [abs_func_other_port].e1hov_tag);
7968
7969                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7970                 }
7971         }
7972
7973         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7974 /* invalid MF config */
7975                 if (SC_VN(sc) >= 1) {
7976                         PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
7977                         return 1;
7978                 }
7979
7980                 return 0;
7981         }
7982
7983         /* get the MF configuration */
7984         mf_info->mf_config[SC_VN(sc)] =
7985             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7986
7987         switch (mf_info->mf_mode) {
7988         case MULTI_FUNCTION_SD:
7989
7990                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7991                 break;
7992
7993         case MULTI_FUNCTION_SI:
7994
7995                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7996                 break;
7997
7998         case MULTI_FUNCTION_AFEX:
7999
8000                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8001                 break;
8002
8003         default:
8004
8005                 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8006                             mf_info->mf_mode);
8007                 return 1;
8008         }
8009
8010         /* get the congestion management parameters */
8011
8012         vnic = 0;
8013         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8014 /* get min/max bw */
8015                 val = MFCFG_RD(sc, func_mf_config[i].config);
8016                 mf_info->min_bw[vnic] =
8017                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8018                      FUNC_MF_CFG_MIN_BW_SHIFT);
8019                 mf_info->max_bw[vnic] =
8020                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8021                      FUNC_MF_CFG_MAX_BW_SHIFT);
8022                 vnic++;
8023         }
8024
8025         return bnx2x_check_valid_mf_cfg(sc);
8026 }
8027
8028 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8029 {
8030         int port;
8031         uint32_t mac_hi, mac_lo, val;
8032
8033         PMD_INIT_FUNC_TRACE(sc);
8034
8035         port = SC_PORT(sc);
8036         mac_hi = mac_lo = 0;
8037
8038         sc->link_params.sc = sc;
8039         sc->link_params.port = port;
8040
8041         /* get the hardware config info */
8042         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8043         sc->devinfo.hw_config2 =
8044             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8045
8046         sc->link_params.hw_led_mode =
8047             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8048              SHARED_HW_CFG_LED_MODE_SHIFT);
8049
8050         /* get the port feature config */
8051         sc->port.config =
8052             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8053
8054         /* get the link params */
8055         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8056             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8057             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8058         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8059             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8060             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8061
8062         /* get the lane config */
8063         sc->link_params.lane_config =
8064             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8065
8066         /* get the link config */
8067         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8068         sc->port.link_config[ELINK_INT_PHY] = val;
8069         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8070         sc->port.link_config[ELINK_EXT_PHY1] =
8071             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8072
8073         /* get the override preemphasis flag and enable it or turn it off */
8074         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8075         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8076                 sc->link_params.feature_config_flags |=
8077                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8078         } else {
8079                 sc->link_params.feature_config_flags &=
8080                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8081         }
8082
8083         /* get the initial value of the link params */
8084         sc->link_params.multi_phy_config =
8085             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8086
8087         /* get external phy info */
8088         sc->port.ext_phy_config =
8089             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8090
8091         /* get the multifunction configuration */
8092         bnx2x_get_mf_cfg_info(sc);
8093
8094         /* get the mac address */
8095         if (IS_MF(sc)) {
8096                 mac_hi =
8097                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8098                 mac_lo =
8099                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8100         } else {
8101                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8102                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8103         }
8104
8105         if ((mac_lo == 0) && (mac_hi == 0)) {
8106                 *sc->mac_addr_str = 0;
8107                 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8108         } else {
8109                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8110                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8111                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8112                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8113                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8114                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8115                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8116                          "%02x:%02x:%02x:%02x:%02x:%02x",
8117                          sc->link_params.mac_addr[0],
8118                          sc->link_params.mac_addr[1],
8119                          sc->link_params.mac_addr[2],
8120                          sc->link_params.mac_addr[3],
8121                          sc->link_params.mac_addr[4],
8122                          sc->link_params.mac_addr[5]);
8123                 PMD_DRV_LOG(DEBUG, sc,
8124                             "Ethernet address: %s", sc->mac_addr_str);
8125         }
8126
8127         return 0;
8128 }
8129
8130 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8131 {
8132         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8133         switch (sc->link_params.phy[phy_idx].media_type) {
8134         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8135         case ELINK_ETH_PHY_SFP_1G_FIBER:
8136         case ELINK_ETH_PHY_XFP_FIBER:
8137         case ELINK_ETH_PHY_KR:
8138         case ELINK_ETH_PHY_CX4:
8139                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8140                 sc->media = IFM_10G_CX4;
8141                 break;
8142         case ELINK_ETH_PHY_DA_TWINAX:
8143                 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8144                 sc->media = IFM_10G_TWINAX;
8145                 break;
8146         case ELINK_ETH_PHY_BASE_T:
8147                 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8148                 sc->media = IFM_10G_T;
8149                 break;
8150         case ELINK_ETH_PHY_NOT_PRESENT:
8151                 PMD_DRV_LOG(INFO, sc, "Media not present.");
8152                 sc->media = 0;
8153                 break;
8154         case ELINK_ETH_PHY_UNSPECIFIED:
8155         default:
8156                 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8157                 sc->media = 0;
8158                 break;
8159         }
8160 }
8161
8162 #define GET_FIELD(value, fname)                     \
8163 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8164 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8165 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8166
8167 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8168 {
8169         int pfid = SC_FUNC(sc);
8170         int igu_sb_id;
8171         uint32_t val;
8172         uint8_t fid, igu_sb_cnt = 0;
8173
8174         sc->igu_base_sb = 0xff;
8175
8176         if (CHIP_INT_MODE_IS_BC(sc)) {
8177                 int vn = SC_VN(sc);
8178                 igu_sb_cnt = sc->igu_sb_cnt;
8179                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8180                                    FP_SB_MAX_E1x);
8181                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8182                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8183                 return 0;
8184         }
8185
8186         /* IGU in normal mode - read CAM */
8187         for (igu_sb_id = 0;
8188              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8189                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8190                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8191                         continue;
8192                 }
8193                 fid = IGU_FID(val);
8194                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8195                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8196                                 continue;
8197                         }
8198                         if (IGU_VEC(val) == 0) {
8199                                 /* default status block */
8200                                 sc->igu_dsb_id = igu_sb_id;
8201                         } else {
8202                                 if (sc->igu_base_sb == 0xff) {
8203                                         sc->igu_base_sb = igu_sb_id;
8204                                 }
8205                                 igu_sb_cnt++;
8206                         }
8207                 }
8208         }
8209
8210         /*
8211          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8212          * that number of CAM entries will not be equal to the value advertised in
8213          * PCI. Driver should use the minimal value of both as the actual status
8214          * block count
8215          */
8216         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8217
8218         if (igu_sb_cnt == 0) {
8219                 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8220                 return -1;
8221         }
8222
8223         return 0;
8224 }
8225
8226 /*
8227 * Gather various information from the device config space, the device itself,
8228 * shmem, and the user input.
8229 */
8230 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8231 {
8232         uint32_t val;
8233         int rc;
8234
8235         /* get the chip revision (chip metal comes from pci config space) */
8236         sc->devinfo.chip_id = sc->link_params.chip_id =
8237             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8238              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8239              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8240              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8241
8242         /* force 57811 according to MISC register */
8243         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8244                 if (CHIP_IS_57810(sc)) {
8245                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8246                                                (sc->
8247                                                 devinfo.chip_id & 0x0000ffff));
8248                 } else if (CHIP_IS_57810_MF(sc)) {
8249                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8250                                                (sc->
8251                                                 devinfo.chip_id & 0x0000ffff));
8252                 }
8253                 sc->devinfo.chip_id |= 0x1;
8254         }
8255
8256         PMD_DRV_LOG(DEBUG, sc,
8257                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8258                     sc->devinfo.chip_id,
8259                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8260                     ((sc->devinfo.chip_id >> 12) & 0xf),
8261                     ((sc->devinfo.chip_id >> 4) & 0xff),
8262                     ((sc->devinfo.chip_id >> 0) & 0xf));
8263
8264         val = (REG_RD(sc, 0x2874) & 0x55);
8265         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8266                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8267                 PMD_DRV_LOG(DEBUG, sc, "single port device");
8268         }
8269
8270         /* set the doorbell size */
8271         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8272
8273         /* determine whether the device is in 2 port or 4 port mode */
8274         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8275         if (CHIP_IS_E2E3(sc)) {
8276 /*
8277  * Read port4mode_en_ovwr[0]:
8278  *   If 1, four port mode is in port4mode_en_ovwr[1].
8279  *   If 0, four port mode is in port4mode_en[0].
8280  */
8281                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8282                 if (val & 1) {
8283                         val = ((val >> 1) & 1);
8284                 } else {
8285                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8286                 }
8287
8288                 sc->devinfo.chip_port_mode =
8289                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8290
8291                 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8292         }
8293
8294         /* get the function and path info for the device */
8295         bnx2x_get_function_num(sc);
8296
8297         /* get the shared memory base address */
8298         sc->devinfo.shmem_base =
8299             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8300         sc->devinfo.shmem2_base =
8301             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8302                         MISC_REG_GENERIC_CR_0));
8303
8304         if (!sc->devinfo.shmem_base) {
8305 /* this should ONLY prevent upcoming shmem reads */
8306                 PMD_DRV_LOG(INFO, sc, "MCP not active");
8307                 sc->flags |= BNX2X_NO_MCP_FLAG;
8308                 return 0;
8309         }
8310
8311         /* make sure the shared memory contents are valid */
8312         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8313         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8314             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8315                 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8316                             val);
8317                 return 0;
8318         }
8319
8320         /* get the bootcode version */
8321         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8322         snprintf(sc->devinfo.bc_ver_str,
8323                  sizeof(sc->devinfo.bc_ver_str),
8324                  "%d.%d.%d",
8325                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8326                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8327                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8328         PMD_DRV_LOG(INFO, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8329
8330         /* get the bootcode shmem address */
8331         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8332
8333         /* clean indirect addresses as they're not used */
8334         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8335         if (IS_PF(sc)) {
8336                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8337                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8338                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8339                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8340                 if (CHIP_IS_E1x(sc)) {
8341                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8342                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8343                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8344                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8345                 }
8346         }
8347
8348         /* get the nvram size */
8349         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8350         sc->devinfo.flash_size =
8351             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8352
8353         bnx2x_set_power_state(sc, PCI_PM_D0);
8354         /* get various configuration parameters from shmem */
8355         bnx2x_get_shmem_info(sc);
8356
8357         /* initialize IGU parameters */
8358         if (CHIP_IS_E1x(sc)) {
8359                 sc->devinfo.int_block = INT_BLOCK_HC;
8360                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8361                 sc->igu_base_sb = 0;
8362         } else {
8363                 sc->devinfo.int_block = INT_BLOCK_IGU;
8364
8365 /* do not allow device reset during IGU info preocessing */
8366                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8367
8368                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8369
8370                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8371                         int tout = 5000;
8372
8373                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8374                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8375                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8376
8377                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8378                                 tout--;
8379                                 DELAY(1000);
8380                         }
8381
8382                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8383                                 PMD_DRV_LOG(NOTICE, sc,
8384                                             "FORCING IGU Normal Mode failed!!!");
8385                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8386                                 return -1;
8387                         }
8388                 }
8389
8390                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8391                         PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8392                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8393                 } else {
8394                         PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8395                 }
8396
8397                 rc = bnx2x_get_igu_cam_info(sc);
8398
8399                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8400
8401                 if (rc) {
8402                         return rc;
8403                 }
8404         }
8405
8406         /*
8407          * Get base FW non-default (fast path) status block ID. This value is
8408          * used to initialize the fw_sb_id saved on the fp/queue structure to
8409          * determine the id used by the FW.
8410          */
8411         if (CHIP_IS_E1x(sc)) {
8412                 sc->base_fw_ndsb =
8413                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8414         } else {
8415 /*
8416  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8417  * the same queue are indicated on the same IGU SB). So we prefer
8418  * FW and IGU SBs to be the same value.
8419  */
8420                 sc->base_fw_ndsb = sc->igu_base_sb;
8421         }
8422
8423         elink_phy_probe(&sc->link_params);
8424
8425         return 0;
8426 }
8427
8428 static void
8429 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8430 {
8431         uint32_t cfg_size = 0;
8432         uint32_t idx;
8433         uint8_t port = SC_PORT(sc);
8434
8435         /* aggregation of supported attributes of all external phys */
8436         sc->port.supported[0] = 0;
8437         sc->port.supported[1] = 0;
8438
8439         switch (sc->link_params.num_phys) {
8440         case 1:
8441                 sc->port.supported[0] =
8442                     sc->link_params.phy[ELINK_INT_PHY].supported;
8443                 cfg_size = 1;
8444                 break;
8445         case 2:
8446                 sc->port.supported[0] =
8447                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8448                 cfg_size = 1;
8449                 break;
8450         case 3:
8451                 if (sc->link_params.multi_phy_config &
8452                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8453                         sc->port.supported[1] =
8454                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8455                         sc->port.supported[0] =
8456                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8457                 } else {
8458                         sc->port.supported[0] =
8459                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8460                         sc->port.supported[1] =
8461                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8462                 }
8463                 cfg_size = 2;
8464                 break;
8465         }
8466
8467         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8468                 PMD_DRV_LOG(ERR, sc,
8469                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8470                             SHMEM_RD(sc,
8471                                      dev_info.port_hw_config
8472                                      [port].external_phy_config),
8473                             SHMEM_RD(sc,
8474                                      dev_info.port_hw_config
8475                                      [port].external_phy_config2));
8476                 return;
8477         }
8478
8479         if (CHIP_IS_E3(sc))
8480                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8481         else {
8482                 switch (switch_cfg) {
8483                 case ELINK_SWITCH_CFG_1G:
8484                         sc->port.phy_addr =
8485                             REG_RD(sc,
8486                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8487                         break;
8488                 case ELINK_SWITCH_CFG_10G:
8489                         sc->port.phy_addr =
8490                             REG_RD(sc,
8491                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8492                         break;
8493                 default:
8494                         PMD_DRV_LOG(ERR, sc,
8495                                     "Invalid switch config in"
8496                                     "link_config=0x%08x",
8497                                     sc->port.link_config[0]);
8498                         return;
8499                 }
8500         }
8501
8502         PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8503
8504         /* mask what we support according to speed_cap_mask per configuration */
8505         for (idx = 0; idx < cfg_size; idx++) {
8506                 if (!(sc->link_params.speed_cap_mask[idx] &
8507                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8508                         sc->port.supported[idx] &=
8509                             ~ELINK_SUPPORTED_10baseT_Half;
8510                 }
8511
8512                 if (!(sc->link_params.speed_cap_mask[idx] &
8513                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8514                         sc->port.supported[idx] &=
8515                             ~ELINK_SUPPORTED_10baseT_Full;
8516                 }
8517
8518                 if (!(sc->link_params.speed_cap_mask[idx] &
8519                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8520                         sc->port.supported[idx] &=
8521                             ~ELINK_SUPPORTED_100baseT_Half;
8522                 }
8523
8524                 if (!(sc->link_params.speed_cap_mask[idx] &
8525                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8526                         sc->port.supported[idx] &=
8527                             ~ELINK_SUPPORTED_100baseT_Full;
8528                 }
8529
8530                 if (!(sc->link_params.speed_cap_mask[idx] &
8531                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8532                         sc->port.supported[idx] &=
8533                             ~ELINK_SUPPORTED_1000baseT_Full;
8534                 }
8535
8536                 if (!(sc->link_params.speed_cap_mask[idx] &
8537                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8538                         sc->port.supported[idx] &=
8539                             ~ELINK_SUPPORTED_2500baseX_Full;
8540                 }
8541
8542                 if (!(sc->link_params.speed_cap_mask[idx] &
8543                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8544                         sc->port.supported[idx] &=
8545                             ~ELINK_SUPPORTED_10000baseT_Full;
8546                 }
8547
8548                 if (!(sc->link_params.speed_cap_mask[idx] &
8549                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8550                         sc->port.supported[idx] &=
8551                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8552                 }
8553         }
8554
8555         PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8556                     sc->port.supported[0], sc->port.supported[1]);
8557 }
8558
8559 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8560 {
8561         uint32_t link_config;
8562         uint32_t idx;
8563         uint32_t cfg_size = 0;
8564
8565         sc->port.advertising[0] = 0;
8566         sc->port.advertising[1] = 0;
8567
8568         switch (sc->link_params.num_phys) {
8569         case 1:
8570         case 2:
8571                 cfg_size = 1;
8572                 break;
8573         case 3:
8574                 cfg_size = 2;
8575                 break;
8576         }
8577
8578         for (idx = 0; idx < cfg_size; idx++) {
8579                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8580                 link_config = sc->port.link_config[idx];
8581
8582                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8583                 case PORT_FEATURE_LINK_SPEED_AUTO:
8584                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8585                                 sc->link_params.req_line_speed[idx] =
8586                                     ELINK_SPEED_AUTO_NEG;
8587                                 sc->port.advertising[idx] |=
8588                                     sc->port.supported[idx];
8589                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8590                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8591                                         sc->port.advertising[idx] |=
8592                                             (ELINK_SUPPORTED_100baseT_Half |
8593                                              ELINK_SUPPORTED_100baseT_Full);
8594                         } else {
8595                                 /* force 10G, no AN */
8596                                 sc->link_params.req_line_speed[idx] =
8597                                     ELINK_SPEED_10000;
8598                                 sc->port.advertising[idx] |=
8599                                     (ADVERTISED_10000baseT_Full |
8600                                      ADVERTISED_FIBRE);
8601                                 continue;
8602                         }
8603                         break;
8604
8605                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8606                         if (sc->
8607                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8608                         {
8609                                 sc->link_params.req_line_speed[idx] =
8610                                     ELINK_SPEED_10;
8611                                 sc->port.advertising[idx] |=
8612                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8613                         } else {
8614                                 PMD_DRV_LOG(ERR, sc,
8615                                             "Invalid NVRAM config link_config=0x%08x "
8616                                             "speed_cap_mask=0x%08x",
8617                                             link_config,
8618                                             sc->
8619                                             link_params.speed_cap_mask[idx]);
8620                                 return;
8621                         }
8622                         break;
8623
8624                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8625                         if (sc->
8626                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8627                         {
8628                                 sc->link_params.req_line_speed[idx] =
8629                                     ELINK_SPEED_10;
8630                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8631                                 sc->port.advertising[idx] |=
8632                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8633                         } else {
8634                                 PMD_DRV_LOG(ERR, sc,
8635                                             "Invalid NVRAM config link_config=0x%08x "
8636                                             "speed_cap_mask=0x%08x",
8637                                             link_config,
8638                                             sc->
8639                                             link_params.speed_cap_mask[idx]);
8640                                 return;
8641                         }
8642                         break;
8643
8644                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8645                         if (sc->
8646                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8647                         {
8648                                 sc->link_params.req_line_speed[idx] =
8649                                     ELINK_SPEED_100;
8650                                 sc->port.advertising[idx] |=
8651                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8652                         } else {
8653                                 PMD_DRV_LOG(ERR, sc,
8654                                             "Invalid NVRAM config link_config=0x%08x "
8655                                             "speed_cap_mask=0x%08x",
8656                                             link_config,
8657                                             sc->
8658                                             link_params.speed_cap_mask[idx]);
8659                                 return;
8660                         }
8661                         break;
8662
8663                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8664                         if (sc->
8665                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8666                         {
8667                                 sc->link_params.req_line_speed[idx] =
8668                                     ELINK_SPEED_100;
8669                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8670                                 sc->port.advertising[idx] |=
8671                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8672                         } else {
8673                                 PMD_DRV_LOG(ERR, sc,
8674                                             "Invalid NVRAM config link_config=0x%08x "
8675                                             "speed_cap_mask=0x%08x",
8676                                             link_config,
8677                                             sc->
8678                                             link_params.speed_cap_mask[idx]);
8679                                 return;
8680                         }
8681                         break;
8682
8683                 case PORT_FEATURE_LINK_SPEED_1G:
8684                         if (sc->port.supported[idx] &
8685                             ELINK_SUPPORTED_1000baseT_Full) {
8686                                 sc->link_params.req_line_speed[idx] =
8687                                     ELINK_SPEED_1000;
8688                                 sc->port.advertising[idx] |=
8689                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8690                         } else {
8691                                 PMD_DRV_LOG(ERR, sc,
8692                                             "Invalid NVRAM config link_config=0x%08x "
8693                                             "speed_cap_mask=0x%08x",
8694                                             link_config,
8695                                             sc->
8696                                             link_params.speed_cap_mask[idx]);
8697                                 return;
8698                         }
8699                         break;
8700
8701                 case PORT_FEATURE_LINK_SPEED_2_5G:
8702                         if (sc->port.supported[idx] &
8703                             ELINK_SUPPORTED_2500baseX_Full) {
8704                                 sc->link_params.req_line_speed[idx] =
8705                                     ELINK_SPEED_2500;
8706                                 sc->port.advertising[idx] |=
8707                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8708                         } else {
8709                                 PMD_DRV_LOG(ERR, sc,
8710                                             "Invalid NVRAM config link_config=0x%08x "
8711                                             "speed_cap_mask=0x%08x",
8712                                             link_config,
8713                                             sc->
8714                                             link_params.speed_cap_mask[idx]);
8715                                 return;
8716                         }
8717                         break;
8718
8719                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8720                         if (sc->port.supported[idx] &
8721                             ELINK_SUPPORTED_10000baseT_Full) {
8722                                 sc->link_params.req_line_speed[idx] =
8723                                     ELINK_SPEED_10000;
8724                                 sc->port.advertising[idx] |=
8725                                     (ADVERTISED_10000baseT_Full |
8726                                      ADVERTISED_FIBRE);
8727                         } else {
8728                                 PMD_DRV_LOG(ERR, sc,
8729                                             "Invalid NVRAM config link_config=0x%08x "
8730                                             "speed_cap_mask=0x%08x",
8731                                             link_config,
8732                                             sc->
8733                                             link_params.speed_cap_mask[idx]);
8734                                 return;
8735                         }
8736                         break;
8737
8738                 case PORT_FEATURE_LINK_SPEED_20G:
8739                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8740                         break;
8741
8742                 default:
8743                         PMD_DRV_LOG(ERR, sc,
8744                                     "Invalid NVRAM config link_config=0x%08x "
8745                                     "speed_cap_mask=0x%08x", link_config,
8746                                     sc->link_params.speed_cap_mask[idx]);
8747                         sc->link_params.req_line_speed[idx] =
8748                             ELINK_SPEED_AUTO_NEG;
8749                         sc->port.advertising[idx] = sc->port.supported[idx];
8750                         break;
8751                 }
8752
8753                 sc->link_params.req_flow_ctrl[idx] =
8754                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8755
8756                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8757                         if (!
8758                             (sc->
8759                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8760                                 sc->link_params.req_flow_ctrl[idx] =
8761                                     ELINK_FLOW_CTRL_NONE;
8762                         } else {
8763                                 bnx2x_set_requested_fc(sc);
8764                         }
8765                 }
8766         }
8767 }
8768
8769 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8770 {
8771         uint8_t port = SC_PORT(sc);
8772         uint32_t eee_mode;
8773
8774         PMD_INIT_FUNC_TRACE(sc);
8775
8776         /* shmem data already read in bnx2x_get_shmem_info() */
8777
8778         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8779         bnx2x_link_settings_requested(sc);
8780
8781         /* configure link feature according to nvram value */
8782         eee_mode =
8783             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8784               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8785              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8786         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8787                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8788                                             ELINK_EEE_MODE_ENABLE_LPI |
8789                                             ELINK_EEE_MODE_OUTPUT_TIME);
8790         } else {
8791                 sc->link_params.eee_mode = 0;
8792         }
8793
8794         /* get the media type */
8795         bnx2x_media_detect(sc);
8796 }
8797
8798 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8799 {
8800         uint32_t flags = MODE_ASIC | MODE_PORT2;
8801
8802         if (CHIP_IS_E2(sc)) {
8803                 flags |= MODE_E2;
8804         } else if (CHIP_IS_E3(sc)) {
8805                 flags |= MODE_E3;
8806                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8807                         flags |= MODE_E3_A0;
8808                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8809
8810                         flags |= MODE_E3_B0 | MODE_COS3;
8811                 }
8812         }
8813
8814         if (IS_MF(sc)) {
8815                 flags |= MODE_MF;
8816                 switch (sc->devinfo.mf_info.mf_mode) {
8817                 case MULTI_FUNCTION_SD:
8818                         flags |= MODE_MF_SD;
8819                         break;
8820                 case MULTI_FUNCTION_SI:
8821                         flags |= MODE_MF_SI;
8822                         break;
8823                 case MULTI_FUNCTION_AFEX:
8824                         flags |= MODE_MF_AFEX;
8825                         break;
8826                 }
8827         } else {
8828                 flags |= MODE_SF;
8829         }
8830
8831 #if defined(__LITTLE_ENDIAN)
8832         flags |= MODE_LITTLE_ENDIAN;
8833 #else /* __BIG_ENDIAN */
8834         flags |= MODE_BIG_ENDIAN;
8835 #endif
8836
8837         INIT_MODE_FLAGS(sc) = flags;
8838 }
8839
8840 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8841 {
8842         struct bnx2x_fastpath *fp;
8843         char buf[32];
8844         uint32_t i;
8845
8846         if (IS_PF(sc)) {
8847 /************************/
8848 /* DEFAULT STATUS BLOCK */
8849 /************************/
8850
8851                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8852                                   &sc->def_sb_dma, "def_sb",
8853                                   RTE_CACHE_LINE_SIZE) != 0) {
8854                         return -1;
8855                 }
8856
8857                 sc->def_sb =
8858                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8859 /***************/
8860 /* EVENT QUEUE */
8861 /***************/
8862
8863                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8864                                   &sc->eq_dma, "ev_queue",
8865                                   RTE_CACHE_LINE_SIZE) != 0) {
8866                         sc->def_sb = NULL;
8867                         return -1;
8868                 }
8869
8870                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8871
8872 /*************/
8873 /* SLOW PATH */
8874 /*************/
8875
8876                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8877                                   &sc->sp_dma, "sp",
8878                                   RTE_CACHE_LINE_SIZE) != 0) {
8879                         sc->eq = NULL;
8880                         sc->def_sb = NULL;
8881                         return -1;
8882                 }
8883
8884                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8885
8886 /*******************/
8887 /* SLOW PATH QUEUE */
8888 /*******************/
8889
8890                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8891                                   &sc->spq_dma, "sp_queue",
8892                                   RTE_CACHE_LINE_SIZE) != 0) {
8893                         sc->sp = NULL;
8894                         sc->eq = NULL;
8895                         sc->def_sb = NULL;
8896                         return -1;
8897                 }
8898
8899                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8900
8901 /***************************/
8902 /* FW DECOMPRESSION BUFFER */
8903 /***************************/
8904
8905                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8906                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8907                         sc->spq = NULL;
8908                         sc->sp = NULL;
8909                         sc->eq = NULL;
8910                         sc->def_sb = NULL;
8911                         return -1;
8912                 }
8913
8914                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8915         }
8916
8917         /*************/
8918         /* FASTPATHS */
8919         /*************/
8920
8921         /* allocate DMA memory for each fastpath structure */
8922         for (i = 0; i < sc->num_queues; i++) {
8923                 fp = &sc->fp[i];
8924                 fp->sc = sc;
8925                 fp->index = i;
8926
8927 /*******************/
8928 /* FP STATUS BLOCK */
8929 /*******************/
8930
8931                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8932                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8933                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8934                         PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8935                         return -1;
8936                 } else {
8937                         if (CHIP_IS_E2E3(sc)) {
8938                                 fp->status_block.e2_sb =
8939                                     (struct host_hc_status_block_e2 *)
8940                                     fp->sb_dma.vaddr;
8941                         } else {
8942                                 fp->status_block.e1x_sb =
8943                                     (struct host_hc_status_block_e1x *)
8944                                     fp->sb_dma.vaddr;
8945                         }
8946                 }
8947         }
8948
8949         return 0;
8950 }
8951
8952 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8953 {
8954         struct bnx2x_fastpath *fp;
8955         int i;
8956
8957         for (i = 0; i < sc->num_queues; i++) {
8958                 fp = &sc->fp[i];
8959
8960 /*******************/
8961 /* FP STATUS BLOCK */
8962 /*******************/
8963
8964                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8965         }
8966
8967         /***************************/
8968         /* FW DECOMPRESSION BUFFER */
8969         /***************************/
8970
8971         sc->gz_buf = NULL;
8972
8973         /*******************/
8974         /* SLOW PATH QUEUE */
8975         /*******************/
8976
8977         sc->spq = NULL;
8978
8979         /*************/
8980         /* SLOW PATH */
8981         /*************/
8982
8983         sc->sp = NULL;
8984
8985         /***************/
8986         /* EVENT QUEUE */
8987         /***************/
8988
8989         sc->eq = NULL;
8990
8991         /************************/
8992         /* DEFAULT STATUS BLOCK */
8993         /************************/
8994
8995         sc->def_sb = NULL;
8996
8997 }
8998
8999 /*
9000 * Previous driver DMAE transaction may have occurred when pre-boot stage
9001 * ended and boot began. This would invalidate the addresses of the
9002 * transaction, resulting in was-error bit set in the PCI causing all
9003 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9004 * the interrupt which detected this from the pglueb and the was-done bit
9005 */
9006 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9007 {
9008         uint32_t val;
9009
9010         if (!CHIP_IS_E1x(sc)) {
9011                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9012                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9013                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9014                                1 << SC_FUNC(sc));
9015                 }
9016         }
9017 }
9018
9019 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9020 {
9021         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9022                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9023         if (!rc) {
9024                 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9025                 return -1;
9026         }
9027
9028         return 0;
9029 }
9030
9031 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9032 {
9033         struct bnx2x_prev_list_node *tmp;
9034
9035         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9036                 if ((sc->pcie_bus == tmp->bus) &&
9037                     (sc->pcie_device == tmp->slot) &&
9038                     (SC_PATH(sc) == tmp->path)) {
9039                         return tmp;
9040                 }
9041         }
9042
9043         return NULL;
9044 }
9045
9046 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9047 {
9048         struct bnx2x_prev_list_node *tmp;
9049         int rc = FALSE;
9050
9051         rte_spinlock_lock(&bnx2x_prev_mtx);
9052
9053         tmp = bnx2x_prev_path_get_entry(sc);
9054         if (tmp) {
9055                 if (tmp->aer) {
9056                         PMD_DRV_LOG(DEBUG, sc,
9057                                     "Path %d/%d/%d was marked by AER",
9058                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9059                 } else {
9060                         rc = TRUE;
9061                         PMD_DRV_LOG(DEBUG, sc,
9062                                     "Path %d/%d/%d was already cleaned from previous drivers",
9063                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9064                 }
9065         }
9066
9067         rte_spinlock_unlock(&bnx2x_prev_mtx);
9068
9069         return rc;
9070 }
9071
9072 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9073 {
9074         struct bnx2x_prev_list_node *tmp;
9075
9076         rte_spinlock_lock(&bnx2x_prev_mtx);
9077
9078         /* Check whether the entry for this path already exists */
9079         tmp = bnx2x_prev_path_get_entry(sc);
9080         if (tmp) {
9081                 if (!tmp->aer) {
9082                         PMD_DRV_LOG(DEBUG, sc,
9083                                     "Re-marking AER in path %d/%d/%d",
9084                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9085                 } else {
9086                         PMD_DRV_LOG(DEBUG, sc,
9087                                     "Removing AER indication from path %d/%d/%d",
9088                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9089                         tmp->aer = 0;
9090                 }
9091
9092                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9093                 return 0;
9094         }
9095
9096         rte_spinlock_unlock(&bnx2x_prev_mtx);
9097
9098         /* Create an entry for this path and add it */
9099         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9100                          RTE_CACHE_LINE_SIZE);
9101         if (!tmp) {
9102                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9103                 return -1;
9104         }
9105
9106         tmp->bus = sc->pcie_bus;
9107         tmp->slot = sc->pcie_device;
9108         tmp->path = SC_PATH(sc);
9109         tmp->aer = 0;
9110         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9111
9112         rte_spinlock_lock(&bnx2x_prev_mtx);
9113
9114         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9115
9116         rte_spinlock_unlock(&bnx2x_prev_mtx);
9117
9118         return 0;
9119 }
9120
9121 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9122 {
9123         int i;
9124
9125         /* only E2 and onwards support FLR */
9126         if (CHIP_IS_E1x(sc)) {
9127                 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9128                 return -1;
9129         }
9130
9131         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9132         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9133                 PMD_DRV_LOG(WARNING, sc,
9134                             "FLR not supported by BC_VER: 0x%08x",
9135                             sc->devinfo.bc_ver);
9136                 return -1;
9137         }
9138
9139         /* Wait for Transaction Pending bit clean */
9140         for (i = 0; i < 4; i++) {
9141                 if (i) {
9142                         DELAY(((1 << (i - 1)) * 100) * 1000);
9143                 }
9144
9145                 if (!bnx2x_is_pcie_pending(sc)) {
9146                         goto clear;
9147                 }
9148         }
9149
9150         PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9151                     "proceeding with reset anyway");
9152
9153 clear:
9154         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9155
9156         return 0;
9157 }
9158
9159 struct bnx2x_mac_vals {
9160         uint32_t xmac_addr;
9161         uint32_t xmac_val;
9162         uint32_t emac_addr;
9163         uint32_t emac_val;
9164         uint32_t umac_addr;
9165         uint32_t umac_val;
9166         uint32_t bmac_addr;
9167         uint32_t bmac_val[2];
9168 };
9169
9170 static void
9171 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9172 {
9173         uint32_t val, base_addr, offset, mask, reset_reg;
9174         uint8_t mac_stopped = FALSE;
9175         uint8_t port = SC_PORT(sc);
9176         uint32_t wb_data[2];
9177
9178         /* reset addresses as they also mark which values were changed */
9179         vals->bmac_addr = 0;
9180         vals->umac_addr = 0;
9181         vals->xmac_addr = 0;
9182         vals->emac_addr = 0;
9183
9184         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9185
9186         if (!CHIP_IS_E3(sc)) {
9187                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9188                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9189                 if ((mask & reset_reg) && val) {
9190                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9191                             : NIG_REG_INGRESS_BMAC0_MEM;
9192                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9193                             : BIGMAC_REGISTER_BMAC_CONTROL;
9194
9195                         /*
9196                          * use rd/wr since we cannot use dmae. This is safe
9197                          * since MCP won't access the bus due to the request
9198                          * to unload, and no function on the path can be
9199                          * loaded at this time.
9200                          */
9201                         wb_data[0] = REG_RD(sc, base_addr + offset);
9202                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9203                         vals->bmac_addr = base_addr + offset;
9204                         vals->bmac_val[0] = wb_data[0];
9205                         vals->bmac_val[1] = wb_data[1];
9206                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9207                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9208                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9209                 }
9210
9211                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9212                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9213                 REG_WR(sc, vals->emac_addr, 0);
9214                 mac_stopped = TRUE;
9215         } else {
9216                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9217                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9218                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9219                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9220                                val & ~(1 << 1));
9221                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9222                                val | (1 << 1));
9223                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9224                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9225                         REG_WR(sc, vals->xmac_addr, 0);
9226                         mac_stopped = TRUE;
9227                 }
9228
9229                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9230                 if (mask & reset_reg) {
9231                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9232                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9233                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9234                         REG_WR(sc, vals->umac_addr, 0);
9235                         mac_stopped = TRUE;
9236                 }
9237         }
9238
9239         if (mac_stopped) {
9240                 DELAY(20000);
9241         }
9242 }
9243
9244 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9245 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9246 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9247 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9248
9249 static void
9250 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9251 {
9252         uint16_t rcq, bd;
9253         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9254
9255         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9256         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9257
9258         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9259         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9260 }
9261
9262 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9263 {
9264         uint32_t reset_reg, tmp_reg = 0, rc;
9265         uint8_t prev_undi = FALSE;
9266         struct bnx2x_mac_vals mac_vals;
9267         uint32_t timer_count = 1000;
9268         uint32_t prev_brb;
9269
9270         /*
9271          * It is possible a previous function received 'common' answer,
9272          * but hasn't loaded yet, therefore creating a scenario of
9273          * multiple functions receiving 'common' on the same path.
9274          */
9275         memset(&mac_vals, 0, sizeof(mac_vals));
9276
9277         if (bnx2x_prev_is_path_marked(sc)) {
9278                 return bnx2x_prev_mcp_done(sc);
9279         }
9280
9281         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9282
9283         /* Reset should be performed after BRB is emptied */
9284         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9285                 /* Close the MAC Rx to prevent BRB from filling up */
9286                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9287
9288                 /* close LLH filters towards the BRB */
9289                 elink_set_rx_filter(&sc->link_params, 0);
9290
9291                 /*
9292                  * Check if the UNDI driver was previously loaded.
9293                  * UNDI driver initializes CID offset for normal bell to 0x7
9294                  */
9295                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9296                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9297                         if (tmp_reg == 0x7) {
9298                                 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9299                                 prev_undi = TRUE;
9300                                 /* clear the UNDI indication */
9301                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9302                                 /* clear possible idle check errors */
9303                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9304                         }
9305                 }
9306
9307                 /* wait until BRB is empty */
9308                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9309                 while (timer_count) {
9310                         prev_brb = tmp_reg;
9311
9312                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9313                         if (!tmp_reg) {
9314                                 break;
9315                         }
9316
9317                         PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9318
9319                         /* reset timer as long as BRB actually gets emptied */
9320                         if (prev_brb > tmp_reg) {
9321                                 timer_count = 1000;
9322                         } else {
9323                                 timer_count--;
9324                         }
9325
9326                         /* If UNDI resides in memory, manually increment it */
9327                         if (prev_undi) {
9328                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9329                         }
9330
9331                         DELAY(10);
9332                 }
9333
9334                 if (!timer_count) {
9335                         PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9336                 }
9337         }
9338
9339         /* No packets are in the pipeline, path is ready for reset */
9340         bnx2x_reset_common(sc);
9341
9342         if (mac_vals.xmac_addr) {
9343                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9344         }
9345         if (mac_vals.umac_addr) {
9346                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9347         }
9348         if (mac_vals.emac_addr) {
9349                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9350         }
9351         if (mac_vals.bmac_addr) {
9352                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9353                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9354         }
9355
9356         rc = bnx2x_prev_mark_path(sc, prev_undi);
9357         if (rc) {
9358                 bnx2x_prev_mcp_done(sc);
9359                 return rc;
9360         }
9361
9362         return bnx2x_prev_mcp_done(sc);
9363 }
9364
9365 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9366 {
9367         int rc;
9368
9369         /* Test if previous unload process was already finished for this path */
9370         if (bnx2x_prev_is_path_marked(sc)) {
9371                 return bnx2x_prev_mcp_done(sc);
9372         }
9373
9374         /*
9375          * If function has FLR capabilities, and existing FW version matches
9376          * the one required, then FLR will be sufficient to clean any residue
9377          * left by previous driver
9378          */
9379         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9380         if (!rc) {
9381                 /* fw version is good */
9382                 rc = bnx2x_do_flr(sc);
9383         }
9384
9385         if (!rc) {
9386                 /* FLR was performed */
9387                 return 0;
9388         }
9389
9390         PMD_DRV_LOG(INFO, sc, "Could not FLR");
9391
9392         /* Close the MCP request, return failure */
9393         rc = bnx2x_prev_mcp_done(sc);
9394         if (!rc) {
9395                 rc = BNX2X_PREV_WAIT_NEEDED;
9396         }
9397
9398         return rc;
9399 }
9400
9401 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9402 {
9403         int time_counter = 10;
9404         uint32_t fw, hw_lock_reg, hw_lock_val;
9405         uint32_t rc = 0;
9406
9407         PMD_INIT_FUNC_TRACE(sc);
9408
9409         /*
9410          * Clear HW from errors which may have resulted from an interrupted
9411          * DMAE transaction.
9412          */
9413         bnx2x_prev_interrupted_dmae(sc);
9414
9415         /* Release previously held locks */
9416         hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9417                         (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9418                         (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9419
9420         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9421         if (hw_lock_val) {
9422                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9423                         PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9424                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9425                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9426                 }
9427                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9428                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9429         }
9430
9431         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9432                 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9433                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9434         }
9435
9436         do {
9437                 /* Lock MCP using an unload request */
9438                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9439                 if (!fw) {
9440                         PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9441                         rc = -1;
9442                         break;
9443                 }
9444
9445                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9446                         rc = bnx2x_prev_unload_common(sc);
9447                         break;
9448                 }
9449
9450                 /* non-common reply from MCP might require looping */
9451                 rc = bnx2x_prev_unload_uncommon(sc);
9452                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9453                         break;
9454                 }
9455
9456                 DELAY(20000);
9457         } while (--time_counter);
9458
9459         if (!time_counter || rc) {
9460                 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9461                 rc = -1;
9462         }
9463
9464         return rc;
9465 }
9466
9467 static void
9468 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9469 {
9470         if (!CHIP_IS_E1x(sc)) {
9471                 sc->dcb_state = dcb_on;
9472                 sc->dcbx_enabled = dcbx_enabled;
9473         } else {
9474                 sc->dcb_state = FALSE;
9475                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9476         }
9477         PMD_DRV_LOG(DEBUG, sc,
9478                     "DCB state [%s:%s]",
9479                     dcb_on ? "ON" : "OFF",
9480                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9481                     (dcbx_enabled ==
9482                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9483                     : (dcbx_enabled ==
9484                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9485                     "on-chip with negotiation" : "invalid");
9486 }
9487
9488 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9489 {
9490         int cid_count = BNX2X_L2_MAX_CID(sc);
9491
9492         if (CNIC_SUPPORT(sc)) {
9493                 cid_count += CNIC_CID_MAX;
9494         }
9495
9496         return roundup(cid_count, QM_CID_ROUND);
9497 }
9498
9499 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9500 {
9501         int pri, cos;
9502
9503         uint32_t pri_map = 0;
9504
9505         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9506                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9507                 if (cos < sc->max_cos) {
9508                         sc->prio_to_cos[pri] = cos;
9509                 } else {
9510                         PMD_DRV_LOG(WARNING, sc,
9511                                     "Invalid COS %d for priority %d "
9512                                     "(max COS is %d), setting to 0", cos, pri,
9513                                     (sc->max_cos - 1));
9514                         sc->prio_to_cos[pri] = 0;
9515                 }
9516         }
9517 }
9518
9519 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9520 {
9521         struct {
9522                 uint8_t id;
9523                 uint8_t next;
9524         } pci_cap;
9525         uint16_t status;
9526         struct bnx2x_pci_cap *cap;
9527
9528         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9529                                          RTE_CACHE_LINE_SIZE);
9530         if (!cap) {
9531                 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9532                 return -ENOMEM;
9533         }
9534
9535 #ifndef __FreeBSD__
9536         pci_read(sc, PCI_STATUS, &status, 2);
9537         if (!(status & PCI_STATUS_CAP_LIST)) {
9538 #else
9539         pci_read(sc, PCIR_STATUS, &status, 2);
9540         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9541 #endif
9542                 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9543                 return -1;
9544         }
9545
9546 #ifndef __FreeBSD__
9547         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9548 #else
9549         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9550 #endif
9551         while (pci_cap.next) {
9552                 cap->addr = pci_cap.next & ~3;
9553                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9554                 if (pci_cap.id == 0xff)
9555                         break;
9556                 cap->id = pci_cap.id;
9557                 cap->type = BNX2X_PCI_CAP;
9558                 cap->next = rte_zmalloc("pci_cap",
9559                                         sizeof(struct bnx2x_pci_cap),
9560                                         RTE_CACHE_LINE_SIZE);
9561                 if (!cap->next) {
9562                         PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9563                         return -ENOMEM;
9564                 }
9565                 cap = cap->next;
9566         }
9567
9568         return 0;
9569 }
9570
9571 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9572 {
9573         if (IS_VF(sc)) {
9574                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9575                                         sc->igu_sb_cnt);
9576                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9577                                         sc->igu_sb_cnt);
9578         } else {
9579                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9580                 sc->max_tx_queues = sc->max_rx_queues;
9581         }
9582 }
9583
9584 #define FW_HEADER_LEN 104
9585 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9586 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9587
9588 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9589 {
9590         const char *fwname;
9591         int f;
9592         struct stat st;
9593
9594         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9595                 ? FW_NAME_57711 : FW_NAME_57810;
9596         f = open(fwname, O_RDONLY);
9597         if (f < 0) {
9598                 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9599                 return;
9600         }
9601
9602         if (fstat(f, &st) < 0) {
9603                 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9604                 close(f);
9605                 return;
9606         }
9607
9608         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9609         if (!sc->firmware) {
9610                 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9611                 close(f);
9612                 return;
9613         }
9614
9615         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9616                 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9617                 close(f);
9618                 return;
9619         }
9620         close(f);
9621
9622         sc->fw_len = st.st_size;
9623         if (sc->fw_len < FW_HEADER_LEN) {
9624                 PMD_DRV_LOG(NOTICE, sc,
9625                             "Invalid fw size: %" PRIu64, sc->fw_len);
9626                 return;
9627         }
9628         PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9629 }
9630
9631 static void
9632 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9633 {
9634         uint32_t *src = (uint32_t *) data;
9635         uint32_t i, j, tmp;
9636
9637         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9638                 tmp = rte_be_to_cpu_32(src[j]);
9639                 dst[i].op = (tmp >> 24) & 0xFF;
9640                 dst[i].offset = tmp & 0xFFFFFF;
9641                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9642         }
9643 }
9644
9645 static void
9646 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9647 {
9648         uint16_t *src = (uint16_t *) data;
9649         uint32_t i;
9650
9651         for (i = 0; i < len / 2; ++i)
9652                 dst[i] = rte_be_to_cpu_16(src[i]);
9653 }
9654
9655 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9656 {
9657         uint32_t *src = (uint32_t *) data;
9658         uint32_t i;
9659
9660         for (i = 0; i < len / 4; ++i)
9661                 dst[i] = rte_be_to_cpu_32(src[i]);
9662 }
9663
9664 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9665 {
9666         uint32_t *src = (uint32_t *) data;
9667         uint32_t i, j, tmp;
9668
9669         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9670                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9671                 tmp = rte_be_to_cpu_32(src[j]);
9672                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9673                 dst[i].m2 = tmp & 0xFFFF;
9674                 ++j;
9675                 tmp = rte_be_to_cpu_32(src[j]);
9676                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9677                 dst[i].size = tmp & 0xFFFF;
9678         }
9679 }
9680
9681 /*
9682 * Device attach function.
9683 *
9684 * Allocates device resources, performs secondary chip identification, and
9685 * initializes driver instance variables. This function is called from driver
9686 * load after a successful probe.
9687 *
9688 * Returns:
9689 *   0 = Success, >0 = Failure
9690 */
9691 int bnx2x_attach(struct bnx2x_softc *sc)
9692 {
9693         int rc;
9694
9695         PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9696
9697         rc = bnx2x_pci_get_caps(sc);
9698         if (rc) {
9699                 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9700                 return rc;
9701         }
9702
9703         sc->state = BNX2X_STATE_CLOSED;
9704
9705         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9706
9707         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9708
9709         /* get PCI capabilites */
9710         bnx2x_probe_pci_caps(sc);
9711
9712         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9713                 uint32_t val;
9714                 pci_read(sc,
9715                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9716                          2);
9717                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9718         } else {
9719                 sc->igu_sb_cnt = 1;
9720         }
9721
9722         /* Init RTE stuff */
9723         bnx2x_init_rte(sc);
9724
9725         if (IS_PF(sc)) {
9726                 /* Enable internal target-read (in case we are probed after PF
9727                  * FLR). Must be done prior to any BAR read access. Only for
9728                  * 57712 and up
9729                  */
9730                 if (!CHIP_IS_E1x(sc)) {
9731                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9732                                1);
9733                         DELAY(200000);
9734                 }
9735
9736                 /* get device info and set params */
9737                 if (bnx2x_get_device_info(sc) != 0) {
9738                         PMD_DRV_LOG(NOTICE, sc, "getting device info");
9739                         return -ENXIO;
9740                 }
9741
9742 /* get phy settings from shmem and 'and' against admin settings */
9743                 bnx2x_get_phy_info(sc);
9744         } else {
9745                 /* Left mac of VF unfilled, PF should set it for VF */
9746                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9747         }
9748
9749         sc->wol = 0;
9750
9751         /* set the default MTU (changed via ifconfig) */
9752         sc->mtu = ETHER_MTU;
9753
9754         bnx2x_set_modes_bitmap(sc);
9755
9756         /* need to reset chip if UNDI was active */
9757         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9758 /* init fw_seq */
9759                 sc->fw_seq =
9760                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9761                      DRV_MSG_SEQ_NUMBER_MASK);
9762                 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9763                             sc->fw_seq);
9764                 bnx2x_prev_unload(sc);
9765         }
9766
9767         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9768
9769         /* calculate qm_cid_count */
9770         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9771
9772         sc->max_cos = 1;
9773         bnx2x_init_multi_cos(sc);
9774
9775         return 0;
9776 }
9777
9778 static void
9779 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9780                uint16_t index, uint8_t op, uint8_t update)
9781 {
9782         uint32_t igu_addr = sc->igu_base_addr;
9783         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9784         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9785 }
9786
9787 static void
9788 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9789            uint16_t index, uint8_t op, uint8_t update)
9790 {
9791         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9792                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9793         else {
9794                 uint8_t segment;
9795                 if (CHIP_INT_MODE_IS_BC(sc)) {
9796                         segment = storm;
9797                 } else if (igu_sb_id != sc->igu_dsb_id) {
9798                         segment = IGU_SEG_ACCESS_DEF;
9799                 } else if (storm == ATTENTION_ID) {
9800                         segment = IGU_SEG_ACCESS_ATTN;
9801                 } else {
9802                         segment = IGU_SEG_ACCESS_DEF;
9803                 }
9804                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9805         }
9806 }
9807
9808 static void
9809 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9810                      uint8_t is_pf)
9811 {
9812         uint32_t data, ctl, cnt = 100;
9813         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9814         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9815         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9816             (idu_sb_id / 32) * 4;
9817         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9818         uint32_t func_encode = func |
9819             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9820         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9821
9822         /* Not supported in BC mode */
9823         if (CHIP_INT_MODE_IS_BC(sc)) {
9824                 return;
9825         }
9826
9827         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9828                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9829                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9830
9831         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9832                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9833                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9834
9835         REG_WR(sc, igu_addr_data, data);
9836
9837         mb();
9838
9839         PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9840                     ctl, igu_addr_ctl);
9841         REG_WR(sc, igu_addr_ctl, ctl);
9842
9843         mb();
9844
9845         /* wait for clean up to finish */
9846         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9847                 DELAY(20000);
9848         }
9849
9850         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9851                 PMD_DRV_LOG(DEBUG, sc,
9852                             "Unable to finish IGU cleanup: "
9853                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9854                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9855         }
9856 }
9857
9858 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9859 {
9860         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9861 }
9862
9863 /*******************/
9864 /* ECORE CALLBACKS */
9865 /*******************/
9866
9867 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9868 {
9869         uint32_t val = 0x1400;
9870
9871         PMD_INIT_FUNC_TRACE(sc);
9872
9873         /* reset_common */
9874         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9875                0xd3ffff7f);
9876
9877         if (CHIP_IS_E3(sc)) {
9878                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9879                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9880         }
9881
9882         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9883 }
9884
9885 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9886 {
9887         uint32_t shmem_base[2];
9888         uint32_t shmem2_base[2];
9889
9890         /* Avoid common init in case MFW supports LFA */
9891         if (SHMEM2_RD(sc, size) >
9892             (uint32_t) offsetof(struct shmem2_region,
9893                                 lfa_host_addr[SC_PORT(sc)])) {
9894                 return;
9895         }
9896
9897         shmem_base[0] = sc->devinfo.shmem_base;
9898         shmem2_base[0] = sc->devinfo.shmem2_base;
9899
9900         if (!CHIP_IS_E1x(sc)) {
9901                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9902                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9903         }
9904
9905         bnx2x_acquire_phy_lock(sc);
9906         elink_common_init_phy(sc, shmem_base, shmem2_base,
9907                               sc->devinfo.chip_id, 0);
9908         bnx2x_release_phy_lock(sc);
9909 }
9910
9911 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9912 {
9913         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9914
9915         val &= ~IGU_PF_CONF_FUNC_EN;
9916
9917         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9918         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9919         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9920 }
9921
9922 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9923 {
9924         uint16_t devctl;
9925         int r_order, w_order;
9926
9927         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9928
9929         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9930         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9931
9932         ecore_init_pxp_arb(sc, r_order, w_order);
9933 }
9934
9935 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9936 {
9937         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9938         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9939         return base + (SC_ABS_FUNC(sc)) * stride;
9940 }
9941
9942 /*
9943  * Called only on E1H or E2.
9944  * When pretending to be PF, the pretend value is the function number 0..7.
9945  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9946  * combination.
9947  */
9948 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9949 {
9950         uint32_t pretend_reg;
9951
9952         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9953                 return -1;
9954
9955         /* get my own pretend register */
9956         pretend_reg = bnx2x_get_pretend_reg(sc);
9957         REG_WR(sc, pretend_reg, pretend_func_val);
9958         REG_RD(sc, pretend_reg);
9959         return 0;
9960 }
9961
9962 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9963 {
9964         int is_required;
9965         uint32_t val;
9966         int port;
9967
9968         is_required = 0;
9969         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9970                SHARED_HW_CFG_FAN_FAILURE_MASK);
9971
9972         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9973                 is_required = 1;
9974         }
9975         /*
9976          * The fan failure mechanism is usually related to the PHY type since
9977          * the power consumption of the board is affected by the PHY. Currently,
9978          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9979          */
9980         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9981                 for (port = PORT_0; port < PORT_MAX; port++) {
9982                         is_required |= elink_fan_failure_det_req(sc,
9983                                                                  sc->
9984                                                                  devinfo.shmem_base,
9985                                                                  sc->
9986                                                                  devinfo.shmem2_base,
9987                                                                  port);
9988                 }
9989         }
9990
9991         if (is_required == 0) {
9992                 return;
9993         }
9994
9995         /* Fan failure is indicated by SPIO 5 */
9996         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9997
9998         /* set to active low mode */
9999         val = REG_RD(sc, MISC_REG_SPIO_INT);
10000         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10001         REG_WR(sc, MISC_REG_SPIO_INT, val);
10002
10003         /* enable interrupt to signal the IGU */
10004         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10005         val |= MISC_SPIO_SPIO5;
10006         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10007 }
10008
10009 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10010 {
10011         uint32_t val;
10012
10013         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10014         if (!CHIP_IS_E1x(sc)) {
10015                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10016         } else {
10017                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10018         }
10019         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10020         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10021         /*
10022          * mask read length error interrupts in brb for parser
10023          * (parsing unit and 'checksum and crc' unit)
10024          * these errors are legal (PU reads fixed length and CAC can cause
10025          * read length error on truncated packets)
10026          */
10027         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10028         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10029         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10030         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10031         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10032         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10033         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10034         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10035         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10036         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10037         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10038         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10039         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10040         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10041         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10042         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10043         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10044         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10045         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10046
10047         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10048                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10049                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10050         if (!CHIP_IS_E1x(sc)) {
10051                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10052                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10053         }
10054         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10055
10056         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10057         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10058         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10059         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10060
10061         if (!CHIP_IS_E1x(sc)) {
10062 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10063                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10064         }
10065
10066         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10067         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10068         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10069         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10070 }
10071
10072 /**
10073  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10074  *
10075  * @sc:     driver handle
10076  */
10077 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10078 {
10079         uint8_t abs_func_id;
10080         uint32_t val;
10081
10082         PMD_DRV_LOG(DEBUG, sc,
10083                     "starting common init for func %d", SC_ABS_FUNC(sc));
10084
10085         /*
10086          * take the RESET lock to protect undi_unload flow from accessing
10087          * registers while we are resetting the chip
10088          */
10089         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10090
10091         bnx2x_reset_common(sc);
10092
10093         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10094
10095         val = 0xfffc;
10096         if (CHIP_IS_E3(sc)) {
10097                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10098                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10099         }
10100
10101         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10102
10103         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10104
10105         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10106
10107         if (!CHIP_IS_E1x(sc)) {
10108 /*
10109  * 4-port mode or 2-port mode we need to turn off master-enable for
10110  * everyone. After that we turn it back on for self. So, we disregard
10111  * multi-function, and always disable all functions on the given path,
10112  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10113  */
10114                 for (abs_func_id = SC_PATH(sc);
10115                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10116                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10117                                 REG_WR(sc,
10118                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10119                                        1);
10120                                 continue;
10121                         }
10122
10123                         bnx2x_pretend_func(sc, abs_func_id);
10124
10125                         /* clear pf enable */
10126                         bnx2x_pf_disable(sc);
10127
10128                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10129                 }
10130         }
10131
10132         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10133
10134         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10135         bnx2x_init_pxp(sc);
10136
10137 #ifdef __BIG_ENDIAN
10138         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10139         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10140         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10141         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10142         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10143         /* make sure this value is 0 */
10144         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10145
10146         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10147         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10148         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10149         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10150         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10151 #endif
10152
10153         ecore_ilt_init_page_size(sc, INITOP_SET);
10154
10155         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10156                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10157         }
10158
10159         /* let the HW do it's magic... */
10160         DELAY(100000);
10161
10162         /* finish PXP init */
10163
10164         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10165         if (val != 1) {
10166                 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10167                 return -1;
10168         }
10169         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10170         if (val != 1) {
10171                 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10172                 return -1;
10173         }
10174
10175         /*
10176          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10177          * entries with value "0" and valid bit on. This needs to be done by the
10178          * first PF that is loaded in a path (i.e. common phase)
10179          */
10180         if (!CHIP_IS_E1x(sc)) {
10181 /*
10182  * In E2 there is a bug in the timers block that can cause function 6 / 7
10183  * (i.e. vnic3) to start even if it is marked as "scan-off".
10184  * This occurs when a different function (func2,3) is being marked
10185  * as "scan-off". Real-life scenario for example: if a driver is being
10186  * load-unloaded while func6,7 are down. This will cause the timer to access
10187  * the ilt, translate to a logical address and send a request to read/write.
10188  * Since the ilt for the function that is down is not valid, this will cause
10189  * a translation error which is unrecoverable.
10190  * The Workaround is intended to make sure that when this happens nothing
10191  * fatal will occur. The workaround:
10192  *  1.  First PF driver which loads on a path will:
10193  *      a.  After taking the chip out of reset, by using pretend,
10194  *          it will write "0" to the following registers of
10195  *          the other vnics.
10196  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10197  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10198  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10199  *          And for itself it will write '1' to
10200  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10201  *          dmae-operations (writing to pram for example.)
10202  *          note: can be done for only function 6,7 but cleaner this
10203  *            way.
10204  *      b.  Write zero+valid to the entire ILT.
10205  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10206  *          VNIC3 (of that port). The range allocated will be the
10207  *          entire ILT. This is needed to prevent  ILT range error.
10208  *  2.  Any PF driver load flow:
10209  *      a.  ILT update with the physical addresses of the allocated
10210  *          logical pages.
10211  *      b.  Wait 20msec. - note that this timeout is needed to make
10212  *          sure there are no requests in one of the PXP internal
10213  *          queues with "old" ILT addresses.
10214  *      c.  PF enable in the PGLC.
10215  *      d.  Clear the was_error of the PF in the PGLC. (could have
10216  *          occurred while driver was down)
10217  *      e.  PF enable in the CFC (WEAK + STRONG)
10218  *      f.  Timers scan enable
10219  *  3.  PF driver unload flow:
10220  *      a.  Clear the Timers scan_en.
10221  *      b.  Polling for scan_on=0 for that PF.
10222  *      c.  Clear the PF enable bit in the PXP.
10223  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10224  *      e.  Write zero+valid to all ILT entries (The valid bit must
10225  *          stay set)
10226  *      f.  If this is VNIC 3 of a port then also init
10227  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10228  *          to the last enrty in the ILT.
10229  *
10230  *      Notes:
10231  *      Currently the PF error in the PGLC is non recoverable.
10232  *      In the future the there will be a recovery routine for this error.
10233  *      Currently attention is masked.
10234  *      Having an MCP lock on the load/unload process does not guarantee that
10235  *      there is no Timer disable during Func6/7 enable. This is because the
10236  *      Timers scan is currently being cleared by the MCP on FLR.
10237  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10238  *      there is error before clearing it. But the flow above is simpler and
10239  *      more general.
10240  *      All ILT entries are written by zero+valid and not just PF6/7
10241  *      ILT entries since in the future the ILT entries allocation for
10242  *      PF-s might be dynamic.
10243  */
10244                 struct ilt_client_info ilt_cli;
10245                 struct ecore_ilt ilt;
10246
10247                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10248                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10249
10250 /* initialize dummy TM client */
10251                 ilt_cli.start = 0;
10252                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10253                 ilt_cli.client_num = ILT_CLIENT_TM;
10254
10255 /*
10256  * Step 1: set zeroes to all ilt page entries with valid bit on
10257  * Step 2: set the timers first/last ilt entry to point
10258  * to the entire range to prevent ILT range error for 3rd/4th
10259  * vnic (this code assumes existence of the vnic)
10260  *
10261  * both steps performed by call to ecore_ilt_client_init_op()
10262  * with dummy TM client
10263  *
10264  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10265  * and his brother are split registers
10266  */
10267
10268                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10269                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10270                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10271
10272                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10273                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10274                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10275         }
10276
10277         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10278         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10279
10280         if (!CHIP_IS_E1x(sc)) {
10281                 int factor = 0;
10282
10283                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10284                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10285
10286 /* let the HW do it's magic... */
10287                 do {
10288                         DELAY(200000);
10289                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10290                 } while (factor-- && (val != 1));
10291
10292                 if (val != 1) {
10293                         PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10294                         return -1;
10295                 }
10296         }
10297
10298         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10299
10300         /* clean the DMAE memory */
10301         sc->dmae_ready = 1;
10302         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10303
10304         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10305
10306         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10307
10308         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10309
10310         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10311
10312         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10313         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10314         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10315         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10316
10317         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10318
10319         /* QM queues pointers table */
10320         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10321
10322         /* soft reset pulse */
10323         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10324         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10325
10326         if (CNIC_SUPPORT(sc))
10327                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10328
10329         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10330         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10331
10332         if (!CHIP_REV_IS_SLOW(sc)) {
10333 /* enable hw interrupt from doorbell Q */
10334                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10335         }
10336
10337         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10338
10339         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10340         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10341         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10342
10343         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10344                 if (IS_MF_AFEX(sc)) {
10345                         /*
10346                          * configure that AFEX and VLAN headers must be
10347                          * received in AFEX mode
10348                          */
10349                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10350                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10351                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10352                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10353                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10354                 } else {
10355                         /*
10356                          * Bit-map indicating which L2 hdrs may appear
10357                          * after the basic Ethernet header
10358                          */
10359                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10360                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10361                 }
10362         }
10363
10364         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10365         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10366         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10367         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10368
10369         if (!CHIP_IS_E1x(sc)) {
10370 /* reset VFC memories */
10371                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10372                        VFC_MEMORIES_RST_REG_CAM_RST |
10373                        VFC_MEMORIES_RST_REG_RAM_RST);
10374                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10375                        VFC_MEMORIES_RST_REG_CAM_RST |
10376                        VFC_MEMORIES_RST_REG_RAM_RST);
10377
10378                 DELAY(20000);
10379         }
10380
10381         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10382         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10383         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10384         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10385
10386         /* sync semi rtc */
10387         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10388         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10389
10390         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10391         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10392         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10393
10394         if (!CHIP_IS_E1x(sc)) {
10395                 if (IS_MF_AFEX(sc)) {
10396                         /*
10397                          * configure that AFEX and VLAN headers must be
10398                          * sent in AFEX mode
10399                          */
10400                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10401                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10402                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10403                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10404                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10405                 } else {
10406                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10407                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10408                 }
10409         }
10410
10411         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10412
10413         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10414
10415         if (CNIC_SUPPORT(sc)) {
10416                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10417                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10418                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10419                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10420                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10421                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10422                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10423                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10424                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10425                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10426         }
10427         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10428
10429         if (sizeof(union cdu_context) != 1024) {
10430 /* we currently assume that a context is 1024 bytes */
10431                 PMD_DRV_LOG(NOTICE, sc,
10432                             "please adjust the size of cdu_context(%ld)",
10433                             (long)sizeof(union cdu_context));
10434         }
10435
10436         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10437         val = (4 << 24) + (0 << 12) + 1024;
10438         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10439
10440         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10441
10442         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10443         /* enable context validation interrupt from CFC */
10444         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10445
10446         /* set the thresholds to prevent CFC/CDU race */
10447         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10448         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10449
10450         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10451                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10452         }
10453
10454         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10455         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10456
10457         /* Reset PCIE errors for debug */
10458         REG_WR(sc, 0x2814, 0xffffffff);
10459         REG_WR(sc, 0x3820, 0xffffffff);
10460
10461         if (!CHIP_IS_E1x(sc)) {
10462                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10463                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10464                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10465                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10466                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10467                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10468                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10469                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10470                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10471                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10472                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10473         }
10474
10475         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10476
10477         /* in E3 this done in per-port section */
10478         if (!CHIP_IS_E3(sc))
10479                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10480
10481         if (CHIP_IS_E1H(sc)) {
10482 /* not applicable for E2 (and above ...) */
10483                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10484         }
10485
10486         if (CHIP_REV_IS_SLOW(sc)) {
10487                 DELAY(200000);
10488         }
10489
10490         /* finish CFC init */
10491         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10492         if (val != 1) {
10493                 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10494                 return -1;
10495         }
10496         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10497         if (val != 1) {
10498                 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10499                 return -1;
10500         }
10501         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10502         if (val != 1) {
10503                 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10504                 return -1;
10505         }
10506         REG_WR(sc, CFC_REG_DEBUG0, 0);
10507
10508         bnx2x_setup_fan_failure_detection(sc);
10509
10510         /* clear PXP2 attentions */
10511         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10512
10513         bnx2x_enable_blocks_attention(sc);
10514
10515         if (!CHIP_REV_IS_SLOW(sc)) {
10516                 ecore_enable_blocks_parity(sc);
10517         }
10518
10519         if (!BNX2X_NOMCP(sc)) {
10520                 if (CHIP_IS_E1x(sc)) {
10521                         bnx2x_common_init_phy(sc);
10522                 }
10523         }
10524
10525         return 0;
10526 }
10527
10528 /**
10529  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10530  *
10531  * @sc:     driver handle
10532  */
10533 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10534 {
10535         int rc = bnx2x_init_hw_common(sc);
10536
10537         if (rc) {
10538                 return rc;
10539         }
10540
10541         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10542         if (!BNX2X_NOMCP(sc)) {
10543                 bnx2x_common_init_phy(sc);
10544         }
10545
10546         return 0;
10547 }
10548
10549 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10550 {
10551         int port = SC_PORT(sc);
10552         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10553         uint32_t low, high;
10554         uint32_t val;
10555
10556         PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10557
10558         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10559
10560         ecore_init_block(sc, BLOCK_MISC, init_phase);
10561         ecore_init_block(sc, BLOCK_PXP, init_phase);
10562         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10563
10564         /*
10565          * Timers bug workaround: disables the pf_master bit in pglue at
10566          * common phase, we need to enable it here before any dmae access are
10567          * attempted. Therefore we manually added the enable-master to the
10568          * port phase (it also happens in the function phase)
10569          */
10570         if (!CHIP_IS_E1x(sc)) {
10571                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10572         }
10573
10574         ecore_init_block(sc, BLOCK_ATC, init_phase);
10575         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10576         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10577         ecore_init_block(sc, BLOCK_QM, init_phase);
10578
10579         ecore_init_block(sc, BLOCK_TCM, init_phase);
10580         ecore_init_block(sc, BLOCK_UCM, init_phase);
10581         ecore_init_block(sc, BLOCK_CCM, init_phase);
10582         ecore_init_block(sc, BLOCK_XCM, init_phase);
10583
10584         /* QM cid (connection) count */
10585         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10586
10587         if (CNIC_SUPPORT(sc)) {
10588                 ecore_init_block(sc, BLOCK_TM, init_phase);
10589                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10590                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10591         }
10592
10593         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10594
10595         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10596
10597         if (CHIP_IS_E1H(sc)) {
10598                 if (IS_MF(sc)) {
10599                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10600                 } else if (sc->mtu > 4096) {
10601                         if (BNX2X_ONE_PORT(sc)) {
10602                                 low = 160;
10603                         } else {
10604                                 val = sc->mtu;
10605                                 /* (24*1024 + val*4)/256 */
10606                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10607                         }
10608                 } else {
10609                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10610                 }
10611                 high = (low + 56);      /* 14*1024/256 */
10612                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10613                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10614         }
10615
10616         if (CHIP_IS_MODE_4_PORT(sc)) {
10617                 REG_WR(sc, SC_PORT(sc) ?
10618                        BRB1_REG_MAC_GUARANTIED_1 :
10619                        BRB1_REG_MAC_GUARANTIED_0, 40);
10620         }
10621
10622         ecore_init_block(sc, BLOCK_PRS, init_phase);
10623         if (CHIP_IS_E3B0(sc)) {
10624                 if (IS_MF_AFEX(sc)) {
10625                         /* configure headers for AFEX mode */
10626                         if (SC_PORT(sc)) {
10627                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10628                                        0xE);
10629                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10630                                        0x6);
10631                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10632                         } else {
10633                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10634                                        0xE);
10635                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10636                                        0x6);
10637                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10638                         }
10639                 } else {
10640                         /* Ovlan exists only if we are in multi-function +
10641                          * switch-dependent mode, in switch-independent there
10642                          * is no ovlan headers
10643                          */
10644                         REG_WR(sc, SC_PORT(sc) ?
10645                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10646                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10647                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10648                 }
10649         }
10650
10651         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10652         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10653         ecore_init_block(sc, BLOCK_USDM, init_phase);
10654         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10655
10656         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10657         ecore_init_block(sc, BLOCK_USEM, init_phase);
10658         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10659         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10660
10661         ecore_init_block(sc, BLOCK_UPB, init_phase);
10662         ecore_init_block(sc, BLOCK_XPB, init_phase);
10663
10664         ecore_init_block(sc, BLOCK_PBF, init_phase);
10665
10666         if (CHIP_IS_E1x(sc)) {
10667 /* configure PBF to work without PAUSE mtu 9000 */
10668                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10669
10670 /* update threshold */
10671                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10672 /* update init credit */
10673                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10674                        (9040 / 16) + 553 - 22);
10675
10676 /* probe changes */
10677                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10678                 DELAY(50);
10679                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10680         }
10681
10682         if (CNIC_SUPPORT(sc)) {
10683                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10684         }
10685
10686         ecore_init_block(sc, BLOCK_CDU, init_phase);
10687         ecore_init_block(sc, BLOCK_CFC, init_phase);
10688         ecore_init_block(sc, BLOCK_HC, init_phase);
10689         ecore_init_block(sc, BLOCK_IGU, init_phase);
10690         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10691         /* init aeu_mask_attn_func_0/1:
10692          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10693          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10694          *             bits 4-7 are used for "per vn group attention" */
10695         val = IS_MF(sc) ? 0xF7 : 0x7;
10696         val |= 0x10;
10697         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10698
10699         ecore_init_block(sc, BLOCK_NIG, init_phase);
10700
10701         if (!CHIP_IS_E1x(sc)) {
10702 /* Bit-map indicating which L2 hdrs may appear after the
10703  * basic Ethernet header
10704  */
10705                 if (IS_MF_AFEX(sc)) {
10706                         REG_WR(sc, SC_PORT(sc) ?
10707                                NIG_REG_P1_HDRS_AFTER_BASIC :
10708                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10709                 } else {
10710                         REG_WR(sc, SC_PORT(sc) ?
10711                                NIG_REG_P1_HDRS_AFTER_BASIC :
10712                                NIG_REG_P0_HDRS_AFTER_BASIC,
10713                                IS_MF_SD(sc) ? 7 : 6);
10714                 }
10715
10716                 if (CHIP_IS_E3(sc)) {
10717                         REG_WR(sc, SC_PORT(sc) ?
10718                                NIG_REG_LLH1_MF_MODE :
10719                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10720                 }
10721         }
10722         if (!CHIP_IS_E3(sc)) {
10723                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10724         }
10725
10726         /* 0x2 disable mf_ov, 0x1 enable */
10727         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10728                (IS_MF_SD(sc) ? 0x1 : 0x2));
10729
10730         if (!CHIP_IS_E1x(sc)) {
10731                 val = 0;
10732                 switch (sc->devinfo.mf_info.mf_mode) {
10733                 case MULTI_FUNCTION_SD:
10734                         val = 1;
10735                         break;
10736                 case MULTI_FUNCTION_SI:
10737                 case MULTI_FUNCTION_AFEX:
10738                         val = 2;
10739                         break;
10740                 }
10741
10742                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10743                             NIG_REG_LLH0_CLS_TYPE), val);
10744         }
10745         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10746         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10747         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10748
10749         /* If SPIO5 is set to generate interrupts, enable it for this port */
10750         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10751         if (val & MISC_SPIO_SPIO5) {
10752                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10753                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10754                 val = REG_RD(sc, reg_addr);
10755                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10756                 REG_WR(sc, reg_addr, val);
10757         }
10758
10759         return 0;
10760 }
10761
10762 static uint32_t
10763 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10764                        uint32_t expected, uint32_t poll_count)
10765 {
10766         uint32_t cur_cnt = poll_count;
10767         uint32_t val;
10768
10769         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10770                 DELAY(FLR_WAIT_INTERVAL);
10771         }
10772
10773         return val;
10774 }
10775
10776 static int
10777 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10778                               __rte_unused const char *msg, uint32_t poll_cnt)
10779 {
10780         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10781
10782         if (val != 0) {
10783                 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10784                 return -1;
10785         }
10786
10787         return 0;
10788 }
10789
10790 /* Common routines with VF FLR cleanup */
10791 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10792 {
10793         /* adjust polling timeout */
10794         if (CHIP_REV_IS_EMUL(sc)) {
10795                 return FLR_POLL_CNT * 2000;
10796         }
10797
10798         if (CHIP_REV_IS_FPGA(sc)) {
10799                 return FLR_POLL_CNT * 120;
10800         }
10801
10802         return FLR_POLL_CNT;
10803 }
10804
10805 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10806 {
10807         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10808         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10809                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10810                                           "CFC PF usage counter timed out",
10811                                           poll_cnt)) {
10812                 return -1;
10813         }
10814
10815         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10816         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10817                                           DORQ_REG_PF_USAGE_CNT,
10818                                           "DQ PF usage counter timed out",
10819                                           poll_cnt)) {
10820                 return -1;
10821         }
10822
10823         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10824         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10825                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10826                                           "QM PF usage counter timed out",
10827                                           poll_cnt)) {
10828                 return -1;
10829         }
10830
10831         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10832         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10833                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10834                                           "Timers VNIC usage counter timed out",
10835                                           poll_cnt)) {
10836                 return -1;
10837         }
10838
10839         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10840                                           TM_REG_LIN0_NUM_SCANS +
10841                                           4 * SC_PORT(sc),
10842                                           "Timers NUM_SCANS usage counter timed out",
10843                                           poll_cnt)) {
10844                 return -1;
10845         }
10846
10847         /* Wait DMAE PF usage counter to zero */
10848         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10849                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10850                                           "DMAE dommand register timed out",
10851                                           poll_cnt)) {
10852                 return -1;
10853         }
10854
10855         return 0;
10856 }
10857
10858 #define OP_GEN_PARAM(param)                                            \
10859         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10860 #define OP_GEN_TYPE(type)                                           \
10861         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10862 #define OP_GEN_AGG_VECT(index)                                             \
10863         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10864
10865 static int
10866 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10867                      uint32_t poll_cnt)
10868 {
10869         uint32_t op_gen_command = 0;
10870         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10871                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10872         int ret = 0;
10873
10874         if (REG_RD(sc, comp_addr)) {
10875                 PMD_DRV_LOG(NOTICE, sc,
10876                             "Cleanup complete was not 0 before sending");
10877                 return -1;
10878         }
10879
10880         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10881         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10882         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10883         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10884
10885         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10886
10887         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10888                 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10889                 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10890                             (REG_RD(sc, comp_addr)));
10891                 rte_panic("FLR cleanup failed");
10892                 return -1;
10893         }
10894
10895         /* Zero completion for nxt FLR */
10896         REG_WR(sc, comp_addr, 0);
10897
10898         return ret;
10899 }
10900
10901 static void
10902 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10903                        uint32_t poll_count)
10904 {
10905         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10906         uint32_t cur_cnt = poll_count;
10907
10908         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10909         crd = crd_start = REG_RD(sc, regs->crd);
10910         init_crd = REG_RD(sc, regs->init_crd);
10911
10912         while ((crd != init_crd) &&
10913                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10914                 (init_crd - crd_start))) {
10915                 if (cur_cnt--) {
10916                         DELAY(FLR_WAIT_INTERVAL);
10917                         crd = REG_RD(sc, regs->crd);
10918                         crd_freed = REG_RD(sc, regs->crd_freed);
10919                 } else {
10920                         break;
10921                 }
10922         }
10923 }
10924
10925 static void
10926 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10927                        uint32_t poll_count)
10928 {
10929         uint32_t occup, to_free, freed, freed_start;
10930         uint32_t cur_cnt = poll_count;
10931
10932         occup = to_free = REG_RD(sc, regs->lines_occup);
10933         freed = freed_start = REG_RD(sc, regs->lines_freed);
10934
10935         while (occup &&
10936                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10937                 to_free)) {
10938                 if (cur_cnt--) {
10939                         DELAY(FLR_WAIT_INTERVAL);
10940                         occup = REG_RD(sc, regs->lines_occup);
10941                         freed = REG_RD(sc, regs->lines_freed);
10942                 } else {
10943                         break;
10944                 }
10945         }
10946 }
10947
10948 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10949 {
10950         struct pbf_pN_cmd_regs cmd_regs[] = {
10951                 {0, (CHIP_IS_E3B0(sc)) ?
10952                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10953                  (CHIP_IS_E3B0(sc)) ?
10954                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10955                 {1, (CHIP_IS_E3B0(sc)) ?
10956                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10957                  (CHIP_IS_E3B0(sc)) ?
10958                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10959                 {4, (CHIP_IS_E3B0(sc)) ?
10960                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10961                  (CHIP_IS_E3B0(sc)) ?
10962                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10963                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10964         };
10965
10966         struct pbf_pN_buf_regs buf_regs[] = {
10967                 {0, (CHIP_IS_E3B0(sc)) ?
10968                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10969                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10970                  (CHIP_IS_E3B0(sc)) ?
10971                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10972                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10973                 {1, (CHIP_IS_E3B0(sc)) ?
10974                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10975                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10976                  (CHIP_IS_E3B0(sc)) ?
10977                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10978                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10979                 {4, (CHIP_IS_E3B0(sc)) ?
10980                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10981                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10982                  (CHIP_IS_E3B0(sc)) ?
10983                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10984                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10985         };
10986
10987         uint32_t i;
10988
10989         /* Verify the command queues are flushed P0, P1, P4 */
10990         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10991                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10992         }
10993
10994         /* Verify the transmission buffers are flushed P0, P1, P4 */
10995         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10996                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10997         }
10998 }
10999
11000 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11001 {
11002         __rte_unused uint32_t val;
11003
11004         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11005         PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11006
11007         val = REG_RD(sc, PBF_REG_DISABLE_PF);
11008         PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11009
11010         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11011         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11012
11013         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11014         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11015
11016         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11017         PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11018
11019         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11020         PMD_DRV_LOG(DEBUG, sc,
11021                     "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11022
11023         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11024         PMD_DRV_LOG(DEBUG, sc,
11025                     "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11026
11027         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11028         PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11029                     val);
11030 }
11031
11032 /**
11033  *      bnx2x_pf_flr_clnup
11034  *      a. re-enable target read on the PF
11035  *      b. poll cfc per function usgae counter
11036  *      c. poll the qm perfunction usage counter
11037  *      d. poll the tm per function usage counter
11038  *      e. poll the tm per function scan-done indication
11039  *      f. clear the dmae channel associated wit hthe PF
11040  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11041  *      h. call the common flr cleanup code with -1 (pf indication)
11042  */
11043 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11044 {
11045         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11046
11047         /* Re-enable PF target read access */
11048         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11049
11050         /* Poll HW usage counters */
11051         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11052                 return -1;
11053         }
11054
11055         /* Zero the igu 'trailing edge' and 'leading edge' */
11056
11057         /* Send the FW cleanup command */
11058         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11059                 return -1;
11060         }
11061
11062         /* ATC cleanup */
11063
11064         /* Verify TX hw is flushed */
11065         bnx2x_tx_hw_flushed(sc, poll_cnt);
11066
11067         /* Wait 100ms (not adjusted according to platform) */
11068         DELAY(100000);
11069
11070         /* Verify no pending pci transactions */
11071         if (bnx2x_is_pcie_pending(sc)) {
11072                 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11073         }
11074
11075         /* Debug */
11076         bnx2x_hw_enable_status(sc);
11077
11078         /*
11079          * Master enable - Due to WB DMAE writes performed before this
11080          * register is re-initialized as part of the regular function init
11081          */
11082         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11083
11084         return 0;
11085 }
11086
11087 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11088 {
11089         int port = SC_PORT(sc);
11090         int func = SC_FUNC(sc);
11091         int init_phase = PHASE_PF0 + func;
11092         struct ecore_ilt *ilt = sc->ilt;
11093         uint16_t cdu_ilt_start;
11094         uint32_t addr, val;
11095         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11096         int main_mem_width, rc;
11097         uint32_t i;
11098
11099         PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11100
11101         /* FLR cleanup */
11102         if (!CHIP_IS_E1x(sc)) {
11103                 rc = bnx2x_pf_flr_clnup(sc);
11104                 if (rc) {
11105                         PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11106                         return rc;
11107                 }
11108         }
11109
11110         /* set MSI reconfigure capability */
11111         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11112                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11113                 val = REG_RD(sc, addr);
11114                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11115                 REG_WR(sc, addr, val);
11116         }
11117
11118         ecore_init_block(sc, BLOCK_PXP, init_phase);
11119         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11120
11121         ilt = sc->ilt;
11122         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11123
11124         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11125                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11126                 ilt->lines[cdu_ilt_start + i].page_mapping =
11127                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11128                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11129         }
11130         ecore_ilt_init_op(sc, INITOP_SET);
11131
11132         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11133
11134         if (!CHIP_IS_E1x(sc)) {
11135                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11136
11137 /* Turn on a single ISR mode in IGU if driver is going to use
11138  * INT#x or MSI
11139  */
11140                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11141                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11142                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11143                 }
11144
11145 /*
11146  * Timers workaround bug: function init part.
11147  * Need to wait 20msec after initializing ILT,
11148  * needed to make sure there are no requests in
11149  * one of the PXP internal queues with "old" ILT addresses
11150  */
11151                 DELAY(20000);
11152
11153 /*
11154  * Master enable - Due to WB DMAE writes performed before this
11155  * register is re-initialized as part of the regular function
11156  * init
11157  */
11158                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11159 /* Enable the function in IGU */
11160                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11161         }
11162
11163         sc->dmae_ready = 1;
11164
11165         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11166
11167         if (!CHIP_IS_E1x(sc))
11168                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11169
11170         ecore_init_block(sc, BLOCK_ATC, init_phase);
11171         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11172         ecore_init_block(sc, BLOCK_NIG, init_phase);
11173         ecore_init_block(sc, BLOCK_SRC, init_phase);
11174         ecore_init_block(sc, BLOCK_MISC, init_phase);
11175         ecore_init_block(sc, BLOCK_TCM, init_phase);
11176         ecore_init_block(sc, BLOCK_UCM, init_phase);
11177         ecore_init_block(sc, BLOCK_CCM, init_phase);
11178         ecore_init_block(sc, BLOCK_XCM, init_phase);
11179         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11180         ecore_init_block(sc, BLOCK_USEM, init_phase);
11181         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11182         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11183
11184         if (!CHIP_IS_E1x(sc))
11185                 REG_WR(sc, QM_REG_PF_EN, 1);
11186
11187         if (!CHIP_IS_E1x(sc)) {
11188                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11189                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11190                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11191                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11192         }
11193         ecore_init_block(sc, BLOCK_QM, init_phase);
11194
11195         ecore_init_block(sc, BLOCK_TM, init_phase);
11196         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11197
11198         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11199         ecore_init_block(sc, BLOCK_PRS, init_phase);
11200         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11201         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11202         ecore_init_block(sc, BLOCK_USDM, init_phase);
11203         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11204         ecore_init_block(sc, BLOCK_UPB, init_phase);
11205         ecore_init_block(sc, BLOCK_XPB, init_phase);
11206         ecore_init_block(sc, BLOCK_PBF, init_phase);
11207         if (!CHIP_IS_E1x(sc))
11208                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11209
11210         ecore_init_block(sc, BLOCK_CDU, init_phase);
11211
11212         ecore_init_block(sc, BLOCK_CFC, init_phase);
11213
11214         if (!CHIP_IS_E1x(sc))
11215                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11216
11217         if (IS_MF(sc)) {
11218                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11219                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11220         }
11221
11222         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11223
11224         /* HC init per function */
11225         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11226                 if (CHIP_IS_E1H(sc)) {
11227                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11228
11229                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11230                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11231                 }
11232                 ecore_init_block(sc, BLOCK_HC, init_phase);
11233
11234         } else {
11235                 uint32_t num_segs, sb_idx, prod_offset;
11236
11237                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11238
11239                 if (!CHIP_IS_E1x(sc)) {
11240                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11241                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11242                 }
11243
11244                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11245
11246                 if (!CHIP_IS_E1x(sc)) {
11247                         int dsb_idx = 0;
11248         /**
11249          * Producer memory:
11250          * E2 mode: address 0-135 match to the mapping memory;
11251          * 136 - PF0 default prod; 137 - PF1 default prod;
11252          * 138 - PF2 default prod; 139 - PF3 default prod;
11253          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11254          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11255          * 144-147 reserved.
11256          *
11257          * E1.5 mode - In backward compatible mode;
11258          * for non default SB; each even line in the memory
11259          * holds the U producer and each odd line hold
11260          * the C producer. The first 128 producers are for
11261          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11262          * producers are for the DSB for each PF.
11263          * Each PF has five segments: (the order inside each
11264          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11265          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11266          * 144-147 attn prods;
11267          */
11268                         /* non-default-status-blocks */
11269                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11270                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11271                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11272                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11273                                     num_segs;
11274
11275                                 for (i = 0; i < num_segs; i++) {
11276                                         addr = IGU_REG_PROD_CONS_MEMORY +
11277                                             (prod_offset + i) * 4;
11278                                         REG_WR(sc, addr, 0);
11279                                 }
11280                                 /* send consumer update with value 0 */
11281                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11282                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11283                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11284                         }
11285
11286                         /* default-status-blocks */
11287                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11288                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11289
11290                         if (CHIP_IS_MODE_4_PORT(sc))
11291                                 dsb_idx = SC_FUNC(sc);
11292                         else
11293                                 dsb_idx = SC_VN(sc);
11294
11295                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11296                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11297                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11298
11299                         /*
11300                          * igu prods come in chunks of E1HVN_MAX (4) -
11301                          * does not matters what is the current chip mode
11302                          */
11303                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11304                                 addr = IGU_REG_PROD_CONS_MEMORY +
11305                                     (prod_offset + i) * 4;
11306                                 REG_WR(sc, addr, 0);
11307                         }
11308                         /* send consumer update with 0 */
11309                         if (CHIP_INT_MODE_IS_BC(sc)) {
11310                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11311                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11312                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11313                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11314                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11315                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11316                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11317                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11318                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11319                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11320                         } else {
11321                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11322                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11323                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11324                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11325                         }
11326                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11327
11328                         /* !!! these should become driver const once
11329                            rf-tool supports split-68 const */
11330                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11331                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11332                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11333                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11334                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11335                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11336                 }
11337         }
11338
11339         /* Reset PCIE errors for debug */
11340         REG_WR(sc, 0x2114, 0xffffffff);
11341         REG_WR(sc, 0x2120, 0xffffffff);
11342
11343         if (CHIP_IS_E1x(sc)) {
11344                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11345                 main_mem_base = HC_REG_MAIN_MEMORY +
11346                     SC_PORT(sc) * (main_mem_size * 4);
11347                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11348                 main_mem_width = 8;
11349
11350                 val = REG_RD(sc, main_mem_prty_clr);
11351                 if (val) {
11352                         PMD_DRV_LOG(DEBUG, sc,
11353                                     "Parity errors in HC block during function init (0x%x)!",
11354                                     val);
11355                 }
11356
11357 /* Clear "false" parity errors in MSI-X table */
11358                 for (i = main_mem_base;
11359                      i < main_mem_base + main_mem_size * 4;
11360                      i += main_mem_width) {
11361                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11362                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11363                                        i, main_mem_width / 4);
11364                 }
11365 /* Clear HC parity attention */
11366                 REG_RD(sc, main_mem_prty_clr);
11367         }
11368
11369         /* Enable STORMs SP logging */
11370         REG_WR8(sc, BAR_USTRORM_INTMEM +
11371                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11372         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11373                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11374         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11375                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11376         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11377                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11378
11379         elink_phy_probe(&sc->link_params);
11380
11381         return 0;
11382 }
11383
11384 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11385 {
11386         if (!BNX2X_NOMCP(sc)) {
11387                 bnx2x_acquire_phy_lock(sc);
11388                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11389                 bnx2x_release_phy_lock(sc);
11390         } else {
11391                 if (!CHIP_REV_IS_SLOW(sc)) {
11392                         PMD_DRV_LOG(WARNING, sc,
11393                                     "Bootcode is missing - cannot reset link");
11394                 }
11395         }
11396 }
11397
11398 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11399 {
11400         int port = SC_PORT(sc);
11401         uint32_t val;
11402
11403         /* reset physical Link */
11404         bnx2x_link_reset(sc);
11405
11406         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11407
11408         /* Do not rcv packets to BRB */
11409         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11410         /* Do not direct rcv packets that are not for MCP to the BRB */
11411         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11412                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11413
11414         /* Configure AEU */
11415         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11416
11417         DELAY(100000);
11418
11419         /* Check for BRB port occupancy */
11420         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11421         if (val) {
11422                 PMD_DRV_LOG(DEBUG, sc,
11423                             "BRB1 is not empty, %d blocks are occupied", val);
11424         }
11425 }
11426
11427 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11428 {
11429         int reg;
11430         uint32_t wb_write[2];
11431
11432         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11433
11434         wb_write[0] = ONCHIP_ADDR1(addr);
11435         wb_write[1] = ONCHIP_ADDR2(addr);
11436         REG_WR_DMAE(sc, reg, wb_write, 2);
11437 }
11438
11439 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11440 {
11441         uint32_t i, base = FUNC_ILT_BASE(func);
11442         for (i = base; i < base + ILT_PER_FUNC; i++) {
11443                 bnx2x_ilt_wr(sc, i, 0);
11444         }
11445 }
11446
11447 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11448 {
11449         struct bnx2x_fastpath *fp;
11450         int port = SC_PORT(sc);
11451         int func = SC_FUNC(sc);
11452         int i;
11453
11454         /* Disable the function in the FW */
11455         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11456         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11457         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11458         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11459
11460         /* FP SBs */
11461         FOR_EACH_ETH_QUEUE(sc, i) {
11462                 fp = &sc->fp[i];
11463                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11464                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11465                         SB_DISABLED);
11466         }
11467
11468         /* SP SB */
11469         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11470                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11471
11472         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11473                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11474                        0);
11475         }
11476
11477         /* Configure IGU */
11478         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11479                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11480                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11481         } else {
11482                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11483                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11484         }
11485
11486         if (CNIC_LOADED(sc)) {
11487 /* Disable Timer scan */
11488                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11489 /*
11490  * Wait for at least 10ms and up to 2 second for the timers
11491  * scan to complete
11492  */
11493                 for (i = 0; i < 200; i++) {
11494                         DELAY(10000);
11495                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11496                                 break;
11497                 }
11498         }
11499
11500         /* Clear ILT */
11501         bnx2x_clear_func_ilt(sc, func);
11502
11503         /*
11504          * Timers workaround bug for E2: if this is vnic-3,
11505          * we need to set the entire ilt range for this timers.
11506          */
11507         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11508                 struct ilt_client_info ilt_cli;
11509 /* use dummy TM client */
11510                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11511                 ilt_cli.start = 0;
11512                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11513                 ilt_cli.client_num = ILT_CLIENT_TM;
11514
11515                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11516         }
11517
11518         /* this assumes that reset_port() called before reset_func() */
11519         if (!CHIP_IS_E1x(sc)) {
11520                 bnx2x_pf_disable(sc);
11521         }
11522
11523         sc->dmae_ready = 0;
11524 }
11525
11526 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11527 {
11528         rte_free(sc->init_ops);
11529         rte_free(sc->init_ops_offsets);
11530         rte_free(sc->init_data);
11531         rte_free(sc->iro_array);
11532 }
11533
11534 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11535 {
11536         uint32_t len, i;
11537         uint8_t *p = sc->firmware;
11538         uint32_t off[24];
11539
11540         for (i = 0; i < 24; ++i)
11541                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11542
11543         len = off[0];
11544         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11545         if (!sc->init_ops)
11546                 goto alloc_failed;
11547         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11548
11549         len = off[2];
11550         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11551         if (!sc->init_ops_offsets)
11552                 goto alloc_failed;
11553         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11554
11555         len = off[4];
11556         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11557         if (!sc->init_data)
11558                 goto alloc_failed;
11559         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11560
11561         sc->tsem_int_table_data = p + off[7];
11562         sc->tsem_pram_data = p + off[9];
11563         sc->usem_int_table_data = p + off[11];
11564         sc->usem_pram_data = p + off[13];
11565         sc->csem_int_table_data = p + off[15];
11566         sc->csem_pram_data = p + off[17];
11567         sc->xsem_int_table_data = p + off[19];
11568         sc->xsem_pram_data = p + off[21];
11569
11570         len = off[22];
11571         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11572         if (!sc->iro_array)
11573                 goto alloc_failed;
11574         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11575
11576         return 0;
11577
11578 alloc_failed:
11579         bnx2x_release_firmware(sc);
11580         return -1;
11581 }
11582
11583 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11584 {
11585 #define MIN_PREFIX_SIZE (10)
11586
11587         int n = MIN_PREFIX_SIZE;
11588         uint16_t xlen;
11589
11590         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11591             len <= MIN_PREFIX_SIZE) {
11592                 return -1;
11593         }
11594
11595         /* optional extra fields are present */
11596         if (zbuf[3] & 0x4) {
11597                 xlen = zbuf[13];
11598                 xlen <<= 8;
11599                 xlen += zbuf[12];
11600
11601                 n += xlen;
11602         }
11603         /* file name is present */
11604         if (zbuf[3] & 0x8) {
11605                 while ((zbuf[n++] != 0) && (n < len)) ;
11606         }
11607
11608         return n;
11609 }
11610
11611 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11612 {
11613         int ret;
11614         int data_begin = cut_gzip_prefix(zbuf, len);
11615
11616         PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11617
11618         if (data_begin <= 0) {
11619                 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11620                 return -1;
11621         }
11622
11623         memset(&zlib_stream, 0, sizeof(zlib_stream));
11624         zlib_stream.next_in = zbuf + data_begin;
11625         zlib_stream.avail_in = len - data_begin;
11626         zlib_stream.next_out = sc->gz_buf;
11627         zlib_stream.avail_out = FW_BUF_SIZE;
11628
11629         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11630         if (ret != Z_OK) {
11631                 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11632                 return ret;
11633         }
11634
11635         ret = inflate(&zlib_stream, Z_FINISH);
11636         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11637                 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11638                             zlib_stream.msg);
11639         }
11640
11641         sc->gz_outlen = zlib_stream.total_out;
11642         if (sc->gz_outlen & 0x3) {
11643                 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11644                             sc->gz_outlen);
11645         }
11646         sc->gz_outlen >>= 2;
11647
11648         inflateEnd(&zlib_stream);
11649
11650         if (ret == Z_STREAM_END)
11651                 return 0;
11652
11653         return ret;
11654 }
11655
11656 static void
11657 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11658                           uint32_t addr, uint32_t len)
11659 {
11660         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11661 }
11662
11663 void
11664 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11665                           uint32_t * data)
11666 {
11667         uint8_t i;
11668         for (i = 0; i < size / 4; i++) {
11669                 REG_WR(sc, addr + (i * 4), data[i]);
11670         }
11671 }
11672
11673 #ifdef RTE_LIBRTE_BNX2X_DEBUG
11674 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11675 {
11676         uint32_t phy_type_idx = ext_phy_type >> 8;
11677         static const char *types[] =
11678             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11679                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11680                 "BNX2X-8727",
11681                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11682         };
11683
11684         if (phy_type_idx < 12)
11685                 return types[phy_type_idx];
11686         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11687                 return types[12];
11688         else
11689                 return types[13];
11690 }
11691
11692 static const char *get_state(uint32_t state)
11693 {
11694         uint32_t state_idx = state >> 12;
11695         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11696                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11697                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11698                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11699                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11700         };
11701
11702         if (state_idx <= 0xF)
11703                 return states[state_idx];
11704         else
11705                 return states[0x10];
11706 }
11707
11708 static const char *get_recovery_state(uint32_t state)
11709 {
11710         static const char *states[] = { "NONE", "DONE", "INIT",
11711                 "WAIT", "FAILED", "NIC_LOADING"
11712         };
11713         return states[state];
11714 }
11715
11716 static const char *get_rx_mode(uint32_t mode)
11717 {
11718         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11719                 "PROMISC", "MAX_MULTICAST", "ERROR"
11720         };
11721
11722         if (mode < 0x4)
11723                 return modes[mode];
11724         else if (BNX2X_MAX_MULTICAST == mode)
11725                 return modes[4];
11726         else
11727                 return modes[5];
11728 }
11729
11730 #define BNX2X_INFO_STR_MAX 256
11731 static const char *get_bnx2x_flags(uint32_t flags)
11732 {
11733         int i;
11734         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11735                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11736                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11737                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11738         };
11739         static char flag_str[BNX2X_INFO_STR_MAX];
11740         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11741
11742         for (i = 0; i < 5; i++)
11743                 if (flags & (1 << i)) {
11744                         strcat(flag_str, flag[i]);
11745                         flags ^= (1 << i);
11746                 }
11747         if (flags) {
11748                 static char unknown[BNX2X_INFO_STR_MAX];
11749                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11750                 strcat(flag_str, unknown);
11751         }
11752         return flag_str;
11753 }
11754 #endif
11755
11756 /*
11757  * Prints useful adapter info.
11758  */
11759 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11760 {
11761         int i = 0;
11762         __rte_unused uint32_t ext_phy_type;
11763
11764         PMD_INIT_FUNC_TRACE(sc);
11765         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11766                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11767                                                               sc->
11768                                                               devinfo.shmem_base
11769                                                               + offsetof(struct
11770                                                                          shmem_region,
11771                                                                          dev_info.port_hw_config
11772                                                                          [0].external_phy_config)));
11773         else
11774                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11775                                                                 sc->
11776                                                                 devinfo.shmem_base
11777                                                                 +
11778                                                                 offsetof(struct
11779                                                                          shmem_region,
11780                                                                          dev_info.port_hw_config
11781                                                                          [0].external_phy_config)));
11782
11783         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11784         /* Hardware chip info. */
11785         PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11786         PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11787                      (CHIP_METAL(sc) >> 4));
11788
11789         /* Bus info. */
11790         PMD_DRV_LOG(INFO, sc,
11791                     "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11792         switch (sc->devinfo.pcie_link_speed) {
11793         case 1:
11794                 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11795                 break;
11796         case 2:
11797                 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11798                 break;
11799         case 4:
11800                 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11801                 break;
11802         default:
11803                 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11804         }
11805
11806         /* Device features. */
11807         PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11808
11809         /* Miscellaneous flags. */
11810         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11811                 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11812                 i++;
11813         }
11814
11815         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11816                 if (i > 0)
11817                         PMD_DRV_LOG(INFO, sc, "|");
11818                 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11819                 i++;
11820         }
11821
11822         if (IS_PF(sc)) {
11823                 PMD_DRV_LOG(INFO, sc, "%12s : ", "Queues");
11824                 switch (sc->sp->rss_rdata.rss_mode) {
11825                 case ETH_RSS_MODE_DISABLED:
11826                         PMD_DRV_LOG(INFO, sc, "%19s", "None");
11827                         break;
11828                 case ETH_RSS_MODE_REGULAR:
11829                         PMD_DRV_LOG(INFO, sc,
11830                                     "%18s : %d", "RSS", sc->num_queues);
11831                         break;
11832                 default:
11833                         PMD_DRV_LOG(INFO, sc, "%22s", "Unknown");
11834                         break;
11835                 }
11836         }
11837
11838         /* RTE and Driver versions */
11839         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11840                         rte_version());
11841         PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11842                         bnx2x_pmd_version());
11843
11844         /* Firmware versions and device features. */
11845         PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11846                      "Firmware",
11847                      BNX2X_5710_FW_MAJOR_VERSION,
11848                      BNX2X_5710_FW_MINOR_VERSION,
11849                      BNX2X_5710_FW_REVISION_VERSION);
11850         PMD_DRV_LOG(INFO, sc, "%12s : %s",
11851                      "Bootcode", sc->devinfo.bc_ver_str);
11852
11853         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11854         PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11855         PMD_DRV_LOG(INFO, sc,
11856                     "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11857         PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11858                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11859         PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11860         PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11861         PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11862         PMD_DRV_LOG(INFO, sc,
11863                     "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11864         PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11865                         sc->link_params.mac_addr[0],
11866                         sc->link_params.mac_addr[1],
11867                         sc->link_params.mac_addr[2],
11868                         sc->link_params.mac_addr[3],
11869                         sc->link_params.mac_addr[4],
11870                         sc->link_params.mac_addr[5]);
11871         PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11872         PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11873         if (sc->recovery_state)
11874                 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11875                              get_recovery_state(sc->recovery_state));
11876         PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11877                      sc->cq_spq_left, sc->eq_spq_left);
11878         PMD_DRV_LOG(INFO, sc,
11879                     "%12s : %x", "Switch", sc->link_params.switch_cfg);
11880         PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11881 }