drivers/net/bnx2x/bnx2x.c

   1 /*-
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015 QLogic Corporation.
  10  * All rights reserved.
  11  * www.qlogic.com
  12  *
  13  * See LICENSE.bnx2x_pmd for copyright and licensing details.
  14  */
  15
  16 #define BNX2X_DRIVER_VERSION "1.78.18"
  17
  18 #include "bnx2x.h"
  19 #include "bnx2x_vfpf.h"
  20 #include "ecore_sp.h"
  21 #include "ecore_init.h"
  22 #include "ecore_init_ops.h"
  23
  24 #include "rte_version.h"
  25
  26 #include <sys/types.h>
  27 #include <sys/stat.h>
  28 #include <fcntl.h>
  29 #include <zlib.h>
  30
  31 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  32 #define BNX2X_PMD_VERSION_MAJOR 1
  33 #define BNX2X_PMD_VERSION_MINOR 0
  34 #define BNX2X_PMD_VERSION_REVISION 5
  35 #define BNX2X_PMD_VERSION_PATCH 1
  36
  37 static inline const char *
  38 bnx2x_pmd_version(void)
  39 {
  40         static char version[32];
  41
  42         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  43                         BNX2X_PMD_VER_PREFIX,
  44                         BNX2X_DRIVER_VERSION,
  45                         BNX2X_PMD_VERSION_MAJOR,
  46                         BNX2X_PMD_VERSION_MINOR,
  47                         BNX2X_PMD_VERSION_REVISION,
  48                         BNX2X_PMD_VERSION_PATCH);
  49
  50         return version;
  51 }
  52
  53 static z_stream zlib_stream;
  54
  55 #define EVL_VLID_MASK 0x0FFF
  56
  57 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  58 #define BNX2X_DEF_SB_IDX     0x0002
  59
  60 /*
  61  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  62  * function HW initialization.
  63  */
  64 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  65 #define FLR_WAIT_INTERVAL 50    /* usecs */
  66 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  67
  68 struct pbf_pN_buf_regs {
  69         int pN;
  70         uint32_t init_crd;
  71         uint32_t crd;
  72         uint32_t crd_freed;
  73 };
  74
  75 struct pbf_pN_cmd_regs {
  76         int pN;
  77         uint32_t lines_occup;
  78         uint32_t lines_freed;
  79 };
  80
  81 /* resources needed for unloading a previously loaded device */
  82
  83 #define BNX2X_PREV_WAIT_NEEDED 1
  84 rte_spinlock_t bnx2x_prev_mtx;
  85 struct bnx2x_prev_list_node {
  86         LIST_ENTRY(bnx2x_prev_list_node) node;
  87         uint8_t bus;
  88         uint8_t slot;
  89         uint8_t path;
  90         uint8_t aer;
  91         uint8_t undi;
  92 };
  93
  94 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  95         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  96
  97 static int load_count[2][3] = { { 0 } };
  98         /* per-path: 0-common, 1-port0, 2-port1 */
  99
 100 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 101                                 uint8_t cmng_type);
 102 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 103 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 104                               uint8_t port);
 105 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 106 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 107 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 108 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 109 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 110                                      uint8_t print);
 111 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 112 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 113 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 114 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 115                                  struct bnx2x_fastpath *fp,
 116                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 117 static void bnx2x_link_report(struct bnx2x_softc *sc);
 118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 123 static __rte_noinline
 124 int bnx2x_nic_load(struct bnx2x_softc *sc);
 125
 126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 128 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 129                          uint8_t storm, uint16_t index, uint8_t op,
 130                          uint8_t update);
 131
 132 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 133 {
 134         int res;
 135
 136         mb();
 137         res = ((*addr) & (1UL << nr)) != 0;
 138         mb();
 139         return res;
 140 }
 141
 142 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 143 {
 144         __sync_fetch_and_or(addr, (1UL << nr));
 145 }
 146
 147 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 148 {
 149         __sync_fetch_and_and(addr, ~(1UL << nr));
 150 }
 151
 152 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 153 {
 154         unsigned long mask = (1UL << nr);
 155         return __sync_fetch_and_and(addr, ~mask) & mask;
 156 }
 157
 158 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 159 {
 160         return __sync_val_compare_and_swap(addr, old, new);
 161 }
 162
 163 int
 164 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 165               const char *msg, uint32_t align)
 166 {
 167         char mz_name[RTE_MEMZONE_NAMESIZE];
 168         const struct rte_memzone *z;
 169
 170         dma->sc = sc;
 171         if (IS_PF(sc))
 172                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 173                         rte_get_timer_cycles());
 174         else
 175                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 176                         rte_get_timer_cycles());
 177
 178         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 179         z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
 180                                         SOCKET_ID_ANY,
 181                                         0, align);
 182         if (z == NULL) {
 183                 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
 184                 return -ENOMEM;
 185         }
 186         dma->paddr = (uint64_t) z->iova;
 187         dma->vaddr = z->addr;
 188
 189         PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 190
 191         return 0;
 192 }
 193
 194 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 195 {
 196         uint32_t lock_status;
 197         uint32_t resource_bit = (1 << resource);
 198         int func = SC_FUNC(sc);
 199         uint32_t hw_lock_control_reg;
 200         int cnt;
 201
 202         PMD_INIT_FUNC_TRACE();
 203
 204         /* validate the resource is within range */
 205         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 206                 PMD_DRV_LOG(NOTICE,
 207                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 208                             resource);
 209                 return -1;
 210         }
 211
 212         if (func <= 5) {
 213                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 214         } else {
 215                 hw_lock_control_reg =
 216                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 217         }
 218
 219         /* validate the resource is not already taken */
 220         lock_status = REG_RD(sc, hw_lock_control_reg);
 221         if (lock_status & resource_bit) {
 222                 PMD_DRV_LOG(NOTICE,
 223                             "resource in use (status 0x%x bit 0x%x)",
 224                             lock_status, resource_bit);
 225                 return -1;
 226         }
 227
 228         /* try every 5ms for 5 seconds */
 229         for (cnt = 0; cnt < 1000; cnt++) {
 230                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 231                 lock_status = REG_RD(sc, hw_lock_control_reg);
 232                 if (lock_status & resource_bit) {
 233                         return 0;
 234                 }
 235                 DELAY(5000);
 236         }
 237
 238         PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
 239         return -1;
 240 }
 241
 242 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 243 {
 244         uint32_t lock_status;
 245         uint32_t resource_bit = (1 << resource);
 246         int func = SC_FUNC(sc);
 247         uint32_t hw_lock_control_reg;
 248
 249         PMD_INIT_FUNC_TRACE();
 250
 251         /* validate the resource is within range */
 252         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 253                 PMD_DRV_LOG(NOTICE,
 254                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 255                             resource);
 256                 return -1;
 257         }
 258
 259         if (func <= 5) {
 260                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 261         } else {
 262                 hw_lock_control_reg =
 263                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 264         }
 265
 266         /* validate the resource is currently taken */
 267         lock_status = REG_RD(sc, hw_lock_control_reg);
 268         if (!(lock_status & resource_bit)) {
 269                 PMD_DRV_LOG(NOTICE,
 270                             "resource not in use (status 0x%x bit 0x%x)",
 271                             lock_status, resource_bit);
 272                 return -1;
 273         }
 274
 275         REG_WR(sc, hw_lock_control_reg, resource_bit);
 276         return 0;
 277 }
 278
 279 /* copy command into DMAE command memory and set DMAE command Go */
 280 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 281 {
 282         uint32_t cmd_offset;
 283         uint32_t i;
 284
 285         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 286         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 287                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 288         }
 289
 290         REG_WR(sc, dmae_reg_go_c[idx], 1);
 291 }
 292
 293 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 294 {
 295         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 296                           DMAE_COMMAND_C_TYPE_ENABLE);
 297 }
 298
 299 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 300 {
 301         return opcode & ~DMAE_COMMAND_SRC_RESET;
 302 }
 303
 304 uint32_t
 305 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 306                 uint8_t with_comp, uint8_t comp_type)
 307 {
 308         uint32_t opcode = 0;
 309
 310         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 311                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 312
 313         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 314
 315         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 316
 317         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 318                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 319
 320         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 321
 322 #ifdef __BIG_ENDIAN
 323         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 324 #else
 325         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 326 #endif
 327
 328         if (with_comp) {
 329                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 330         }
 331
 332         return opcode;
 333 }
 334
 335 static void
 336 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 337                         uint8_t src_type, uint8_t dst_type)
 338 {
 339         memset(dmae, 0, sizeof(struct dmae_command));
 340
 341         /* set the opcode */
 342         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 343                                        TRUE, DMAE_COMP_PCI);
 344
 345         /* fill in the completion parameters */
 346         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 347         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 348         dmae->comp_val = DMAE_COMP_VAL;
 349 }
 350
 351 /* issue a DMAE command over the init channel and wait for completion */
 352 static int
 353 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 354 {
 355         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 356         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 357
 358         /* reset completion */
 359         *wb_comp = 0;
 360
 361         /* post the command on the channel used for initializations */
 362         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 363
 364         /* wait for completion */
 365         DELAY(500);
 366
 367         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 368                 if (!timeout ||
 369                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 370                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 371                         PMD_DRV_LOG(INFO, "DMAE timeout!");
 372                         return DMAE_TIMEOUT;
 373                 }
 374
 375                 timeout--;
 376                 DELAY(50);
 377         }
 378
 379         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 380                 PMD_DRV_LOG(INFO, "DMAE PCI error!");
 381                 return DMAE_PCI_ERROR;
 382         }
 383
 384         return 0;
 385 }
 386
 387 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 388 {
 389         struct dmae_command dmae;
 390         uint32_t *data;
 391         uint32_t i;
 392         int rc;
 393
 394         if (!sc->dmae_ready) {
 395                 data = BNX2X_SP(sc, wb_data[0]);
 396
 397                 for (i = 0; i < len32; i++) {
 398                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 399                 }
 400
 401                 return;
 402         }
 403
 404         /* set opcode and fixed command fields */
 405         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 406
 407         /* fill in addresses and len */
 408         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 409         dmae.src_addr_hi = 0;
 410         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 411         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 412         dmae.len = len32;
 413
 414         /* issue the command and wait for completion */
 415         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 416                 rte_panic("DMAE failed (%d)", rc);
 417         };
 418 }
 419
 420 void
 421 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
 422                uint32_t len32)
 423 {
 424         struct dmae_command dmae;
 425         int rc;
 426
 427         if (!sc->dmae_ready) {
 428                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 429                 return;
 430         }
 431
 432         /* set opcode and fixed command fields */
 433         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 434
 435         /* fill in addresses and len */
 436         dmae.src_addr_lo = U64_LO(dma_addr);
 437         dmae.src_addr_hi = U64_HI(dma_addr);
 438         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 439         dmae.dst_addr_hi = 0;
 440         dmae.len = len32;
 441
 442         /* issue the command and wait for completion */
 443         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 444                 rte_panic("DMAE failed (%d)", rc);
 445         }
 446 }
 447
 448 static void
 449 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
 450                         uint32_t addr, uint32_t len)
 451 {
 452         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 453         uint32_t offset = 0;
 454
 455         while (len > dmae_wr_max) {
 456                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 457                                (addr + offset), /* dst GRC address */
 458                                dmae_wr_max);
 459                 offset += (dmae_wr_max * 4);
 460                 len -= dmae_wr_max;
 461         }
 462
 463         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 464                        (addr + offset), /* dst GRC address */
 465                        len);
 466 }
 467
 468 void
 469 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 470                        uint32_t cid)
 471 {
 472         /* ustorm cxt validation */
 473         cxt->ustorm_ag_context.cdu_usage =
 474             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 475                                    CDU_REGION_NUMBER_UCM_AG,
 476                                    ETH_CONNECTION_TYPE);
 477         /* xcontext validation */
 478         cxt->xstorm_ag_context.cdu_reserved =
 479             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 480                                    CDU_REGION_NUMBER_XCM_AG,
 481                                    ETH_CONNECTION_TYPE);
 482 }
 483
 484 static void
 485 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 486                             uint8_t sb_index, uint8_t ticks)
 487 {
 488         uint32_t addr =
 489             (BAR_CSTRORM_INTMEM +
 490              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 491
 492         REG_WR8(sc, addr, ticks);
 493 }
 494
 495 static void
 496 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 497                             uint8_t sb_index, uint8_t disable)
 498 {
 499         uint32_t enable_flag =
 500             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 501         uint32_t addr =
 502             (BAR_CSTRORM_INTMEM +
 503              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 504         uint8_t flags;
 505
 506         /* clear and set */
 507         flags = REG_RD8(sc, addr);
 508         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 509         flags |= enable_flag;
 510         REG_WR8(sc, addr, flags);
 511 }
 512
 513 void
 514 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 515                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 516 {
 517         uint8_t ticks = (usec / 4);
 518
 519         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 520
 521         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 522         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 523 }
 524
 525 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 526 {
 527         return REG_RD(sc, reg_addr);
 528 }
 529
 530 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 531 {
 532         REG_WR(sc, reg_addr, val);
 533 }
 534
 535 void
 536 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 537                    __rte_unused const elink_log_id_t elink_log_id, ...)
 538 {
 539         PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
 540 }
 541
 542 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 543 {
 544         uint32_t spio_reg;
 545
 546         /* Only 2 SPIOs are configurable */
 547         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 548                 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
 549                 return -1;
 550         }
 551
 552         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 553
 554         /* read SPIO and mask except the float bits */
 555         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 556
 557         switch (mode) {
 558         case MISC_SPIO_OUTPUT_LOW:
 559                 /* clear FLOAT and set CLR */
 560                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 561                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 562                 break;
 563
 564         case MISC_SPIO_OUTPUT_HIGH:
 565                 /* clear FLOAT and set SET */
 566                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 567                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 568                 break;
 569
 570         case MISC_SPIO_INPUT_HI_Z:
 571                 /* set FLOAT */
 572                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 573                 break;
 574
 575         default:
 576                 break;
 577         }
 578
 579         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 580         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 581
 582         return 0;
 583 }
 584
 585 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 586 {
 587         /* The GPIO should be swapped if swap register is set and active */
 588         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 589                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 590         int gpio_shift = gpio_num;
 591         if (gpio_port)
 592                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 593
 594         uint32_t gpio_mask = (1 << gpio_shift);
 595         uint32_t gpio_reg;
 596
 597         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 598                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 599                 return -1;
 600         }
 601
 602         /* read GPIO value */
 603         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 604
 605         /* get the requested pin value */
 606         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 607 }
 608
 609 static int
 610 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 611 {
 612         /* The GPIO should be swapped if swap register is set and active */
 613         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 614                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 615         int gpio_shift = gpio_num;
 616         if (gpio_port)
 617                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 618
 619         uint32_t gpio_mask = (1 << gpio_shift);
 620         uint32_t gpio_reg;
 621
 622         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 623                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 624                 return -1;
 625         }
 626
 627         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 628
 629         /* read GPIO and mask except the float bits */
 630         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 631
 632         switch (mode) {
 633         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 634                 /* clear FLOAT and set CLR */
 635                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 636                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 637                 break;
 638
 639         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 640                 /* clear FLOAT and set SET */
 641                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 642                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 643                 break;
 644
 645         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 646                 /* set FLOAT */
 647                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 648                 break;
 649
 650         default:
 651                 break;
 652         }
 653
 654         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 655         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 656
 657         return 0;
 658 }
 659
 660 static int
 661 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 662 {
 663         uint32_t gpio_reg;
 664
 665         /* any port swapping should be handled by caller */
 666
 667         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 668
 669         /* read GPIO and mask except the float bits */
 670         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 671         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 672         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 673         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 674
 675         switch (mode) {
 676         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 677                 /* set CLR */
 678                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 679                 break;
 680
 681         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 682                 /* set SET */
 683                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 684                 break;
 685
 686         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 687                 /* set FLOAT */
 688                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 689                 break;
 690
 691         default:
 692                 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
 693                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 694                 return -1;
 695         }
 696
 697         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 698         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 699
 700         return 0;
 701 }
 702
 703 static int
 704 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 705                    uint8_t port)
 706 {
 707         /* The GPIO should be swapped if swap register is set and active */
 708         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 709                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 710         int gpio_shift = gpio_num;
 711         if (gpio_port)
 712                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 713
 714         uint32_t gpio_mask = (1 << gpio_shift);
 715         uint32_t gpio_reg;
 716
 717         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 718                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 719                 return -1;
 720         }
 721
 722         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 723
 724         /* read GPIO int */
 725         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 726
 727         switch (mode) {
 728         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 729                 /* clear SET and set CLR */
 730                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 731                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 732                 break;
 733
 734         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 735                 /* clear CLR and set SET */
 736                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 737                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 738                 break;
 739
 740         default:
 741                 break;
 742         }
 743
 744         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 745         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 746
 747         return 0;
 748 }
 749
 750 uint32_t
 751 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 752 {
 753         return bnx2x_gpio_read(sc, gpio_num, port);
 754 }
 755
 756 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 757                             uint8_t port)
 758 {
 759         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 760 }
 761
 762 uint8_t
 763 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 764                          uint8_t mode /* 0=low 1=high */ )
 765 {
 766         return bnx2x_gpio_mult_write(sc, pins, mode);
 767 }
 768
 769 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 770                                 uint8_t port)
 771 {
 772         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 773 }
 774
 775 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 776 {
 777         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 778                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 779 }
 780
 781 /* send the MCP a request, block until there is a reply */
 782 uint32_t
 783 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 784 {
 785         int mb_idx = SC_FW_MB_IDX(sc);
 786         uint32_t seq;
 787         uint32_t rc = 0;
 788         uint32_t cnt = 1;
 789         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 790
 791         seq = ++sc->fw_seq;
 792         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 793         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 794
 795         PMD_DRV_LOG(DEBUG,
 796                     "wrote command 0x%08x to FW MB param 0x%08x",
 797                     (command | seq), param);
 798
 799         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 800         do {
 801                 DELAY(delay * 1000);
 802                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 803         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 804
 805         /* is this a reply to our command? */
 806         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 807                 rc &= FW_MSG_CODE_MASK;
 808         } else {
 809                 /* Ruh-roh! */
 810                 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
 811                 rc = 0;
 812         }
 813
 814         return rc;
 815 }
 816
 817 static uint32_t
 818 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 819 {
 820         return elink_cb_fw_command(sc, command, param);
 821 }
 822
 823 static void
 824 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 825                            rte_iova_t mapping)
 826 {
 827         REG_WR(sc, addr, U64_LO(mapping));
 828         REG_WR(sc, (addr + 4), U64_HI(mapping));
 829 }
 830
 831 static void
 832 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
 833                       uint16_t abs_fid)
 834 {
 835         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 836                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 837         __storm_memset_dma_mapping(sc, addr, mapping);
 838 }
 839
 840 static void
 841 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 842 {
 843         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 844                 pf_id);
 845         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 846                 pf_id);
 847         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 848                 pf_id);
 849         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 850                 pf_id);
 851 }
 852
 853 static void
 854 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 855 {
 856         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 857                 enable);
 858         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 859                 enable);
 860         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 861                 enable);
 862         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 863                 enable);
 864 }
 865
 866 static void
 867 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 868                      uint16_t pfid)
 869 {
 870         uint32_t addr;
 871         size_t size;
 872
 873         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 874         size = sizeof(struct event_ring_data);
 875         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 876 }
 877
 878 static void
 879 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 880 {
 881         uint32_t addr = (BAR_CSTRORM_INTMEM +
 882                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 883         REG_WR16(sc, addr, eq_prod);
 884 }
 885
 886 /*
 887  * Post a slowpath command.
 888  *
 889  * A slowpath command is used to propagate a configuration change through
 890  * the controller in a controlled manner, allowing each STORM processor and
 891  * other H/W blocks to phase in the change.  The commands sent on the
 892  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 893  * completion of the ramrod will occur in different ways.  Here's a
 894  * breakdown of ramrods and how they complete:
 895  *
 896  * RAMROD_CMD_ID_ETH_PORT_SETUP
 897  *   Used to setup the leading connection on a port.  Completes on the
 898  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 899  *
 900  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 901  *   Used to setup an additional connection on a port.  Completes on the
 902  *   RCQ of the multi-queue/RSS connection being initialized.
 903  *
 904  * RAMROD_CMD_ID_ETH_STAT_QUERY
 905  *   Used to force the storm processors to update the statistics database
 906  *   in host memory.  This ramrod is send on the leading connection CID and
 907  *   completes as an index increment of the CSTORM on the default status
 908  *   block.
 909  *
 910  * RAMROD_CMD_ID_ETH_UPDATE
 911  *   Used to update the state of the leading connection, usually to udpate
 912  *   the RSS indirection table.  Completes on the RCQ of the leading
 913  *   connection. (Not currently used under FreeBSD until OS support becomes
 914  *   available.)
 915  *
 916  * RAMROD_CMD_ID_ETH_HALT
 917  *   Used when tearing down a connection prior to driver unload.  Completes
 918  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 919  *   use this on the leading connection.
 920  *
 921  * RAMROD_CMD_ID_ETH_SET_MAC
 922  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 923  *   the RCQ of the leading connection.
 924  *
 925  * RAMROD_CMD_ID_ETH_CFC_DEL
 926  *   Used when tearing down a conneciton prior to driver unload.  Completes
 927  *   on the RCQ of the leading connection (since the current connection
 928  *   has been completely removed from controller memory).
 929  *
 930  * RAMROD_CMD_ID_ETH_PORT_DEL
 931  *   Used to tear down the leading connection prior to driver unload,
 932  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 933  *   default status block.
 934  *
 935  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 936  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 937  *   RSS connection that is being offloaded.  (Not currently used under
 938  *   FreeBSD.)
 939  *
 940  * There can only be one command pending per function.
 941  *
 942  * Returns:
 943  *   0 = Success, !0 = Failure.
 944  */
 945
 946 /* must be called under the spq lock */
 947 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 948 {
 949         struct eth_spe *next_spe = sc->spq_prod_bd;
 950
 951         if (sc->spq_prod_bd == sc->spq_last_bd) {
 952                 /* wrap back to the first eth_spq */
 953                 sc->spq_prod_bd = sc->spq;
 954                 sc->spq_prod_idx = 0;
 955         } else {
 956                 sc->spq_prod_bd++;
 957                 sc->spq_prod_idx++;
 958         }
 959
 960         return next_spe;
 961 }
 962
 963 /* must be called under the spq lock */
 964 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 965 {
 966         int func = SC_FUNC(sc);
 967
 968         /*
 969          * Make sure that BD data is updated before writing the producer.
 970          * BD data is written to the memory, the producer is read from the
 971          * memory, thus we need a full memory barrier to ensure the ordering.
 972          */
 973         mb();
 974
 975         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 976                  sc->spq_prod_idx);
 977
 978         mb();
 979 }
 980
 981 /**
 982  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 983  *
 984  * @cmd:      command to check
 985  * @cmd_type: command type
 986  */
 987 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
 988 {
 989         if ((cmd_type == NONE_CONNECTION_TYPE) ||
 990             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
 991             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
 992             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
 993             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
 994             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
 995             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
 996                 return TRUE;
 997         } else {
 998                 return FALSE;
 999         }
1000 }
1001
1002 /**
1003  * bnx2x_sp_post - place a single command on an SP ring
1004  *
1005  * @sc:         driver handle
1006  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1007  * @cid:        SW CID the command is related to
1008  * @data_hi:    command private data address (high 32 bits)
1009  * @data_lo:    command private data address (low 32 bits)
1010  * @cmd_type:   command type (e.g. NONE, ETH)
1011  *
1012  * SP data is handled as if it's always an address pair, thus data fields are
1013  * not swapped to little endian in upper functions. Instead this function swaps
1014  * data as if it's two uint32 fields.
1015  */
1016 int
1017 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1018             uint32_t data_lo, int cmd_type)
1019 {
1020         struct eth_spe *spe;
1021         uint16_t type;
1022         int common;
1023
1024         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1025
1026         if (common) {
1027                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1028                         PMD_DRV_LOG(INFO, "EQ ring is full!");
1029                         return -1;
1030                 }
1031         } else {
1032                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1033                         PMD_DRV_LOG(INFO, "SPQ ring is full!");
1034                         return -1;
1035                 }
1036         }
1037
1038         spe = bnx2x_sp_get_next(sc);
1039
1040         /* CID needs port number to be encoded int it */
1041         spe->hdr.conn_and_cmd_data =
1042             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1043
1044         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1045
1046         /* TBD: Check if it works for VFs */
1047         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1048                  SPE_HDR_FUNCTION_ID);
1049
1050         spe->hdr.type = htole16(type);
1051
1052         spe->data.update_data_addr.hi = htole32(data_hi);
1053         spe->data.update_data_addr.lo = htole32(data_lo);
1054
1055         /*
1056          * It's ok if the actual decrement is issued towards the memory
1057          * somewhere between the lock and unlock. Thus no more explict
1058          * memory barrier is needed.
1059          */
1060         if (common) {
1061                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1062         } else {
1063                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1064         }
1065
1066         PMD_DRV_LOG(DEBUG,
1067                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1068                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1069                     sc->spq_prod_idx,
1070                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1071                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1072                                 (uint8_t *) sc->spq_prod_bd -
1073                                 (uint8_t *) sc->spq), command, common,
1074                     HW_CID(sc, cid), data_hi, data_lo, type,
1075                     atomic_load_acq_long(&sc->cq_spq_left),
1076                     atomic_load_acq_long(&sc->eq_spq_left));
1077
1078         bnx2x_sp_prod_update(sc);
1079
1080         return 0;
1081 }
1082
1083 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1084 {
1085         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1086                  sc->fw_drv_pulse_wr_seq);
1087 }
1088
1089 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1090 {
1091         uint16_t hw_cons;
1092         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1093
1094         if (unlikely(!txq)) {
1095                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1096                 return 0;
1097         }
1098
1099         mb();                   /* status block fields can change */
1100         hw_cons = le16toh(*fp->tx_cons_sb);
1101         return hw_cons != txq->tx_pkt_head;
1102 }
1103
1104 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1105 {
1106         /* expand this for multi-cos if ever supported */
1107         return bnx2x_tx_queue_has_work(fp);
1108 }
1109
1110 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1111 {
1112         uint16_t rx_cq_cons_sb;
1113         struct bnx2x_rx_queue *rxq;
1114         rxq = fp->sc->rx_queues[fp->index];
1115         if (unlikely(!rxq)) {
1116                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1117                 return 0;
1118         }
1119
1120         mb();                   /* status block fields can change */
1121         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1122         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1123                      MAX_RCQ_ENTRIES(rxq)))
1124                 rx_cq_cons_sb++;
1125         return rxq->rx_cq_head != rx_cq_cons_sb;
1126 }
1127
1128 static void
1129 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1130              union eth_rx_cqe *rr_cqe)
1131 {
1132 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1133         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1134 #endif
1135         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1136         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1137         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1138
1139         PMD_DRV_LOG(DEBUG,
1140                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1141                     fp->index, cid, command, sc->state,
1142                     rr_cqe->ramrod_cqe.ramrod_type);
1143
1144         switch (command) {
1145         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1146                 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1147                 drv_cmd = ECORE_Q_CMD_UPDATE;
1148                 break;
1149
1150         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1151                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1152                 drv_cmd = ECORE_Q_CMD_SETUP;
1153                 break;
1154
1155         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1156                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1157                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1158                 break;
1159
1160         case (RAMROD_CMD_ID_ETH_HALT):
1161                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1162                 drv_cmd = ECORE_Q_CMD_HALT;
1163                 break;
1164
1165         case (RAMROD_CMD_ID_ETH_TERMINATE):
1166                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1167                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1168                 break;
1169
1170         case (RAMROD_CMD_ID_ETH_EMPTY):
1171                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1172                 drv_cmd = ECORE_Q_CMD_EMPTY;
1173                 break;
1174
1175         default:
1176                 PMD_DRV_LOG(DEBUG,
1177                             "ERROR: unexpected MC reply (%d)"
1178                             "on fp[%d]", command, fp->index);
1179                 return;
1180         }
1181
1182         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1183             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1184                 /*
1185                  * q_obj->complete_cmd() failure means that this was
1186                  * an unexpected completion.
1187                  *
1188                  * In this case we don't want to increase the sc->spq_left
1189                  * because apparently we haven't sent this command the first
1190                  * place.
1191                  */
1192                 // rte_panic("Unexpected SP completion");
1193                 return;
1194         }
1195
1196         atomic_add_acq_long(&sc->cq_spq_left, 1);
1197
1198         PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1199                     atomic_load_acq_long(&sc->cq_spq_left));
1200 }
1201
1202 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1203 {
1204         struct bnx2x_rx_queue *rxq;
1205         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1206         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1207
1208         rxq = sc->rx_queues[fp->index];
1209         if (!rxq) {
1210                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1211                 return 0;
1212         }
1213
1214         /* CQ "next element" is of the size of the regular element */
1215         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1216         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1217                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1218                 hw_cq_cons++;
1219         }
1220
1221         bd_cons = rxq->rx_bd_head;
1222         bd_prod = rxq->rx_bd_tail;
1223         bd_prod_fw = bd_prod;
1224         sw_cq_cons = rxq->rx_cq_head;
1225         sw_cq_prod = rxq->rx_cq_tail;
1226
1227         /*
1228          * Memory barrier necessary as speculative reads of the rx
1229          * buffer can be ahead of the index in the status block
1230          */
1231         rmb();
1232
1233         while (sw_cq_cons != hw_cq_cons) {
1234                 union eth_rx_cqe *cqe;
1235                 struct eth_fast_path_rx_cqe *cqe_fp;
1236                 uint8_t cqe_fp_flags;
1237                 enum eth_rx_cqe_type cqe_fp_type;
1238
1239                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1240                 bd_prod = RX_BD(bd_prod, rxq);
1241                 bd_cons = RX_BD(bd_cons, rxq);
1242
1243                 cqe = &rxq->cq_ring[comp_ring_cons];
1244                 cqe_fp = &cqe->fast_path_cqe;
1245                 cqe_fp_flags = cqe_fp->type_error_flags;
1246                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1247
1248                 /* is this a slowpath msg? */
1249                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1250                         bnx2x_sp_event(sc, fp, cqe);
1251                         goto next_cqe;
1252                 }
1253
1254                 /* is this an error packet? */
1255                 if (unlikely(cqe_fp_flags &
1256                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1257                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1258                                    cqe_fp_flags, sw_cq_cons);
1259                         goto next_rx;
1260                 }
1261
1262                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1263
1264 next_rx:
1265                 bd_cons = NEXT_RX_BD(bd_cons);
1266                 bd_prod = NEXT_RX_BD(bd_prod);
1267                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1268
1269 next_cqe:
1270                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1271                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1272
1273         }                       /* while work to do */
1274
1275         rxq->rx_bd_head = bd_cons;
1276         rxq->rx_bd_tail = bd_prod_fw;
1277         rxq->rx_cq_head = sw_cq_cons;
1278         rxq->rx_cq_tail = sw_cq_prod;
1279
1280         /* Update producers */
1281         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1282
1283         return sw_cq_cons != hw_cq_cons;
1284 }
1285
1286 static uint16_t
1287 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1288                 uint16_t pkt_idx, uint16_t bd_idx)
1289 {
1290         struct eth_tx_start_bd *tx_start_bd =
1291             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1292         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1293         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1294
1295         if (likely(tx_mbuf != NULL)) {
1296                 rte_pktmbuf_free_seg(tx_mbuf);
1297         } else {
1298                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1299                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1300         }
1301
1302         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1303         txq->nb_tx_avail += nbd;
1304
1305         while (nbd--)
1306                 bd_idx = NEXT_TX_BD(bd_idx);
1307
1308         return bd_idx;
1309 }
1310
1311 /* processes transmit completions */
1312 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1313 {
1314         uint16_t bd_cons, hw_cons, sw_cons;
1315         __rte_unused uint16_t tx_bd_avail;
1316
1317         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1318
1319         if (unlikely(!txq)) {
1320                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1321                 return 0;
1322         }
1323
1324         bd_cons = txq->tx_bd_head;
1325         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1326         sw_cons = txq->tx_pkt_head;
1327
1328         while (sw_cons != hw_cons) {
1329                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1330                 sw_cons++;
1331         }
1332
1333         txq->tx_pkt_head = sw_cons;
1334         txq->tx_bd_head = bd_cons;
1335
1336         tx_bd_avail = txq->nb_tx_avail;
1337
1338         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1339                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1340                    fp->index, tx_bd_avail, hw_cons,
1341                    txq->tx_pkt_head, txq->tx_pkt_tail,
1342                    txq->tx_bd_head, txq->tx_bd_tail);
1343         return TRUE;
1344 }
1345
1346 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1347 {
1348         struct bnx2x_fastpath *fp;
1349         int i, count;
1350
1351         /* wait until all TX fastpath tasks have completed */
1352         for (i = 0; i < sc->num_queues; i++) {
1353                 fp = &sc->fp[i];
1354
1355                 count = 1000;
1356
1357                 while (bnx2x_has_tx_work(fp)) {
1358                         bnx2x_txeof(sc, fp);
1359
1360                         if (count == 0) {
1361                                 PMD_TX_LOG(ERR,
1362                                            "Timeout waiting for fp[%d] "
1363                                            "transmits to complete!", i);
1364                                 rte_panic("tx drain failure");
1365                                 return;
1366                         }
1367
1368                         count--;
1369                         DELAY(1000);
1370                         rmb();
1371                 }
1372         }
1373
1374         return;
1375 }
1376
1377 static int
1378 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1379                  int mac_type, uint8_t wait_for_comp)
1380 {
1381         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1382         int rc;
1383
1384         /* wait for completion of requested */
1385         if (wait_for_comp) {
1386                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1387         }
1388
1389         /* Set the mac type of addresses we want to clear */
1390         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1391
1392         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1393         if (rc < 0)
1394                 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1395
1396         return rc;
1397 }
1398
1399 static int
1400 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1401                         unsigned long *rx_accept_flags,
1402                         unsigned long *tx_accept_flags)
1403 {
1404         /* Clear the flags first */
1405         *rx_accept_flags = 0;
1406         *tx_accept_flags = 0;
1407
1408         switch (rx_mode) {
1409         case BNX2X_RX_MODE_NONE:
1410                 /*
1411                  * 'drop all' supersedes any accept flags that may have been
1412                  * passed to the function.
1413                  */
1414                 break;
1415
1416         case BNX2X_RX_MODE_NORMAL:
1417                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1418                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1419                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1420
1421                 /* internal switching mode */
1422                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1423                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1424                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1425
1426                 break;
1427
1428         case BNX2X_RX_MODE_ALLMULTI:
1429                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1430                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1431                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1432
1433                 /* internal switching mode */
1434                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1435                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1436                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1437
1438                 break;
1439
1440         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1441         case BNX2X_RX_MODE_PROMISC:
1442                 /*
1443                  * According to deffinition of SI mode, iface in promisc mode
1444                  * should receive matched and unmatched (in resolution of port)
1445                  * unicast packets.
1446                  */
1447                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1448                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1449                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1450                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1451
1452                 /* internal switching mode */
1453                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1454                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1455
1456                 if (IS_MF_SI(sc)) {
1457                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1458                 } else {
1459                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1460                 }
1461
1462                 break;
1463
1464         default:
1465                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1466                 return -1;
1467         }
1468
1469         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1470         if (rx_mode != BNX2X_RX_MODE_NONE) {
1471                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1472                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1473         }
1474
1475         return 0;
1476 }
1477
1478 static int
1479 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1480                   unsigned long rx_mode_flags,
1481                   unsigned long rx_accept_flags,
1482                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1483 {
1484         struct ecore_rx_mode_ramrod_params ramrod_param;
1485         int rc;
1486
1487         memset(&ramrod_param, 0, sizeof(ramrod_param));
1488
1489         /* Prepare ramrod parameters */
1490         ramrod_param.cid = 0;
1491         ramrod_param.cl_id = cl_id;
1492         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1493         ramrod_param.func_id = SC_FUNC(sc);
1494
1495         ramrod_param.pstate = &sc->sp_state;
1496         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1497
1498         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1499         ramrod_param.rdata_mapping =
1500             (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1501             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1502
1503         ramrod_param.ramrod_flags = ramrod_flags;
1504         ramrod_param.rx_mode_flags = rx_mode_flags;
1505
1506         ramrod_param.rx_accept_flags = rx_accept_flags;
1507         ramrod_param.tx_accept_flags = tx_accept_flags;
1508
1509         rc = ecore_config_rx_mode(sc, &ramrod_param);
1510         if (rc < 0) {
1511                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1512                 return rc;
1513         }
1514
1515         return 0;
1516 }
1517
1518 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1519 {
1520         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1521         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1522         int rc;
1523
1524         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1525                                    &tx_accept_flags);
1526         if (rc) {
1527                 return rc;
1528         }
1529
1530         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1531         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1532         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1533
1534         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1535                                  rx_accept_flags, tx_accept_flags,
1536                                  ramrod_flags);
1537 }
1538
1539 /* returns the "mcp load_code" according to global load_count array */
1540 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1541 {
1542         int path = SC_PATH(sc);
1543         int port = SC_PORT(sc);
1544
1545         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1546                     path, load_count[path][0], load_count[path][1],
1547                     load_count[path][2]);
1548
1549         load_count[path][0]++;
1550         load_count[path][1 + port]++;
1551         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1552                     path, load_count[path][0], load_count[path][1],
1553                     load_count[path][2]);
1554         if (load_count[path][0] == 1)
1555                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1556         else if (load_count[path][1 + port] == 1)
1557                 return FW_MSG_CODE_DRV_LOAD_PORT;
1558         else
1559                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1560 }
1561
1562 /* returns the "mcp load_code" according to global load_count array */
1563 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1564 {
1565         int port = SC_PORT(sc);
1566         int path = SC_PATH(sc);
1567
1568         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1569                     path, load_count[path][0], load_count[path][1],
1570                     load_count[path][2]);
1571         load_count[path][0]--;
1572         load_count[path][1 + port]--;
1573         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1574                     path, load_count[path][0], load_count[path][1],
1575                     load_count[path][2]);
1576         if (load_count[path][0] == 0) {
1577                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1578         } else if (load_count[path][1 + port] == 0) {
1579                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1580         } else {
1581                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1582         }
1583 }
1584
1585 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1586 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1587 {
1588         uint32_t reset_code = 0;
1589
1590         /* Select the UNLOAD request mode */
1591         if (unload_mode == UNLOAD_NORMAL) {
1592                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1593         } else {
1594                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1595         }
1596
1597         /* Send the request to the MCP */
1598         if (!BNX2X_NOMCP(sc)) {
1599                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1600         } else {
1601                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1602         }
1603
1604         return reset_code;
1605 }
1606
1607 /* send UNLOAD_DONE command to the MCP */
1608 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1609 {
1610         uint32_t reset_param =
1611             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1612
1613         /* Report UNLOAD_DONE to MCP */
1614         if (!BNX2X_NOMCP(sc)) {
1615                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1616         }
1617 }
1618
1619 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1620 {
1621         int tout = 50;
1622
1623         if (!sc->port.pmf) {
1624                 return 0;
1625         }
1626
1627         /*
1628          * (assumption: No Attention from MCP at this stage)
1629          * PMF probably in the middle of TX disable/enable transaction
1630          * 1. Sync IRS for default SB
1631          * 2. Sync SP queue - this guarantees us that attention handling started
1632          * 3. Wait, that TX disable/enable transaction completes
1633          *
1634          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1635          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1636          * received completion for the transaction the state is TX_STOPPED.
1637          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1638          * transaction.
1639          */
1640
1641         while (ecore_func_get_state(sc, &sc->func_obj) !=
1642                ECORE_F_STATE_STARTED && tout--) {
1643                 DELAY(20000);
1644         }
1645
1646         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1647                 /*
1648                  * Failed to complete the transaction in a "good way"
1649                  * Force both transactions with CLR bit.
1650                  */
1651                 struct ecore_func_state_params func_params = { NULL };
1652
1653                 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1654                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1655
1656                 func_params.f_obj = &sc->func_obj;
1657                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1658
1659                 /* STARTED-->TX_STOPPED */
1660                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1661                 ecore_func_state_change(sc, &func_params);
1662
1663                 /* TX_STOPPED-->STARTED */
1664                 func_params.cmd = ECORE_F_CMD_TX_START;
1665                 return ecore_func_state_change(sc, &func_params);
1666         }
1667
1668         return 0;
1669 }
1670
1671 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1672 {
1673         struct bnx2x_fastpath *fp = &sc->fp[index];
1674         struct ecore_queue_state_params q_params = { NULL };
1675         int rc;
1676
1677         PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1678
1679         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1680         /* We want to wait for completion in this context */
1681         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1682
1683         /* Stop the primary connection: */
1684
1685         /* ...halt the connection */
1686         q_params.cmd = ECORE_Q_CMD_HALT;
1687         rc = ecore_queue_state_change(sc, &q_params);
1688         if (rc) {
1689                 return rc;
1690         }
1691
1692         /* ...terminate the connection */
1693         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1694         memset(&q_params.params.terminate, 0,
1695                sizeof(q_params.params.terminate));
1696         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1697         rc = ecore_queue_state_change(sc, &q_params);
1698         if (rc) {
1699                 return rc;
1700         }
1701
1702         /* ...delete cfc entry */
1703         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1704         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1705         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1706         return ecore_queue_state_change(sc, &q_params);
1707 }
1708
1709 /* wait for the outstanding SP commands */
1710 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1711 {
1712         unsigned long tmp;
1713         int tout = 5000;        /* wait for 5 secs tops */
1714
1715         while (tout--) {
1716                 mb();
1717                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1718                         return TRUE;
1719                 }
1720
1721                 DELAY(1000);
1722         }
1723
1724         mb();
1725
1726         tmp = atomic_load_acq_long(&sc->sp_state);
1727         if (tmp & mask) {
1728                 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1729                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1730                 return FALSE;
1731         }
1732
1733         return FALSE;
1734 }
1735
1736 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1737 {
1738         struct ecore_func_state_params func_params = { NULL };
1739         int rc;
1740
1741         /* prepare parameters for function state transitions */
1742         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1743         func_params.f_obj = &sc->func_obj;
1744         func_params.cmd = ECORE_F_CMD_STOP;
1745
1746         /*
1747          * Try to stop the function the 'good way'. If it fails (in case
1748          * of a parity error during bnx2x_chip_cleanup()) and we are
1749          * not in a debug mode, perform a state transaction in order to
1750          * enable further HW_RESET transaction.
1751          */
1752         rc = ecore_func_state_change(sc, &func_params);
1753         if (rc) {
1754                 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1755                             "Running a dry transaction");
1756                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1757                 return ecore_func_state_change(sc, &func_params);
1758         }
1759
1760         return 0;
1761 }
1762
1763 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1764 {
1765         struct ecore_func_state_params func_params = { NULL };
1766
1767         /* Prepare parameters for function state transitions */
1768         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1769
1770         func_params.f_obj = &sc->func_obj;
1771         func_params.cmd = ECORE_F_CMD_HW_RESET;
1772
1773         func_params.params.hw_init.load_phase = load_code;
1774
1775         return ecore_func_state_change(sc, &func_params);
1776 }
1777
1778 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1779 {
1780         if (disable_hw) {
1781                 /* prevent the HW from sending interrupts */
1782                 bnx2x_int_disable(sc);
1783         }
1784 }
1785
1786 static void
1787 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1788 {
1789         int port = SC_PORT(sc);
1790         struct ecore_mcast_ramrod_params rparam = { NULL };
1791         uint32_t reset_code;
1792         int i, rc = 0;
1793
1794         bnx2x_drain_tx_queues(sc);
1795
1796         /* give HW time to discard old tx messages */
1797         DELAY(1000);
1798
1799         /* Clean all ETH MACs */
1800         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1801                               FALSE);
1802         if (rc < 0) {
1803                 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1804         }
1805
1806         /* Clean up UC list  */
1807         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1808                               TRUE);
1809         if (rc < 0) {
1810                 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1811         }
1812
1813         /* Disable LLH */
1814         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1815
1816         /* Set "drop all" to stop Rx */
1817
1818         /*
1819          * We need to take the if_maddr_lock() here in order to prevent
1820          * a race between the completion code and this code.
1821          */
1822
1823         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1824                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1825         } else {
1826                 bnx2x_set_storm_rx_mode(sc);
1827         }
1828
1829         /* Clean up multicast configuration */
1830         rparam.mcast_obj = &sc->mcast_obj;
1831         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1832         if (rc < 0) {
1833                 PMD_DRV_LOG(NOTICE,
1834                             "Failed to send DEL MCAST command (%d)", rc);
1835         }
1836
1837         /*
1838          * Send the UNLOAD_REQUEST to the MCP. This will return if
1839          * this function should perform FUNCTION, PORT, or COMMON HW
1840          * reset.
1841          */
1842         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1843
1844         /*
1845          * (assumption: No Attention from MCP at this stage)
1846          * PMF probably in the middle of TX disable/enable transaction
1847          */
1848         rc = bnx2x_func_wait_started(sc);
1849         if (rc) {
1850                 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1851         }
1852
1853         /*
1854          * Close multi and leading connections
1855          * Completions for ramrods are collected in a synchronous way
1856          */
1857         for (i = 0; i < sc->num_queues; i++) {
1858                 if (bnx2x_stop_queue(sc, i)) {
1859                         goto unload_error;
1860                 }
1861         }
1862
1863         /*
1864          * If SP settings didn't get completed so far - something
1865          * very wrong has happen.
1866          */
1867         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1868                 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1869         }
1870
1871 unload_error:
1872
1873         rc = bnx2x_func_stop(sc);
1874         if (rc) {
1875                 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1876         }
1877
1878         /* disable HW interrupts */
1879         bnx2x_int_disable_sync(sc, TRUE);
1880
1881         /* Reset the chip */
1882         rc = bnx2x_reset_hw(sc, reset_code);
1883         if (rc) {
1884                 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1885         }
1886
1887         /* Report UNLOAD_DONE to MCP */
1888         bnx2x_send_unload_done(sc, keep_link);
1889 }
1890
1891 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1892 {
1893         uint32_t val;
1894
1895         PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1896
1897         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1898         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1899                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1900         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1901 }
1902
1903 /*
1904  * Cleans the object that have internal lists without sending
1905  * ramrods. Should be run when interrutps are disabled.
1906  */
1907 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1908 {
1909         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1910         struct ecore_mcast_ramrod_params rparam = { NULL };
1911         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1912         int rc;
1913
1914         /* Cleanup MACs' object first... */
1915
1916         /* Wait for completion of requested */
1917         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1918         /* Perform a dry cleanup */
1919         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1920
1921         /* Clean ETH primary MAC */
1922         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1923         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1924                                  &ramrod_flags);
1925         if (rc != 0) {
1926                 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1927         }
1928
1929         /* Cleanup UC list */
1930         vlan_mac_flags = 0;
1931         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1932         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1933         if (rc != 0) {
1934                 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1935         }
1936
1937         /* Now clean mcast object... */
1938
1939         rparam.mcast_obj = &sc->mcast_obj;
1940         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1941
1942         /* Add a DEL command... */
1943         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1944         if (rc < 0) {
1945                 PMD_DRV_LOG(NOTICE,
1946                             "Failed to send DEL MCAST command (%d)", rc);
1947         }
1948
1949         /* now wait until all pending commands are cleared */
1950
1951         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1952         while (rc != 0) {
1953                 if (rc < 0) {
1954                         PMD_DRV_LOG(NOTICE,
1955                                     "Failed to clean MCAST object (%d)", rc);
1956                         return;
1957                 }
1958
1959                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1960         }
1961 }
1962
1963 /* stop the controller */
1964 __rte_noinline
1965 int
1966 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1967 {
1968         uint8_t global = FALSE;
1969         uint32_t val;
1970
1971         PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1972
1973         /* mark driver as unloaded in shmem2 */
1974         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1975                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1976                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1977                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1978         }
1979
1980         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1981             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1982                 /*
1983                  * We can get here if the driver has been unloaded
1984                  * during parity error recovery and is either waiting for a
1985                  * leader to complete or for other functions to unload and
1986                  * then ifconfig down has been issued. In this case we want to
1987                  * unload and let other functions to complete a recovery
1988                  * process.
1989                  */
1990                 sc->recovery_state = BNX2X_RECOVERY_DONE;
1991                 sc->is_leader = 0;
1992                 bnx2x_release_leader_lock(sc);
1993                 mb();
1994
1995                 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
1996                 return -1;
1997         }
1998
1999         /*
2000          * Nothing to do during unload if previous bnx2x_nic_load()
2001          * did not completed successfully - all resourses are released.
2002          */
2003         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2004                 return 0;
2005         }
2006
2007         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2008         mb();
2009
2010         sc->rx_mode = BNX2X_RX_MODE_NONE;
2011         bnx2x_set_rx_mode(sc);
2012         mb();
2013
2014         if (IS_PF(sc)) {
2015                 /* set ALWAYS_ALIVE bit in shmem */
2016                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2017
2018                 bnx2x_drv_pulse(sc);
2019
2020                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2021                 bnx2x_save_statistics(sc);
2022         }
2023
2024         /* wait till consumers catch up with producers in all queues */
2025         bnx2x_drain_tx_queues(sc);
2026
2027         /* if VF indicate to PF this function is going down (PF will delete sp
2028          * elements and clear initializations
2029          */
2030         if (IS_VF(sc)) {
2031                 bnx2x_vf_unload(sc);
2032         } else if (unload_mode != UNLOAD_RECOVERY) {
2033                 /* if this is a normal/close unload need to clean up chip */
2034                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2035         } else {
2036                 /* Send the UNLOAD_REQUEST to the MCP */
2037                 bnx2x_send_unload_req(sc, unload_mode);
2038
2039                 /*
2040                  * Prevent transactions to host from the functions on the
2041                  * engine that doesn't reset global blocks in case of global
2042                  * attention once gloabl blocks are reset and gates are opened
2043                  * (the engine which leader will perform the recovery
2044                  * last).
2045                  */
2046                 if (!CHIP_IS_E1x(sc)) {
2047                         bnx2x_pf_disable(sc);
2048                 }
2049
2050                 /* disable HW interrupts */
2051                 bnx2x_int_disable_sync(sc, TRUE);
2052
2053                 /* Report UNLOAD_DONE to MCP */
2054                 bnx2x_send_unload_done(sc, FALSE);
2055         }
2056
2057         /*
2058          * At this stage no more interrupts will arrive so we may safely clean
2059          * the queue'able objects here in case they failed to get cleaned so far.
2060          */
2061         if (IS_PF(sc)) {
2062                 bnx2x_squeeze_objects(sc);
2063         }
2064
2065         /* There should be no more pending SP commands at this stage */
2066         sc->sp_state = 0;
2067
2068         sc->port.pmf = 0;
2069
2070         if (IS_PF(sc)) {
2071                 bnx2x_free_mem(sc);
2072         }
2073
2074         bnx2x_free_fw_stats_mem(sc);
2075
2076         sc->state = BNX2X_STATE_CLOSED;
2077
2078         /*
2079          * Check if there are pending parity attentions. If there are - set
2080          * RECOVERY_IN_PROGRESS.
2081          */
2082         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2083                 bnx2x_set_reset_in_progress(sc);
2084
2085                 /* Set RESET_IS_GLOBAL if needed */
2086                 if (global) {
2087                         bnx2x_set_reset_global(sc);
2088                 }
2089         }
2090
2091         /*
2092          * The last driver must disable a "close the gate" if there is no
2093          * parity attention or "process kill" pending.
2094          */
2095         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2096             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2097                 bnx2x_disable_close_the_gate(sc);
2098         }
2099
2100         PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2101
2102         return 0;
2103 }
2104
2105 /*
2106  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2107  * visible to the controller.
2108  *
2109  * If an mbuf is submitted to this routine and cannot be given to the
2110  * controller (e.g. it has too many fragments) then the function may free
2111  * the mbuf and return to the caller.
2112  *
2113  * Returns:
2114  *     int: Number of TX BDs used for the mbuf
2115  *
2116  *   Note the side effect that an mbuf may be freed if it causes a problem.
2117  */
2118 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2119 {
2120         struct eth_tx_start_bd *tx_start_bd;
2121         uint16_t bd_prod, pkt_prod;
2122         struct bnx2x_softc *sc;
2123         uint32_t nbds = 0;
2124
2125         sc = txq->sc;
2126         bd_prod = txq->tx_bd_tail;
2127         pkt_prod = txq->tx_pkt_tail;
2128
2129         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2130
2131         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2132
2133         tx_start_bd->addr =
2134             rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
2135         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2136         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2137         tx_start_bd->general_data =
2138             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2139
2140         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2141
2142         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2143                 tx_start_bd->vlan_or_ethertype =
2144                     rte_cpu_to_le_16(m0->vlan_tci);
2145                 tx_start_bd->bd_flags.as_bitfield |=
2146                     (X_ETH_OUTBAND_VLAN <<
2147                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2148         } else {
2149                 if (IS_PF(sc))
2150                         tx_start_bd->vlan_or_ethertype =
2151                             rte_cpu_to_le_16(pkt_prod);
2152                 else {
2153                         struct ether_hdr *eh =
2154                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2155
2156                         tx_start_bd->vlan_or_ethertype =
2157                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2158                 }
2159         }
2160
2161         bd_prod = NEXT_TX_BD(bd_prod);
2162         if (IS_VF(sc)) {
2163                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2164                 const struct ether_hdr *eh =
2165                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2166                 uint8_t mac_type = UNICAST_ADDRESS;
2167
2168                 tx_parse_bd =
2169                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2170                 if (is_multicast_ether_addr(&eh->d_addr)) {
2171                         if (is_broadcast_ether_addr(&eh->d_addr))
2172                                 mac_type = BROADCAST_ADDRESS;
2173                         else
2174                                 mac_type = MULTICAST_ADDRESS;
2175                 }
2176                 tx_parse_bd->parsing_data =
2177                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2178
2179                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2180                            &eh->d_addr.addr_bytes[0], 2);
2181                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2182                            &eh->d_addr.addr_bytes[2], 2);
2183                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2184                            &eh->d_addr.addr_bytes[4], 2);
2185                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2186                            &eh->s_addr.addr_bytes[0], 2);
2187                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2188                            &eh->s_addr.addr_bytes[2], 2);
2189                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2190                            &eh->s_addr.addr_bytes[4], 2);
2191
2192                 tx_parse_bd->data.mac_addr.dst_hi =
2193                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2194                 tx_parse_bd->data.mac_addr.dst_mid =
2195                     rte_cpu_to_be_16(tx_parse_bd->data.
2196                                      mac_addr.dst_mid);
2197                 tx_parse_bd->data.mac_addr.dst_lo =
2198                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2199                 tx_parse_bd->data.mac_addr.src_hi =
2200                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2201                 tx_parse_bd->data.mac_addr.src_mid =
2202                     rte_cpu_to_be_16(tx_parse_bd->data.
2203                                      mac_addr.src_mid);
2204                 tx_parse_bd->data.mac_addr.src_lo =
2205                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2206
2207                 PMD_TX_LOG(DEBUG,
2208                            "PBD dst %x %x %x src %x %x %x p_data %x",
2209                            tx_parse_bd->data.mac_addr.dst_hi,
2210                            tx_parse_bd->data.mac_addr.dst_mid,
2211                            tx_parse_bd->data.mac_addr.dst_lo,
2212                            tx_parse_bd->data.mac_addr.src_hi,
2213                            tx_parse_bd->data.mac_addr.src_mid,
2214                            tx_parse_bd->data.mac_addr.src_lo,
2215                            tx_parse_bd->parsing_data);
2216         }
2217
2218         PMD_TX_LOG(DEBUG,
2219                    "start bd: nbytes %d flags %x vlan %x",
2220                    tx_start_bd->nbytes,
2221                    tx_start_bd->bd_flags.as_bitfield,
2222                    tx_start_bd->vlan_or_ethertype);
2223
2224         bd_prod = NEXT_TX_BD(bd_prod);
2225         pkt_prod++;
2226
2227         if (TX_IDX(bd_prod) < 2)
2228                 nbds++;
2229
2230         txq->nb_tx_avail -= 2;
2231         txq->tx_bd_tail = bd_prod;
2232         txq->tx_pkt_tail = pkt_prod;
2233
2234         return nbds + 2;
2235 }
2236
2237 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2238 {
2239         return L2_ILT_LINES(sc);
2240 }
2241
2242 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2243 {
2244         struct ilt_client_info *ilt_client;
2245         struct ecore_ilt *ilt = sc->ilt;
2246         uint16_t line = 0;
2247
2248         PMD_INIT_FUNC_TRACE();
2249
2250         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2251
2252         /* CDU */
2253         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2254         ilt_client->client_num = ILT_CLIENT_CDU;
2255         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2256         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2257         ilt_client->start = line;
2258         line += bnx2x_cid_ilt_lines(sc);
2259
2260         if (CNIC_SUPPORT(sc)) {
2261                 line += CNIC_ILT_LINES;
2262         }
2263
2264         ilt_client->end = (line - 1);
2265
2266         /* QM */
2267         if (QM_INIT(sc->qm_cid_count)) {
2268                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2269                 ilt_client->client_num = ILT_CLIENT_QM;
2270                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2271                 ilt_client->flags = 0;
2272                 ilt_client->start = line;
2273
2274                 /* 4 bytes for each cid */
2275                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2276                                      QM_ILT_PAGE_SZ);
2277
2278                 ilt_client->end = (line - 1);
2279         }
2280
2281         if (CNIC_SUPPORT(sc)) {
2282                 /* SRC */
2283                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2284                 ilt_client->client_num = ILT_CLIENT_SRC;
2285                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2286                 ilt_client->flags = 0;
2287                 ilt_client->start = line;
2288                 line += SRC_ILT_LINES;
2289                 ilt_client->end = (line - 1);
2290
2291                 /* TM */
2292                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2293                 ilt_client->client_num = ILT_CLIENT_TM;
2294                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2295                 ilt_client->flags = 0;
2296                 ilt_client->start = line;
2297                 line += TM_ILT_LINES;
2298                 ilt_client->end = (line - 1);
2299         }
2300
2301         assert((line <= ILT_MAX_LINES));
2302 }
2303
2304 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2305 {
2306         int i;
2307
2308         for (i = 0; i < sc->num_queues; i++) {
2309                 /* get the Rx buffer size for RX frames */
2310                 sc->fp[i].rx_buf_size =
2311                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2312         }
2313 }
2314
2315 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2316 {
2317
2318         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2319
2320         return sc->ilt == NULL;
2321 }
2322
2323 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2324 {
2325         sc->ilt->lines = rte_calloc("",
2326                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2327                                     RTE_CACHE_LINE_SIZE);
2328         return sc->ilt->lines == NULL;
2329 }
2330
2331 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2332 {
2333         rte_free(sc->ilt);
2334         sc->ilt = NULL;
2335 }
2336
2337 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2338 {
2339         if (sc->ilt->lines != NULL) {
2340                 rte_free(sc->ilt->lines);
2341                 sc->ilt->lines = NULL;
2342         }
2343 }
2344
2345 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2346 {
2347         uint32_t i;
2348
2349         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2350                 sc->context[i].vcxt = NULL;
2351                 sc->context[i].size = 0;
2352         }
2353
2354         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2355
2356         bnx2x_free_ilt_lines_mem(sc);
2357 }
2358
2359 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2360 {
2361         int context_size;
2362         int allocated;
2363         int i;
2364         char cdu_name[RTE_MEMZONE_NAMESIZE];
2365
2366         /*
2367          * Allocate memory for CDU context:
2368          * This memory is allocated separately and not in the generic ILT
2369          * functions because CDU differs in few aspects:
2370          * 1. There can be multiple entities allocating memory for context -
2371          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2372          * its own ILT lines.
2373          * 2. Since CDU page-size is not a single 4KB page (which is the case
2374          * for the other ILT clients), to be efficient we want to support
2375          * allocation of sub-page-size in the last entry.
2376          * 3. Context pointers are used by the driver to pass to FW / update
2377          * the context (for the other ILT clients the pointers are used just to
2378          * free the memory during unload).
2379          */
2380         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2381         for (i = 0, allocated = 0; allocated < context_size; i++) {
2382                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2383                                           (context_size - allocated));
2384
2385                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2386                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2387                                   &sc->context[i].vcxt_dma,
2388                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2389                         bnx2x_free_mem(sc);
2390                         return -1;
2391                 }
2392
2393                 sc->context[i].vcxt =
2394                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2395
2396                 allocated += sc->context[i].size;
2397         }
2398
2399         bnx2x_alloc_ilt_lines_mem(sc);
2400
2401         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2402                 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2403                 bnx2x_free_mem(sc);
2404                 return -1;
2405         }
2406
2407         return 0;
2408 }
2409
2410 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2411 {
2412         sc->fw_stats_num = 0;
2413
2414         sc->fw_stats_req_size = 0;
2415         sc->fw_stats_req = NULL;
2416         sc->fw_stats_req_mapping = 0;
2417
2418         sc->fw_stats_data_size = 0;
2419         sc->fw_stats_data = NULL;
2420         sc->fw_stats_data_mapping = 0;
2421 }
2422
2423 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2424 {
2425         uint8_t num_queue_stats;
2426         int num_groups, vf_headroom = 0;
2427
2428         /* number of queues for statistics is number of eth queues */
2429         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2430
2431         /*
2432          * Total number of FW statistics requests =
2433          *   1 for port stats + 1 for PF stats + num of queues
2434          */
2435         sc->fw_stats_num = (2 + num_queue_stats);
2436
2437         /*
2438          * Request is built from stats_query_header and an array of
2439          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2440          * rules. The real number or requests is configured in the
2441          * stats_query_header.
2442          */
2443         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2444         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2445                 num_groups++;
2446
2447         sc->fw_stats_req_size =
2448             (sizeof(struct stats_query_header) +
2449              (num_groups * sizeof(struct stats_query_cmd_group)));
2450
2451         /*
2452          * Data for statistics requests + stats_counter.
2453          * stats_counter holds per-STORM counters that are incremented when
2454          * STORM has finished with the current request. Memory for FCoE
2455          * offloaded statistics are counted anyway, even if they will not be sent.
2456          * VF stats are not accounted for here as the data of VF stats is stored
2457          * in memory allocated by the VF, not here.
2458          */
2459         sc->fw_stats_data_size =
2460             (sizeof(struct stats_counter) +
2461              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2462              /* sizeof(struct fcoe_statistics_params) + */
2463              (sizeof(struct per_queue_stats) * num_queue_stats));
2464
2465         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2466                           &sc->fw_stats_dma, "fw_stats",
2467                           RTE_CACHE_LINE_SIZE) != 0) {
2468                 bnx2x_free_fw_stats_mem(sc);
2469                 return -1;
2470         }
2471
2472         /* set up the shortcuts */
2473
2474         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2475         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2476
2477         sc->fw_stats_data =
2478             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2479                                          sc->fw_stats_req_size);
2480         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2481                                      sc->fw_stats_req_size);
2482
2483         return 0;
2484 }
2485
2486 /*
2487  * Bits map:
2488  * 0-7  - Engine0 load counter.
2489  * 8-15 - Engine1 load counter.
2490  * 16   - Engine0 RESET_IN_PROGRESS bit.
2491  * 17   - Engine1 RESET_IN_PROGRESS bit.
2492  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2493  *        function on the engine
2494  * 19   - Engine1 ONE_IS_LOADED.
2495  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2496  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2497  *        for just the one belonging to its engine).
2498  */
2499 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2500 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2501 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2502 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2503 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2504 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2505 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2506 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2507
2508 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2509 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2510 {
2511         uint32_t val;
2512         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2513         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2514         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2515         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2516 }
2517
2518 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2519 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2520 {
2521         uint32_t val;
2522         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2523         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2524         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2525         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2526 }
2527
2528 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2529 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2530 {
2531         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2532 }
2533
2534 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2535 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2536 {
2537         uint32_t val;
2538         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2539             BNX2X_PATH0_RST_IN_PROG_BIT;
2540
2541         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2542
2543         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2544         /* Clear the bit */
2545         val &= ~bit;
2546         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2547
2548         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2549 }
2550
2551 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2552 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2553 {
2554         uint32_t val;
2555         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2556             BNX2X_PATH0_RST_IN_PROG_BIT;
2557
2558         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2559
2560         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2561         /* Set the bit */
2562         val |= bit;
2563         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2564
2565         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2566 }
2567
2568 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2569 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2570 {
2571         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2572         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2573             BNX2X_PATH0_RST_IN_PROG_BIT;
2574
2575         /* return false if bit is set */
2576         return (val & bit) ? FALSE : TRUE;
2577 }
2578
2579 /* get the load status for an engine, should be run under rtnl lock */
2580 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2581 {
2582         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2583             BNX2X_PATH0_LOAD_CNT_MASK;
2584         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2585             BNX2X_PATH0_LOAD_CNT_SHIFT;
2586         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2587
2588         val = ((val & mask) >> shift);
2589
2590         return val != 0;
2591 }
2592
2593 /* set pf load mark */
2594 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2595 {
2596         uint32_t val;
2597         uint32_t val1;
2598         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2599             BNX2X_PATH0_LOAD_CNT_MASK;
2600         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2601             BNX2X_PATH0_LOAD_CNT_SHIFT;
2602
2603         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2604
2605         PMD_INIT_FUNC_TRACE();
2606
2607         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2608
2609         /* get the current counter value */
2610         val1 = ((val & mask) >> shift);
2611
2612         /* set bit of this PF */
2613         val1 |= (1 << SC_ABS_FUNC(sc));
2614
2615         /* clear the old value */
2616         val &= ~mask;
2617
2618         /* set the new one */
2619         val |= ((val1 << shift) & mask);
2620
2621         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2622
2623         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2624 }
2625
2626 /* clear pf load mark */
2627 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2628 {
2629         uint32_t val1, val;
2630         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2631             BNX2X_PATH0_LOAD_CNT_MASK;
2632         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2633             BNX2X_PATH0_LOAD_CNT_SHIFT;
2634
2635         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2636         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2637
2638         /* get the current counter value */
2639         val1 = (val & mask) >> shift;
2640
2641         /* clear bit of that PF */
2642         val1 &= ~(1 << SC_ABS_FUNC(sc));
2643
2644         /* clear the old value */
2645         val &= ~mask;
2646
2647         /* set the new one */
2648         val |= ((val1 << shift) & mask);
2649
2650         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2651         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2652         return val1 != 0;
2653 }
2654
2655 /* send load requrest to mcp and analyze response */
2656 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2657 {
2658         PMD_INIT_FUNC_TRACE();
2659
2660         /* init fw_seq */
2661         sc->fw_seq =
2662             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2663              DRV_MSG_SEQ_NUMBER_MASK);
2664
2665         PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2666
2667 #ifdef BNX2X_PULSE
2668         /* get the current FW pulse sequence */
2669         sc->fw_drv_pulse_wr_seq =
2670             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2671              DRV_PULSE_SEQ_MASK);
2672 #else
2673         /* set ALWAYS_ALIVE bit in shmem */
2674         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2675         bnx2x_drv_pulse(sc);
2676 #endif
2677
2678         /* load request */
2679         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2680                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2681
2682         /* if the MCP fails to respond we must abort */
2683         if (!(*load_code)) {
2684                 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2685                 return -1;
2686         }
2687
2688         /* if MCP refused then must abort */
2689         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2690                 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2691                 return -1;
2692         }
2693
2694         return 0;
2695 }
2696
2697 /*
2698  * Check whether another PF has already loaded FW to chip. In virtualized
2699  * environments a pf from anoth VM may have already initialized the device
2700  * including loading FW.
2701  */
2702 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2703 {
2704         uint32_t my_fw, loaded_fw;
2705
2706         /* is another pf loaded on this engine? */
2707         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2708             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2709                 /* build my FW version dword */
2710                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2711                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2712                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2713                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2714
2715                 /* read loaded FW from chip */
2716                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2717                 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2718                             loaded_fw, my_fw);
2719
2720                 /* abort nic load if version mismatch */
2721                 if (my_fw != loaded_fw) {
2722                         PMD_DRV_LOG(NOTICE,
2723                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2724                                     loaded_fw, my_fw);
2725                         return -1;
2726                 }
2727         }
2728
2729         return 0;
2730 }
2731
2732 /* mark PMF if applicable */
2733 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2734 {
2735         uint32_t ncsi_oem_data_addr;
2736
2737         PMD_INIT_FUNC_TRACE();
2738
2739         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2740             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2741             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2742                 /*
2743                  * Barrier here for ordering between the writing to sc->port.pmf here
2744                  * and reading it from the periodic task.
2745                  */
2746                 sc->port.pmf = 1;
2747                 mb();
2748         } else {
2749                 sc->port.pmf = 0;
2750         }
2751
2752         PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2753
2754         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2755                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2756                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2757                         if (ncsi_oem_data_addr) {
2758                                 REG_WR(sc,
2759                                        (ncsi_oem_data_addr +
2760                                         offsetof(struct glob_ncsi_oem_data,
2761                                                  driver_version)), 0);
2762                         }
2763                 }
2764         }
2765 }
2766
2767 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2768 {
2769         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2770         int abs_func;
2771         int vn;
2772
2773         if (BNX2X_NOMCP(sc)) {
2774                 return;         /* what should be the default bvalue in this case */
2775         }
2776
2777         /*
2778          * The formula for computing the absolute function number is...
2779          * For 2 port configuration (4 functions per port):
2780          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2781          * For 4 port configuration (2 functions per port):
2782          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2783          */
2784         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2785                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2786                 if (abs_func >= E1H_FUNC_MAX) {
2787                         break;
2788                 }
2789                 sc->devinfo.mf_info.mf_config[vn] =
2790                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2791         }
2792
2793         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2794             FUNC_MF_CFG_FUNC_DISABLED) {
2795                 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2796                 sc->flags |= BNX2X_MF_FUNC_DIS;
2797         } else {
2798                 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2799                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2800         }
2801 }
2802
2803 /* acquire split MCP access lock register */
2804 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2805 {
2806         uint32_t j, val;
2807
2808         for (j = 0; j < 1000; j++) {
2809                 val = (1UL << 31);
2810                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2811                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2812                 if (val & (1L << 31))
2813                         break;
2814
2815                 DELAY(5000);
2816         }
2817
2818         if (!(val & (1L << 31))) {
2819                 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2820                 return -1;
2821         }
2822
2823         return 0;
2824 }
2825
2826 /* release split MCP access lock register */
2827 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2828 {
2829         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2830 }
2831
2832 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2833 {
2834         int port = SC_PORT(sc);
2835         uint32_t ext_phy_config;
2836
2837         /* mark the failure */
2838         ext_phy_config =
2839             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2840
2841         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2842         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2843         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2844                  ext_phy_config);
2845
2846         /* log the failure */
2847         PMD_DRV_LOG(INFO,
2848                     "Fan Failure has caused the driver to shutdown "
2849                     "the card to prevent permanent damage. "
2850                     "Please contact OEM Support for assistance");
2851
2852         rte_panic("Schedule task to handle fan failure");
2853 }
2854
2855 /* this function is called upon a link interrupt */
2856 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2857 {
2858         uint32_t pause_enabled = 0;
2859         struct host_port_stats *pstats;
2860         int cmng_fns;
2861
2862         /* Make sure that we are synced with the current statistics */
2863         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2864
2865         elink_link_update(&sc->link_params, &sc->link_vars);
2866
2867         if (sc->link_vars.link_up) {
2868
2869                 /* dropless flow control */
2870                 if (sc->dropless_fc) {
2871                         pause_enabled = 0;
2872
2873                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2874                                 pause_enabled = 1;
2875                         }
2876
2877                         REG_WR(sc,
2878                                (BAR_USTRORM_INTMEM +
2879                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2880                                pause_enabled);
2881                 }
2882
2883                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2884                         pstats = BNX2X_SP(sc, port_stats);
2885                         /* reset old mac stats */
2886                         memset(&(pstats->mac_stx[0]), 0,
2887                                sizeof(struct mac_stx));
2888                 }
2889
2890                 if (sc->state == BNX2X_STATE_OPEN) {
2891                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2892                 }
2893         }
2894
2895         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2896                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2897
2898                 if (cmng_fns != CMNG_FNS_NONE) {
2899                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2900                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2901                 }
2902         }
2903
2904         bnx2x_link_report(sc);
2905
2906         if (IS_MF(sc)) {
2907                 bnx2x_link_sync_notify(sc);
2908         }
2909 }
2910
2911 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2912 {
2913         int port = SC_PORT(sc);
2914         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2915             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2916         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2917             NIG_REG_MASK_INTERRUPT_PORT0;
2918         uint32_t aeu_mask;
2919         uint32_t nig_mask = 0;
2920         uint32_t reg_addr;
2921         uint32_t igu_acked;
2922         uint32_t cnt;
2923
2924         if (sc->attn_state & asserted) {
2925                 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2926         }
2927
2928         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2929
2930         aeu_mask = REG_RD(sc, aeu_addr);
2931
2932         aeu_mask &= ~(asserted & 0x3ff);
2933
2934         REG_WR(sc, aeu_addr, aeu_mask);
2935
2936         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2937
2938         sc->attn_state |= asserted;
2939
2940         if (asserted & ATTN_HARD_WIRED_MASK) {
2941                 if (asserted & ATTN_NIG_FOR_FUNC) {
2942
2943                         /* save nig interrupt mask */
2944                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2945
2946                         /* If nig_mask is not set, no need to call the update function */
2947                         if (nig_mask) {
2948                                 REG_WR(sc, nig_int_mask_addr, 0);
2949
2950                                 bnx2x_link_attn(sc);
2951                         }
2952
2953                         /* handle unicore attn? */
2954                 }
2955
2956                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2957                         PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2958                 }
2959
2960                 if (asserted & GPIO_2_FUNC) {
2961                         PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2962                 }
2963
2964                 if (asserted & GPIO_3_FUNC) {
2965                         PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2966                 }
2967
2968                 if (asserted & GPIO_4_FUNC) {
2969                         PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2970                 }
2971
2972                 if (port == 0) {
2973                         if (asserted & ATTN_GENERAL_ATTN_1) {
2974                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2975                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2976                         }
2977                         if (asserted & ATTN_GENERAL_ATTN_2) {
2978                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2979                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2980                         }
2981                         if (asserted & ATTN_GENERAL_ATTN_3) {
2982                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2983                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2984                         }
2985                 } else {
2986                         if (asserted & ATTN_GENERAL_ATTN_4) {
2987                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2988                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2989                         }
2990                         if (asserted & ATTN_GENERAL_ATTN_5) {
2991                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2992                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2993                         }
2994                         if (asserted & ATTN_GENERAL_ATTN_6) {
2995                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
2996                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2997                         }
2998                 }
2999         }
3000         /* hardwired */
3001         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3002                 reg_addr =
3003                     (HC_REG_COMMAND_REG + port * 32 +
3004                      COMMAND_REG_ATTN_BITS_SET);
3005         } else {
3006                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3007         }
3008
3009         PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3010                     asserted,
3011                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3012                     reg_addr);
3013         REG_WR(sc, reg_addr, asserted);
3014
3015         /* now set back the mask */
3016         if (asserted & ATTN_NIG_FOR_FUNC) {
3017                 /*
3018                  * Verify that IGU ack through BAR was written before restoring
3019                  * NIG mask. This loop should exit after 2-3 iterations max.
3020                  */
3021                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3022                         cnt = 0;
3023
3024                         do {
3025                                 igu_acked =
3026                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3027                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3028                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3029
3030                         if (!igu_acked) {
3031                                 PMD_DRV_LOG(ERR,
3032                                             "Failed to verify IGU ack on time");
3033                         }
3034
3035                         mb();
3036                 }
3037
3038                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3039
3040         }
3041 }
3042
3043 static void
3044 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3045                      __rte_unused const char *blk)
3046 {
3047         PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3048 }
3049
3050 static int
3051 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3052                               uint8_t print)
3053 {
3054         uint32_t cur_bit = 0;
3055         int i = 0;
3056
3057         for (i = 0; sig; i++) {
3058                 cur_bit = ((uint32_t) 0x1 << i);
3059                 if (sig & cur_bit) {
3060                         switch (cur_bit) {
3061                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3062                                 if (print)
3063                                         bnx2x_print_next_block(sc, par_num++,
3064                                                              "BRB");
3065                                 break;
3066                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3067                                 if (print)
3068                                         bnx2x_print_next_block(sc, par_num++,
3069                                                              "PARSER");
3070                                 break;
3071                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3072                                 if (print)
3073                                         bnx2x_print_next_block(sc, par_num++,
3074                                                              "TSDM");
3075                                 break;
3076                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3077                                 if (print)
3078                                         bnx2x_print_next_block(sc, par_num++,
3079                                                              "SEARCHER");
3080                                 break;
3081                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3082                                 if (print)
3083                                         bnx2x_print_next_block(sc, par_num++,
3084                                                              "TCM");
3085                                 break;
3086                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3087                                 if (print)
3088                                         bnx2x_print_next_block(sc, par_num++,
3089                                                              "TSEMI");
3090                                 break;
3091                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3092                                 if (print)
3093                                         bnx2x_print_next_block(sc, par_num++,
3094                                                              "XPB");
3095                                 break;
3096                         }
3097
3098                         /* Clear the bit */
3099                         sig &= ~cur_bit;
3100                 }
3101         }
3102
3103         return par_num;
3104 }
3105
3106 static int
3107 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3108                               uint8_t * global, uint8_t print)
3109 {
3110         int i = 0;
3111         uint32_t cur_bit = 0;
3112         for (i = 0; sig; i++) {
3113                 cur_bit = ((uint32_t) 0x1 << i);
3114                 if (sig & cur_bit) {
3115                         switch (cur_bit) {
3116                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3117                                 if (print)
3118                                         bnx2x_print_next_block(sc, par_num++,
3119                                                              "PBF");
3120                                 break;
3121                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3122                                 if (print)
3123                                         bnx2x_print_next_block(sc, par_num++,
3124                                                              "QM");
3125                                 break;
3126                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3127                                 if (print)
3128                                         bnx2x_print_next_block(sc, par_num++,
3129                                                              "TM");
3130                                 break;
3131                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3132                                 if (print)
3133                                         bnx2x_print_next_block(sc, par_num++,
3134                                                              "XSDM");
3135                                 break;
3136                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3137                                 if (print)
3138                                         bnx2x_print_next_block(sc, par_num++,
3139                                                              "XCM");
3140                                 break;
3141                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3142                                 if (print)
3143                                         bnx2x_print_next_block(sc, par_num++,
3144                                                              "XSEMI");
3145                                 break;
3146                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3147                                 if (print)
3148                                         bnx2x_print_next_block(sc, par_num++,
3149                                                              "DOORBELLQ");
3150                                 break;
3151                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3152                                 if (print)
3153                                         bnx2x_print_next_block(sc, par_num++,
3154                                                              "NIG");
3155                                 break;
3156                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3157                                 if (print)
3158                                         bnx2x_print_next_block(sc, par_num++,
3159                                                              "VAUX PCI CORE");
3160                                 *global = TRUE;
3161                                 break;
3162                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3163                                 if (print)
3164                                         bnx2x_print_next_block(sc, par_num++,
3165                                                              "DEBUG");
3166                                 break;
3167                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3168                                 if (print)
3169                                         bnx2x_print_next_block(sc, par_num++,
3170                                                              "USDM");
3171                                 break;
3172                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3173                                 if (print)
3174                                         bnx2x_print_next_block(sc, par_num++,
3175                                                              "UCM");
3176                                 break;
3177                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3178                                 if (print)
3179                                         bnx2x_print_next_block(sc, par_num++,
3180                                                              "USEMI");
3181                                 break;
3182                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3183                                 if (print)
3184                                         bnx2x_print_next_block(sc, par_num++,
3185                                                              "UPB");
3186                                 break;
3187                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3188                                 if (print)
3189                                         bnx2x_print_next_block(sc, par_num++,
3190                                                              "CSDM");
3191                                 break;
3192                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3193                                 if (print)
3194                                         bnx2x_print_next_block(sc, par_num++,
3195                                                              "CCM");
3196                                 break;
3197                         }
3198
3199                         /* Clear the bit */
3200                         sig &= ~cur_bit;
3201                 }
3202         }
3203
3204         return par_num;
3205 }
3206
3207 static int
3208 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3209                               uint8_t print)
3210 {
3211         uint32_t cur_bit = 0;
3212         int i = 0;
3213
3214         for (i = 0; sig; i++) {
3215                 cur_bit = ((uint32_t) 0x1 << i);
3216                 if (sig & cur_bit) {
3217                         switch (cur_bit) {
3218                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3219                                 if (print)
3220                                         bnx2x_print_next_block(sc, par_num++,
3221                                                              "CSEMI");
3222                                 break;
3223                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3224                                 if (print)
3225                                         bnx2x_print_next_block(sc, par_num++,
3226                                                              "PXP");
3227                                 break;
3228                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3229                                 if (print)
3230                                         bnx2x_print_next_block(sc, par_num++,
3231                                                              "PXPPCICLOCKCLIENT");
3232                                 break;
3233                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3234                                 if (print)
3235                                         bnx2x_print_next_block(sc, par_num++,
3236                                                              "CFC");
3237                                 break;
3238                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3239                                 if (print)
3240                                         bnx2x_print_next_block(sc, par_num++,
3241                                                              "CDU");
3242                                 break;
3243                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3244                                 if (print)
3245                                         bnx2x_print_next_block(sc, par_num++,
3246                                                              "DMAE");
3247                                 break;
3248                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3249                                 if (print)
3250                                         bnx2x_print_next_block(sc, par_num++,
3251                                                              "IGU");
3252                                 break;
3253                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3254                                 if (print)
3255                                         bnx2x_print_next_block(sc, par_num++,
3256                                                              "MISC");
3257                                 break;
3258                         }
3259
3260                         /* Clear the bit */
3261                         sig &= ~cur_bit;
3262                 }
3263         }
3264
3265         return par_num;
3266 }
3267
3268 static int
3269 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3270                               uint8_t * global, uint8_t print)
3271 {
3272         uint32_t cur_bit = 0;
3273         int i = 0;
3274
3275         for (i = 0; sig; i++) {
3276                 cur_bit = ((uint32_t) 0x1 << i);
3277                 if (sig & cur_bit) {
3278                         switch (cur_bit) {
3279                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3280                                 if (print)
3281                                         bnx2x_print_next_block(sc, par_num++,
3282                                                              "MCP ROM");
3283                                 *global = TRUE;
3284                                 break;
3285                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3286                                 if (print)
3287                                         bnx2x_print_next_block(sc, par_num++,
3288                                                              "MCP UMP RX");
3289                                 *global = TRUE;
3290                                 break;
3291                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3292                                 if (print)
3293                                         bnx2x_print_next_block(sc, par_num++,
3294                                                              "MCP UMP TX");
3295                                 *global = TRUE;
3296                                 break;
3297                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3298                                 if (print)
3299                                         bnx2x_print_next_block(sc, par_num++,
3300                                                              "MCP SCPAD");
3301                                 *global = TRUE;
3302                                 break;
3303                         }
3304
3305                         /* Clear the bit */
3306                         sig &= ~cur_bit;
3307                 }
3308         }
3309
3310         return par_num;
3311 }
3312
3313 static int
3314 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3315                               uint8_t print)
3316 {
3317         uint32_t cur_bit = 0;
3318         int i = 0;
3319
3320         for (i = 0; sig; i++) {
3321                 cur_bit = ((uint32_t) 0x1 << i);
3322                 if (sig & cur_bit) {
3323                         switch (cur_bit) {
3324                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3325                                 if (print)
3326                                         bnx2x_print_next_block(sc, par_num++,
3327                                                              "PGLUE_B");
3328                                 break;
3329                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3330                                 if (print)
3331                                         bnx2x_print_next_block(sc, par_num++,
3332                                                              "ATC");
3333                                 break;
3334                         }
3335
3336                         /* Clear the bit */
3337                         sig &= ~cur_bit;
3338                 }
3339         }
3340
3341         return par_num;
3342 }
3343
3344 static uint8_t
3345 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3346                 uint32_t * sig)
3347 {
3348         int par_num = 0;
3349
3350         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3351             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3352             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3353             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3354             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3355                 PMD_DRV_LOG(ERR,
3356                             "Parity error: HW block parity attention:"
3357                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3358                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3359                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3360                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3361                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3362                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3363
3364                 if (print)
3365                         PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3366
3367                 par_num =
3368                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3369                                                   HW_PRTY_ASSERT_SET_0,
3370                                                   par_num, print);
3371                 par_num =
3372                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3373                                                   HW_PRTY_ASSERT_SET_1,
3374                                                   par_num, global, print);
3375                 par_num =
3376                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3377                                                   HW_PRTY_ASSERT_SET_2,
3378                                                   par_num, print);
3379                 par_num =
3380                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3381                                                   HW_PRTY_ASSERT_SET_3,
3382                                                   par_num, global, print);
3383                 par_num =
3384                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3385                                                   HW_PRTY_ASSERT_SET_4,
3386                                                   par_num, print);
3387
3388                 if (print)
3389                         PMD_DRV_LOG(INFO, "");
3390
3391                 return TRUE;
3392         }
3393
3394         return FALSE;
3395 }
3396
3397 static uint8_t
3398 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3399 {
3400         struct attn_route attn = { {0} };
3401         int port = SC_PORT(sc);
3402
3403         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3404         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3405         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3406         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3407
3408         if (!CHIP_IS_E1x(sc))
3409                 attn.sig[4] =
3410                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3411
3412         return bnx2x_parity_attn(sc, global, print, attn.sig);
3413 }
3414
3415 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3416 {
3417         uint32_t val;
3418
3419         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3420                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3421                 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3422                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3423                         PMD_DRV_LOG(INFO,
3424                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3425                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3426                         PMD_DRV_LOG(INFO,
3427                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3428                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3429                         PMD_DRV_LOG(INFO,
3430                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3431                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3432                         PMD_DRV_LOG(INFO,
3433                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3434                 if (val &
3435                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3436                         PMD_DRV_LOG(INFO,
3437                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3438                 if (val &
3439                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3440                         PMD_DRV_LOG(INFO,
3441                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3442                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3443                         PMD_DRV_LOG(INFO,
3444                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3445                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3446                         PMD_DRV_LOG(INFO,
3447                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3448                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3449                         PMD_DRV_LOG(INFO,
3450                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3451         }
3452
3453         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3454                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3455                 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3456                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3457                         PMD_DRV_LOG(INFO,
3458                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3459                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3460                         PMD_DRV_LOG(INFO,
3461                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3462                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3463                         PMD_DRV_LOG(INFO,
3464                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3465                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3466                         PMD_DRV_LOG(INFO,
3467                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3468                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3469                         PMD_DRV_LOG(INFO,
3470                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3471                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3472                         PMD_DRV_LOG(INFO,
3473                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3474         }
3475
3476         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3477                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3478                 PMD_DRV_LOG(INFO,
3479                             "ERROR: FATAL parity attention set4 0x%08x",
3480                             (uint32_t) (attn &
3481                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3482                                          |
3483                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3484         }
3485 }
3486
3487 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3488 {
3489         int port = SC_PORT(sc);
3490
3491         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3492 }
3493
3494 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3495 {
3496         int port = SC_PORT(sc);
3497
3498         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3499 }
3500
3501 /*
3502  * called due to MCP event (on pmf):
3503  *   reread new bandwidth configuration
3504  *   configure FW
3505  *   notify others function about the change
3506  */
3507 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3508 {
3509         if (sc->link_vars.link_up) {
3510                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3511                 bnx2x_link_sync_notify(sc);
3512         }
3513
3514         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3515 }
3516
3517 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3518 {
3519         bnx2x_config_mf_bw(sc);
3520         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3521 }
3522
3523 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3524 {
3525         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3526 }
3527
3528 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3529
3530 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3531 {
3532         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3533
3534         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3535                 ETH_STAT_INFO_VERSION_LEN);
3536
3537         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3538                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3539                                               ether_stat->mac_local + MAC_PAD,
3540                                               MAC_PAD, ETH_ALEN);
3541
3542         ether_stat->mtu_size = sc->mtu;
3543
3544         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3545         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3546
3547         ether_stat->txq_size = sc->tx_ring_size;
3548         ether_stat->rxq_size = sc->rx_ring_size;
3549 }
3550
3551 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3552 {
3553         enum drv_info_opcode op_code;
3554         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3555
3556         /* if drv_info version supported by MFW doesn't match - send NACK */
3557         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3558                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3559                 return;
3560         }
3561
3562         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3563                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3564
3565         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3566
3567         switch (op_code) {
3568         case ETH_STATS_OPCODE:
3569                 bnx2x_drv_info_ether_stat(sc);
3570                 break;
3571         case FCOE_STATS_OPCODE:
3572         case ISCSI_STATS_OPCODE:
3573         default:
3574                 /* if op code isn't supported - send NACK */
3575                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3576                 return;
3577         }
3578
3579         /*
3580          * If we got drv_info attn from MFW then these fields are defined in
3581          * shmem2 for sure
3582          */
3583         SHMEM2_WR(sc, drv_info_host_addr_lo,
3584                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3585         SHMEM2_WR(sc, drv_info_host_addr_hi,
3586                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3587
3588         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3589 }
3590
3591 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3592 {
3593         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3594 /*
3595  * This is the only place besides the function initialization
3596  * where the sc->flags can change so it is done without any
3597  * locks
3598  */
3599                 if (sc->devinfo.
3600                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3601                         PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3602                         sc->flags |= BNX2X_MF_FUNC_DIS;
3603                         bnx2x_e1h_disable(sc);
3604                 } else {
3605                         PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3606                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3607                         bnx2x_e1h_enable(sc);
3608                 }
3609                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3610         }
3611
3612         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3613                 bnx2x_config_mf_bw(sc);
3614                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3615         }
3616
3617         /* Report results to MCP */
3618         if (dcc_event)
3619                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3620         else
3621                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3622 }
3623
3624 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3625 {
3626         int port = SC_PORT(sc);
3627         uint32_t val;
3628
3629         sc->port.pmf = 1;
3630
3631         /*
3632          * We need the mb() to ensure the ordering between the writing to
3633          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3634          */
3635         mb();
3636
3637         /* enable nig attention */
3638         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3639         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3640                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3641                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3642         } else if (!CHIP_IS_E1x(sc)) {
3643                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3644                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3645         }
3646
3647         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3648 }
3649
3650 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3651 {
3652         char last_idx;
3653         int i, rc = 0;
3654         __rte_unused uint32_t row0, row1, row2, row3;
3655
3656         /* XSTORM */
3657         last_idx =
3658             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3659         if (last_idx)
3660                 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3661
3662         /* print the asserts */
3663         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3664
3665                 row0 =
3666                     REG_RD(sc,
3667                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3668                 row1 =
3669                     REG_RD(sc,
3670                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3671                            4);
3672                 row2 =
3673                     REG_RD(sc,
3674                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3675                            8);
3676                 row3 =
3677                     REG_RD(sc,
3678                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3679                            12);
3680
3681                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3682                         PMD_DRV_LOG(ERR,
3683                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3684                                     i, row3, row2, row1, row0);
3685                         rc++;
3686                 } else {
3687                         break;
3688                 }
3689         }
3690
3691         /* TSTORM */
3692         last_idx =
3693             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3694         if (last_idx) {
3695                 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3696         }
3697
3698         /* print the asserts */
3699         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3700
3701                 row0 =
3702                     REG_RD(sc,
3703                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3704                 row1 =
3705                     REG_RD(sc,
3706                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3707                            4);
3708                 row2 =
3709                     REG_RD(sc,
3710                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3711                            8);
3712                 row3 =
3713                     REG_RD(sc,
3714                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3715                            12);
3716
3717                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3718                         PMD_DRV_LOG(ERR,
3719                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3720                                     i, row3, row2, row1, row0);
3721                         rc++;
3722                 } else {
3723                         break;
3724                 }
3725         }
3726
3727         /* CSTORM */
3728         last_idx =
3729             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3730         if (last_idx) {
3731                 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3732         }
3733
3734         /* print the asserts */
3735         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3736
3737                 row0 =
3738                     REG_RD(sc,
3739                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3740                 row1 =
3741                     REG_RD(sc,
3742                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3743                            4);
3744                 row2 =
3745                     REG_RD(sc,
3746                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3747                            8);
3748                 row3 =
3749                     REG_RD(sc,
3750                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3751                            12);
3752
3753                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3754                         PMD_DRV_LOG(ERR,
3755                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3756                                     i, row3, row2, row1, row0);
3757                         rc++;
3758                 } else {
3759                         break;
3760                 }
3761         }
3762
3763         /* USTORM */
3764         last_idx =
3765             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3766         if (last_idx) {
3767                 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3768         }
3769
3770         /* print the asserts */
3771         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3772
3773                 row0 =
3774                     REG_RD(sc,
3775                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3776                 row1 =
3777                     REG_RD(sc,
3778                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3779                            4);
3780                 row2 =
3781                     REG_RD(sc,
3782                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3783                            8);
3784                 row3 =
3785                     REG_RD(sc,
3786                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3787                            12);
3788
3789                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3790                         PMD_DRV_LOG(ERR,
3791                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3792                                     i, row3, row2, row1, row0);
3793                         rc++;
3794                 } else {
3795                         break;
3796                 }
3797         }
3798
3799         return rc;
3800 }
3801
3802 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3803 {
3804         int func = SC_FUNC(sc);
3805         uint32_t val;
3806
3807         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3808
3809                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3810
3811                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3812                         bnx2x_read_mf_cfg(sc);
3813                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3814                             MFCFG_RD(sc,
3815                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3816                         val =
3817                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3818
3819                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3820                                 bnx2x_dcc_event(sc,
3821                                               (val &
3822                                                DRV_STATUS_DCC_EVENT_MASK));
3823
3824                         if (val & DRV_STATUS_SET_MF_BW)
3825                                 bnx2x_set_mf_bw(sc);
3826
3827                         if (val & DRV_STATUS_DRV_INFO_REQ)
3828                                 bnx2x_handle_drv_info_req(sc);
3829
3830                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3831                                 bnx2x_pmf_update(sc);
3832
3833                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3834                                 bnx2x_handle_eee_event(sc);
3835
3836                         if (sc->link_vars.periodic_flags &
3837                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3838                                 /* sync with link */
3839                                 sc->link_vars.periodic_flags &=
3840                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3841                                 if (IS_MF(sc)) {
3842                                         bnx2x_link_sync_notify(sc);
3843                                 }
3844                                 bnx2x_link_report(sc);
3845                         }
3846
3847                         /*
3848                          * Always call it here: bnx2x_link_report() will
3849                          * prevent the link indication duplication.
3850                          */
3851                         bnx2x_link_status_update(sc);
3852
3853                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3854
3855                         PMD_DRV_LOG(ERR, "MC assert!");
3856                         bnx2x_mc_assert(sc);
3857                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3858                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3859                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3860                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3861                         rte_panic("MC assert!");
3862
3863                 } else if (attn & BNX2X_MCP_ASSERT) {
3864
3865                         PMD_DRV_LOG(ERR, "MCP assert!");
3866                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3867
3868                 } else {
3869                         PMD_DRV_LOG(ERR,
3870                                     "Unknown HW assert! (attn 0x%08x)", attn);
3871                 }
3872         }
3873
3874         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3875                 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3876                 if (attn & BNX2X_GRC_TIMEOUT) {
3877                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3878                         PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3879                 }
3880                 if (attn & BNX2X_GRC_RSV) {
3881                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3882                         PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3883                 }
3884                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3885         }
3886 }
3887
3888 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3889 {
3890         int port = SC_PORT(sc);
3891         int reg_offset;
3892         uint32_t val0, mask0, val1, mask1;
3893         uint32_t val;
3894
3895         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3896                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3897                 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3898 /* CFC error attention */
3899                 if (val & 0x2) {
3900                         PMD_DRV_LOG(ERR, "FATAL error from CFC");
3901                 }
3902         }
3903
3904         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3905                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3906                 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3907 /* RQ_USDMDP_FIFO_OVERFLOW */
3908                 if (val & 0x18000) {
3909                         PMD_DRV_LOG(ERR, "FATAL error from PXP");
3910                 }
3911
3912                 if (!CHIP_IS_E1x(sc)) {
3913                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3914                         PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3915                 }
3916         }
3917 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3918 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3919
3920         if (attn & AEU_PXP2_HW_INT_BIT) {
3921 /*  CQ47854 workaround do not panic on
3922  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3923  */
3924                 if (!CHIP_IS_E1x(sc)) {
3925                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3926                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3927                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3928                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3929                         /*
3930                          * If the only PXP2_EOP_ERROR_BIT is set in
3931                          * STS0 and STS1 - clear it
3932                          *
3933                          * probably we lose additional attentions between
3934                          * STS0 and STS_CLR0, in this case user will not
3935                          * be notified about them
3936                          */
3937                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3938                             !(val1 & mask1))
3939                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3940
3941                         /* print the register, since no one can restore it */
3942                         PMD_DRV_LOG(ERR,
3943                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3944
3945                         /*
3946                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3947                          * then notify
3948                          */
3949                         if (val0 & PXP2_EOP_ERROR_BIT) {
3950                                 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3951
3952                                 /*
3953                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3954                                  * set then clear attention from PXP2 block without panic
3955                                  */
3956                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3957                                     ((val1 & mask1) == 0))
3958                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3959                         }
3960                 }
3961         }
3962
3963         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3964                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3965                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3966
3967                 val = REG_RD(sc, reg_offset);
3968                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3969                 REG_WR(sc, reg_offset, val);
3970
3971                 PMD_DRV_LOG(ERR,
3972                             "FATAL HW block attention set2 0x%x",
3973                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3974                 rte_panic("HW block attention set2");
3975         }
3976 }
3977
3978 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3979 {
3980         int port = SC_PORT(sc);
3981         int reg_offset;
3982         uint32_t val;
3983
3984         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3985                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3986                 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3987 /* DORQ discard attention */
3988                 if (val & 0x2) {
3989                         PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3990                 }
3991         }
3992
3993         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3994                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3995                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3996
3997                 val = REG_RD(sc, reg_offset);
3998                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3999                 REG_WR(sc, reg_offset, val);
4000
4001                 PMD_DRV_LOG(ERR,
4002                             "FATAL HW block attention set1 0x%08x",
4003                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4004                 rte_panic("HW block attention set1");
4005         }
4006 }
4007
4008 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4009 {
4010         int port = SC_PORT(sc);
4011         int reg_offset;
4012         uint32_t val;
4013
4014         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4015             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4016
4017         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4018                 val = REG_RD(sc, reg_offset);
4019                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4020                 REG_WR(sc, reg_offset, val);
4021
4022                 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4023
4024 /* Fan failure attention */
4025                 elink_hw_reset_phy(&sc->link_params);
4026                 bnx2x_fan_failure(sc);
4027         }
4028
4029         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4030                 elink_handle_module_detect_int(&sc->link_params);
4031         }
4032
4033         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4034                 val = REG_RD(sc, reg_offset);
4035                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4036                 REG_WR(sc, reg_offset, val);
4037
4038                 rte_panic("FATAL HW block attention set0 0x%lx",
4039                           (attn & HW_INTERRUT_ASSERT_SET_0));
4040         }
4041 }
4042
4043 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4044 {
4045         struct attn_route attn;
4046         struct attn_route *group_mask;
4047         int port = SC_PORT(sc);
4048         int index;
4049         uint32_t reg_addr;
4050         uint32_t val;
4051         uint32_t aeu_mask;
4052         uint8_t global = FALSE;
4053
4054         /*
4055          * Need to take HW lock because MCP or other port might also
4056          * try to handle this event.
4057          */
4058         bnx2x_acquire_alr(sc);
4059
4060         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4061                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4062
4063 /* disable HW interrupts */
4064                 bnx2x_int_disable(sc);
4065                 bnx2x_release_alr(sc);
4066                 return;
4067         }
4068
4069         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4070         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4071         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4072         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4073         if (!CHIP_IS_E1x(sc)) {
4074                 attn.sig[4] =
4075                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4076         } else {
4077                 attn.sig[4] = 0;
4078         }
4079
4080         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4081                 if (deasserted & (1 << index)) {
4082                         group_mask = &sc->attn_group[index];
4083
4084                         bnx2x_attn_int_deasserted4(sc,
4085                                                  attn.
4086                                                  sig[4] & group_mask->sig[4]);
4087                         bnx2x_attn_int_deasserted3(sc,
4088                                                  attn.
4089                                                  sig[3] & group_mask->sig[3]);
4090                         bnx2x_attn_int_deasserted1(sc,
4091                                                  attn.
4092                                                  sig[1] & group_mask->sig[1]);
4093                         bnx2x_attn_int_deasserted2(sc,
4094                                                  attn.
4095                                                  sig[2] & group_mask->sig[2]);
4096                         bnx2x_attn_int_deasserted0(sc,
4097                                                  attn.
4098                                                  sig[0] & group_mask->sig[0]);
4099                 }
4100         }
4101
4102         bnx2x_release_alr(sc);
4103
4104         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4105                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4106                             COMMAND_REG_ATTN_BITS_CLR);
4107         } else {
4108                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4109         }
4110
4111         val = ~deasserted;
4112         PMD_DRV_LOG(DEBUG,
4113                     "about to mask 0x%08x at %s addr 0x%08x", val,
4114                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4115                     reg_addr);
4116         REG_WR(sc, reg_addr, val);
4117
4118         if (~sc->attn_state & deasserted) {
4119                 PMD_DRV_LOG(ERR, "IGU error");
4120         }
4121
4122         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4123             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4124
4125         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4126
4127         aeu_mask = REG_RD(sc, reg_addr);
4128
4129         aeu_mask |= (deasserted & 0x3ff);
4130
4131         REG_WR(sc, reg_addr, aeu_mask);
4132         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4133
4134         sc->attn_state &= ~deasserted;
4135 }
4136
4137 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4138 {
4139         /* read local copy of bits */
4140         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4141         uint32_t attn_ack =
4142             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4143         uint32_t attn_state = sc->attn_state;
4144
4145         /* look for changed bits */
4146         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4147         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4148
4149         PMD_DRV_LOG(DEBUG,
4150                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4151                     attn_bits, attn_ack, asserted, deasserted);
4152
4153         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4154                 PMD_DRV_LOG(ERR, "BAD attention state");
4155         }
4156
4157         /* handle bits that were raised */
4158         if (asserted) {
4159                 bnx2x_attn_int_asserted(sc, asserted);
4160         }
4161
4162         if (deasserted) {
4163                 bnx2x_attn_int_deasserted(sc, deasserted);
4164         }
4165 }
4166
4167 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4168 {
4169         struct host_sp_status_block *def_sb = sc->def_sb;
4170         uint16_t rc = 0;
4171
4172         mb();                   /* status block is written to by the chip */
4173
4174         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4175                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4176                 rc |= BNX2X_DEF_SB_ATT_IDX;
4177         }
4178
4179         if (sc->def_idx != def_sb->sp_sb.running_index) {
4180                 sc->def_idx = def_sb->sp_sb.running_index;
4181                 rc |= BNX2X_DEF_SB_IDX;
4182         }
4183
4184         mb();
4185
4186         return rc;
4187 }
4188
4189 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4190                                                           uint32_t cid)
4191 {
4192         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4193 }
4194
4195 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4196 {
4197         struct ecore_mcast_ramrod_params rparam;
4198         int rc;
4199
4200         memset(&rparam, 0, sizeof(rparam));
4201
4202         rparam.mcast_obj = &sc->mcast_obj;
4203
4204         /* clear pending state for the last command */
4205         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4206
4207         /* if there are pending mcast commands - send them */
4208         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4209                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4210                 if (rc < 0) {
4211                         PMD_DRV_LOG(INFO,
4212                                     "Failed to send pending mcast commands (%d)",
4213                                     rc);
4214                 }
4215         }
4216 }
4217
4218 static void
4219 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4220 {
4221         unsigned long ramrod_flags = 0;
4222         int rc = 0;
4223         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4224         struct ecore_vlan_mac_obj *vlan_mac_obj;
4225
4226         /* always push next commands out, don't wait here */
4227         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4228
4229         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4230         case ECORE_FILTER_MAC_PENDING:
4231                 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4232                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4233                 break;
4234
4235         case ECORE_FILTER_MCAST_PENDING:
4236                 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4237                 bnx2x_handle_mcast_eqe(sc);
4238                 return;
4239
4240         default:
4241                 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4242                             elem->message.data.eth_event.echo);
4243                 return;
4244         }
4245
4246         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4247
4248         if (rc < 0) {
4249                 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4250         } else if (rc > 0) {
4251                 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4252         }
4253 }
4254
4255 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4256 {
4257         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4258
4259         /* send rx_mode command again if was requested */
4260         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4261                 bnx2x_set_storm_rx_mode(sc);
4262         }
4263 }
4264
4265 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4266 {
4267         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4268         wmb();                  /* keep prod updates ordered */
4269 }
4270
4271 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4272 {
4273         uint16_t hw_cons, sw_cons, sw_prod;
4274         union event_ring_elem *elem;
4275         uint8_t echo;
4276         uint32_t cid;
4277         uint8_t opcode;
4278         int spqe_cnt = 0;
4279         struct ecore_queue_sp_obj *q_obj;
4280         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4281         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4282
4283         hw_cons = le16toh(*sc->eq_cons_sb);
4284
4285         /*
4286          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4287          * when we get to the next-page we need to adjust so the loop
4288          * condition below will be met. The next element is the size of a
4289          * regular element and hence incrementing by 1
4290          */
4291         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4292                 hw_cons++;
4293         }
4294
4295         /*
4296          * This function may never run in parallel with itself for a
4297          * specific sc and no need for a read memory barrier here.
4298          */
4299         sw_cons = sc->eq_cons;
4300         sw_prod = sc->eq_prod;
4301
4302         for (;
4303              sw_cons != hw_cons;
4304              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4305
4306                 elem = &sc->eq[EQ_DESC(sw_cons)];
4307
4308 /* elem CID originates from FW, actually LE */
4309                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4310                 opcode = elem->message.opcode;
4311
4312 /* handle eq element */
4313                 switch (opcode) {
4314                 case EVENT_RING_OPCODE_STAT_QUERY:
4315                         PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4316                                     sc->stats_comp++);
4317                         /* nothing to do with stats comp */
4318                         goto next_spqe;
4319
4320                 case EVENT_RING_OPCODE_CFC_DEL:
4321                         /* handle according to cid range */
4322                         /* we may want to verify here that the sc state is HALTING */
4323                         PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4324                                     cid);
4325                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4326                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4327                                 break;
4328                         }
4329                         goto next_spqe;
4330
4331                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4332                         PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4333                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4334                                 break;
4335                         }
4336                         goto next_spqe;
4337
4338                 case EVENT_RING_OPCODE_START_TRAFFIC:
4339                         PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4340                         if (f_obj->complete_cmd
4341                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4342                                 break;
4343                         }
4344                         goto next_spqe;
4345
4346                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4347                         echo = elem->message.data.function_update_event.echo;
4348                         if (echo == SWITCH_UPDATE) {
4349                                 PMD_DRV_LOG(DEBUG,
4350                                             "got FUNC_SWITCH_UPDATE ramrod");
4351                                 if (f_obj->complete_cmd(sc, f_obj,
4352                                                         ECORE_F_CMD_SWITCH_UPDATE))
4353                                 {
4354                                         break;
4355                                 }
4356                         } else {
4357                                 PMD_DRV_LOG(DEBUG,
4358                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4359                                 f_obj->complete_cmd(sc, f_obj,
4360                                                     ECORE_F_CMD_AFEX_UPDATE);
4361                         }
4362                         goto next_spqe;
4363
4364                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4365                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4366                         if (q_obj->complete_cmd(sc, q_obj,
4367                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4368                                 break;
4369                         }
4370                         goto next_spqe;
4371
4372                 case EVENT_RING_OPCODE_FUNCTION_START:
4373                         PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4374                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4375                                 break;
4376                         }
4377                         goto next_spqe;
4378
4379                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4380                         PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4381                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4382                                 break;
4383                         }
4384                         goto next_spqe;
4385                 }
4386
4387                 switch (opcode | sc->state) {
4388                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4389                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4390                         cid =
4391                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4392                         PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4393                                     cid);
4394                         rss_raw->clear_pending(rss_raw);
4395                         break;
4396
4397                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4398                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4399                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4400                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4401                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4402                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4403                         PMD_DRV_LOG(DEBUG,
4404                                     "got (un)set mac ramrod");
4405                         bnx2x_handle_classification_eqe(sc, elem);
4406                         break;
4407
4408                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4409                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4410                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4411                         PMD_DRV_LOG(DEBUG,
4412                                     "got mcast ramrod");
4413                         bnx2x_handle_mcast_eqe(sc);
4414                         break;
4415
4416                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4417                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4418                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4419                         PMD_DRV_LOG(DEBUG,
4420                                     "got rx_mode ramrod");
4421                         bnx2x_handle_rx_mode_eqe(sc);
4422                         break;
4423
4424                 default:
4425                         /* unknown event log error and continue */
4426                         PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4427                                     elem->message.opcode, sc->state);
4428                 }
4429
4430 next_spqe:
4431                 spqe_cnt++;
4432         }                       /* for */
4433
4434         mb();
4435         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4436
4437         sc->eq_cons = sw_cons;
4438         sc->eq_prod = sw_prod;
4439
4440         /* make sure that above mem writes were issued towards the memory */
4441         wmb();
4442
4443         /* update producer */
4444         bnx2x_update_eq_prod(sc, sc->eq_prod);
4445 }
4446
4447 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4448 {
4449         uint16_t status;
4450         int rc = 0;
4451
4452         /* what work needs to be performed? */
4453         status = bnx2x_update_dsb_idx(sc);
4454
4455         /* HW attentions */
4456         if (status & BNX2X_DEF_SB_ATT_IDX) {
4457                 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4458                 bnx2x_attn_int(sc);
4459                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4460                 rc = 1;
4461         }
4462
4463         /* SP events: STAT_QUERY and others */
4464         if (status & BNX2X_DEF_SB_IDX) {
4465 /* handle EQ completions */
4466                 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4467                 bnx2x_eq_int(sc);
4468                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4469                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4470                 status &= ~BNX2X_DEF_SB_IDX;
4471         }
4472
4473         /* if status is non zero then something went wrong */
4474         if (unlikely(status)) {
4475                 PMD_DRV_LOG(INFO,
4476                             "Got an unknown SP interrupt! (0x%04x)", status);
4477         }
4478
4479         /* ack status block only if something was actually handled */
4480         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4481                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4482
4483         return rc;
4484 }
4485
4486 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4487 {
4488         struct bnx2x_softc *sc = fp->sc;
4489         uint8_t more_rx = FALSE;
4490
4491         PMD_DRV_LOG(DEBUG, "---> FP TASK QUEUE (%d) <--", fp->index);
4492
4493         /* update the fastpath index */
4494         bnx2x_update_fp_sb_idx(fp);
4495
4496         if (scan_fp) {
4497                 if (bnx2x_has_rx_work(fp)) {
4498                         more_rx = bnx2x_rxeof(sc, fp);
4499                 }
4500
4501                 if (more_rx) {
4502                         /* still more work to do */
4503                         bnx2x_handle_fp_tq(fp, scan_fp);
4504                         return;
4505                 }
4506         }
4507
4508         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4509                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4510 }
4511
4512 /*
4513  * Legacy interrupt entry point.
4514  *
4515  * Verifies that the controller generated the interrupt and
4516  * then calls a separate routine to handle the various
4517  * interrupt causes: link, RX, and TX.
4518  */
4519 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4520 {
4521         struct bnx2x_fastpath *fp;
4522         uint32_t status, mask;
4523         int i, rc = 0;
4524
4525         /*
4526          * 0 for ustorm, 1 for cstorm
4527          * the bits returned from ack_int() are 0-15
4528          * bit 0 = attention status block
4529          * bit 1 = fast path status block
4530          * a mask of 0x2 or more = tx/rx event
4531          * a mask of 1 = slow path event
4532          */
4533
4534         status = bnx2x_ack_int(sc);
4535
4536         /* the interrupt is not for us */
4537         if (unlikely(status == 0)) {
4538                 return 0;
4539         }
4540
4541         PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4542         //bnx2x_dump_status_block(sc);
4543
4544         FOR_EACH_ETH_QUEUE(sc, i) {
4545                 fp = &sc->fp[i];
4546                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4547                 if (status & mask) {
4548                         bnx2x_handle_fp_tq(fp, scan_fp);
4549                         status &= ~mask;
4550                 }
4551         }
4552
4553         if (unlikely(status & 0x1)) {
4554                 rc = bnx2x_handle_sp_tq(sc);
4555                 status &= ~0x1;
4556         }
4557
4558         if (unlikely(status)) {
4559                 PMD_DRV_LOG(WARNING,
4560                             "Unexpected fastpath status (0x%08x)!", status);
4561         }
4562
4563         return rc;
4564 }
4565
4566 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4567 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4568 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4569 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4570 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4571 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4572 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4573 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4574 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4575
4576 static struct
4577 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4578         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4579         .init_hw_cmn = bnx2x_init_hw_common,
4580         .init_hw_port = bnx2x_init_hw_port,
4581         .init_hw_func = bnx2x_init_hw_func,
4582
4583         .reset_hw_cmn = bnx2x_reset_common,
4584         .reset_hw_port = bnx2x_reset_port,
4585         .reset_hw_func = bnx2x_reset_func,
4586
4587         .init_fw = bnx2x_init_firmware,
4588         .release_fw = bnx2x_release_firmware,
4589 };
4590
4591 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4592 {
4593         sc->dmae_ready = 0;
4594
4595         PMD_INIT_FUNC_TRACE();
4596
4597         ecore_init_func_obj(sc,
4598                             &sc->func_obj,
4599                             BNX2X_SP(sc, func_rdata),
4600                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4601                             BNX2X_SP(sc, func_afex_rdata),
4602                             (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4603                             &bnx2x_func_sp_drv);
4604 }
4605
4606 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4607 {
4608         struct ecore_func_state_params func_params = { NULL };
4609         int rc;
4610
4611         PMD_INIT_FUNC_TRACE();
4612
4613         /* prepare the parameters for function state transitions */
4614         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4615
4616         func_params.f_obj = &sc->func_obj;
4617         func_params.cmd = ECORE_F_CMD_HW_INIT;
4618
4619         func_params.params.hw_init.load_phase = load_code;
4620
4621         /*
4622          * Via a plethora of function pointers, we will eventually reach
4623          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4624          */
4625         rc = ecore_func_state_change(sc, &func_params);
4626
4627         return rc;
4628 }
4629
4630 static void
4631 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4632 {
4633         uint32_t i;
4634
4635         if (!(len % 4) && !(addr % 4)) {
4636                 for (i = 0; i < len; i += 4) {
4637                         REG_WR(sc, (addr + i), fill);
4638                 }
4639         } else {
4640                 for (i = 0; i < len; i++) {
4641                         REG_WR8(sc, (addr + i), fill);
4642                 }
4643         }
4644 }
4645
4646 /* writes FP SP data to FW - data_size in dwords */
4647 static void
4648 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4649                   uint32_t data_size)
4650 {
4651         uint32_t index;
4652
4653         for (index = 0; index < data_size; index++) {
4654                 REG_WR(sc,
4655                        (BAR_CSTRORM_INTMEM +
4656                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4657                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4658         }
4659 }
4660
4661 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4662 {
4663         struct hc_status_block_data_e2 sb_data_e2;
4664         struct hc_status_block_data_e1x sb_data_e1x;
4665         uint32_t *sb_data_p;
4666         uint32_t data_size = 0;
4667
4668         if (!CHIP_IS_E1x(sc)) {
4669                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4670                 sb_data_e2.common.state = SB_DISABLED;
4671                 sb_data_e2.common.p_func.vf_valid = FALSE;
4672                 sb_data_p = (uint32_t *) & sb_data_e2;
4673                 data_size = (sizeof(struct hc_status_block_data_e2) /
4674                              sizeof(uint32_t));
4675         } else {
4676                 memset(&sb_data_e1x, 0,
4677                        sizeof(struct hc_status_block_data_e1x));
4678                 sb_data_e1x.common.state = SB_DISABLED;
4679                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4680                 sb_data_p = (uint32_t *) & sb_data_e1x;
4681                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4682                              sizeof(uint32_t));
4683         }
4684
4685         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4686
4687         bnx2x_fill(sc,
4688                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4689                  CSTORM_STATUS_BLOCK_SIZE);
4690         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4691                  0, CSTORM_SYNC_BLOCK_SIZE);
4692 }
4693
4694 static void
4695 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4696                   struct hc_sp_status_block_data *sp_sb_data)
4697 {
4698         uint32_t i;
4699
4700         for (i = 0;
4701              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4702              i++) {
4703                 REG_WR(sc,
4704                        (BAR_CSTRORM_INTMEM +
4705                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4706                         (i * sizeof(uint32_t))),
4707                        *((uint32_t *) sp_sb_data + i));
4708         }
4709 }
4710
4711 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4712 {
4713         struct hc_sp_status_block_data sp_sb_data;
4714
4715         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4716
4717         sp_sb_data.state = SB_DISABLED;
4718         sp_sb_data.p_func.vf_valid = FALSE;
4719
4720         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4721
4722         bnx2x_fill(sc,
4723                  (BAR_CSTRORM_INTMEM +
4724                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4725                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4726         bnx2x_fill(sc,
4727                  (BAR_CSTRORM_INTMEM +
4728                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4729                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4730 }
4731
4732 static void
4733 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4734                              int igu_seg_id)
4735 {
4736         hc_sm->igu_sb_id = igu_sb_id;
4737         hc_sm->igu_seg_id = igu_seg_id;
4738         hc_sm->timer_value = 0xFF;
4739         hc_sm->time_to_expire = 0xFFFFFFFF;
4740 }
4741
4742 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4743 {
4744         /* zero out state machine indices */
4745
4746         /* rx indices */
4747         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4748
4749         /* tx indices */
4750         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4751         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4752         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4753         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4754
4755         /* map indices */
4756
4757         /* rx indices */
4758         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4759             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4760
4761         /* tx indices */
4762         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4763             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4764         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4765             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4766         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4767             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4768         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4769             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4770 }
4771
4772 static void
4773 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4774             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4775 {
4776         struct hc_status_block_data_e2 sb_data_e2;
4777         struct hc_status_block_data_e1x sb_data_e1x;
4778         struct hc_status_block_sm *hc_sm_p;
4779         uint32_t *sb_data_p;
4780         int igu_seg_id;
4781         int data_size;
4782
4783         if (CHIP_INT_MODE_IS_BC(sc)) {
4784                 igu_seg_id = HC_SEG_ACCESS_NORM;
4785         } else {
4786                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4787         }
4788
4789         bnx2x_zero_fp_sb(sc, fw_sb_id);
4790
4791         if (!CHIP_IS_E1x(sc)) {
4792                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4793                 sb_data_e2.common.state = SB_ENABLED;
4794                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4795                 sb_data_e2.common.p_func.vf_id = vfid;
4796                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4797                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4798                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4799                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4800                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4801                 hc_sm_p = sb_data_e2.common.state_machine;
4802                 sb_data_p = (uint32_t *) & sb_data_e2;
4803                 data_size = (sizeof(struct hc_status_block_data_e2) /
4804                              sizeof(uint32_t));
4805                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4806         } else {
4807                 memset(&sb_data_e1x, 0,
4808                        sizeof(struct hc_status_block_data_e1x));
4809                 sb_data_e1x.common.state = SB_ENABLED;
4810                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4811                 sb_data_e1x.common.p_func.vf_id = 0xff;
4812                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4813                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4814                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4815                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4816                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4817                 hc_sm_p = sb_data_e1x.common.state_machine;
4818                 sb_data_p = (uint32_t *) & sb_data_e1x;
4819                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4820                              sizeof(uint32_t));
4821                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4822         }
4823
4824         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4825         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4826
4827         /* write indices to HW - PCI guarantees endianity of regpairs */
4828         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4829 }
4830
4831 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4832 {
4833         if (CHIP_IS_E1x(fp->sc)) {
4834                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4835         } else {
4836                 return fp->cl_id;
4837         }
4838 }
4839
4840 static uint32_t
4841 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4842 {
4843         uint32_t offset = BAR_USTRORM_INTMEM;
4844
4845         if (IS_VF(sc)) {
4846                 return PXP_VF_ADDR_USDM_QUEUES_START +
4847                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4848                          sizeof(struct ustorm_queue_zone_data));
4849         } else if (!CHIP_IS_E1x(sc)) {
4850                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4851         } else {
4852                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4853         }
4854
4855         return offset;
4856 }
4857
4858 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4859 {
4860         struct bnx2x_fastpath *fp = &sc->fp[idx];
4861         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4862         unsigned long q_type = 0;
4863         int cos;
4864
4865         fp->sc = sc;
4866         fp->index = idx;
4867
4868         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4869         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4870
4871         if (CHIP_IS_E1x(sc))
4872                 fp->cl_id = SC_L_ID(sc) + idx;
4873         else
4874 /* want client ID same as IGU SB ID for non-E1 */
4875                 fp->cl_id = fp->igu_sb_id;
4876         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4877
4878         /* setup sb indices */
4879         if (!CHIP_IS_E1x(sc)) {
4880                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4881                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4882         } else {
4883                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4884                 fp->sb_running_index =
4885                     fp->status_block.e1x_sb->sb.running_index;
4886         }
4887
4888         /* init shortcut */
4889         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4890
4891         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4892
4893         for (cos = 0; cos < sc->max_cos; cos++) {
4894                 cids[cos] = idx;
4895         }
4896         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4897
4898         /* nothing more for a VF to do */
4899         if (IS_VF(sc)) {
4900                 return;
4901         }
4902
4903         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4904                     fp->fw_sb_id, fp->igu_sb_id);
4905
4906         bnx2x_update_fp_sb_idx(fp);
4907
4908         /* Configure Queue State object */
4909         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4910         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4911
4912         ecore_init_queue_obj(sc,
4913                              &sc->sp_objs[idx].q_obj,
4914                              fp->cl_id,
4915                              cids,
4916                              sc->max_cos,
4917                              SC_FUNC(sc),
4918                              BNX2X_SP(sc, q_rdata),
4919                              (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
4920                              q_type);
4921
4922         /* configure classification DBs */
4923         ecore_init_mac_obj(sc,
4924                            &sc->sp_objs[idx].mac_obj,
4925                            fp->cl_id,
4926                            idx,
4927                            SC_FUNC(sc),
4928                            BNX2X_SP(sc, mac_rdata),
4929                            (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4930                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4931                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4932 }
4933
4934 static void
4935 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4936                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4937 {
4938         union ustorm_eth_rx_producers rx_prods;
4939         uint32_t i;
4940
4941         /* update producers */
4942         rx_prods.prod.bd_prod = rx_bd_prod;
4943         rx_prods.prod.cqe_prod = rx_cq_prod;
4944         rx_prods.prod.reserved = 0;
4945
4946         /*
4947          * Make sure that the BD and SGE data is updated before updating the
4948          * producers since FW might read the BD/SGE right after the producer
4949          * is updated.
4950          * This is only applicable for weak-ordered memory model archs such
4951          * as IA-64. The following barrier is also mandatory since FW will
4952          * assumes BDs must have buffers.
4953          */
4954         wmb();
4955
4956         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4957                 REG_WR(sc,
4958                        (fp->ustorm_rx_prods_offset + (i * 4)),
4959                        rx_prods.raw_data[i]);
4960         }
4961
4962         wmb();                  /* keep prod updates ordered */
4963 }
4964
4965 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4966 {
4967         struct bnx2x_fastpath *fp;
4968         int i;
4969         struct bnx2x_rx_queue *rxq;
4970
4971         for (i = 0; i < sc->num_queues; i++) {
4972                 fp = &sc->fp[i];
4973                 rxq = sc->rx_queues[fp->index];
4974                 if (!rxq) {
4975                         PMD_RX_LOG(ERR, "RX queue is NULL");
4976                         return;
4977                 }
4978
4979                 rxq->rx_bd_head = 0;
4980                 rxq->rx_bd_tail = rxq->nb_rx_desc;
4981                 rxq->rx_cq_head = 0;
4982                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4983                 *fp->rx_cq_cons_sb = 0;
4984
4985                 /*
4986                  * Activate the BD ring...
4987                  * Warning, this will generate an interrupt (to the TSTORM)
4988                  * so this can only be done after the chip is initialized
4989                  */
4990                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4991
4992                 if (i != 0) {
4993                         continue;
4994                 }
4995         }
4996 }
4997
4998 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
4999 {
5000         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5001
5002         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5003         fp->tx_db.data.zero_fill1 = 0;
5004         fp->tx_db.data.prod = 0;
5005
5006         if (!txq) {
5007                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5008                 return;
5009         }
5010
5011         txq->tx_pkt_tail = 0;
5012         txq->tx_pkt_head = 0;
5013         txq->tx_bd_tail = 0;
5014         txq->tx_bd_head = 0;
5015 }
5016
5017 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5018 {
5019         int i;
5020
5021         for (i = 0; i < sc->num_queues; i++) {
5022                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5023         }
5024 }
5025
5026 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5027 {
5028         struct host_sp_status_block *def_sb = sc->def_sb;
5029         rte_iova_t mapping = sc->def_sb_dma.paddr;
5030         int igu_sp_sb_index;
5031         int igu_seg_id;
5032         int port = SC_PORT(sc);
5033         int func = SC_FUNC(sc);
5034         int reg_offset, reg_offset_en5;
5035         uint64_t section;
5036         int index, sindex;
5037         struct hc_sp_status_block_data sp_sb_data;
5038
5039         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5040
5041         if (CHIP_INT_MODE_IS_BC(sc)) {
5042                 igu_sp_sb_index = DEF_SB_IGU_ID;
5043                 igu_seg_id = HC_SEG_ACCESS_DEF;
5044         } else {
5045                 igu_sp_sb_index = sc->igu_dsb_id;
5046                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5047         }
5048
5049         /* attentions */
5050         section = ((uint64_t) mapping +
5051                    offsetof(struct host_sp_status_block, atten_status_block));
5052         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5053         sc->attn_state = 0;
5054
5055         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5056             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5057
5058         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5059             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5060
5061         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5062 /* take care of sig[0]..sig[4] */
5063                 for (sindex = 0; sindex < 4; sindex++) {
5064                         sc->attn_group[index].sig[sindex] =
5065                             REG_RD(sc,
5066                                    (reg_offset + (sindex * 0x4) +
5067                                     (0x10 * index)));
5068                 }
5069
5070                 if (!CHIP_IS_E1x(sc)) {
5071                         /*
5072                          * enable5 is separate from the rest of the registers,
5073                          * and the address skip is 4 and not 16 between the
5074                          * different groups
5075                          */
5076                         sc->attn_group[index].sig[4] =
5077                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5078                 } else {
5079                         sc->attn_group[index].sig[4] = 0;
5080                 }
5081         }
5082
5083         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5084                 reg_offset =
5085                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5086                 REG_WR(sc, reg_offset, U64_LO(section));
5087                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5088         } else if (!CHIP_IS_E1x(sc)) {
5089                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5090                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5091         }
5092
5093         section = ((uint64_t) mapping +
5094                    offsetof(struct host_sp_status_block, sp_sb));
5095
5096         bnx2x_zero_sp_sb(sc);
5097
5098         /* PCI guarantees endianity of regpair */
5099         sp_sb_data.state = SB_ENABLED;
5100         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5101         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5102         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5103         sp_sb_data.igu_seg_id = igu_seg_id;
5104         sp_sb_data.p_func.pf_id = func;
5105         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5106         sp_sb_data.p_func.vf_id = 0xff;
5107
5108         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5109
5110         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5111 }
5112
5113 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5114 {
5115         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5116         sc->spq_prod_idx = 0;
5117         sc->dsb_sp_prod =
5118             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5119         sc->spq_prod_bd = sc->spq;
5120         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5121 }
5122
5123 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5124 {
5125         union event_ring_elem *elem;
5126         int i;
5127
5128         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5129                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5130
5131                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5132                                                          BNX2X_PAGE_SIZE *
5133                                                          (i % NUM_EQ_PAGES)));
5134                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5135                                                          BNX2X_PAGE_SIZE *
5136                                                          (i % NUM_EQ_PAGES)));
5137         }
5138
5139         sc->eq_cons = 0;
5140         sc->eq_prod = NUM_EQ_DESC;
5141         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5142
5143         atomic_store_rel_long(&sc->eq_spq_left,
5144                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5145                                    NUM_EQ_DESC) - 1));
5146 }
5147
5148 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5149 {
5150         int i;
5151
5152         if (IS_MF_SI(sc)) {
5153 /*
5154  * In switch independent mode, the TSTORM needs to accept
5155  * packets that failed classification, since approximate match
5156  * mac addresses aren't written to NIG LLH.
5157  */
5158                 REG_WR8(sc,
5159                         (BAR_TSTRORM_INTMEM +
5160                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5161         } else
5162                 REG_WR8(sc,
5163                         (BAR_TSTRORM_INTMEM +
5164                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5165
5166         /*
5167          * Zero this manually as its initialization is currently missing
5168          * in the initTool.
5169          */
5170         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5171                 REG_WR(sc,
5172                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5173                        0);
5174         }
5175
5176         if (!CHIP_IS_E1x(sc)) {
5177                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5178                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5179                         HC_IGU_NBC_MODE);
5180         }
5181 }
5182
5183 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5184 {
5185         switch (load_code) {
5186         case FW_MSG_CODE_DRV_LOAD_COMMON:
5187         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5188                 bnx2x_init_internal_common(sc);
5189                 /* no break */
5190
5191         case FW_MSG_CODE_DRV_LOAD_PORT:
5192                 /* nothing to do */
5193                 /* no break */
5194
5195         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5196                 /* internal memory per function is initialized inside bnx2x_pf_init */
5197                 break;
5198
5199         default:
5200                 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5201                             load_code);
5202                 break;
5203         }
5204 }
5205
5206 static void
5207 storm_memset_func_cfg(struct bnx2x_softc *sc,
5208                       struct tstorm_eth_function_common_config *tcfg,
5209                       uint16_t abs_fid)
5210 {
5211         uint32_t addr;
5212         size_t size;
5213
5214         addr = (BAR_TSTRORM_INTMEM +
5215                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5216         size = sizeof(struct tstorm_eth_function_common_config);
5217         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5218 }
5219
5220 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5221 {
5222         struct tstorm_eth_function_common_config tcfg = { 0 };
5223
5224         if (CHIP_IS_E1x(sc)) {
5225                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5226         }
5227
5228         /* Enable the function in the FW */
5229         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5230         storm_memset_func_en(sc, p->func_id, 1);
5231
5232         /* spq */
5233         if (p->func_flgs & FUNC_FLG_SPQ) {
5234                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5235                 REG_WR(sc,
5236                        (XSEM_REG_FAST_MEMORY +
5237                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5238         }
5239 }
5240
5241 /*
5242  * Calculates the sum of vn_min_rates.
5243  * It's needed for further normalizing of the min_rates.
5244  * Returns:
5245  *   sum of vn_min_rates.
5246  *     or
5247  *   0 - if all the min_rates are 0.
5248  * In the later case fainess algorithm should be deactivated.
5249  * If all min rates are not zero then those that are zeroes will be set to 1.
5250  */
5251 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5252 {
5253         uint32_t vn_cfg;
5254         uint32_t vn_min_rate;
5255         int all_zero = 1;
5256         int vn;
5257
5258         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5259                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5260                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5261                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5262
5263                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5264                         /* skip hidden VNs */
5265                         vn_min_rate = 0;
5266                 } else if (!vn_min_rate) {
5267                         /* If min rate is zero - set it to 100 */
5268                         vn_min_rate = DEF_MIN_RATE;
5269                 } else {
5270                         all_zero = 0;
5271                 }
5272
5273                 input->vnic_min_rate[vn] = vn_min_rate;
5274         }
5275
5276         /* if ETS or all min rates are zeros - disable fairness */
5277         if (all_zero) {
5278                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5279         } else {
5280                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5281         }
5282 }
5283
5284 static uint16_t
5285 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5286 {
5287         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5288                             FUNC_MF_CFG_MAX_BW_SHIFT);
5289
5290         if (!max_cfg) {
5291                 PMD_DRV_LOG(DEBUG,
5292                             "Max BW configured to 0 - using 100 instead");
5293                 max_cfg = 100;
5294         }
5295
5296         return max_cfg;
5297 }
5298
5299 static void
5300 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5301 {
5302         uint16_t vn_max_rate;
5303         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5304         uint32_t max_cfg;
5305
5306         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5307                 vn_max_rate = 0;
5308         } else {
5309                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5310
5311                 if (IS_MF_SI(sc)) {
5312                         /* max_cfg in percents of linkspeed */
5313                         vn_max_rate =
5314                             ((sc->link_vars.line_speed * max_cfg) / 100);
5315                 } else {        /* SD modes */
5316                         /* max_cfg is absolute in 100Mb units */
5317                         vn_max_rate = (max_cfg * 100);
5318                 }
5319         }
5320
5321         input->vnic_max_rate[vn] = vn_max_rate;
5322 }
5323
5324 static void
5325 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5326 {
5327         struct cmng_init_input input;
5328         int vn;
5329
5330         memset(&input, 0, sizeof(struct cmng_init_input));
5331
5332         input.port_rate = sc->link_vars.line_speed;
5333
5334         if (cmng_type == CMNG_FNS_MINMAX) {
5335 /* read mf conf from shmem */
5336                 if (read_cfg) {
5337                         bnx2x_read_mf_cfg(sc);
5338                 }
5339
5340 /* get VN min rate and enable fairness if not 0 */
5341                 bnx2x_calc_vn_min(sc, &input);
5342
5343 /* get VN max rate */
5344                 if (sc->port.pmf) {
5345                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5346                                 bnx2x_calc_vn_max(sc, vn, &input);
5347                         }
5348                 }
5349
5350 /* always enable rate shaping and fairness */
5351                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5352
5353                 ecore_init_cmng(&input, &sc->cmng);
5354                 return;
5355         }
5356 }
5357
5358 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5359 {
5360         if (CHIP_REV_IS_SLOW(sc)) {
5361                 return CMNG_FNS_NONE;
5362         }
5363
5364         if (IS_MF(sc)) {
5365                 return CMNG_FNS_MINMAX;
5366         }
5367
5368         return CMNG_FNS_NONE;
5369 }
5370
5371 static void
5372 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5373 {
5374         int vn;
5375         int func;
5376         uint32_t addr;
5377         size_t size;
5378
5379         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5380         size = sizeof(struct cmng_struct_per_port);
5381         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5382
5383         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5384                 func = func_by_vn(sc, vn);
5385
5386                 addr = (BAR_XSTRORM_INTMEM +
5387                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5388                 size = sizeof(struct rate_shaping_vars_per_vn);
5389                 ecore_storm_memset_struct(sc, addr, size,
5390                                           (uint32_t *) & cmng->
5391                                           vnic.vnic_max_rate[vn]);
5392
5393                 addr = (BAR_XSTRORM_INTMEM +
5394                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5395                 size = sizeof(struct fairness_vars_per_vn);
5396                 ecore_storm_memset_struct(sc, addr, size,
5397                                           (uint32_t *) & cmng->
5398                                           vnic.vnic_min_rate[vn]);
5399         }
5400 }
5401
5402 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5403 {
5404         struct bnx2x_func_init_params func_init;
5405         struct event_ring_data eq_data;
5406         uint16_t flags;
5407
5408         memset(&eq_data, 0, sizeof(struct event_ring_data));
5409         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5410
5411         if (!CHIP_IS_E1x(sc)) {
5412 /* reset IGU PF statistics: MSIX + ATTN */
5413 /* PF */
5414                 REG_WR(sc,
5415                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5416                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5417                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5418                          4)), 0);
5419 /* ATTN */
5420                 REG_WR(sc,
5421                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5422                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5423                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5424                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5425                          4)), 0);
5426         }
5427
5428         /* function setup flags */
5429         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5430
5431         func_init.func_flgs = flags;
5432         func_init.pf_id = SC_FUNC(sc);
5433         func_init.func_id = SC_FUNC(sc);
5434         func_init.spq_map = sc->spq_dma.paddr;
5435         func_init.spq_prod = sc->spq_prod_idx;
5436
5437         bnx2x_func_init(sc, &func_init);
5438
5439         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5440
5441         /*
5442          * Congestion management values depend on the link rate.
5443          * There is no active link so initial link rate is set to 10Gbps.
5444          * When the link comes up the congestion management values are
5445          * re-calculated according to the actual link rate.
5446          */
5447         sc->link_vars.line_speed = SPEED_10000;
5448         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5449
5450         /* Only the PMF sets the HW */
5451         if (sc->port.pmf) {
5452                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5453         }
5454
5455         /* init Event Queue - PCI bus guarantees correct endainity */
5456         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5457         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5458         eq_data.producer = sc->eq_prod;
5459         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5460         eq_data.sb_id = DEF_SB_ID;
5461         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5462 }
5463
5464 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5465 {
5466         int port = SC_PORT(sc);
5467         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5468         uint32_t val = REG_RD(sc, addr);
5469         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5470             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5471         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5472         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5473
5474         if (msix) {
5475                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5476                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5477                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5478                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5479                 if (single_msix) {
5480                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5481                 }
5482         } else if (msi) {
5483                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5484                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5485                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5486                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5487         } else {
5488                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5489                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5490                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5491                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5492
5493                 REG_WR(sc, addr, val);
5494
5495                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5496         }
5497
5498         REG_WR(sc, addr, val);
5499
5500         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5501         mb();
5502
5503         /* init leading/trailing edge */
5504         if (IS_MF(sc)) {
5505                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5506                 if (sc->port.pmf) {
5507                         /* enable nig and gpio3 attention */
5508                         val |= 0x1100;
5509                 }
5510         } else {
5511                 val = 0xffff;
5512         }
5513
5514         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5515         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5516
5517         /* make sure that interrupts are indeed enabled from here on */
5518         mb();
5519 }
5520
5521 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5522 {
5523         uint32_t val;
5524         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5525             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5526         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5527         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5528
5529         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5530
5531         if (msix) {
5532                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5533                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5534                 if (single_msix) {
5535                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5536                 }
5537         } else if (msi) {
5538                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5539                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5540                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5541         } else {
5542                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5543                 val |= (IGU_PF_CONF_INT_LINE_EN |
5544                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5545         }
5546
5547         /* clean previous status - need to configure igu prior to ack */
5548         if ((!msix) || single_msix) {
5549                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5550                 bnx2x_ack_int(sc);
5551         }
5552
5553         val |= IGU_PF_CONF_FUNC_EN;
5554
5555         PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5556                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5557
5558         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5559
5560         mb();
5561
5562         /* init leading/trailing edge */
5563         if (IS_MF(sc)) {
5564                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5565                 if (sc->port.pmf) {
5566                         /* enable nig and gpio3 attention */
5567                         val |= 0x1100;
5568                 }
5569         } else {
5570                 val = 0xffff;
5571         }
5572
5573         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5574         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5575
5576         /* make sure that interrupts are indeed enabled from here on */
5577         mb();
5578 }
5579
5580 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5581 {
5582         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5583                 bnx2x_hc_int_enable(sc);
5584         } else {
5585                 bnx2x_igu_int_enable(sc);
5586         }
5587 }
5588
5589 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5590 {
5591         int port = SC_PORT(sc);
5592         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5593         uint32_t val = REG_RD(sc, addr);
5594
5595         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5596                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5597                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5598         /* flush all outstanding writes */
5599         mb();
5600
5601         REG_WR(sc, addr, val);
5602         if (REG_RD(sc, addr) != val) {
5603                 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5604         }
5605 }
5606
5607 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5608 {
5609         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5610
5611         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5612                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5613
5614         PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5615
5616         /* flush all outstanding writes */
5617         mb();
5618
5619         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5620         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5621                 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5622         }
5623 }
5624
5625 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5626 {
5627         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5628                 bnx2x_hc_int_disable(sc);
5629         } else {
5630                 bnx2x_igu_int_disable(sc);
5631         }
5632 }
5633
5634 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5635 {
5636         int i;
5637
5638         PMD_INIT_FUNC_TRACE();
5639
5640         for (i = 0; i < sc->num_queues; i++) {
5641                 bnx2x_init_eth_fp(sc, i);
5642         }
5643
5644         rmb();                  /* ensure status block indices were read */
5645
5646         bnx2x_init_rx_rings(sc);
5647         bnx2x_init_tx_rings(sc);
5648
5649         if (IS_VF(sc)) {
5650                 bnx2x_memset_stats(sc);
5651                 return;
5652         }
5653
5654         /* initialize MOD_ABS interrupts */
5655         elink_init_mod_abs_int(sc, &sc->link_vars,
5656                                sc->devinfo.chip_id,
5657                                sc->devinfo.shmem_base,
5658                                sc->devinfo.shmem2_base, SC_PORT(sc));
5659
5660         bnx2x_init_def_sb(sc);
5661         bnx2x_update_dsb_idx(sc);
5662         bnx2x_init_sp_ring(sc);
5663         bnx2x_init_eq_ring(sc);
5664         bnx2x_init_internal(sc, load_code);
5665         bnx2x_pf_init(sc);
5666         bnx2x_stats_init(sc);
5667
5668         /* flush all before enabling interrupts */
5669         mb();
5670
5671         bnx2x_int_enable(sc);
5672
5673         /* check for SPIO5 */
5674         bnx2x_attn_int_deasserted0(sc,
5675                                  REG_RD(sc,
5676                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5677                                          SC_PORT(sc) * 4)) &
5678                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5679 }
5680
5681 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5682 {
5683         /* mcast rules must be added to tx if tx switching is enabled */
5684         ecore_obj_type o_type;
5685         if (sc->flags & BNX2X_TX_SWITCHING)
5686                 o_type = ECORE_OBJ_TYPE_RX_TX;
5687         else
5688                 o_type = ECORE_OBJ_TYPE_RX;
5689
5690         /* RX_MODE controlling object */
5691         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5692
5693         /* multicast configuration controlling object */
5694         ecore_init_mcast_obj(sc,
5695                              &sc->mcast_obj,
5696                              sc->fp[0].cl_id,
5697                              sc->fp[0].index,
5698                              SC_FUNC(sc),
5699                              SC_FUNC(sc),
5700                              BNX2X_SP(sc, mcast_rdata),
5701                              (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5702                              ECORE_FILTER_MCAST_PENDING,
5703                              &sc->sp_state, o_type);
5704
5705         /* Setup CAM credit pools */
5706         ecore_init_mac_credit_pool(sc,
5707                                    &sc->macs_pool,
5708                                    SC_FUNC(sc),
5709                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5710                                    VNICS_PER_PATH(sc));
5711
5712         ecore_init_vlan_credit_pool(sc,
5713                                     &sc->vlans_pool,
5714                                     SC_ABS_FUNC(sc) >> 1,
5715                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5716                                     VNICS_PER_PATH(sc));
5717
5718         /* RSS configuration object */
5719         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5720                                   sc->fp[0].cl_id,
5721                                   sc->fp[0].index,
5722                                   SC_FUNC(sc),
5723                                   SC_FUNC(sc),
5724                                   BNX2X_SP(sc, rss_rdata),
5725                                   (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5726                                   ECORE_FILTER_RSS_CONF_PENDING,
5727                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5728 }
5729
5730 /*
5731  * Initialize the function. This must be called before sending CLIENT_SETUP
5732  * for the first client.
5733  */
5734 static int bnx2x_func_start(struct bnx2x_softc *sc)
5735 {
5736         struct ecore_func_state_params func_params = { NULL };
5737         struct ecore_func_start_params *start_params =
5738             &func_params.params.start;
5739
5740         /* Prepare parameters for function state transitions */
5741         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5742
5743         func_params.f_obj = &sc->func_obj;
5744         func_params.cmd = ECORE_F_CMD_START;
5745
5746         /* Function parameters */
5747         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5748         start_params->sd_vlan_tag = OVLAN(sc);
5749
5750         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5751                 start_params->network_cos_mode = STATIC_COS;
5752         } else {                /* CHIP_IS_E1X */
5753                 start_params->network_cos_mode = FW_WRR;
5754         }
5755
5756         start_params->gre_tunnel_mode = 0;
5757         start_params->gre_tunnel_rss = 0;
5758
5759         return ecore_func_state_change(sc, &func_params);
5760 }
5761
5762 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5763 {
5764         uint16_t pmcsr;
5765
5766         /* If there is no power capability, silently succeed */
5767         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5768                 PMD_DRV_LOG(WARNING, "No power capability");
5769                 return 0;
5770         }
5771
5772         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5773                  2);
5774
5775         switch (state) {
5776         case PCI_PM_D0:
5777                 pci_write_word(sc,
5778                                (sc->devinfo.pcie_pm_cap_reg +
5779                                 PCIR_POWER_STATUS),
5780                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5781
5782                 if (pmcsr & PCIM_PSTAT_DMASK) {
5783                         /* delay required during transition out of D3hot */
5784                         DELAY(20000);
5785                 }
5786
5787                 break;
5788
5789         case PCI_PM_D3hot:
5790                 /* don't shut down the power for emulation and FPGA */
5791                 if (CHIP_REV_IS_SLOW(sc)) {
5792                         return 0;
5793                 }
5794
5795                 pmcsr &= ~PCIM_PSTAT_DMASK;
5796                 pmcsr |= PCIM_PSTAT_D3;
5797
5798                 if (sc->wol) {
5799                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5800                 }
5801
5802                 pci_write_long(sc,
5803                                (sc->devinfo.pcie_pm_cap_reg +
5804                                 PCIR_POWER_STATUS), pmcsr);
5805
5806                 /*
5807                  * No more memory access after this point until device is brought back
5808                  * to D0 state.
5809                  */
5810                 break;
5811
5812         default:
5813                 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5814                             state);
5815                 return -1;
5816         }
5817
5818         return 0;
5819 }
5820
5821 /* return true if succeeded to acquire the lock */
5822 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5823 {
5824         uint32_t lock_status;
5825         uint32_t resource_bit = (1 << resource);
5826         int func = SC_FUNC(sc);
5827         uint32_t hw_lock_control_reg;
5828
5829         /* Validating that the resource is within range */
5830         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5831                 PMD_DRV_LOG(INFO,
5832                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5833                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5834                 return FALSE;
5835         }
5836
5837         if (func <= 5) {
5838                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5839         } else {
5840                 hw_lock_control_reg =
5841                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5842         }
5843
5844         /* try to acquire the lock */
5845         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5846         lock_status = REG_RD(sc, hw_lock_control_reg);
5847         if (lock_status & resource_bit) {
5848                 return TRUE;
5849         }
5850
5851         PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5852
5853         return FALSE;
5854 }
5855
5856 /*
5857  * Get the recovery leader resource id according to the engine this function
5858  * belongs to. Currently only only 2 engines is supported.
5859  */
5860 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5861 {
5862         if (SC_PATH(sc)) {
5863                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5864         } else {
5865                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5866         }
5867 }
5868
5869 /* try to acquire a leader lock for current engine */
5870 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5871 {
5872         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5873 }
5874
5875 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5876 {
5877         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5878 }
5879
5880 /* close gates #2, #3 and #4 */
5881 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5882 {
5883         uint32_t val;
5884
5885         /* gates #2 and #4a are closed/opened */
5886         /* #4 */
5887         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5888         /* #2 */
5889         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5890
5891         /* #3 */
5892         if (CHIP_IS_E1x(sc)) {
5893 /* prevent interrupts from HC on both ports */
5894                 val = REG_RD(sc, HC_REG_CONFIG_1);
5895                 if (close)
5896                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5897                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5898                 else
5899                         REG_WR(sc, HC_REG_CONFIG_1,
5900                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5901
5902                 val = REG_RD(sc, HC_REG_CONFIG_0);
5903                 if (close)
5904                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5905                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5906                 else
5907                         REG_WR(sc, HC_REG_CONFIG_0,
5908                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5909
5910         } else {
5911 /* Prevent incoming interrupts in IGU */
5912                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5913
5914                 if (close)
5915                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5916                                (val & ~(uint32_t)
5917                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5918                 else
5919                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5920                                (val |
5921                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5922         }
5923
5924         wmb();
5925 }
5926
5927 /* poll for pending writes bit, it should get cleared in no more than 1s */
5928 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5929 {
5930         uint32_t cnt = 1000;
5931         uint32_t pend_bits = 0;
5932
5933         do {
5934                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5935
5936                 if (pend_bits == 0) {
5937                         break;
5938                 }
5939
5940                 DELAY(1000);
5941         } while (cnt-- > 0);
5942
5943         if (cnt <= 0) {
5944                 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5945                             pend_bits);
5946                 return -1;
5947         }
5948
5949         return 0;
5950 }
5951
5952 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5953
5954 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5955 {
5956         /* Do some magic... */
5957         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5958         *magic_val = val & SHARED_MF_CLP_MAGIC;
5959         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5960 }
5961
5962 /* restore the value of the 'magic' bit */
5963 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5964 {
5965         /* Restore the 'magic' bit value... */
5966         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5967         MFCFG_WR(sc, shared_mf_config.clp_mb,
5968                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5969 }
5970
5971 /* prepare for MCP reset, takes care of CLP configurations */
5972 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5973 {
5974         uint32_t shmem;
5975         uint32_t validity_offset;
5976
5977         /* set `magic' bit in order to save MF config */
5978         bnx2x_clp_reset_prep(sc, magic_val);
5979
5980         /* get shmem offset */
5981         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5982         validity_offset =
5983             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5984
5985         /* Clear validity map flags */
5986         if (shmem > 0) {
5987                 REG_WR(sc, shmem + validity_offset, 0);
5988         }
5989 }
5990
5991 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
5992 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
5993
5994 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5995 {
5996         /* special handling for emulation and FPGA (10 times longer) */
5997         if (CHIP_REV_IS_SLOW(sc)) {
5998                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
5999         } else {
6000                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6001         }
6002 }
6003
6004 /* initialize shmem_base and waits for validity signature to appear */
6005 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6006 {
6007         int cnt = 0;
6008         uint32_t val = 0;
6009
6010         do {
6011                 sc->devinfo.shmem_base =
6012                     sc->link_params.shmem_base =
6013                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6014
6015                 if (sc->devinfo.shmem_base) {
6016                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6017                         if (val & SHR_MEM_VALIDITY_MB)
6018                                 return 0;
6019                 }
6020
6021                 bnx2x_mcp_wait_one(sc);
6022
6023         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6024
6025         PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6026
6027         return -1;
6028 }
6029
6030 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6031 {
6032         int rc = bnx2x_init_shmem(sc);
6033
6034         /* Restore the `magic' bit value */
6035         bnx2x_clp_reset_done(sc, magic_val);
6036
6037         return rc;
6038 }
6039
6040 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6041 {
6042         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6043         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6044         wmb();
6045 }
6046
6047 /*
6048  * Reset the whole chip except for:
6049  *      - PCIE core
6050  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6051  *      - IGU
6052  *      - MISC (including AEU)
6053  *      - GRC
6054  *      - RBCN, RBCP
6055  */
6056 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6057 {
6058         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6059         uint32_t global_bits2, stay_reset2;
6060
6061         /*
6062          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6063          * (per chip) blocks.
6064          */
6065         global_bits2 =
6066             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6067             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6068
6069         /*
6070          * Don't reset the following blocks.
6071          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6072          *            reset, as in 4 port device they might still be owned
6073          *            by the MCP (there is only one leader per path).
6074          */
6075         not_reset_mask1 =
6076             MISC_REGISTERS_RESET_REG_1_RST_HC |
6077             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6078             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6079
6080         not_reset_mask2 =
6081             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6082             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6083             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6084             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6085             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6086             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6087             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6088             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6089             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6090             MISC_REGISTERS_RESET_REG_2_PGLC |
6091             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6092             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6093             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6094             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6095             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6096
6097         /*
6098          * Keep the following blocks in reset:
6099          *  - all xxMACs are handled by the elink code.
6100          */
6101         stay_reset2 =
6102             MISC_REGISTERS_RESET_REG_2_XMAC |
6103             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6104
6105         /* Full reset masks according to the chip */
6106         reset_mask1 = 0xffffffff;
6107
6108         if (CHIP_IS_E1H(sc))
6109                 reset_mask2 = 0x1ffff;
6110         else if (CHIP_IS_E2(sc))
6111                 reset_mask2 = 0xfffff;
6112         else                    /* CHIP_IS_E3 */
6113                 reset_mask2 = 0x3ffffff;
6114
6115         /* Don't reset global blocks unless we need to */
6116         if (!global)
6117                 reset_mask2 &= ~global_bits2;
6118
6119         /*
6120          * In case of attention in the QM, we need to reset PXP
6121          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6122          * because otherwise QM reset would release 'close the gates' shortly
6123          * before resetting the PXP, then the PSWRQ would send a write
6124          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6125          * read the payload data from PSWWR, but PSWWR would not
6126          * respond. The write queue in PGLUE would stuck, dmae commands
6127          * would not return. Therefore it's important to reset the second
6128          * reset register (containing the
6129          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6130          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6131          * bit).
6132          */
6133         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6134                reset_mask2 & (~not_reset_mask2));
6135
6136         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6137                reset_mask1 & (~not_reset_mask1));
6138
6139         mb();
6140         wmb();
6141
6142         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6143                reset_mask2 & (~stay_reset2));
6144
6145         mb();
6146         wmb();
6147
6148         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6149         wmb();
6150 }
6151
6152 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6153 {
6154         int cnt = 1000;
6155         uint32_t val = 0;
6156         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6157         uint32_t tags_63_32 = 0;
6158
6159         /* Empty the Tetris buffer, wait for 1s */
6160         do {
6161                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6162                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6163                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6164                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6165                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6166                 if (CHIP_IS_E3(sc)) {
6167                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6168                 }
6169
6170                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6171                     ((port_is_idle_0 & 0x1) == 0x1) &&
6172                     ((port_is_idle_1 & 0x1) == 0x1) &&
6173                     (pgl_exp_rom2 == 0xffffffff) &&
6174                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6175                         break;
6176                 DELAY(1000);
6177         } while (cnt-- > 0);
6178
6179         if (cnt <= 0) {
6180                 PMD_DRV_LOG(NOTICE,
6181                             "ERROR: Tetris buffer didn't get empty or there "
6182                             "are still outstanding read requests after 1s! "
6183                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6184                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6185                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6186                             pgl_exp_rom2);
6187                 return -1;
6188         }
6189
6190         mb();
6191
6192         /* Close gates #2, #3 and #4 */
6193         bnx2x_set_234_gates(sc, TRUE);
6194
6195         /* Poll for IGU VQs for 57712 and newer chips */
6196         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6197                 return -1;
6198         }
6199
6200         /* clear "unprepared" bit */
6201         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6202         mb();
6203
6204         /* Make sure all is written to the chip before the reset */
6205         wmb();
6206
6207         /*
6208          * Wait for 1ms to empty GLUE and PCI-E core queues,
6209          * PSWHST, GRC and PSWRD Tetris buffer.
6210          */
6211         DELAY(1000);
6212
6213         /* Prepare to chip reset: */
6214         /* MCP */
6215         if (global) {
6216                 bnx2x_reset_mcp_prep(sc, &val);
6217         }
6218
6219         /* PXP */
6220         bnx2x_pxp_prep(sc);
6221         mb();
6222
6223         /* reset the chip */
6224         bnx2x_process_kill_chip_reset(sc, global);
6225         mb();
6226
6227         /* Recover after reset: */
6228         /* MCP */
6229         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6230                 return -1;
6231         }
6232
6233         /* Open the gates #2, #3 and #4 */
6234         bnx2x_set_234_gates(sc, FALSE);
6235
6236         return 0;
6237 }
6238
6239 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6240 {
6241         int rc = 0;
6242         uint8_t global = bnx2x_reset_is_global(sc);
6243         uint32_t load_code;
6244
6245         /*
6246          * If not going to reset MCP, load "fake" driver to reset HW while
6247          * driver is owner of the HW.
6248          */
6249         if (!global && !BNX2X_NOMCP(sc)) {
6250                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6251                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6252                 if (!load_code) {
6253                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6254                         rc = -1;
6255                         goto exit_leader_reset;
6256                 }
6257
6258                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6259                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6260                         PMD_DRV_LOG(NOTICE,
6261                                     "MCP unexpected response, aborting");
6262                         rc = -1;
6263                         goto exit_leader_reset2;
6264                 }
6265
6266                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6267                 if (!load_code) {
6268                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6269                         rc = -1;
6270                         goto exit_leader_reset2;
6271                 }
6272         }
6273
6274         /* try to recover after the failure */
6275         if (bnx2x_process_kill(sc, global)) {
6276                 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6277                             SC_PATH(sc));
6278                 rc = -1;
6279                 goto exit_leader_reset2;
6280         }
6281
6282         /*
6283          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6284          * state.
6285          */
6286         bnx2x_set_reset_done(sc);
6287         if (global) {
6288                 bnx2x_clear_reset_global(sc);
6289         }
6290
6291 exit_leader_reset2:
6292
6293         /* unload "fake driver" if it was loaded */
6294         if (!global &&!BNX2X_NOMCP(sc)) {
6295                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6296                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6297         }
6298
6299 exit_leader_reset:
6300
6301         sc->is_leader = 0;
6302         bnx2x_release_leader_lock(sc);
6303
6304         mb();
6305         return rc;
6306 }
6307
6308 /*
6309  * prepare INIT transition, parameters configured:
6310  *   - HC configuration
6311  *   - Queue's CDU context
6312  */
6313 static void
6314 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6315                    struct ecore_queue_init_params *init_params)
6316 {
6317         uint8_t cos;
6318         int cxt_index, cxt_offset;
6319
6320         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6321         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6322
6323         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6324         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6325
6326         /* HC rate */
6327         init_params->rx.hc_rate =
6328             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6329         init_params->tx.hc_rate =
6330             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6331
6332         /* FW SB ID */
6333         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6334
6335         /* CQ index among the SB indices */
6336         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6337         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6338
6339         /* set maximum number of COSs supported by this queue */
6340         init_params->max_cos = sc->max_cos;
6341
6342         /* set the context pointers queue object */
6343         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6344                 cxt_index = fp->index / ILT_PAGE_CIDS;
6345                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6346                 init_params->cxts[cos] =
6347                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6348         }
6349 }
6350
6351 /* set flags that are common for the Tx-only and not normal connections */
6352 static unsigned long
6353 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6354 {
6355         unsigned long flags = 0;
6356
6357         /* PF driver will always initialize the Queue to an ACTIVE state */
6358         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6359
6360         /*
6361          * tx only connections collect statistics (on the same index as the
6362          * parent connection). The statistics are zeroed when the parent
6363          * connection is initialized.
6364          */
6365
6366         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6367         if (zero_stats) {
6368                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6369         }
6370
6371         /*
6372          * tx only connections can support tx-switching, though their
6373          * CoS-ness doesn't survive the loopback
6374          */
6375         if (sc->flags & BNX2X_TX_SWITCHING) {
6376                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6377         }
6378
6379         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6380
6381         return flags;
6382 }
6383
6384 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6385 {
6386         unsigned long flags = 0;
6387
6388         if (IS_MF_SD(sc)) {
6389                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6390         }
6391
6392         if (leading) {
6393                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6394                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6395         }
6396
6397         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6398
6399         /* merge with common flags */
6400         return flags | bnx2x_get_common_flags(sc, TRUE);
6401 }
6402
6403 static void
6404 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6405                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6406 {
6407         gen_init->stat_id = bnx2x_stats_id(fp);
6408         gen_init->spcl_id = fp->cl_id;
6409         gen_init->mtu = sc->mtu;
6410         gen_init->cos = cos;
6411 }
6412
6413 static void
6414 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6415                  struct rxq_pause_params *pause,
6416                  struct ecore_rxq_setup_params *rxq_init)
6417 {
6418         struct bnx2x_rx_queue *rxq;
6419
6420         rxq = sc->rx_queues[fp->index];
6421         if (!rxq) {
6422                 PMD_RX_LOG(ERR, "RX queue is NULL");
6423                 return;
6424         }
6425         /* pause */
6426         pause->bd_th_lo = BD_TH_LO(sc);
6427         pause->bd_th_hi = BD_TH_HI(sc);
6428
6429         pause->rcq_th_lo = RCQ_TH_LO(sc);
6430         pause->rcq_th_hi = RCQ_TH_HI(sc);
6431
6432         /* validate rings have enough entries to cross high thresholds */
6433         if (sc->dropless_fc &&
6434             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6435                 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6436         }
6437
6438         if (sc->dropless_fc &&
6439             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6440                 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6441         }
6442
6443         pause->pri_map = 1;
6444
6445         /* rxq setup */
6446         rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6447         rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6448         rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6449                                               BNX2X_PAGE_SIZE);
6450
6451         /*
6452          * This should be a maximum number of data bytes that may be
6453          * placed on the BD (not including paddings).
6454          */
6455         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6456
6457         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6458         rxq_init->rss_engine_id = SC_FUNC(sc);
6459         rxq_init->mcast_engine_id = SC_FUNC(sc);
6460
6461         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6462         rxq_init->fw_sb_id = fp->fw_sb_id;
6463
6464         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6465
6466         /*
6467          * configure silent vlan removal
6468          * if multi function mode is afex, then mask default vlan
6469          */
6470         if (IS_MF_AFEX(sc)) {
6471                 rxq_init->silent_removal_value =
6472                     sc->devinfo.mf_info.afex_def_vlan_tag;
6473                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6474         }
6475 }
6476
6477 static void
6478 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6479                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6480 {
6481         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6482
6483         if (!txq) {
6484                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6485                 return;
6486         }
6487         txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6488         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6489         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6490         txq_init->fw_sb_id = fp->fw_sb_id;
6491
6492         /*
6493          * set the TSS leading client id for TX classfication to the
6494          * leading RSS client id
6495          */
6496         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6497 }
6498
6499 /*
6500  * This function performs 2 steps in a queue state machine:
6501  *   1) RESET->INIT
6502  *   2) INIT->SETUP
6503  */
6504 static int
6505 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6506 {
6507         struct ecore_queue_state_params q_params = { NULL };
6508         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6509         int rc;
6510
6511         PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6512
6513         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6514
6515         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6516
6517         /* we want to wait for completion in this context */
6518         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6519
6520         /* prepare the INIT parameters */
6521         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6522
6523         /* Set the command */
6524         q_params.cmd = ECORE_Q_CMD_INIT;
6525
6526         /* Change the state to INIT */
6527         rc = ecore_queue_state_change(sc, &q_params);
6528         if (rc) {
6529                 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6530                 return rc;
6531         }
6532
6533         PMD_DRV_LOG(DEBUG, "init complete");
6534
6535         /* now move the Queue to the SETUP state */
6536         memset(setup_params, 0, sizeof(*setup_params));
6537
6538         /* set Queue flags */
6539         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6540
6541         /* set general SETUP parameters */
6542         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6543                               FIRST_TX_COS_INDEX);
6544
6545         bnx2x_pf_rx_q_prep(sc, fp,
6546                          &setup_params->pause_params,
6547                          &setup_params->rxq_params);
6548
6549         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6550
6551         /* Set the command */
6552         q_params.cmd = ECORE_Q_CMD_SETUP;
6553
6554         /* change the state to SETUP */
6555         rc = ecore_queue_state_change(sc, &q_params);
6556         if (rc) {
6557                 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6558                 return rc;
6559         }
6560
6561         return rc;
6562 }
6563
6564 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6565 {
6566         if (IS_PF(sc))
6567                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6568         else                    /* VF */
6569                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6570 }
6571
6572 static int
6573 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6574                   uint8_t config_hash)
6575 {
6576         struct ecore_config_rss_params params = { NULL };
6577         uint32_t i;
6578
6579         /*
6580          * Although RSS is meaningless when there is a single HW queue we
6581          * still need it enabled in order to have HW Rx hash generated.
6582          */
6583
6584         params.rss_obj = rss_obj;
6585
6586         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6587
6588         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6589
6590         /* RSS configuration */
6591         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6592         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6593         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6594         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6595         if (rss_obj->udp_rss_v4) {
6596                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6597         }
6598         if (rss_obj->udp_rss_v6) {
6599                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6600         }
6601
6602         /* Hash bits */
6603         params.rss_result_mask = MULTI_MASK;
6604
6605         rte_memcpy(params.ind_table, rss_obj->ind_table,
6606                          sizeof(params.ind_table));
6607
6608         if (config_hash) {
6609 /* RSS keys */
6610                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6611                         params.rss_key[i] = (uint32_t) rte_rand();
6612                 }
6613
6614                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6615         }
6616
6617         if (IS_PF(sc))
6618                 return ecore_config_rss(sc, &params);
6619         else
6620                 return bnx2x_vf_config_rss(sc, &params);
6621 }
6622
6623 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6624 {
6625         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6626 }
6627
6628 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6629 {
6630         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6631         uint32_t i;
6632
6633         /*
6634          * Prepare the initial contents of the indirection table if
6635          * RSS is enabled
6636          */
6637         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6638                 sc->rss_conf_obj.ind_table[i] =
6639                     (sc->fp->cl_id + (i % num_eth_queues));
6640         }
6641
6642         if (sc->udp_rss) {
6643                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6644         }
6645
6646         /*
6647          * For 57711 SEARCHER configuration (rss_keys) is
6648          * per-port, so if explicit configuration is needed, do it only
6649          * for a PMF.
6650          *
6651          * For 57712 and newer it's a per-function configuration.
6652          */
6653         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6654 }
6655
6656 static int
6657 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6658                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6659                 unsigned long *ramrod_flags)
6660 {
6661         struct ecore_vlan_mac_ramrod_params ramrod_param;
6662         int rc;
6663
6664         memset(&ramrod_param, 0, sizeof(ramrod_param));
6665
6666         /* fill in general parameters */
6667         ramrod_param.vlan_mac_obj = obj;
6668         ramrod_param.ramrod_flags = *ramrod_flags;
6669
6670         /* fill a user request section if needed */
6671         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6672                 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6673                                  ETH_ALEN);
6674
6675                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6676
6677 /* Set the command: ADD or DEL */
6678                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6679                     ECORE_VLAN_MAC_DEL;
6680         }
6681
6682         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6683
6684         if (rc == ECORE_EXISTS) {
6685                 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6686 /* do not treat adding same MAC as error */
6687                 rc = 0;
6688         } else if (rc < 0) {
6689                 PMD_DRV_LOG(ERR,
6690                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6691         }
6692
6693         return rc;
6694 }
6695
6696 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6697 {
6698         unsigned long ramrod_flags = 0;
6699
6700         PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6701
6702         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6703
6704         /* Eth MAC is set on RSS leading client (fp[0]) */
6705         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6706                                &sc->sp_objs->mac_obj,
6707                                set, ECORE_ETH_MAC, &ramrod_flags);
6708 }
6709
6710 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6711 {
6712         uint32_t sel_phy_idx = 0;
6713
6714         if (sc->link_params.num_phys <= 1) {
6715                 return ELINK_INT_PHY;
6716         }
6717
6718         if (sc->link_vars.link_up) {
6719                 sel_phy_idx = ELINK_EXT_PHY1;
6720 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6721                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6722                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6723                      ELINK_SUPPORTED_FIBRE))
6724                         sel_phy_idx = ELINK_EXT_PHY2;
6725         } else {
6726                 switch (elink_phy_selection(&sc->link_params)) {
6727                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6728                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6729                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6730                         sel_phy_idx = ELINK_EXT_PHY1;
6731                         break;
6732                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6733                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6734                         sel_phy_idx = ELINK_EXT_PHY2;
6735                         break;
6736                 }
6737         }
6738
6739         return sel_phy_idx;
6740 }
6741
6742 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6743 {
6744         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6745
6746         /*
6747          * The selected activated PHY is always after swapping (in case PHY
6748          * swapping is enabled). So when swapping is enabled, we need to reverse
6749          * the configuration
6750          */
6751
6752         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6753                 if (sel_phy_idx == ELINK_EXT_PHY1)
6754                         sel_phy_idx = ELINK_EXT_PHY2;
6755                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6756                         sel_phy_idx = ELINK_EXT_PHY1;
6757         }
6758
6759         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6760 }
6761
6762 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6763 {
6764         /*
6765          * Initialize link parameters structure variables
6766          * It is recommended to turn off RX FC for jumbo frames
6767          * for better performance
6768          */
6769         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6770                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6771         } else {
6772                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6773         }
6774 }
6775
6776 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6777 {
6778         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6779         switch (sc->link_vars.ieee_fc &
6780                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6781         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6782         default:
6783                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6784                                                    ADVERTISED_Pause);
6785                 break;
6786
6787         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6788                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6789                                                   ADVERTISED_Pause);
6790                 break;
6791
6792         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6793                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6794                 break;
6795         }
6796 }
6797
6798 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6799 {
6800         uint16_t line_speed = sc->link_vars.line_speed;
6801         if (IS_MF(sc)) {
6802                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6803                                                       sc->devinfo.
6804                                                       mf_info.mf_config[SC_VN
6805                                                                         (sc)]);
6806
6807 /* calculate the current MAX line speed limit for the MF devices */
6808                 if (IS_MF_SI(sc)) {
6809                         line_speed = (line_speed * maxCfg) / 100;
6810                 } else {        /* SD mode */
6811                         uint16_t vn_max_rate = maxCfg * 100;
6812
6813                         if (vn_max_rate < line_speed) {
6814                                 line_speed = vn_max_rate;
6815                         }
6816                 }
6817         }
6818
6819         return line_speed;
6820 }
6821
6822 static void
6823 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6824 {
6825         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6826
6827         memset(data, 0, sizeof(*data));
6828
6829         /* fill the report data with the effective line speed */
6830         data->line_speed = line_speed;
6831
6832         /* Link is down */
6833         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6834                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6835                             &data->link_report_flags);
6836         }
6837
6838         /* Full DUPLEX */
6839         if (sc->link_vars.duplex == DUPLEX_FULL) {
6840                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6841                             &data->link_report_flags);
6842         }
6843
6844         /* Rx Flow Control is ON */
6845         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6846                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6847         }
6848
6849         /* Tx Flow Control is ON */
6850         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6851                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6852         }
6853 }
6854
6855 /* report link status to OS, should be called under phy_lock */
6856 static void bnx2x_link_report(struct bnx2x_softc *sc)
6857 {
6858         struct bnx2x_link_report_data cur_data;
6859
6860         /* reread mf_cfg */
6861         if (IS_PF(sc)) {
6862                 bnx2x_read_mf_cfg(sc);
6863         }
6864
6865         /* Read the current link report info */
6866         bnx2x_fill_report_data(sc, &cur_data);
6867
6868         /* Don't report link down or exactly the same link status twice */
6869         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6870             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6871                           &sc->last_reported_link.link_report_flags) &&
6872              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6873                           &cur_data.link_report_flags))) {
6874                 return;
6875         }
6876
6877         sc->link_cnt++;
6878
6879         /* report new link params and remember the state for the next time */
6880         rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6881
6882         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6883                          &cur_data.link_report_flags)) {
6884                 PMD_DRV_LOG(INFO, "NIC Link is Down");
6885         } else {
6886                 __rte_unused const char *duplex;
6887                 __rte_unused const char *flow;
6888
6889                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6890                                            &cur_data.link_report_flags)) {
6891                         duplex = "full";
6892                 } else {
6893                         duplex = "half";
6894                 }
6895
6896 /*
6897  * Handle the FC at the end so that only these flags would be
6898  * possibly set. This way we may easily check if there is no FC
6899  * enabled.
6900  */
6901                 if (cur_data.link_report_flags) {
6902                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6903                                          &cur_data.link_report_flags) &&
6904                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6905                                          &cur_data.link_report_flags)) {
6906                                 flow = "ON - receive & transmit";
6907                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6908                                                 &cur_data.link_report_flags) &&
6909                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6910                                                  &cur_data.link_report_flags)) {
6911                                 flow = "ON - receive";
6912                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6913                                                  &cur_data.link_report_flags) &&
6914                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6915                                                 &cur_data.link_report_flags)) {
6916                                 flow = "ON - transmit";
6917                         } else {
6918                                 flow = "none";  /* possible? */
6919                         }
6920                 } else {
6921                         flow = "none";
6922                 }
6923
6924                 PMD_DRV_LOG(INFO,
6925                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6926                             cur_data.line_speed, duplex, flow);
6927         }
6928 }
6929
6930 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6931 {
6932         if (sc->state != BNX2X_STATE_OPEN) {
6933                 return;
6934         }
6935
6936         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6937                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6938         } else {
6939                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6940                                           ELINK_SUPPORTED_10baseT_Full |
6941                                           ELINK_SUPPORTED_100baseT_Half |
6942                                           ELINK_SUPPORTED_100baseT_Full |
6943                                           ELINK_SUPPORTED_1000baseT_Full |
6944                                           ELINK_SUPPORTED_2500baseX_Full |
6945                                           ELINK_SUPPORTED_10000baseT_Full |
6946                                           ELINK_SUPPORTED_TP |
6947                                           ELINK_SUPPORTED_FIBRE |
6948                                           ELINK_SUPPORTED_Autoneg |
6949                                           ELINK_SUPPORTED_Pause |
6950                                           ELINK_SUPPORTED_Asym_Pause);
6951                 sc->port.advertising[0] = sc->port.supported[0];
6952
6953                 sc->link_params.sc = sc;
6954                 sc->link_params.port = SC_PORT(sc);
6955                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6956                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6957                 sc->link_params.req_line_speed[0] = SPEED_10000;
6958                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6959                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6960
6961                 if (CHIP_REV_IS_FPGA(sc)) {
6962                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6963                         sc->link_vars.line_speed = ELINK_SPEED_1000;
6964                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6965                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6966                 } else {
6967                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6968                         sc->link_vars.line_speed = ELINK_SPEED_10000;
6969                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6970                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6971                 }
6972
6973                 sc->link_vars.link_up = 1;
6974
6975                 sc->link_vars.duplex = DUPLEX_FULL;
6976                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6977
6978                 if (IS_PF(sc)) {
6979                         REG_WR(sc,
6980                                NIG_REG_EGRESS_DRAIN0_MODE +
6981                                sc->link_params.port * 4, 0);
6982                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6983                         bnx2x_link_report(sc);
6984                 }
6985         }
6986
6987         if (IS_PF(sc)) {
6988                 if (sc->link_vars.link_up) {
6989                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6990                 } else {
6991                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
6992                 }
6993                 bnx2x_link_report(sc);
6994         } else {
6995                 bnx2x_link_report(sc);
6996                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6997         }
6998 }
6999
7000 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7001 {
7002         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7003         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7004         struct elink_params *lp = &sc->link_params;
7005
7006         bnx2x_set_requested_fc(sc);
7007
7008         if (load_mode == LOAD_DIAG) {
7009                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7010 /* Prefer doing PHY loopback at 10G speed, if possible */
7011                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7012                         if (lp->speed_cap_mask[cfg_idx] &
7013                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7014                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7015                         } else {
7016                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7017                         }
7018                 }
7019         }
7020
7021         if (load_mode == LOAD_LOOPBACK_EXT) {
7022                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7023         }
7024
7025         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7026
7027         bnx2x_calc_fc_adv(sc);
7028
7029         if (sc->link_vars.link_up) {
7030                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7031                 bnx2x_link_report(sc);
7032         }
7033
7034         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7035         return rc;
7036 }
7037
7038 /* update flags in shmem */
7039 static void
7040 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7041 {
7042         uint32_t drv_flags;
7043
7044         if (SHMEM2_HAS(sc, drv_flags)) {
7045                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7046                 drv_flags = SHMEM2_RD(sc, drv_flags);
7047
7048                 if (set) {
7049                         drv_flags |= flags;
7050                 } else {
7051                         drv_flags &= ~flags;
7052                 }
7053
7054                 SHMEM2_WR(sc, drv_flags, drv_flags);
7055
7056                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7057         }
7058 }
7059
7060 /* periodic timer callout routine, only runs when the interface is up */
7061 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7062 {
7063         if ((sc->state != BNX2X_STATE_OPEN) ||
7064             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7065                 PMD_DRV_LOG(INFO, "periodic callout exit (state=0x%x)",
7066                             sc->state);
7067                 return;
7068         }
7069         if (!CHIP_REV_IS_SLOW(sc)) {
7070 /*
7071  * This barrier is needed to ensure the ordering between the writing
7072  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7073  * the reading here.
7074  */
7075                 mb();
7076                 if (sc->port.pmf) {
7077                         elink_period_func(&sc->link_params, &sc->link_vars);
7078                 }
7079         }
7080 #ifdef BNX2X_PULSE
7081         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7082                 int mb_idx = SC_FW_MB_IDX(sc);
7083                 uint32_t drv_pulse;
7084                 uint32_t mcp_pulse;
7085
7086                 ++sc->fw_drv_pulse_wr_seq;
7087                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7088
7089                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7090                 bnx2x_drv_pulse(sc);
7091
7092                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7093                              MCP_PULSE_SEQ_MASK);
7094
7095 /*
7096  * The delta between driver pulse and mcp response should
7097  * be 1 (before mcp response) or 0 (after mcp response).
7098  */
7099                 if ((drv_pulse != mcp_pulse) &&
7100                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7101                         /* someone lost a heartbeat... */
7102                         PMD_DRV_LOG(ERR,
7103                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7104                                     drv_pulse, mcp_pulse);
7105                 }
7106         }
7107 #endif
7108 }
7109
7110 /* start the controller */
7111 static __rte_noinline
7112 int bnx2x_nic_load(struct bnx2x_softc *sc)
7113 {
7114         uint32_t val;
7115         uint32_t load_code = 0;
7116         int i, rc = 0;
7117
7118         PMD_INIT_FUNC_TRACE();
7119
7120         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7121
7122         if (IS_PF(sc)) {
7123 /* must be called before memory allocation and HW init */
7124                 bnx2x_ilt_set_info(sc);
7125         }
7126
7127         bnx2x_set_fp_rx_buf_size(sc);
7128
7129         if (IS_PF(sc)) {
7130                 if (bnx2x_alloc_mem(sc) != 0) {
7131                         sc->state = BNX2X_STATE_CLOSED;
7132                         rc = -ENOMEM;
7133                         goto bnx2x_nic_load_error0;
7134                 }
7135         }
7136
7137         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7138                 sc->state = BNX2X_STATE_CLOSED;
7139                 rc = -ENOMEM;
7140                 goto bnx2x_nic_load_error0;
7141         }
7142
7143         if (IS_VF(sc)) {
7144                 rc = bnx2x_vf_init(sc);
7145                 if (rc) {
7146                         sc->state = BNX2X_STATE_ERROR;
7147                         goto bnx2x_nic_load_error0;
7148                 }
7149         }
7150
7151         if (IS_PF(sc)) {
7152 /* set pf load just before approaching the MCP */
7153                 bnx2x_set_pf_load(sc);
7154
7155 /* if MCP exists send load request and analyze response */
7156                 if (!BNX2X_NOMCP(sc)) {
7157                         /* attempt to load pf */
7158                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7159                                 sc->state = BNX2X_STATE_CLOSED;
7160                                 rc = -ENXIO;
7161                                 goto bnx2x_nic_load_error1;
7162                         }
7163
7164                         /* what did the MCP say? */
7165                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7166                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7167                                 sc->state = BNX2X_STATE_CLOSED;
7168                                 rc = -ENXIO;
7169                                 goto bnx2x_nic_load_error2;
7170                         }
7171                 } else {
7172                         PMD_DRV_LOG(INFO, "Device has no MCP!");
7173                         load_code = bnx2x_nic_load_no_mcp(sc);
7174                 }
7175
7176 /* mark PMF if applicable */
7177                 bnx2x_nic_load_pmf(sc, load_code);
7178
7179 /* Init Function state controlling object */
7180                 bnx2x_init_func_obj(sc);
7181
7182 /* Initialize HW */
7183                 if (bnx2x_init_hw(sc, load_code) != 0) {
7184                         PMD_DRV_LOG(NOTICE, "HW init failed");
7185                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7186                         sc->state = BNX2X_STATE_CLOSED;
7187                         rc = -ENXIO;
7188                         goto bnx2x_nic_load_error2;
7189                 }
7190         }
7191
7192         bnx2x_nic_init(sc, load_code);
7193
7194         /* Init per-function objects */
7195         if (IS_PF(sc)) {
7196                 bnx2x_init_objs(sc);
7197
7198 /* set AFEX default VLAN tag to an invalid value */
7199                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7200
7201                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7202                 rc = bnx2x_func_start(sc);
7203                 if (rc) {
7204                         PMD_DRV_LOG(NOTICE, "Function start failed!");
7205                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7206                         sc->state = BNX2X_STATE_ERROR;
7207                         goto bnx2x_nic_load_error3;
7208                 }
7209
7210 /* send LOAD_DONE command to MCP */
7211                 if (!BNX2X_NOMCP(sc)) {
7212                         load_code =
7213                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7214                         if (!load_code) {
7215                                 PMD_DRV_LOG(NOTICE,
7216                                             "MCP response failure, aborting");
7217                                 sc->state = BNX2X_STATE_ERROR;
7218                                 rc = -ENXIO;
7219                                 goto bnx2x_nic_load_error3;
7220                         }
7221                 }
7222         }
7223
7224         rc = bnx2x_setup_leading(sc);
7225         if (rc) {
7226                 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7227                 sc->state = BNX2X_STATE_ERROR;
7228                 goto bnx2x_nic_load_error3;
7229         }
7230
7231         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7232                 if (IS_PF(sc))
7233                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7234                 else            /* IS_VF(sc) */
7235                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7236
7237                 if (rc) {
7238                         PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7239                         sc->state = BNX2X_STATE_ERROR;
7240                         goto bnx2x_nic_load_error3;
7241                 }
7242         }
7243
7244         rc = bnx2x_init_rss_pf(sc);
7245         if (rc) {
7246                 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7247                 sc->state = BNX2X_STATE_ERROR;
7248                 goto bnx2x_nic_load_error3;
7249         }
7250
7251         /* now when Clients are configured we are ready to work */
7252         sc->state = BNX2X_STATE_OPEN;
7253
7254         /* Configure a ucast MAC */
7255         if (IS_PF(sc)) {
7256                 rc = bnx2x_set_eth_mac(sc, TRUE);
7257         } else {                /* IS_VF(sc) */
7258                 rc = bnx2x_vf_set_mac(sc, TRUE);
7259         }
7260
7261         if (rc) {
7262                 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7263                 sc->state = BNX2X_STATE_ERROR;
7264                 goto bnx2x_nic_load_error3;
7265         }
7266
7267         if (sc->port.pmf) {
7268                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7269                 if (rc) {
7270                         sc->state = BNX2X_STATE_ERROR;
7271                         goto bnx2x_nic_load_error3;
7272                 }
7273         }
7274
7275         sc->link_params.feature_config_flags &=
7276             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7277
7278         /* start the Tx */
7279         switch (LOAD_OPEN) {
7280         case LOAD_NORMAL:
7281         case LOAD_OPEN:
7282                 break;
7283
7284         case LOAD_DIAG:
7285         case LOAD_LOOPBACK_EXT:
7286                 sc->state = BNX2X_STATE_DIAG;
7287                 break;
7288
7289         default:
7290                 break;
7291         }
7292
7293         if (sc->port.pmf) {
7294                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7295         } else {
7296                 bnx2x_link_status_update(sc);
7297         }
7298
7299         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7300 /* mark driver is loaded in shmem2 */
7301                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7302                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7303                           (val |
7304                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7305                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7306         }
7307
7308         /* start fast path */
7309         /* Initialize Rx filter */
7310         bnx2x_set_rx_mode(sc);
7311
7312         /* wait for all pending SP commands to complete */
7313         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7314                 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7315                 bnx2x_periodic_stop(sc);
7316                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7317                 return -ENXIO;
7318         }
7319
7320         PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7321
7322         return 0;
7323
7324 bnx2x_nic_load_error3:
7325
7326         if (IS_PF(sc)) {
7327                 bnx2x_int_disable_sync(sc, 1);
7328
7329 /* clean out queued objects */
7330                 bnx2x_squeeze_objects(sc);
7331         }
7332
7333 bnx2x_nic_load_error2:
7334
7335         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7336                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7337                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7338         }
7339
7340         sc->port.pmf = 0;
7341
7342 bnx2x_nic_load_error1:
7343
7344         /* clear pf_load status, as it was already set */
7345         if (IS_PF(sc)) {
7346                 bnx2x_clear_pf_load(sc);
7347         }
7348
7349 bnx2x_nic_load_error0:
7350
7351         bnx2x_free_fw_stats_mem(sc);
7352         bnx2x_free_mem(sc);
7353
7354         return rc;
7355 }
7356
7357 /*
7358 * Handles controller initialization.
7359 */
7360 int bnx2x_init(struct bnx2x_softc *sc)
7361 {
7362         int other_engine = SC_PATH(sc) ? 0 : 1;
7363         uint8_t other_load_status, load_status;
7364         uint8_t global = FALSE;
7365         int rc;
7366
7367         /* Check if the driver is still running and bail out if it is. */
7368         if (sc->state != BNX2X_STATE_CLOSED) {
7369                 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7370                 rc = 0;
7371                 goto bnx2x_init_done;
7372         }
7373
7374         bnx2x_set_power_state(sc, PCI_PM_D0);
7375
7376         /*
7377          * If parity occurred during the unload, then attentions and/or
7378          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7379          * loaded on the current engine to complete the recovery. Parity recovery
7380          * is only relevant for PF driver.
7381          */
7382         if (IS_PF(sc)) {
7383                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7384                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7385
7386                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7387                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7388                         do {
7389                                 /*
7390                                  * If there are attentions and they are in global blocks, set
7391                                  * the GLOBAL_RESET bit regardless whether it will be this
7392                                  * function that will complete the recovery or not.
7393                                  */
7394                                 if (global) {
7395                                         bnx2x_set_reset_global(sc);
7396                                 }
7397
7398                                 /*
7399                                  * Only the first function on the current engine should try
7400                                  * to recover in open. In case of attentions in global blocks
7401                                  * only the first in the chip should try to recover.
7402                                  */
7403                                 if ((!load_status
7404                                      && (!global ||!other_load_status))
7405                                     && bnx2x_trylock_leader_lock(sc)
7406                                     && !bnx2x_leader_reset(sc)) {
7407                                         PMD_DRV_LOG(INFO,
7408                                                     "Recovered during init");
7409                                         break;
7410                                 }
7411
7412                                 /* recovery has failed... */
7413                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7414
7415                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7416
7417                                 PMD_DRV_LOG(NOTICE,
7418                                             "Recovery flow hasn't properly "
7419                                             "completed yet, try again later. "
7420                                             "If you still see this message after a "
7421                                             "few retries then power cycle is required.");
7422
7423                                 rc = -ENXIO;
7424                                 goto bnx2x_init_done;
7425                         } while (0);
7426                 }
7427         }
7428
7429         sc->recovery_state = BNX2X_RECOVERY_DONE;
7430
7431         rc = bnx2x_nic_load(sc);
7432
7433 bnx2x_init_done:
7434
7435         if (rc) {
7436                 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7437                             "stack notified driver is NOT running!");
7438         }
7439
7440         return rc;
7441 }
7442
7443 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7444 {
7445         uint32_t val = 0;
7446
7447         /*
7448          * Read the ME register to get the function number. The ME register
7449          * holds the relative-function number and absolute-function number. The
7450          * absolute-function number appears only in E2 and above. Before that
7451          * these bits always contained zero, therefore we cannot blindly use them.
7452          */
7453
7454         val = REG_RD(sc, BAR_ME_REGISTER);
7455
7456         sc->pfunc_rel =
7457             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7458         sc->path_id =
7459             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7460             1;
7461
7462         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7463                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7464         } else {
7465                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7466         }
7467
7468         PMD_DRV_LOG(DEBUG,
7469                     "Relative function %d, Absolute function %d, Path %d",
7470                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7471 }
7472
7473 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7474 {
7475         uint32_t shmem2_size;
7476         uint32_t offset;
7477         uint32_t mf_cfg_offset_value;
7478
7479         /* Non 57712 */
7480         offset = (SHMEM_ADDR(sc, func_mb) +
7481                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7482
7483         /* 57712 plus */
7484         if (sc->devinfo.shmem2_base != 0) {
7485                 shmem2_size = SHMEM2_RD(sc, size);
7486                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7487                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7488                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7489                                 offset = mf_cfg_offset_value;
7490                         }
7491                 }
7492         }
7493
7494         return offset;
7495 }
7496
7497 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7498 {
7499         uint32_t ret;
7500         struct bnx2x_pci_cap *caps;
7501
7502         /* ensure PCIe capability is enabled */
7503         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7504         if (NULL != caps) {
7505                 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7506                             "id=0x%04X type=0x%04X addr=0x%08X",
7507                             caps->id, caps->type, caps->addr);
7508                 pci_read(sc, (caps->addr + reg), &ret, 2);
7509                 return ret;
7510         }
7511
7512         PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7513
7514         return 0;
7515 }
7516
7517 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7518 {
7519         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7520                 PCIM_EXP_STA_TRANSACTION_PND;
7521 }
7522
7523 /*
7524 * Walk the PCI capabiites list for the device to find what features are
7525 * supported. These capabilites may be enabled/disabled by firmware so it's
7526 * best to walk the list rather than make assumptions.
7527 */
7528 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7529 {
7530         PMD_INIT_FUNC_TRACE();
7531
7532         struct bnx2x_pci_cap *caps;
7533         uint16_t link_status;
7534 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7535         int reg = 0;
7536 #endif
7537
7538         /* check if PCI Power Management is enabled */
7539         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7540         if (NULL != caps) {
7541                 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7542                             "id=0x%04X type=0x%04X addr=0x%08X",
7543                             caps->id, caps->type, caps->addr);
7544
7545                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7546                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7547         }
7548
7549         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7550
7551         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7552         sc->devinfo.pcie_link_width =
7553             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7554
7555         PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7556                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7557
7558         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7559
7560         /* check if MSI capability is enabled */
7561         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7562         if (NULL != caps) {
7563                 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7564
7565                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7566                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7567         }
7568
7569         /* check if MSI-X capability is enabled */
7570         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7571         if (NULL != caps) {
7572                 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7573
7574                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7575                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7576         }
7577 }
7578
7579 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7580 {
7581         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7582         uint32_t val;
7583
7584         /* get the outer vlan if we're in switch-dependent mode */
7585
7586         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7587         mf_info->ext_id = (uint16_t) val;
7588
7589         mf_info->multi_vnics_mode = 1;
7590
7591         if (!VALID_OVLAN(mf_info->ext_id)) {
7592                 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7593                 return 1;
7594         }
7595
7596         /* get the capabilities */
7597         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7598             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7599                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7600         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7601                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7602                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7603         } else {
7604                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7605         }
7606
7607         mf_info->vnics_per_port =
7608             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7609
7610         return 0;
7611 }
7612
7613 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7614 {
7615         uint32_t retval = 0;
7616         uint32_t val;
7617
7618         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7619
7620         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7621                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7622                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7623                 }
7624                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7625                         retval |= MF_PROTO_SUPPORT_ISCSI;
7626                 }
7627                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7628                         retval |= MF_PROTO_SUPPORT_FCOE;
7629                 }
7630         }
7631
7632         return retval;
7633 }
7634
7635 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7636 {
7637         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7638         uint32_t val;
7639
7640         /*
7641          * There is no outer vlan if we're in switch-independent mode.
7642          * If the mac is valid then assume multi-function.
7643          */
7644
7645         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7646
7647         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7648
7649         mf_info->mf_protos_supported =
7650             bnx2x_get_shmem_ext_proto_support_flags(sc);
7651
7652         mf_info->vnics_per_port =
7653             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7654
7655         return 0;
7656 }
7657
7658 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7659 {
7660         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7661         uint32_t e1hov_tag;
7662         uint32_t func_config;
7663         uint32_t niv_config;
7664
7665         mf_info->multi_vnics_mode = 1;
7666
7667         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7668         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7669         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7670
7671         mf_info->ext_id =
7672             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7673                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7674
7675         mf_info->default_vlan =
7676             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7677                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7678
7679         mf_info->niv_allowed_priorities =
7680             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7681                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7682
7683         mf_info->niv_default_cos =
7684             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7685                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7686
7687         mf_info->afex_vlan_mode =
7688             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7689              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7690
7691         mf_info->niv_mba_enabled =
7692             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7693              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7694
7695         mf_info->mf_protos_supported =
7696             bnx2x_get_shmem_ext_proto_support_flags(sc);
7697
7698         mf_info->vnics_per_port =
7699             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7700
7701         return 0;
7702 }
7703
7704 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7705 {
7706         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7707         uint32_t mf_cfg1;
7708         uint32_t mf_cfg2;
7709         uint32_t ovlan1;
7710         uint32_t ovlan2;
7711         uint8_t i, j;
7712
7713         /* various MF mode sanity checks... */
7714
7715         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7716                 PMD_DRV_LOG(NOTICE,
7717                             "Enumerated function %d is marked as hidden",
7718                             SC_PORT(sc));
7719                 return 1;
7720         }
7721
7722         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7723                 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7724                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7725                 return 1;
7726         }
7727
7728         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7729 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7730                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7731                         PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7732                                     SC_VN(sc), OVLAN(sc));
7733                         return 1;
7734                 }
7735
7736                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7737                         PMD_DRV_LOG(NOTICE,
7738                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7739                                     mf_info->multi_vnics_mode, OVLAN(sc));
7740                         return 1;
7741                 }
7742
7743 /*
7744  * Verify all functions are either MF or SF mode. If MF, make sure
7745  * sure that all non-hidden functions have a valid ovlan. If SF,
7746  * make sure that all non-hidden functions have an invalid ovlan.
7747  */
7748                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7749                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7750                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7751                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7752                             (((mf_info->multi_vnics_mode)
7753                               && !VALID_OVLAN(ovlan1))
7754                              || ((!mf_info->multi_vnics_mode)
7755                                  && VALID_OVLAN(ovlan1)))) {
7756                                 PMD_DRV_LOG(NOTICE,
7757                                             "mf_mode=SD function %d MF config "
7758                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7759                                             i, mf_info->multi_vnics_mode,
7760                                             ovlan1);
7761                                 return 1;
7762                         }
7763                 }
7764
7765 /* Verify all funcs on the same port each have a different ovlan. */
7766                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7767                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7768                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7769                         /* iterate from the next function on the port to the max func */
7770                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7771                                 mf_cfg2 =
7772                                     MFCFG_RD(sc, func_mf_config[j].config);
7773                                 ovlan2 =
7774                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7775                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7776                                     && VALID_OVLAN(ovlan1)
7777                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7778                                     && VALID_OVLAN(ovlan2)
7779                                     && (ovlan1 == ovlan2)) {
7780                                         PMD_DRV_LOG(NOTICE,
7781                                                     "mf_mode=SD functions %d and %d "
7782                                                     "have the same ovlan (%d)",
7783                                                     i, j, ovlan1);
7784                                         return 1;
7785                                 }
7786                         }
7787                 }
7788         }
7789         /* MULTI_FUNCTION_SD */
7790         return 0;
7791 }
7792
7793 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7794 {
7795         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7796         uint32_t val, mac_upper;
7797         uint8_t i, vnic;
7798
7799         /* initialize mf_info defaults */
7800         mf_info->vnics_per_port = 1;
7801         mf_info->multi_vnics_mode = FALSE;
7802         mf_info->path_has_ovlan = FALSE;
7803         mf_info->mf_mode = SINGLE_FUNCTION;
7804
7805         if (!CHIP_IS_MF_CAP(sc)) {
7806                 return 0;
7807         }
7808
7809         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7810                 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7811                 return 1;
7812         }
7813
7814         /* get the MF mode (switch dependent / independent / single-function) */
7815
7816         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7817
7818         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7819         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7820
7821                 mac_upper =
7822                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7823
7824                 /* check for legal upper mac bytes */
7825                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7826                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7827                 } else {
7828                         PMD_DRV_LOG(NOTICE,
7829                                     "Invalid config for Switch Independent mode");
7830                 }
7831
7832                 break;
7833
7834         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7835         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7836
7837                 /* get outer vlan configuration */
7838                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7839
7840                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7841                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7842                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7843                 } else {
7844                         PMD_DRV_LOG(NOTICE,
7845                                     "Invalid config for Switch Dependent mode");
7846                 }
7847
7848                 break;
7849
7850         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7851
7852                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7853                 return 0;
7854
7855         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7856
7857                 /*
7858                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7859                  * and the MAC address is valid.
7860                  */
7861                 mac_upper =
7862                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7863
7864                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7865                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7866                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7867                 } else {
7868                         PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7869                 }
7870
7871                 break;
7872
7873         default:
7874
7875                 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7876                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7877
7878                 return 1;
7879         }
7880
7881         /* set path mf_mode (which could be different than function mf_mode) */
7882         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7883                 mf_info->path_has_ovlan = TRUE;
7884         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7885 /*
7886  * Decide on path multi vnics mode. If we're not in MF mode and in
7887  * 4-port mode, this is good enough to check vnic-0 of the other port
7888  * on the same path
7889  */
7890                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7891                         uint8_t other_port = !(PORT_ID(sc) & 1);
7892                         uint8_t abs_func_other_port =
7893                             (SC_PATH(sc) + (2 * other_port));
7894
7895                         val =
7896                             MFCFG_RD(sc,
7897                                      func_mf_config
7898                                      [abs_func_other_port].e1hov_tag);
7899
7900                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7901                 }
7902         }
7903
7904         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7905 /* invalid MF config */
7906                 if (SC_VN(sc) >= 1) {
7907                         PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7908                         return 1;
7909                 }
7910
7911                 return 0;
7912         }
7913
7914         /* get the MF configuration */
7915         mf_info->mf_config[SC_VN(sc)] =
7916             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7917
7918         switch (mf_info->mf_mode) {
7919         case MULTI_FUNCTION_SD:
7920
7921                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7922                 break;
7923
7924         case MULTI_FUNCTION_SI:
7925
7926                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7927                 break;
7928
7929         case MULTI_FUNCTION_AFEX:
7930
7931                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7932                 break;
7933
7934         default:
7935
7936                 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7937                             mf_info->mf_mode);
7938                 return 1;
7939         }
7940
7941         /* get the congestion management parameters */
7942
7943         vnic = 0;
7944         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7945 /* get min/max bw */
7946                 val = MFCFG_RD(sc, func_mf_config[i].config);
7947                 mf_info->min_bw[vnic] =
7948                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7949                      FUNC_MF_CFG_MIN_BW_SHIFT);
7950                 mf_info->max_bw[vnic] =
7951                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7952                      FUNC_MF_CFG_MAX_BW_SHIFT);
7953                 vnic++;
7954         }
7955
7956         return bnx2x_check_valid_mf_cfg(sc);
7957 }
7958
7959 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
7960 {
7961         int port;
7962         uint32_t mac_hi, mac_lo, val;
7963
7964         PMD_INIT_FUNC_TRACE();
7965
7966         port = SC_PORT(sc);
7967         mac_hi = mac_lo = 0;
7968
7969         sc->link_params.sc = sc;
7970         sc->link_params.port = port;
7971
7972         /* get the hardware config info */
7973         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
7974         sc->devinfo.hw_config2 =
7975             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
7976
7977         sc->link_params.hw_led_mode =
7978             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
7979              SHARED_HW_CFG_LED_MODE_SHIFT);
7980
7981         /* get the port feature config */
7982         sc->port.config =
7983             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
7984
7985         /* get the link params */
7986         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
7987             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
7988             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
7989         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
7990             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
7991             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
7992
7993         /* get the lane config */
7994         sc->link_params.lane_config =
7995             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
7996
7997         /* get the link config */
7998         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
7999         sc->port.link_config[ELINK_INT_PHY] = val;
8000         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8001         sc->port.link_config[ELINK_EXT_PHY1] =
8002             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8003
8004         /* get the override preemphasis flag and enable it or turn it off */
8005         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8006         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8007                 sc->link_params.feature_config_flags |=
8008                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8009         } else {
8010                 sc->link_params.feature_config_flags &=
8011                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8012         }
8013
8014         /* get the initial value of the link params */
8015         sc->link_params.multi_phy_config =
8016             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8017
8018         /* get external phy info */
8019         sc->port.ext_phy_config =
8020             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8021
8022         /* get the multifunction configuration */
8023         bnx2x_get_mf_cfg_info(sc);
8024
8025         /* get the mac address */
8026         if (IS_MF(sc)) {
8027                 mac_hi =
8028                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8029                 mac_lo =
8030                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8031         } else {
8032                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8033                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8034         }
8035
8036         if ((mac_lo == 0) && (mac_hi == 0)) {
8037                 *sc->mac_addr_str = 0;
8038                 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8039         } else {
8040                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8041                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8042                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8043                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8044                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8045                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8046                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8047                          "%02x:%02x:%02x:%02x:%02x:%02x",
8048                          sc->link_params.mac_addr[0],
8049                          sc->link_params.mac_addr[1],
8050                          sc->link_params.mac_addr[2],
8051                          sc->link_params.mac_addr[3],
8052                          sc->link_params.mac_addr[4],
8053                          sc->link_params.mac_addr[5]);
8054                 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8055         }
8056
8057         return 0;
8058 }
8059
8060 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8061 {
8062         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8063         switch (sc->link_params.phy[phy_idx].media_type) {
8064         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8065         case ELINK_ETH_PHY_SFP_1G_FIBER:
8066         case ELINK_ETH_PHY_XFP_FIBER:
8067         case ELINK_ETH_PHY_KR:
8068         case ELINK_ETH_PHY_CX4:
8069                 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8070                 sc->media = IFM_10G_CX4;
8071                 break;
8072         case ELINK_ETH_PHY_DA_TWINAX:
8073                 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8074                 sc->media = IFM_10G_TWINAX;
8075                 break;
8076         case ELINK_ETH_PHY_BASE_T:
8077                 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8078                 sc->media = IFM_10G_T;
8079                 break;
8080         case ELINK_ETH_PHY_NOT_PRESENT:
8081                 PMD_DRV_LOG(INFO, "Media not present.");
8082                 sc->media = 0;
8083                 break;
8084         case ELINK_ETH_PHY_UNSPECIFIED:
8085         default:
8086                 PMD_DRV_LOG(INFO, "Unknown media!");
8087                 sc->media = 0;
8088                 break;
8089         }
8090 }
8091
8092 #define GET_FIELD(value, fname)                     \
8093 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8094 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8095 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8096
8097 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8098 {
8099         int pfid = SC_FUNC(sc);
8100         int igu_sb_id;
8101         uint32_t val;
8102         uint8_t fid, igu_sb_cnt = 0;
8103
8104         sc->igu_base_sb = 0xff;
8105
8106         if (CHIP_INT_MODE_IS_BC(sc)) {
8107                 int vn = SC_VN(sc);
8108                 igu_sb_cnt = sc->igu_sb_cnt;
8109                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8110                                    FP_SB_MAX_E1x);
8111                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8112                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8113                 return 0;
8114         }
8115
8116         /* IGU in normal mode - read CAM */
8117         for (igu_sb_id = 0;
8118              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8119                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8120                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8121                         continue;
8122                 }
8123                 fid = IGU_FID(val);
8124                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8125                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8126                                 continue;
8127                         }
8128                         if (IGU_VEC(val) == 0) {
8129                                 /* default status block */
8130                                 sc->igu_dsb_id = igu_sb_id;
8131                         } else {
8132                                 if (sc->igu_base_sb == 0xff) {
8133                                         sc->igu_base_sb = igu_sb_id;
8134                                 }
8135                                 igu_sb_cnt++;
8136                         }
8137                 }
8138         }
8139
8140         /*
8141          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8142          * that number of CAM entries will not be equal to the value advertised in
8143          * PCI. Driver should use the minimal value of both as the actual status
8144          * block count
8145          */
8146         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8147
8148         if (igu_sb_cnt == 0) {
8149                 PMD_DRV_LOG(ERR, "CAM configuration error");
8150                 return -1;
8151         }
8152
8153         return 0;
8154 }
8155
8156 /*
8157 * Gather various information from the device config space, the device itself,
8158 * shmem, and the user input.
8159 */
8160 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8161 {
8162         uint32_t val;
8163         int rc;
8164
8165         /* get the chip revision (chip metal comes from pci config space) */
8166         sc->devinfo.chip_id = sc->link_params.chip_id =
8167             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8168              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8169              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8170              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8171
8172         /* force 57811 according to MISC register */
8173         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8174                 if (CHIP_IS_57810(sc)) {
8175                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8176                                                (sc->
8177                                                 devinfo.chip_id & 0x0000ffff));
8178                 } else if (CHIP_IS_57810_MF(sc)) {
8179                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8180                                                (sc->
8181                                                 devinfo.chip_id & 0x0000ffff));
8182                 }
8183                 sc->devinfo.chip_id |= 0x1;
8184         }
8185
8186         PMD_DRV_LOG(DEBUG,
8187                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8188                     sc->devinfo.chip_id,
8189                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8190                     ((sc->devinfo.chip_id >> 12) & 0xf),
8191                     ((sc->devinfo.chip_id >> 4) & 0xff),
8192                     ((sc->devinfo.chip_id >> 0) & 0xf));
8193
8194         val = (REG_RD(sc, 0x2874) & 0x55);
8195         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8196                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8197                 PMD_DRV_LOG(DEBUG, "single port device");
8198         }
8199
8200         /* set the doorbell size */
8201         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8202
8203         /* determine whether the device is in 2 port or 4 port mode */
8204         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8205         if (CHIP_IS_E2E3(sc)) {
8206 /*
8207  * Read port4mode_en_ovwr[0]:
8208  *   If 1, four port mode is in port4mode_en_ovwr[1].
8209  *   If 0, four port mode is in port4mode_en[0].
8210  */
8211                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8212                 if (val & 1) {
8213                         val = ((val >> 1) & 1);
8214                 } else {
8215                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8216                 }
8217
8218                 sc->devinfo.chip_port_mode =
8219                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8220
8221                 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8222         }
8223
8224         /* get the function and path info for the device */
8225         bnx2x_get_function_num(sc);
8226
8227         /* get the shared memory base address */
8228         sc->devinfo.shmem_base =
8229             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8230         sc->devinfo.shmem2_base =
8231             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8232                         MISC_REG_GENERIC_CR_0));
8233
8234         if (!sc->devinfo.shmem_base) {
8235 /* this should ONLY prevent upcoming shmem reads */
8236                 PMD_DRV_LOG(INFO, "MCP not active");
8237                 sc->flags |= BNX2X_NO_MCP_FLAG;
8238                 return 0;
8239         }
8240
8241         /* make sure the shared memory contents are valid */
8242         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8243         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8244             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8245                 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8246                             val);
8247                 return 0;
8248         }
8249
8250         /* get the bootcode version */
8251         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8252         snprintf(sc->devinfo.bc_ver_str,
8253                  sizeof(sc->devinfo.bc_ver_str),
8254                  "%d.%d.%d",
8255                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8256                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8257                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8258         PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8259
8260         /* get the bootcode shmem address */
8261         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8262
8263         /* clean indirect addresses as they're not used */
8264         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8265         if (IS_PF(sc)) {
8266                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8267                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8268                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8269                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8270                 if (CHIP_IS_E1x(sc)) {
8271                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8272                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8273                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8274                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8275                 }
8276         }
8277
8278         /* get the nvram size */
8279         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8280         sc->devinfo.flash_size =
8281             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8282
8283         bnx2x_set_power_state(sc, PCI_PM_D0);
8284         /* get various configuration parameters from shmem */
8285         bnx2x_get_shmem_info(sc);
8286
8287         /* initialize IGU parameters */
8288         if (CHIP_IS_E1x(sc)) {
8289                 sc->devinfo.int_block = INT_BLOCK_HC;
8290                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8291                 sc->igu_base_sb = 0;
8292         } else {
8293                 sc->devinfo.int_block = INT_BLOCK_IGU;
8294
8295 /* do not allow device reset during IGU info preocessing */
8296                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8297
8298                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8299
8300                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8301                         int tout = 5000;
8302
8303                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8304                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8305                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8306
8307                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8308                                 tout--;
8309                                 DELAY(1000);
8310                         }
8311
8312                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8313                                 PMD_DRV_LOG(NOTICE,
8314                                             "FORCING IGU Normal Mode failed!!!");
8315                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8316                                 return -1;
8317                         }
8318                 }
8319
8320                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8321                         PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8322                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8323                 } else {
8324                         PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8325                 }
8326
8327                 rc = bnx2x_get_igu_cam_info(sc);
8328
8329                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8330
8331                 if (rc) {
8332                         return rc;
8333                 }
8334         }
8335
8336         /*
8337          * Get base FW non-default (fast path) status block ID. This value is
8338          * used to initialize the fw_sb_id saved on the fp/queue structure to
8339          * determine the id used by the FW.
8340          */
8341         if (CHIP_IS_E1x(sc)) {
8342                 sc->base_fw_ndsb =
8343                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8344         } else {
8345 /*
8346  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8347  * the same queue are indicated on the same IGU SB). So we prefer
8348  * FW and IGU SBs to be the same value.
8349  */
8350                 sc->base_fw_ndsb = sc->igu_base_sb;
8351         }
8352
8353         elink_phy_probe(&sc->link_params);
8354
8355         return 0;
8356 }
8357
8358 static void
8359 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8360 {
8361         uint32_t cfg_size = 0;
8362         uint32_t idx;
8363         uint8_t port = SC_PORT(sc);
8364
8365         /* aggregation of supported attributes of all external phys */
8366         sc->port.supported[0] = 0;
8367         sc->port.supported[1] = 0;
8368
8369         switch (sc->link_params.num_phys) {
8370         case 1:
8371                 sc->port.supported[0] =
8372                     sc->link_params.phy[ELINK_INT_PHY].supported;
8373                 cfg_size = 1;
8374                 break;
8375         case 2:
8376                 sc->port.supported[0] =
8377                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8378                 cfg_size = 1;
8379                 break;
8380         case 3:
8381                 if (sc->link_params.multi_phy_config &
8382                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8383                         sc->port.supported[1] =
8384                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8385                         sc->port.supported[0] =
8386                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8387                 } else {
8388                         sc->port.supported[0] =
8389                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8390                         sc->port.supported[1] =
8391                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8392                 }
8393                 cfg_size = 2;
8394                 break;
8395         }
8396
8397         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8398                 PMD_DRV_LOG(ERR,
8399                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8400                             SHMEM_RD(sc,
8401                                      dev_info.port_hw_config
8402                                      [port].external_phy_config),
8403                             SHMEM_RD(sc,
8404                                      dev_info.port_hw_config
8405                                      [port].external_phy_config2));
8406                 return;
8407         }
8408
8409         if (CHIP_IS_E3(sc))
8410                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8411         else {
8412                 switch (switch_cfg) {
8413                 case ELINK_SWITCH_CFG_1G:
8414                         sc->port.phy_addr =
8415                             REG_RD(sc,
8416                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8417                         break;
8418                 case ELINK_SWITCH_CFG_10G:
8419                         sc->port.phy_addr =
8420                             REG_RD(sc,
8421                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8422                         break;
8423                 default:
8424                         PMD_DRV_LOG(ERR,
8425                                     "Invalid switch config in"
8426                                     "link_config=0x%08x",
8427                                     sc->port.link_config[0]);
8428                         return;
8429                 }
8430         }
8431
8432         PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8433
8434         /* mask what we support according to speed_cap_mask per configuration */
8435         for (idx = 0; idx < cfg_size; idx++) {
8436                 if (!(sc->link_params.speed_cap_mask[idx] &
8437                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8438                         sc->port.supported[idx] &=
8439                             ~ELINK_SUPPORTED_10baseT_Half;
8440                 }
8441
8442                 if (!(sc->link_params.speed_cap_mask[idx] &
8443                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8444                         sc->port.supported[idx] &=
8445                             ~ELINK_SUPPORTED_10baseT_Full;
8446                 }
8447
8448                 if (!(sc->link_params.speed_cap_mask[idx] &
8449                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8450                         sc->port.supported[idx] &=
8451                             ~ELINK_SUPPORTED_100baseT_Half;
8452                 }
8453
8454                 if (!(sc->link_params.speed_cap_mask[idx] &
8455                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8456                         sc->port.supported[idx] &=
8457                             ~ELINK_SUPPORTED_100baseT_Full;
8458                 }
8459
8460                 if (!(sc->link_params.speed_cap_mask[idx] &
8461                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8462                         sc->port.supported[idx] &=
8463                             ~ELINK_SUPPORTED_1000baseT_Full;
8464                 }
8465
8466                 if (!(sc->link_params.speed_cap_mask[idx] &
8467                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8468                         sc->port.supported[idx] &=
8469                             ~ELINK_SUPPORTED_2500baseX_Full;
8470                 }
8471
8472                 if (!(sc->link_params.speed_cap_mask[idx] &
8473                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8474                         sc->port.supported[idx] &=
8475                             ~ELINK_SUPPORTED_10000baseT_Full;
8476                 }
8477
8478                 if (!(sc->link_params.speed_cap_mask[idx] &
8479                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8480                         sc->port.supported[idx] &=
8481                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8482                 }
8483         }
8484
8485         PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8486                     sc->port.supported[0], sc->port.supported[1]);
8487 }
8488
8489 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8490 {
8491         uint32_t link_config;
8492         uint32_t idx;
8493         uint32_t cfg_size = 0;
8494
8495         sc->port.advertising[0] = 0;
8496         sc->port.advertising[1] = 0;
8497
8498         switch (sc->link_params.num_phys) {
8499         case 1:
8500         case 2:
8501                 cfg_size = 1;
8502                 break;
8503         case 3:
8504                 cfg_size = 2;
8505                 break;
8506         }
8507
8508         for (idx = 0; idx < cfg_size; idx++) {
8509                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8510                 link_config = sc->port.link_config[idx];
8511
8512                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8513                 case PORT_FEATURE_LINK_SPEED_AUTO:
8514                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8515                                 sc->link_params.req_line_speed[idx] =
8516                                     ELINK_SPEED_AUTO_NEG;
8517                                 sc->port.advertising[idx] |=
8518                                     sc->port.supported[idx];
8519                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8520                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8521                                         sc->port.advertising[idx] |=
8522                                             (ELINK_SUPPORTED_100baseT_Half |
8523                                              ELINK_SUPPORTED_100baseT_Full);
8524                         } else {
8525                                 /* force 10G, no AN */
8526                                 sc->link_params.req_line_speed[idx] =
8527                                     ELINK_SPEED_10000;
8528                                 sc->port.advertising[idx] |=
8529                                     (ADVERTISED_10000baseT_Full |
8530                                      ADVERTISED_FIBRE);
8531                                 continue;
8532                         }
8533                         break;
8534
8535                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8536                         if (sc->
8537                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8538                         {
8539                                 sc->link_params.req_line_speed[idx] =
8540                                     ELINK_SPEED_10;
8541                                 sc->port.advertising[idx] |=
8542                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8543                         } else {
8544                                 PMD_DRV_LOG(ERR,
8545                                             "Invalid NVRAM config link_config=0x%08x "
8546                                             "speed_cap_mask=0x%08x",
8547                                             link_config,
8548                                             sc->
8549                                             link_params.speed_cap_mask[idx]);
8550                                 return;
8551                         }
8552                         break;
8553
8554                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8555                         if (sc->
8556                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8557                         {
8558                                 sc->link_params.req_line_speed[idx] =
8559                                     ELINK_SPEED_10;
8560                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8561                                 sc->port.advertising[idx] |=
8562                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8563                         } else {
8564                                 PMD_DRV_LOG(ERR,
8565                                             "Invalid NVRAM config link_config=0x%08x "
8566                                             "speed_cap_mask=0x%08x",
8567                                             link_config,
8568                                             sc->
8569                                             link_params.speed_cap_mask[idx]);
8570                                 return;
8571                         }
8572                         break;
8573
8574                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8575                         if (sc->
8576                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8577                         {
8578                                 sc->link_params.req_line_speed[idx] =
8579                                     ELINK_SPEED_100;
8580                                 sc->port.advertising[idx] |=
8581                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8582                         } else {
8583                                 PMD_DRV_LOG(ERR,
8584                                             "Invalid NVRAM config link_config=0x%08x "
8585                                             "speed_cap_mask=0x%08x",
8586                                             link_config,
8587                                             sc->
8588                                             link_params.speed_cap_mask[idx]);
8589                                 return;
8590                         }
8591                         break;
8592
8593                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8594                         if (sc->
8595                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8596                         {
8597                                 sc->link_params.req_line_speed[idx] =
8598                                     ELINK_SPEED_100;
8599                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8600                                 sc->port.advertising[idx] |=
8601                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8602                         } else {
8603                                 PMD_DRV_LOG(ERR,
8604                                             "Invalid NVRAM config link_config=0x%08x "
8605                                             "speed_cap_mask=0x%08x",
8606                                             link_config,
8607                                             sc->
8608                                             link_params.speed_cap_mask[idx]);
8609                                 return;
8610                         }
8611                         break;
8612
8613                 case PORT_FEATURE_LINK_SPEED_1G:
8614                         if (sc->port.supported[idx] &
8615                             ELINK_SUPPORTED_1000baseT_Full) {
8616                                 sc->link_params.req_line_speed[idx] =
8617                                     ELINK_SPEED_1000;
8618                                 sc->port.advertising[idx] |=
8619                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8620                         } else {
8621                                 PMD_DRV_LOG(ERR,
8622                                             "Invalid NVRAM config link_config=0x%08x "
8623                                             "speed_cap_mask=0x%08x",
8624                                             link_config,
8625                                             sc->
8626                                             link_params.speed_cap_mask[idx]);
8627                                 return;
8628                         }
8629                         break;
8630
8631                 case PORT_FEATURE_LINK_SPEED_2_5G:
8632                         if (sc->port.supported[idx] &
8633                             ELINK_SUPPORTED_2500baseX_Full) {
8634                                 sc->link_params.req_line_speed[idx] =
8635                                     ELINK_SPEED_2500;
8636                                 sc->port.advertising[idx] |=
8637                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8638                         } else {
8639                                 PMD_DRV_LOG(ERR,
8640                                             "Invalid NVRAM config link_config=0x%08x "
8641                                             "speed_cap_mask=0x%08x",
8642                                             link_config,
8643                                             sc->
8644                                             link_params.speed_cap_mask[idx]);
8645                                 return;
8646                         }
8647                         break;
8648
8649                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8650                         if (sc->port.supported[idx] &
8651                             ELINK_SUPPORTED_10000baseT_Full) {
8652                                 sc->link_params.req_line_speed[idx] =
8653                                     ELINK_SPEED_10000;
8654                                 sc->port.advertising[idx] |=
8655                                     (ADVERTISED_10000baseT_Full |
8656                                      ADVERTISED_FIBRE);
8657                         } else {
8658                                 PMD_DRV_LOG(ERR,
8659                                             "Invalid NVRAM config link_config=0x%08x "
8660                                             "speed_cap_mask=0x%08x",
8661                                             link_config,
8662                                             sc->
8663                                             link_params.speed_cap_mask[idx]);
8664                                 return;
8665                         }
8666                         break;
8667
8668                 case PORT_FEATURE_LINK_SPEED_20G:
8669                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8670                         break;
8671
8672                 default:
8673                         PMD_DRV_LOG(ERR,
8674                                     "Invalid NVRAM config link_config=0x%08x "
8675                                     "speed_cap_mask=0x%08x", link_config,
8676                                     sc->link_params.speed_cap_mask[idx]);
8677                         sc->link_params.req_line_speed[idx] =
8678                             ELINK_SPEED_AUTO_NEG;
8679                         sc->port.advertising[idx] = sc->port.supported[idx];
8680                         break;
8681                 }
8682
8683                 sc->link_params.req_flow_ctrl[idx] =
8684                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8685
8686                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8687                         if (!
8688                             (sc->
8689                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8690                                 sc->link_params.req_flow_ctrl[idx] =
8691                                     ELINK_FLOW_CTRL_NONE;
8692                         } else {
8693                                 bnx2x_set_requested_fc(sc);
8694                         }
8695                 }
8696         }
8697 }
8698
8699 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8700 {
8701         uint8_t port = SC_PORT(sc);
8702         uint32_t eee_mode;
8703
8704         PMD_INIT_FUNC_TRACE();
8705
8706         /* shmem data already read in bnx2x_get_shmem_info() */
8707
8708         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8709         bnx2x_link_settings_requested(sc);
8710
8711         /* configure link feature according to nvram value */
8712         eee_mode =
8713             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8714               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8715              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8716         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8717                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8718                                             ELINK_EEE_MODE_ENABLE_LPI |
8719                                             ELINK_EEE_MODE_OUTPUT_TIME);
8720         } else {
8721                 sc->link_params.eee_mode = 0;
8722         }
8723
8724         /* get the media type */
8725         bnx2x_media_detect(sc);
8726 }
8727
8728 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8729 {
8730         uint32_t flags = MODE_ASIC | MODE_PORT2;
8731
8732         if (CHIP_IS_E2(sc)) {
8733                 flags |= MODE_E2;
8734         } else if (CHIP_IS_E3(sc)) {
8735                 flags |= MODE_E3;
8736                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8737                         flags |= MODE_E3_A0;
8738                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8739
8740                         flags |= MODE_E3_B0 | MODE_COS3;
8741                 }
8742         }
8743
8744         if (IS_MF(sc)) {
8745                 flags |= MODE_MF;
8746                 switch (sc->devinfo.mf_info.mf_mode) {
8747                 case MULTI_FUNCTION_SD:
8748                         flags |= MODE_MF_SD;
8749                         break;
8750                 case MULTI_FUNCTION_SI:
8751                         flags |= MODE_MF_SI;
8752                         break;
8753                 case MULTI_FUNCTION_AFEX:
8754                         flags |= MODE_MF_AFEX;
8755                         break;
8756                 }
8757         } else {
8758                 flags |= MODE_SF;
8759         }
8760
8761 #if defined(__LITTLE_ENDIAN)
8762         flags |= MODE_LITTLE_ENDIAN;
8763 #else /* __BIG_ENDIAN */
8764         flags |= MODE_BIG_ENDIAN;
8765 #endif
8766
8767         INIT_MODE_FLAGS(sc) = flags;
8768 }
8769
8770 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8771 {
8772         struct bnx2x_fastpath *fp;
8773         char buf[32];
8774         uint32_t i;
8775
8776         if (IS_PF(sc)) {
8777 /************************/
8778 /* DEFAULT STATUS BLOCK */
8779 /************************/
8780
8781                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8782                                   &sc->def_sb_dma, "def_sb",
8783                                   RTE_CACHE_LINE_SIZE) != 0) {
8784                         return -1;
8785                 }
8786
8787                 sc->def_sb =
8788                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8789 /***************/
8790 /* EVENT QUEUE */
8791 /***************/
8792
8793                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8794                                   &sc->eq_dma, "ev_queue",
8795                                   RTE_CACHE_LINE_SIZE) != 0) {
8796                         sc->def_sb = NULL;
8797                         return -1;
8798                 }
8799
8800                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8801
8802 /*************/
8803 /* SLOW PATH */
8804 /*************/
8805
8806                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8807                                   &sc->sp_dma, "sp",
8808                                   RTE_CACHE_LINE_SIZE) != 0) {
8809                         sc->eq = NULL;
8810                         sc->def_sb = NULL;
8811                         return -1;
8812                 }
8813
8814                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8815
8816 /*******************/
8817 /* SLOW PATH QUEUE */
8818 /*******************/
8819
8820                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8821                                   &sc->spq_dma, "sp_queue",
8822                                   RTE_CACHE_LINE_SIZE) != 0) {
8823                         sc->sp = NULL;
8824                         sc->eq = NULL;
8825                         sc->def_sb = NULL;
8826                         return -1;
8827                 }
8828
8829                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8830
8831 /***************************/
8832 /* FW DECOMPRESSION BUFFER */
8833 /***************************/
8834
8835                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8836                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8837                         sc->spq = NULL;
8838                         sc->sp = NULL;
8839                         sc->eq = NULL;
8840                         sc->def_sb = NULL;
8841                         return -1;
8842                 }
8843
8844                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8845         }
8846
8847         /*************/
8848         /* FASTPATHS */
8849         /*************/
8850
8851         /* allocate DMA memory for each fastpath structure */
8852         for (i = 0; i < sc->num_queues; i++) {
8853                 fp = &sc->fp[i];
8854                 fp->sc = sc;
8855                 fp->index = i;
8856
8857 /*******************/
8858 /* FP STATUS BLOCK */
8859 /*******************/
8860
8861                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8862                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8863                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8864                         PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8865                         return -1;
8866                 } else {
8867                         if (CHIP_IS_E2E3(sc)) {
8868                                 fp->status_block.e2_sb =
8869                                     (struct host_hc_status_block_e2 *)
8870                                     fp->sb_dma.vaddr;
8871                         } else {
8872                                 fp->status_block.e1x_sb =
8873                                     (struct host_hc_status_block_e1x *)
8874                                     fp->sb_dma.vaddr;
8875                         }
8876                 }
8877         }
8878
8879         return 0;
8880 }
8881
8882 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8883 {
8884         struct bnx2x_fastpath *fp;
8885         int i;
8886
8887         for (i = 0; i < sc->num_queues; i++) {
8888                 fp = &sc->fp[i];
8889
8890 /*******************/
8891 /* FP STATUS BLOCK */
8892 /*******************/
8893
8894                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8895         }
8896
8897         /***************************/
8898         /* FW DECOMPRESSION BUFFER */
8899         /***************************/
8900
8901         sc->gz_buf = NULL;
8902
8903         /*******************/
8904         /* SLOW PATH QUEUE */
8905         /*******************/
8906
8907         sc->spq = NULL;
8908
8909         /*************/
8910         /* SLOW PATH */
8911         /*************/
8912
8913         sc->sp = NULL;
8914
8915         /***************/
8916         /* EVENT QUEUE */
8917         /***************/
8918
8919         sc->eq = NULL;
8920
8921         /************************/
8922         /* DEFAULT STATUS BLOCK */
8923         /************************/
8924
8925         sc->def_sb = NULL;
8926
8927 }
8928
8929 /*
8930 * Previous driver DMAE transaction may have occurred when pre-boot stage
8931 * ended and boot began. This would invalidate the addresses of the
8932 * transaction, resulting in was-error bit set in the PCI causing all
8933 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8934 * the interrupt which detected this from the pglueb and the was-done bit
8935 */
8936 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8937 {
8938         uint32_t val;
8939
8940         if (!CHIP_IS_E1x(sc)) {
8941                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8942                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8943                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8944                                1 << SC_FUNC(sc));
8945                 }
8946         }
8947 }
8948
8949 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
8950 {
8951         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
8952                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
8953         if (!rc) {
8954                 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
8955                 return -1;
8956         }
8957
8958         return 0;
8959 }
8960
8961 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
8962 {
8963         struct bnx2x_prev_list_node *tmp;
8964
8965         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
8966                 if ((sc->pcie_bus == tmp->bus) &&
8967                     (sc->pcie_device == tmp->slot) &&
8968                     (SC_PATH(sc) == tmp->path)) {
8969                         return tmp;
8970                 }
8971         }
8972
8973         return NULL;
8974 }
8975
8976 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
8977 {
8978         struct bnx2x_prev_list_node *tmp;
8979         int rc = FALSE;
8980
8981         rte_spinlock_lock(&bnx2x_prev_mtx);
8982
8983         tmp = bnx2x_prev_path_get_entry(sc);
8984         if (tmp) {
8985                 if (tmp->aer) {
8986                         PMD_DRV_LOG(DEBUG,
8987                                     "Path %d/%d/%d was marked by AER",
8988                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
8989                 } else {
8990                         rc = TRUE;
8991                         PMD_DRV_LOG(DEBUG,
8992                                     "Path %d/%d/%d was already cleaned from previous drivers",
8993                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
8994                 }
8995         }
8996
8997         rte_spinlock_unlock(&bnx2x_prev_mtx);
8998
8999         return rc;
9000 }
9001
9002 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9003 {
9004         struct bnx2x_prev_list_node *tmp;
9005
9006         rte_spinlock_lock(&bnx2x_prev_mtx);
9007
9008         /* Check whether the entry for this path already exists */
9009         tmp = bnx2x_prev_path_get_entry(sc);
9010         if (tmp) {
9011                 if (!tmp->aer) {
9012                         PMD_DRV_LOG(DEBUG,
9013                                     "Re-marking AER in path %d/%d/%d",
9014                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9015                 } else {
9016                         PMD_DRV_LOG(DEBUG,
9017                                     "Removing AER indication from path %d/%d/%d",
9018                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9019                         tmp->aer = 0;
9020                 }
9021
9022                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9023                 return 0;
9024         }
9025
9026         rte_spinlock_unlock(&bnx2x_prev_mtx);
9027
9028         /* Create an entry for this path and add it */
9029         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9030                          RTE_CACHE_LINE_SIZE);
9031         if (!tmp) {
9032                 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9033                 return -1;
9034         }
9035
9036         tmp->bus = sc->pcie_bus;
9037         tmp->slot = sc->pcie_device;
9038         tmp->path = SC_PATH(sc);
9039         tmp->aer = 0;
9040         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9041
9042         rte_spinlock_lock(&bnx2x_prev_mtx);
9043
9044         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9045
9046         rte_spinlock_unlock(&bnx2x_prev_mtx);
9047
9048         return 0;
9049 }
9050
9051 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9052 {
9053         int i;
9054
9055         /* only E2 and onwards support FLR */
9056         if (CHIP_IS_E1x(sc)) {
9057                 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9058                 return -1;
9059         }
9060
9061         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9062         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9063                 PMD_DRV_LOG(WARNING,
9064                             "FLR not supported by BC_VER: 0x%08x",
9065                             sc->devinfo.bc_ver);
9066                 return -1;
9067         }
9068
9069         /* Wait for Transaction Pending bit clean */
9070         for (i = 0; i < 4; i++) {
9071                 if (i) {
9072                         DELAY(((1 << (i - 1)) * 100) * 1000);
9073                 }
9074
9075                 if (!bnx2x_is_pcie_pending(sc)) {
9076                         goto clear;
9077                 }
9078         }
9079
9080         PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9081                     "proceeding with reset anyway");
9082
9083 clear:
9084         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9085
9086         return 0;
9087 }
9088
9089 struct bnx2x_mac_vals {
9090         uint32_t xmac_addr;
9091         uint32_t xmac_val;
9092         uint32_t emac_addr;
9093         uint32_t emac_val;
9094         uint32_t umac_addr;
9095         uint32_t umac_val;
9096         uint32_t bmac_addr;
9097         uint32_t bmac_val[2];
9098 };
9099
9100 static void
9101 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9102 {
9103         uint32_t val, base_addr, offset, mask, reset_reg;
9104         uint8_t mac_stopped = FALSE;
9105         uint8_t port = SC_PORT(sc);
9106         uint32_t wb_data[2];
9107
9108         /* reset addresses as they also mark which values were changed */
9109         vals->bmac_addr = 0;
9110         vals->umac_addr = 0;
9111         vals->xmac_addr = 0;
9112         vals->emac_addr = 0;
9113
9114         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9115
9116         if (!CHIP_IS_E3(sc)) {
9117                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9118                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9119                 if ((mask & reset_reg) && val) {
9120                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9121                             : NIG_REG_INGRESS_BMAC0_MEM;
9122                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9123                             : BIGMAC_REGISTER_BMAC_CONTROL;
9124
9125                         /*
9126                          * use rd/wr since we cannot use dmae. This is safe
9127                          * since MCP won't access the bus due to the request
9128                          * to unload, and no function on the path can be
9129                          * loaded at this time.
9130                          */
9131                         wb_data[0] = REG_RD(sc, base_addr + offset);
9132                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9133                         vals->bmac_addr = base_addr + offset;
9134                         vals->bmac_val[0] = wb_data[0];
9135                         vals->bmac_val[1] = wb_data[1];
9136                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9137                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9138                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9139                 }
9140
9141                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9142                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9143                 REG_WR(sc, vals->emac_addr, 0);
9144                 mac_stopped = TRUE;
9145         } else {
9146                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9147                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9148                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9149                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9150                                val & ~(1 << 1));
9151                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9152                                val | (1 << 1));
9153                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9154                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9155                         REG_WR(sc, vals->xmac_addr, 0);
9156                         mac_stopped = TRUE;
9157                 }
9158
9159                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9160                 if (mask & reset_reg) {
9161                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9162                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9163                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9164                         REG_WR(sc, vals->umac_addr, 0);
9165                         mac_stopped = TRUE;
9166                 }
9167         }
9168
9169         if (mac_stopped) {
9170                 DELAY(20000);
9171         }
9172 }
9173
9174 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9175 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9176 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9177 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9178
9179 static void
9180 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9181 {
9182         uint16_t rcq, bd;
9183         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9184
9185         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9186         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9187
9188         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9189         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9190 }
9191
9192 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9193 {
9194         uint32_t reset_reg, tmp_reg = 0, rc;
9195         uint8_t prev_undi = FALSE;
9196         struct bnx2x_mac_vals mac_vals;
9197         uint32_t timer_count = 1000;
9198         uint32_t prev_brb;
9199
9200         /*
9201          * It is possible a previous function received 'common' answer,
9202          * but hasn't loaded yet, therefore creating a scenario of
9203          * multiple functions receiving 'common' on the same path.
9204          */
9205         memset(&mac_vals, 0, sizeof(mac_vals));
9206
9207         if (bnx2x_prev_is_path_marked(sc)) {
9208                 return bnx2x_prev_mcp_done(sc);
9209         }
9210
9211         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9212
9213         /* Reset should be performed after BRB is emptied */
9214         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9215                 /* Close the MAC Rx to prevent BRB from filling up */
9216                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9217
9218                 /* close LLH filters towards the BRB */
9219                 elink_set_rx_filter(&sc->link_params, 0);
9220
9221                 /*
9222                  * Check if the UNDI driver was previously loaded.
9223                  * UNDI driver initializes CID offset for normal bell to 0x7
9224                  */
9225                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9226                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9227                         if (tmp_reg == 0x7) {
9228                                 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9229                                 prev_undi = TRUE;
9230                                 /* clear the UNDI indication */
9231                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9232                                 /* clear possible idle check errors */
9233                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9234                         }
9235                 }
9236
9237                 /* wait until BRB is empty */
9238                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9239                 while (timer_count) {
9240                         prev_brb = tmp_reg;
9241
9242                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9243                         if (!tmp_reg) {
9244                                 break;
9245                         }
9246
9247                         PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9248
9249                         /* reset timer as long as BRB actually gets emptied */
9250                         if (prev_brb > tmp_reg) {
9251                                 timer_count = 1000;
9252                         } else {
9253                                 timer_count--;
9254                         }
9255
9256                         /* If UNDI resides in memory, manually increment it */
9257                         if (prev_undi) {
9258                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9259                         }
9260
9261                         DELAY(10);
9262                 }
9263
9264                 if (!timer_count) {
9265                         PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9266                 }
9267         }
9268
9269         /* No packets are in the pipeline, path is ready for reset */
9270         bnx2x_reset_common(sc);
9271
9272         if (mac_vals.xmac_addr) {
9273                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9274         }
9275         if (mac_vals.umac_addr) {
9276                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9277         }
9278         if (mac_vals.emac_addr) {
9279                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9280         }
9281         if (mac_vals.bmac_addr) {
9282                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9283                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9284         }
9285
9286         rc = bnx2x_prev_mark_path(sc, prev_undi);
9287         if (rc) {
9288                 bnx2x_prev_mcp_done(sc);
9289                 return rc;
9290         }
9291
9292         return bnx2x_prev_mcp_done(sc);
9293 }
9294
9295 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9296 {
9297         int rc;
9298
9299         /* Test if previous unload process was already finished for this path */
9300         if (bnx2x_prev_is_path_marked(sc)) {
9301                 return bnx2x_prev_mcp_done(sc);
9302         }
9303
9304         /*
9305          * If function has FLR capabilities, and existing FW version matches
9306          * the one required, then FLR will be sufficient to clean any residue
9307          * left by previous driver
9308          */
9309         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9310         if (!rc) {
9311                 /* fw version is good */
9312                 rc = bnx2x_do_flr(sc);
9313         }
9314
9315         if (!rc) {
9316                 /* FLR was performed */
9317                 return 0;
9318         }
9319
9320         PMD_DRV_LOG(INFO, "Could not FLR");
9321
9322         /* Close the MCP request, return failure */
9323         rc = bnx2x_prev_mcp_done(sc);
9324         if (!rc) {
9325                 rc = BNX2X_PREV_WAIT_NEEDED;
9326         }
9327
9328         return rc;
9329 }
9330
9331 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9332 {
9333         int time_counter = 10;
9334         uint32_t fw, hw_lock_reg, hw_lock_val;
9335         uint32_t rc = 0;
9336
9337         /*
9338          * Clear HW from errors which may have resulted from an interrupted
9339          * DMAE transaction.
9340          */
9341         bnx2x_prev_interrupted_dmae(sc);
9342
9343         /* Release previously held locks */
9344         if (SC_FUNC(sc) <= 5)
9345                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9346         else
9347                 hw_lock_reg =
9348                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9349
9350         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9351         if (hw_lock_val) {
9352                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9353                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9354                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9355                 }
9356                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9357         }
9358
9359         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9360                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9361         }
9362
9363         do {
9364                 /* Lock MCP using an unload request */
9365                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9366                 if (!fw) {
9367                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9368                         rc = -1;
9369                         break;
9370                 }
9371
9372                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9373                         rc = bnx2x_prev_unload_common(sc);
9374                         break;
9375                 }
9376
9377                 /* non-common reply from MCP might require looping */
9378                 rc = bnx2x_prev_unload_uncommon(sc);
9379                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9380                         break;
9381                 }
9382
9383                 DELAY(20000);
9384         } while (--time_counter);
9385
9386         if (!time_counter || rc) {
9387                 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9388                 rc = -1;
9389         }
9390
9391         return rc;
9392 }
9393
9394 static void
9395 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9396 {
9397         if (!CHIP_IS_E1x(sc)) {
9398                 sc->dcb_state = dcb_on;
9399                 sc->dcbx_enabled = dcbx_enabled;
9400         } else {
9401                 sc->dcb_state = FALSE;
9402                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9403         }
9404         PMD_DRV_LOG(DEBUG,
9405                     "DCB state [%s:%s]",
9406                     dcb_on ? "ON" : "OFF",
9407                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9408                     (dcbx_enabled ==
9409                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9410                     : (dcbx_enabled ==
9411                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9412                     "on-chip with negotiation" : "invalid");
9413 }
9414
9415 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9416 {
9417         int cid_count = BNX2X_L2_MAX_CID(sc);
9418
9419         if (CNIC_SUPPORT(sc)) {
9420                 cid_count += CNIC_CID_MAX;
9421         }
9422
9423         return roundup(cid_count, QM_CID_ROUND);
9424 }
9425
9426 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9427 {
9428         int pri, cos;
9429
9430         uint32_t pri_map = 0;
9431
9432         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9433                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9434                 if (cos < sc->max_cos) {
9435                         sc->prio_to_cos[pri] = cos;
9436                 } else {
9437                         PMD_DRV_LOG(WARNING,
9438                                     "Invalid COS %d for priority %d "
9439                                     "(max COS is %d), setting to 0", cos, pri,
9440                                     (sc->max_cos - 1));
9441                         sc->prio_to_cos[pri] = 0;
9442                 }
9443         }
9444 }
9445
9446 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9447 {
9448         struct {
9449                 uint8_t id;
9450                 uint8_t next;
9451         } pci_cap;
9452         uint16_t status;
9453         struct bnx2x_pci_cap *cap;
9454
9455         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9456                                          RTE_CACHE_LINE_SIZE);
9457         if (!cap) {
9458                 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9459                 return -ENOMEM;
9460         }
9461
9462 #ifndef __FreeBSD__
9463         pci_read(sc, PCI_STATUS, &status, 2);
9464         if (!(status & PCI_STATUS_CAP_LIST)) {
9465 #else
9466         pci_read(sc, PCIR_STATUS, &status, 2);
9467         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9468 #endif
9469                 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9470                 return -1;
9471         }
9472
9473 #ifndef __FreeBSD__
9474         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9475 #else
9476         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9477 #endif
9478         while (pci_cap.next) {
9479                 cap->addr = pci_cap.next & ~3;
9480                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9481                 if (pci_cap.id == 0xff)
9482                         break;
9483                 cap->id = pci_cap.id;
9484                 cap->type = BNX2X_PCI_CAP;
9485                 cap->next = rte_zmalloc("pci_cap",
9486                                         sizeof(struct bnx2x_pci_cap),
9487                                         RTE_CACHE_LINE_SIZE);
9488                 if (!cap->next) {
9489                         PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9490                         return -ENOMEM;
9491                 }
9492                 cap = cap->next;
9493         }
9494
9495         return 0;
9496 }
9497
9498 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9499 {
9500         if (IS_VF(sc)) {
9501                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9502                                         sc->igu_sb_cnt);
9503                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9504                                         sc->igu_sb_cnt);
9505         } else {
9506                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9507                 sc->max_tx_queues = sc->max_rx_queues;
9508         }
9509 }
9510
9511 #define FW_HEADER_LEN 104
9512 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9513 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9514
9515 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9516 {
9517         const char *fwname;
9518         int f;
9519         struct stat st;
9520
9521         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9522                 ? FW_NAME_57711 : FW_NAME_57810;
9523         f = open(fwname, O_RDONLY);
9524         if (f < 0) {
9525                 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9526                 return;
9527         }
9528
9529         if (fstat(f, &st) < 0) {
9530                 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9531                 close(f);
9532                 return;
9533         }
9534
9535         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9536         if (!sc->firmware) {
9537                 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9538                 close(f);
9539                 return;
9540         }
9541
9542         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9543                 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9544                 close(f);
9545                 return;
9546         }
9547         close(f);
9548
9549         sc->fw_len = st.st_size;
9550         if (sc->fw_len < FW_HEADER_LEN) {
9551                 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9552                 return;
9553         }
9554         PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9555 }
9556
9557 static void
9558 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9559 {
9560         uint32_t *src = (uint32_t *) data;
9561         uint32_t i, j, tmp;
9562
9563         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9564                 tmp = rte_be_to_cpu_32(src[j]);
9565                 dst[i].op = (tmp >> 24) & 0xFF;
9566                 dst[i].offset = tmp & 0xFFFFFF;
9567                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9568         }
9569 }
9570
9571 static void
9572 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9573 {
9574         uint16_t *src = (uint16_t *) data;
9575         uint32_t i;
9576
9577         for (i = 0; i < len / 2; ++i)
9578                 dst[i] = rte_be_to_cpu_16(src[i]);
9579 }
9580
9581 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9582 {
9583         uint32_t *src = (uint32_t *) data;
9584         uint32_t i;
9585
9586         for (i = 0; i < len / 4; ++i)
9587                 dst[i] = rte_be_to_cpu_32(src[i]);
9588 }
9589
9590 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9591 {
9592         uint32_t *src = (uint32_t *) data;
9593         uint32_t i, j, tmp;
9594
9595         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9596                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9597                 tmp = rte_be_to_cpu_32(src[j]);
9598                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9599                 dst[i].m2 = tmp & 0xFFFF;
9600                 ++j;
9601                 tmp = rte_be_to_cpu_32(src[j]);
9602                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9603                 dst[i].size = tmp & 0xFFFF;
9604         }
9605 }
9606
9607 /*
9608 * Device attach function.
9609 *
9610 * Allocates device resources, performs secondary chip identification, and
9611 * initializes driver instance variables. This function is called from driver
9612 * load after a successful probe.
9613 *
9614 * Returns:
9615 *   0 = Success, >0 = Failure
9616 */
9617 int bnx2x_attach(struct bnx2x_softc *sc)
9618 {
9619         int rc;
9620
9621         PMD_DRV_LOG(DEBUG, "Starting attach...");
9622
9623         rc = bnx2x_pci_get_caps(sc);
9624         if (rc) {
9625                 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9626                 return rc;
9627         }
9628
9629         sc->state = BNX2X_STATE_CLOSED;
9630
9631         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9632
9633         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9634
9635         /* get PCI capabilites */
9636         bnx2x_probe_pci_caps(sc);
9637
9638         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9639                 uint32_t val;
9640                 pci_read(sc,
9641                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9642                          2);
9643                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9644         } else {
9645                 sc->igu_sb_cnt = 1;
9646         }
9647
9648         /* Init RTE stuff */
9649         bnx2x_init_rte(sc);
9650
9651         if (IS_PF(sc)) {
9652                 /* Enable internal target-read (in case we are probed after PF
9653                  * FLR). Must be done prior to any BAR read access. Only for
9654                  * 57712 and up
9655                  */
9656                 if (!CHIP_IS_E1x(sc)) {
9657                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9658                                1);
9659                         DELAY(200000);
9660                 }
9661
9662                 /* get device info and set params */
9663                 if (bnx2x_get_device_info(sc) != 0) {
9664                         PMD_DRV_LOG(NOTICE, "getting device info");
9665                         return -ENXIO;
9666                 }
9667
9668 /* get phy settings from shmem and 'and' against admin settings */
9669                 bnx2x_get_phy_info(sc);
9670         } else {
9671                 /* Left mac of VF unfilled, PF should set it for VF */
9672                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9673         }
9674
9675         sc->wol = 0;
9676
9677         /* set the default MTU (changed via ifconfig) */
9678         sc->mtu = ETHER_MTU;
9679
9680         bnx2x_set_modes_bitmap(sc);
9681
9682         /* need to reset chip if UNDI was active */
9683         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9684 /* init fw_seq */
9685                 sc->fw_seq =
9686                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9687                      DRV_MSG_SEQ_NUMBER_MASK);
9688                 bnx2x_prev_unload(sc);
9689         }
9690
9691         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9692
9693         /* calculate qm_cid_count */
9694         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9695
9696         sc->max_cos = 1;
9697         bnx2x_init_multi_cos(sc);
9698
9699         return 0;
9700 }
9701
9702 static void
9703 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9704                uint16_t index, uint8_t op, uint8_t update)
9705 {
9706         uint32_t igu_addr = sc->igu_base_addr;
9707         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9708         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9709 }
9710
9711 static void
9712 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9713            uint16_t index, uint8_t op, uint8_t update)
9714 {
9715         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9716                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9717         else {
9718                 uint8_t segment;
9719                 if (CHIP_INT_MODE_IS_BC(sc)) {
9720                         segment = storm;
9721                 } else if (igu_sb_id != sc->igu_dsb_id) {
9722                         segment = IGU_SEG_ACCESS_DEF;
9723                 } else if (storm == ATTENTION_ID) {
9724                         segment = IGU_SEG_ACCESS_ATTN;
9725                 } else {
9726                         segment = IGU_SEG_ACCESS_DEF;
9727                 }
9728                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9729         }
9730 }
9731
9732 static void
9733 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9734                      uint8_t is_pf)
9735 {
9736         uint32_t data, ctl, cnt = 100;
9737         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9738         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9739         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9740             (idu_sb_id / 32) * 4;
9741         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9742         uint32_t func_encode = func |
9743             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9744         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9745
9746         /* Not supported in BC mode */
9747         if (CHIP_INT_MODE_IS_BC(sc)) {
9748                 return;
9749         }
9750
9751         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9752                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9753                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9754
9755         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9756                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9757                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9758
9759         REG_WR(sc, igu_addr_data, data);
9760
9761         mb();
9762
9763         PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9764                     ctl, igu_addr_ctl);
9765         REG_WR(sc, igu_addr_ctl, ctl);
9766
9767         mb();
9768
9769         /* wait for clean up to finish */
9770         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9771                 DELAY(20000);
9772         }
9773
9774         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9775                 PMD_DRV_LOG(DEBUG,
9776                             "Unable to finish IGU cleanup: "
9777                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9778                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9779         }
9780 }
9781
9782 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9783 {
9784         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9785 }
9786
9787 /*******************/
9788 /* ECORE CALLBACKS */
9789 /*******************/
9790
9791 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9792 {
9793         uint32_t val = 0x1400;
9794
9795         PMD_INIT_FUNC_TRACE();
9796
9797         /* reset_common */
9798         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9799                0xd3ffff7f);
9800
9801         if (CHIP_IS_E3(sc)) {
9802                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9803                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9804         }
9805
9806         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9807 }
9808
9809 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9810 {
9811         uint32_t shmem_base[2];
9812         uint32_t shmem2_base[2];
9813
9814         /* Avoid common init in case MFW supports LFA */
9815         if (SHMEM2_RD(sc, size) >
9816             (uint32_t) offsetof(struct shmem2_region,
9817                                 lfa_host_addr[SC_PORT(sc)])) {
9818                 return;
9819         }
9820
9821         shmem_base[0] = sc->devinfo.shmem_base;
9822         shmem2_base[0] = sc->devinfo.shmem2_base;
9823
9824         if (!CHIP_IS_E1x(sc)) {
9825                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9826                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9827         }
9828
9829         elink_common_init_phy(sc, shmem_base, shmem2_base,
9830                               sc->devinfo.chip_id, 0);
9831 }
9832
9833 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9834 {
9835         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9836
9837         val &= ~IGU_PF_CONF_FUNC_EN;
9838
9839         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9840         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9841         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9842 }
9843
9844 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9845 {
9846         uint16_t devctl;
9847         int r_order, w_order;
9848
9849         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9850
9851         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9852         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9853
9854         ecore_init_pxp_arb(sc, r_order, w_order);
9855 }
9856
9857 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9858 {
9859         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9860         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9861         return base + (SC_ABS_FUNC(sc)) * stride;
9862 }
9863
9864 /*
9865  * Called only on E1H or E2.
9866  * When pretending to be PF, the pretend value is the function number 0..7.
9867  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9868  * combination.
9869  */
9870 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9871 {
9872         uint32_t pretend_reg;
9873
9874         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9875                 return -1;
9876
9877         /* get my own pretend register */
9878         pretend_reg = bnx2x_get_pretend_reg(sc);
9879         REG_WR(sc, pretend_reg, pretend_func_val);
9880         REG_RD(sc, pretend_reg);
9881         return 0;
9882 }
9883
9884 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9885 {
9886         int is_required;
9887         uint32_t val;
9888         int port;
9889
9890         is_required = 0;
9891         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9892                SHARED_HW_CFG_FAN_FAILURE_MASK);
9893
9894         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9895                 is_required = 1;
9896         }
9897         /*
9898          * The fan failure mechanism is usually related to the PHY type since
9899          * the power consumption of the board is affected by the PHY. Currently,
9900          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9901          */
9902         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9903                 for (port = PORT_0; port < PORT_MAX; port++) {
9904                         is_required |= elink_fan_failure_det_req(sc,
9905                                                                  sc->
9906                                                                  devinfo.shmem_base,
9907                                                                  sc->
9908                                                                  devinfo.shmem2_base,
9909                                                                  port);
9910                 }
9911         }
9912
9913         if (is_required == 0) {
9914                 return;
9915         }
9916
9917         /* Fan failure is indicated by SPIO 5 */
9918         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9919
9920         /* set to active low mode */
9921         val = REG_RD(sc, MISC_REG_SPIO_INT);
9922         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9923         REG_WR(sc, MISC_REG_SPIO_INT, val);
9924
9925         /* enable interrupt to signal the IGU */
9926         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9927         val |= MISC_SPIO_SPIO5;
9928         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9929 }
9930
9931 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9932 {
9933         uint32_t val;
9934
9935         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9936         if (!CHIP_IS_E1x(sc)) {
9937                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9938         } else {
9939                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9940         }
9941         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9942         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9943         /*
9944          * mask read length error interrupts in brb for parser
9945          * (parsing unit and 'checksum and crc' unit)
9946          * these errors are legal (PU reads fixed length and CAC can cause
9947          * read length error on truncated packets)
9948          */
9949         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9950         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9951         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9952         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9953         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9954         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9955         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9956         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9957         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9958         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
9959         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
9960         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
9961         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
9962         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
9963         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
9964         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
9965         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
9966         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
9967         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
9968
9969         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
9970                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
9971                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
9972         if (!CHIP_IS_E1x(sc)) {
9973                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
9974                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
9975         }
9976         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
9977
9978         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
9979         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
9980         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
9981         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
9982
9983         if (!CHIP_IS_E1x(sc)) {
9984 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
9985                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
9986         }
9987
9988         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
9989         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
9990         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
9991         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
9992 }
9993
9994 /**
9995  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
9996  *
9997  * @sc:     driver handle
9998  */
9999 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10000 {
10001         uint8_t abs_func_id;
10002         uint32_t val;
10003
10004         PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10005
10006         /*
10007          * take the RESET lock to protect undi_unload flow from accessing
10008          * registers while we are resetting the chip
10009          */
10010         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10011
10012         bnx2x_reset_common(sc);
10013
10014         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10015
10016         val = 0xfffc;
10017         if (CHIP_IS_E3(sc)) {
10018                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10019                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10020         }
10021
10022         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10023
10024         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10025
10026         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10027
10028         if (!CHIP_IS_E1x(sc)) {
10029 /*
10030  * 4-port mode or 2-port mode we need to turn off master-enable for
10031  * everyone. After that we turn it back on for self. So, we disregard
10032  * multi-function, and always disable all functions on the given path,
10033  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10034  */
10035                 for (abs_func_id = SC_PATH(sc);
10036                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10037                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10038                                 REG_WR(sc,
10039                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10040                                        1);
10041                                 continue;
10042                         }
10043
10044                         bnx2x_pretend_func(sc, abs_func_id);
10045
10046                         /* clear pf enable */
10047                         bnx2x_pf_disable(sc);
10048
10049                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10050                 }
10051         }
10052
10053         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10054
10055         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10056         bnx2x_init_pxp(sc);
10057
10058 #ifdef __BIG_ENDIAN
10059         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10060         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10061         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10062         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10063         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10064         /* make sure this value is 0 */
10065         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10066
10067         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10068         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10069         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10070         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10071         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10072 #endif
10073
10074         ecore_ilt_init_page_size(sc, INITOP_SET);
10075
10076         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10077                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10078         }
10079
10080         /* let the HW do it's magic... */
10081         DELAY(100000);
10082
10083         /* finish PXP init */
10084
10085         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10086         if (val != 1) {
10087                 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10088                 return -1;
10089         }
10090         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10091         if (val != 1) {
10092                 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10093                 return -1;
10094         }
10095
10096         /*
10097          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10098          * entries with value "0" and valid bit on. This needs to be done by the
10099          * first PF that is loaded in a path (i.e. common phase)
10100          */
10101         if (!CHIP_IS_E1x(sc)) {
10102 /*
10103  * In E2 there is a bug in the timers block that can cause function 6 / 7
10104  * (i.e. vnic3) to start even if it is marked as "scan-off".
10105  * This occurs when a different function (func2,3) is being marked
10106  * as "scan-off". Real-life scenario for example: if a driver is being
10107  * load-unloaded while func6,7 are down. This will cause the timer to access
10108  * the ilt, translate to a logical address and send a request to read/write.
10109  * Since the ilt for the function that is down is not valid, this will cause
10110  * a translation error which is unrecoverable.
10111  * The Workaround is intended to make sure that when this happens nothing
10112  * fatal will occur. The workaround:
10113  *  1.  First PF driver which loads on a path will:
10114  *      a.  After taking the chip out of reset, by using pretend,
10115  *          it will write "0" to the following registers of
10116  *          the other vnics.
10117  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10118  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10119  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10120  *          And for itself it will write '1' to
10121  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10122  *          dmae-operations (writing to pram for example.)
10123  *          note: can be done for only function 6,7 but cleaner this
10124  *            way.
10125  *      b.  Write zero+valid to the entire ILT.
10126  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10127  *          VNIC3 (of that port). The range allocated will be the
10128  *          entire ILT. This is needed to prevent  ILT range error.
10129  *  2.  Any PF driver load flow:
10130  *      a.  ILT update with the physical addresses of the allocated
10131  *          logical pages.
10132  *      b.  Wait 20msec. - note that this timeout is needed to make
10133  *          sure there are no requests in one of the PXP internal
10134  *          queues with "old" ILT addresses.
10135  *      c.  PF enable in the PGLC.
10136  *      d.  Clear the was_error of the PF in the PGLC. (could have
10137  *          occurred while driver was down)
10138  *      e.  PF enable in the CFC (WEAK + STRONG)
10139  *      f.  Timers scan enable
10140  *  3.  PF driver unload flow:
10141  *      a.  Clear the Timers scan_en.
10142  *      b.  Polling for scan_on=0 for that PF.
10143  *      c.  Clear the PF enable bit in the PXP.
10144  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10145  *      e.  Write zero+valid to all ILT entries (The valid bit must
10146  *          stay set)
10147  *      f.  If this is VNIC 3 of a port then also init
10148  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10149  *          to the last enrty in the ILT.
10150  *
10151  *      Notes:
10152  *      Currently the PF error in the PGLC is non recoverable.
10153  *      In the future the there will be a recovery routine for this error.
10154  *      Currently attention is masked.
10155  *      Having an MCP lock on the load/unload process does not guarantee that
10156  *      there is no Timer disable during Func6/7 enable. This is because the
10157  *      Timers scan is currently being cleared by the MCP on FLR.
10158  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10159  *      there is error before clearing it. But the flow above is simpler and
10160  *      more general.
10161  *      All ILT entries are written by zero+valid and not just PF6/7
10162  *      ILT entries since in the future the ILT entries allocation for
10163  *      PF-s might be dynamic.
10164  */
10165                 struct ilt_client_info ilt_cli;
10166                 struct ecore_ilt ilt;
10167
10168                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10169                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10170
10171 /* initialize dummy TM client */
10172                 ilt_cli.start = 0;
10173                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10174                 ilt_cli.client_num = ILT_CLIENT_TM;
10175
10176 /*
10177  * Step 1: set zeroes to all ilt page entries with valid bit on
10178  * Step 2: set the timers first/last ilt entry to point
10179  * to the entire range to prevent ILT range error for 3rd/4th
10180  * vnic (this code assumes existence of the vnic)
10181  *
10182  * both steps performed by call to ecore_ilt_client_init_op()
10183  * with dummy TM client
10184  *
10185  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10186  * and his brother are split registers
10187  */
10188
10189                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10190                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10191                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10192
10193                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10194                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10195                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10196         }
10197
10198         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10199         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10200
10201         if (!CHIP_IS_E1x(sc)) {
10202                 int factor = 0;
10203
10204                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10205                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10206
10207 /* let the HW do it's magic... */
10208                 do {
10209                         DELAY(200000);
10210                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10211                 } while (factor-- && (val != 1));
10212
10213                 if (val != 1) {
10214                         PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10215                         return -1;
10216                 }
10217         }
10218
10219         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10220
10221         /* clean the DMAE memory */
10222         sc->dmae_ready = 1;
10223         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10224
10225         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10226
10227         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10228
10229         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10230
10231         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10232
10233         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10234         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10235         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10236         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10237
10238         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10239
10240         /* QM queues pointers table */
10241         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10242
10243         /* soft reset pulse */
10244         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10245         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10246
10247         if (CNIC_SUPPORT(sc))
10248                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10249
10250         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10251         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10252
10253         if (!CHIP_REV_IS_SLOW(sc)) {
10254 /* enable hw interrupt from doorbell Q */
10255                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10256         }
10257
10258         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10259
10260         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10261         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10262         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10263
10264         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10265                 if (IS_MF_AFEX(sc)) {
10266                         /*
10267                          * configure that AFEX and VLAN headers must be
10268                          * received in AFEX mode
10269                          */
10270                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10271                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10272                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10273                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10274                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10275                 } else {
10276                         /*
10277                          * Bit-map indicating which L2 hdrs may appear
10278                          * after the basic Ethernet header
10279                          */
10280                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10281                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10282                 }
10283         }
10284
10285         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10286         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10287         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10288         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10289
10290         if (!CHIP_IS_E1x(sc)) {
10291 /* reset VFC memories */
10292                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10293                        VFC_MEMORIES_RST_REG_CAM_RST |
10294                        VFC_MEMORIES_RST_REG_RAM_RST);
10295                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10296                        VFC_MEMORIES_RST_REG_CAM_RST |
10297                        VFC_MEMORIES_RST_REG_RAM_RST);
10298
10299                 DELAY(20000);
10300         }
10301
10302         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10303         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10304         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10305         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10306
10307         /* sync semi rtc */
10308         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10309         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10310
10311         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10312         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10313         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10314
10315         if (!CHIP_IS_E1x(sc)) {
10316                 if (IS_MF_AFEX(sc)) {
10317                         /*
10318                          * configure that AFEX and VLAN headers must be
10319                          * sent in AFEX mode
10320                          */
10321                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10322                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10323                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10324                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10325                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10326                 } else {
10327                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10328                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10329                 }
10330         }
10331
10332         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10333
10334         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10335
10336         if (CNIC_SUPPORT(sc)) {
10337                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10338                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10339                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10340                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10341                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10342                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10343                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10344                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10345                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10346                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10347         }
10348         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10349
10350         if (sizeof(union cdu_context) != 1024) {
10351 /* we currently assume that a context is 1024 bytes */
10352                 PMD_DRV_LOG(NOTICE,
10353                             "please adjust the size of cdu_context(%ld)",
10354                             (long)sizeof(union cdu_context));
10355         }
10356
10357         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10358         val = (4 << 24) + (0 << 12) + 1024;
10359         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10360
10361         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10362
10363         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10364         /* enable context validation interrupt from CFC */
10365         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10366
10367         /* set the thresholds to prevent CFC/CDU race */
10368         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10369         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10370
10371         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10372                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10373         }
10374
10375         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10376         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10377
10378         /* Reset PCIE errors for debug */
10379         REG_WR(sc, 0x2814, 0xffffffff);
10380         REG_WR(sc, 0x3820, 0xffffffff);
10381
10382         if (!CHIP_IS_E1x(sc)) {
10383                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10384                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10385                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10386                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10387                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10388                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10389                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10390                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10391                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10392                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10393                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10394         }
10395
10396         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10397
10398         /* in E3 this done in per-port section */
10399         if (!CHIP_IS_E3(sc))
10400                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10401
10402         if (CHIP_IS_E1H(sc)) {
10403 /* not applicable for E2 (and above ...) */
10404                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10405         }
10406
10407         if (CHIP_REV_IS_SLOW(sc)) {
10408                 DELAY(200000);
10409         }
10410
10411         /* finish CFC init */
10412         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10413         if (val != 1) {
10414                 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10415                 return -1;
10416         }
10417         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10418         if (val != 1) {
10419                 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10420                 return -1;
10421         }
10422         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10423         if (val != 1) {
10424                 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10425                 return -1;
10426         }
10427         REG_WR(sc, CFC_REG_DEBUG0, 0);
10428
10429         bnx2x_setup_fan_failure_detection(sc);
10430
10431         /* clear PXP2 attentions */
10432         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10433
10434         bnx2x_enable_blocks_attention(sc);
10435
10436         if (!CHIP_REV_IS_SLOW(sc)) {
10437                 ecore_enable_blocks_parity(sc);
10438         }
10439
10440         if (!BNX2X_NOMCP(sc)) {
10441                 if (CHIP_IS_E1x(sc)) {
10442                         bnx2x_common_init_phy(sc);
10443                 }
10444         }
10445
10446         return 0;
10447 }
10448
10449 /**
10450  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10451  *
10452  * @sc:     driver handle
10453  */
10454 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10455 {
10456         int rc = bnx2x_init_hw_common(sc);
10457
10458         if (rc) {
10459                 return rc;
10460         }
10461
10462         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10463         if (!BNX2X_NOMCP(sc)) {
10464                 bnx2x_common_init_phy(sc);
10465         }
10466
10467         return 0;
10468 }
10469
10470 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10471 {
10472         int port = SC_PORT(sc);
10473         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10474         uint32_t low, high;
10475         uint32_t val;
10476
10477         PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10478
10479         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10480
10481         ecore_init_block(sc, BLOCK_MISC, init_phase);
10482         ecore_init_block(sc, BLOCK_PXP, init_phase);
10483         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10484
10485         /*
10486          * Timers bug workaround: disables the pf_master bit in pglue at
10487          * common phase, we need to enable it here before any dmae access are
10488          * attempted. Therefore we manually added the enable-master to the
10489          * port phase (it also happens in the function phase)
10490          */
10491         if (!CHIP_IS_E1x(sc)) {
10492                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10493         }
10494
10495         ecore_init_block(sc, BLOCK_ATC, init_phase);
10496         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10497         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10498         ecore_init_block(sc, BLOCK_QM, init_phase);
10499
10500         ecore_init_block(sc, BLOCK_TCM, init_phase);
10501         ecore_init_block(sc, BLOCK_UCM, init_phase);
10502         ecore_init_block(sc, BLOCK_CCM, init_phase);
10503         ecore_init_block(sc, BLOCK_XCM, init_phase);
10504
10505         /* QM cid (connection) count */
10506         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10507
10508         if (CNIC_SUPPORT(sc)) {
10509                 ecore_init_block(sc, BLOCK_TM, init_phase);
10510                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10511                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10512         }
10513
10514         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10515
10516         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10517
10518         if (CHIP_IS_E1H(sc)) {
10519                 if (IS_MF(sc)) {
10520                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10521                 } else if (sc->mtu > 4096) {
10522                         if (BNX2X_ONE_PORT(sc)) {
10523                                 low = 160;
10524                         } else {
10525                                 val = sc->mtu;
10526                                 /* (24*1024 + val*4)/256 */
10527                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10528                         }
10529                 } else {
10530                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10531                 }
10532                 high = (low + 56);      /* 14*1024/256 */
10533                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10534                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10535         }
10536
10537         if (CHIP_IS_MODE_4_PORT(sc)) {
10538                 REG_WR(sc, SC_PORT(sc) ?
10539                        BRB1_REG_MAC_GUARANTIED_1 :
10540                        BRB1_REG_MAC_GUARANTIED_0, 40);
10541         }
10542
10543         ecore_init_block(sc, BLOCK_PRS, init_phase);
10544         if (CHIP_IS_E3B0(sc)) {
10545                 if (IS_MF_AFEX(sc)) {
10546                         /* configure headers for AFEX mode */
10547                         if (SC_PORT(sc)) {
10548                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10549                                        0xE);
10550                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10551                                        0x6);
10552                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10553                         } else {
10554                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10555                                        0xE);
10556                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10557                                        0x6);
10558                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10559                         }
10560                 } else {
10561                         /* Ovlan exists only if we are in multi-function +
10562                          * switch-dependent mode, in switch-independent there
10563                          * is no ovlan headers
10564                          */
10565                         REG_WR(sc, SC_PORT(sc) ?
10566                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10567                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10568                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10569                 }
10570         }
10571
10572         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10573         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10574         ecore_init_block(sc, BLOCK_USDM, init_phase);
10575         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10576
10577         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10578         ecore_init_block(sc, BLOCK_USEM, init_phase);
10579         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10580         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10581
10582         ecore_init_block(sc, BLOCK_UPB, init_phase);
10583         ecore_init_block(sc, BLOCK_XPB, init_phase);
10584
10585         ecore_init_block(sc, BLOCK_PBF, init_phase);
10586
10587         if (CHIP_IS_E1x(sc)) {
10588 /* configure PBF to work without PAUSE mtu 9000 */
10589                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10590
10591 /* update threshold */
10592                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10593 /* update init credit */
10594                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10595                        (9040 / 16) + 553 - 22);
10596
10597 /* probe changes */
10598                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10599                 DELAY(50);
10600                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10601         }
10602
10603         if (CNIC_SUPPORT(sc)) {
10604                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10605         }
10606
10607         ecore_init_block(sc, BLOCK_CDU, init_phase);
10608         ecore_init_block(sc, BLOCK_CFC, init_phase);
10609         ecore_init_block(sc, BLOCK_HC, init_phase);
10610         ecore_init_block(sc, BLOCK_IGU, init_phase);
10611         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10612         /* init aeu_mask_attn_func_0/1:
10613          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10614          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10615          *             bits 4-7 are used for "per vn group attention" */
10616         val = IS_MF(sc) ? 0xF7 : 0x7;
10617         val |= 0x10;
10618         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10619
10620         ecore_init_block(sc, BLOCK_NIG, init_phase);
10621
10622         if (!CHIP_IS_E1x(sc)) {
10623 /* Bit-map indicating which L2 hdrs may appear after the
10624  * basic Ethernet header
10625  */
10626                 if (IS_MF_AFEX(sc)) {
10627                         REG_WR(sc, SC_PORT(sc) ?
10628                                NIG_REG_P1_HDRS_AFTER_BASIC :
10629                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10630                 } else {
10631                         REG_WR(sc, SC_PORT(sc) ?
10632                                NIG_REG_P1_HDRS_AFTER_BASIC :
10633                                NIG_REG_P0_HDRS_AFTER_BASIC,
10634                                IS_MF_SD(sc) ? 7 : 6);
10635                 }
10636
10637                 if (CHIP_IS_E3(sc)) {
10638                         REG_WR(sc, SC_PORT(sc) ?
10639                                NIG_REG_LLH1_MF_MODE :
10640                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10641                 }
10642         }
10643         if (!CHIP_IS_E3(sc)) {
10644                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10645         }
10646
10647         /* 0x2 disable mf_ov, 0x1 enable */
10648         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10649                (IS_MF_SD(sc) ? 0x1 : 0x2));
10650
10651         if (!CHIP_IS_E1x(sc)) {
10652                 val = 0;
10653                 switch (sc->devinfo.mf_info.mf_mode) {
10654                 case MULTI_FUNCTION_SD:
10655                         val = 1;
10656                         break;
10657                 case MULTI_FUNCTION_SI:
10658                 case MULTI_FUNCTION_AFEX:
10659                         val = 2;
10660                         break;
10661                 }
10662
10663                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10664                             NIG_REG_LLH0_CLS_TYPE), val);
10665         }
10666         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10667         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10668         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10669
10670         /* If SPIO5 is set to generate interrupts, enable it for this port */
10671         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10672         if (val & MISC_SPIO_SPIO5) {
10673                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10674                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10675                 val = REG_RD(sc, reg_addr);
10676                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10677                 REG_WR(sc, reg_addr, val);
10678         }
10679
10680         return 0;
10681 }
10682
10683 static uint32_t
10684 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10685                        uint32_t expected, uint32_t poll_count)
10686 {
10687         uint32_t cur_cnt = poll_count;
10688         uint32_t val;
10689
10690         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10691                 DELAY(FLR_WAIT_INTERVAL);
10692         }
10693
10694         return val;
10695 }
10696
10697 static int
10698 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10699                               __rte_unused const char *msg, uint32_t poll_cnt)
10700 {
10701         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10702
10703         if (val != 0) {
10704                 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10705                 return -1;
10706         }
10707
10708         return 0;
10709 }
10710
10711 /* Common routines with VF FLR cleanup */
10712 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10713 {
10714         /* adjust polling timeout */
10715         if (CHIP_REV_IS_EMUL(sc)) {
10716                 return FLR_POLL_CNT * 2000;
10717         }
10718
10719         if (CHIP_REV_IS_FPGA(sc)) {
10720                 return FLR_POLL_CNT * 120;
10721         }
10722
10723         return FLR_POLL_CNT;
10724 }
10725
10726 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10727 {
10728         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10729         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10730                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10731                                           "CFC PF usage counter timed out",
10732                                           poll_cnt)) {
10733                 return -1;
10734         }
10735
10736         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10737         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10738                                           DORQ_REG_PF_USAGE_CNT,
10739                                           "DQ PF usage counter timed out",
10740                                           poll_cnt)) {
10741                 return -1;
10742         }
10743
10744         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10745         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10746                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10747                                           "QM PF usage counter timed out",
10748                                           poll_cnt)) {
10749                 return -1;
10750         }
10751
10752         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10753         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10754                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10755                                           "Timers VNIC usage counter timed out",
10756                                           poll_cnt)) {
10757                 return -1;
10758         }
10759
10760         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10761                                           TM_REG_LIN0_NUM_SCANS +
10762                                           4 * SC_PORT(sc),
10763                                           "Timers NUM_SCANS usage counter timed out",
10764                                           poll_cnt)) {
10765                 return -1;
10766         }
10767
10768         /* Wait DMAE PF usage counter to zero */
10769         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10770                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10771                                           "DMAE dommand register timed out",
10772                                           poll_cnt)) {
10773                 return -1;
10774         }
10775
10776         return 0;
10777 }
10778
10779 #define OP_GEN_PARAM(param)                                            \
10780         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10781 #define OP_GEN_TYPE(type)                                           \
10782         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10783 #define OP_GEN_AGG_VECT(index)                                             \
10784         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10785
10786 static int
10787 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10788                      uint32_t poll_cnt)
10789 {
10790         uint32_t op_gen_command = 0;
10791         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10792                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10793         int ret = 0;
10794
10795         if (REG_RD(sc, comp_addr)) {
10796                 PMD_DRV_LOG(NOTICE,
10797                             "Cleanup complete was not 0 before sending");
10798                 return -1;
10799         }
10800
10801         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10802         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10803         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10804         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10805
10806         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10807
10808         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10809                 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10810                 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10811                             (REG_RD(sc, comp_addr)));
10812                 rte_panic("FLR cleanup failed");
10813                 return -1;
10814         }
10815
10816         /* Zero completion for nxt FLR */
10817         REG_WR(sc, comp_addr, 0);
10818
10819         return ret;
10820 }
10821
10822 static void
10823 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10824                        uint32_t poll_count)
10825 {
10826         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10827         uint32_t cur_cnt = poll_count;
10828
10829         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10830         crd = crd_start = REG_RD(sc, regs->crd);
10831         init_crd = REG_RD(sc, regs->init_crd);
10832
10833         while ((crd != init_crd) &&
10834                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10835                 (init_crd - crd_start))) {
10836                 if (cur_cnt--) {
10837                         DELAY(FLR_WAIT_INTERVAL);
10838                         crd = REG_RD(sc, regs->crd);
10839                         crd_freed = REG_RD(sc, regs->crd_freed);
10840                 } else {
10841                         break;
10842                 }
10843         }
10844 }
10845
10846 static void
10847 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10848                        uint32_t poll_count)
10849 {
10850         uint32_t occup, to_free, freed, freed_start;
10851         uint32_t cur_cnt = poll_count;
10852
10853         occup = to_free = REG_RD(sc, regs->lines_occup);
10854         freed = freed_start = REG_RD(sc, regs->lines_freed);
10855
10856         while (occup &&
10857                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10858                 to_free)) {
10859                 if (cur_cnt--) {
10860                         DELAY(FLR_WAIT_INTERVAL);
10861                         occup = REG_RD(sc, regs->lines_occup);
10862                         freed = REG_RD(sc, regs->lines_freed);
10863                 } else {
10864                         break;
10865                 }
10866         }
10867 }
10868
10869 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10870 {
10871         struct pbf_pN_cmd_regs cmd_regs[] = {
10872                 {0, (CHIP_IS_E3B0(sc)) ?
10873                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10874                  (CHIP_IS_E3B0(sc)) ?
10875                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10876                 {1, (CHIP_IS_E3B0(sc)) ?
10877                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10878                  (CHIP_IS_E3B0(sc)) ?
10879                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10880                 {4, (CHIP_IS_E3B0(sc)) ?
10881                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10882                  (CHIP_IS_E3B0(sc)) ?
10883                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10884                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10885         };
10886
10887         struct pbf_pN_buf_regs buf_regs[] = {
10888                 {0, (CHIP_IS_E3B0(sc)) ?
10889                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10890                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10891                  (CHIP_IS_E3B0(sc)) ?
10892                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10893                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10894                 {1, (CHIP_IS_E3B0(sc)) ?
10895                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10896                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10897                  (CHIP_IS_E3B0(sc)) ?
10898                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10899                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10900                 {4, (CHIP_IS_E3B0(sc)) ?
10901                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10902                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10903                  (CHIP_IS_E3B0(sc)) ?
10904                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10905                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10906         };
10907
10908         uint32_t i;
10909
10910         /* Verify the command queues are flushed P0, P1, P4 */
10911         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10912                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10913         }
10914
10915         /* Verify the transmission buffers are flushed P0, P1, P4 */
10916         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10917                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10918         }
10919 }
10920
10921 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10922 {
10923         __rte_unused uint32_t val;
10924
10925         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10926         PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10927
10928         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10929         PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10930
10931         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10932         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10933
10934         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10935         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10936
10937         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10938         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10939
10940         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10941         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10942
10943         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10944         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10945
10946         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10947         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10948                     val);
10949 }
10950
10951 /**
10952  *      bnx2x_pf_flr_clnup
10953  *      a. re-enable target read on the PF
10954  *      b. poll cfc per function usgae counter
10955  *      c. poll the qm perfunction usage counter
10956  *      d. poll the tm per function usage counter
10957  *      e. poll the tm per function scan-done indication
10958  *      f. clear the dmae channel associated wit hthe PF
10959  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
10960  *      h. call the common flr cleanup code with -1 (pf indication)
10961  */
10962 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
10963 {
10964         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
10965
10966         /* Re-enable PF target read access */
10967         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10968
10969         /* Poll HW usage counters */
10970         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
10971                 return -1;
10972         }
10973
10974         /* Zero the igu 'trailing edge' and 'leading edge' */
10975
10976         /* Send the FW cleanup command */
10977         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
10978                 return -1;
10979         }
10980
10981         /* ATC cleanup */
10982
10983         /* Verify TX hw is flushed */
10984         bnx2x_tx_hw_flushed(sc, poll_cnt);
10985
10986         /* Wait 100ms (not adjusted according to platform) */
10987         DELAY(100000);
10988
10989         /* Verify no pending pci transactions */
10990         if (bnx2x_is_pcie_pending(sc)) {
10991                 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
10992         }
10993
10994         /* Debug */
10995         bnx2x_hw_enable_status(sc);
10996
10997         /*
10998          * Master enable - Due to WB DMAE writes performed before this
10999          * register is re-initialized as part of the regular function init
11000          */
11001         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11002
11003         return 0;
11004 }
11005
11006 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11007 {
11008         int port = SC_PORT(sc);
11009         int func = SC_FUNC(sc);
11010         int init_phase = PHASE_PF0 + func;
11011         struct ecore_ilt *ilt = sc->ilt;
11012         uint16_t cdu_ilt_start;
11013         uint32_t addr, val;
11014         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11015         int main_mem_width, rc;
11016         uint32_t i;
11017
11018         PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11019
11020         /* FLR cleanup */
11021         if (!CHIP_IS_E1x(sc)) {
11022                 rc = bnx2x_pf_flr_clnup(sc);
11023                 if (rc) {
11024                         PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11025                         return rc;
11026                 }
11027         }
11028
11029         /* set MSI reconfigure capability */
11030         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11031                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11032                 val = REG_RD(sc, addr);
11033                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11034                 REG_WR(sc, addr, val);
11035         }
11036
11037         ecore_init_block(sc, BLOCK_PXP, init_phase);
11038         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11039
11040         ilt = sc->ilt;
11041         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11042
11043         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11044                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11045                 ilt->lines[cdu_ilt_start + i].page_mapping =
11046                     (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11047                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11048         }
11049         ecore_ilt_init_op(sc, INITOP_SET);
11050
11051         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11052
11053         if (!CHIP_IS_E1x(sc)) {
11054                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11055
11056 /* Turn on a single ISR mode in IGU if driver is going to use
11057  * INT#x or MSI
11058  */
11059                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11060                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11061                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11062                 }
11063
11064 /*
11065  * Timers workaround bug: function init part.
11066  * Need to wait 20msec after initializing ILT,
11067  * needed to make sure there are no requests in
11068  * one of the PXP internal queues with "old" ILT addresses
11069  */
11070                 DELAY(20000);
11071
11072 /*
11073  * Master enable - Due to WB DMAE writes performed before this
11074  * register is re-initialized as part of the regular function
11075  * init
11076  */
11077                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11078 /* Enable the function in IGU */
11079                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11080         }
11081
11082         sc->dmae_ready = 1;
11083
11084         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11085
11086         if (!CHIP_IS_E1x(sc))
11087                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11088
11089         ecore_init_block(sc, BLOCK_ATC, init_phase);
11090         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11091         ecore_init_block(sc, BLOCK_NIG, init_phase);
11092         ecore_init_block(sc, BLOCK_SRC, init_phase);
11093         ecore_init_block(sc, BLOCK_MISC, init_phase);
11094         ecore_init_block(sc, BLOCK_TCM, init_phase);
11095         ecore_init_block(sc, BLOCK_UCM, init_phase);
11096         ecore_init_block(sc, BLOCK_CCM, init_phase);
11097         ecore_init_block(sc, BLOCK_XCM, init_phase);
11098         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11099         ecore_init_block(sc, BLOCK_USEM, init_phase);
11100         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11101         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11102
11103         if (!CHIP_IS_E1x(sc))
11104                 REG_WR(sc, QM_REG_PF_EN, 1);
11105
11106         if (!CHIP_IS_E1x(sc)) {
11107                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11108                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11109                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11110                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11111         }
11112         ecore_init_block(sc, BLOCK_QM, init_phase);
11113
11114         ecore_init_block(sc, BLOCK_TM, init_phase);
11115         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11116
11117         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11118         ecore_init_block(sc, BLOCK_PRS, init_phase);
11119         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11120         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11121         ecore_init_block(sc, BLOCK_USDM, init_phase);
11122         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11123         ecore_init_block(sc, BLOCK_UPB, init_phase);
11124         ecore_init_block(sc, BLOCK_XPB, init_phase);
11125         ecore_init_block(sc, BLOCK_PBF, init_phase);
11126         if (!CHIP_IS_E1x(sc))
11127                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11128
11129         ecore_init_block(sc, BLOCK_CDU, init_phase);
11130
11131         ecore_init_block(sc, BLOCK_CFC, init_phase);
11132
11133         if (!CHIP_IS_E1x(sc))
11134                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11135
11136         if (IS_MF(sc)) {
11137                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11138                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11139         }
11140
11141         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11142
11143         /* HC init per function */
11144         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11145                 if (CHIP_IS_E1H(sc)) {
11146                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11147
11148                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11149                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11150                 }
11151                 ecore_init_block(sc, BLOCK_HC, init_phase);
11152
11153         } else {
11154                 uint32_t num_segs, sb_idx, prod_offset;
11155
11156                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11157
11158                 if (!CHIP_IS_E1x(sc)) {
11159                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11160                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11161                 }
11162
11163                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11164
11165                 if (!CHIP_IS_E1x(sc)) {
11166                         int dsb_idx = 0;
11167         /**
11168          * Producer memory:
11169          * E2 mode: address 0-135 match to the mapping memory;
11170          * 136 - PF0 default prod; 137 - PF1 default prod;
11171          * 138 - PF2 default prod; 139 - PF3 default prod;
11172          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11173          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11174          * 144-147 reserved.
11175          *
11176          * E1.5 mode - In backward compatible mode;
11177          * for non default SB; each even line in the memory
11178          * holds the U producer and each odd line hold
11179          * the C producer. The first 128 producers are for
11180          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11181          * producers are for the DSB for each PF.
11182          * Each PF has five segments: (the order inside each
11183          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11184          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11185          * 144-147 attn prods;
11186          */
11187                         /* non-default-status-blocks */
11188                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11189                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11190                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11191                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11192                                     num_segs;
11193
11194                                 for (i = 0; i < num_segs; i++) {
11195                                         addr = IGU_REG_PROD_CONS_MEMORY +
11196                                             (prod_offset + i) * 4;
11197                                         REG_WR(sc, addr, 0);
11198                                 }
11199                                 /* send consumer update with value 0 */
11200                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11201                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11202                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11203                         }
11204
11205                         /* default-status-blocks */
11206                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11207                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11208
11209                         if (CHIP_IS_MODE_4_PORT(sc))
11210                                 dsb_idx = SC_FUNC(sc);
11211                         else
11212                                 dsb_idx = SC_VN(sc);
11213
11214                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11215                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11216                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11217
11218                         /*
11219                          * igu prods come in chunks of E1HVN_MAX (4) -
11220                          * does not matters what is the current chip mode
11221                          */
11222                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11223                                 addr = IGU_REG_PROD_CONS_MEMORY +
11224                                     (prod_offset + i) * 4;
11225                                 REG_WR(sc, addr, 0);
11226                         }
11227                         /* send consumer update with 0 */
11228                         if (CHIP_INT_MODE_IS_BC(sc)) {
11229                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11230                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11231                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11232                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11233                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11234                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11235                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11236                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11237                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11238                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11239                         } else {
11240                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11241                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11242                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11243                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11244                         }
11245                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11246
11247                         /* !!! these should become driver const once
11248                            rf-tool supports split-68 const */
11249                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11250                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11251                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11252                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11253                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11254                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11255                 }
11256         }
11257
11258         /* Reset PCIE errors for debug */
11259         REG_WR(sc, 0x2114, 0xffffffff);
11260         REG_WR(sc, 0x2120, 0xffffffff);
11261
11262         if (CHIP_IS_E1x(sc)) {
11263                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11264                 main_mem_base = HC_REG_MAIN_MEMORY +
11265                     SC_PORT(sc) * (main_mem_size * 4);
11266                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11267                 main_mem_width = 8;
11268
11269                 val = REG_RD(sc, main_mem_prty_clr);
11270                 if (val) {
11271                         PMD_DRV_LOG(DEBUG,
11272                                     "Parity errors in HC block during function init (0x%x)!",
11273                                     val);
11274                 }
11275
11276 /* Clear "false" parity errors in MSI-X table */
11277                 for (i = main_mem_base;
11278                      i < main_mem_base + main_mem_size * 4;
11279                      i += main_mem_width) {
11280                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11281                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11282                                        i, main_mem_width / 4);
11283                 }
11284 /* Clear HC parity attention */
11285                 REG_RD(sc, main_mem_prty_clr);
11286         }
11287
11288         /* Enable STORMs SP logging */
11289         REG_WR8(sc, BAR_USTRORM_INTMEM +
11290                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11291         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11292                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11293         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11294                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11295         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11296                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11297
11298         elink_phy_probe(&sc->link_params);
11299
11300         return 0;
11301 }
11302
11303 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11304 {
11305         if (!BNX2X_NOMCP(sc)) {
11306                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11307         } else {
11308                 if (!CHIP_REV_IS_SLOW(sc)) {
11309                         PMD_DRV_LOG(WARNING,
11310                                     "Bootcode is missing - cannot reset link");
11311                 }
11312         }
11313 }
11314
11315 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11316 {
11317         int port = SC_PORT(sc);
11318         uint32_t val;
11319
11320         /* reset physical Link */
11321         bnx2x_link_reset(sc);
11322
11323         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11324
11325         /* Do not rcv packets to BRB */
11326         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11327         /* Do not direct rcv packets that are not for MCP to the BRB */
11328         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11329                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11330
11331         /* Configure AEU */
11332         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11333
11334         DELAY(100000);
11335
11336         /* Check for BRB port occupancy */
11337         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11338         if (val) {
11339                 PMD_DRV_LOG(DEBUG,
11340                             "BRB1 is not empty, %d blocks are occupied", val);
11341         }
11342 }
11343
11344 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11345 {
11346         int reg;
11347         uint32_t wb_write[2];
11348
11349         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11350
11351         wb_write[0] = ONCHIP_ADDR1(addr);
11352         wb_write[1] = ONCHIP_ADDR2(addr);
11353         REG_WR_DMAE(sc, reg, wb_write, 2);
11354 }
11355
11356 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11357 {
11358         uint32_t i, base = FUNC_ILT_BASE(func);
11359         for (i = base; i < base + ILT_PER_FUNC; i++) {
11360                 bnx2x_ilt_wr(sc, i, 0);
11361         }
11362 }
11363
11364 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11365 {
11366         struct bnx2x_fastpath *fp;
11367         int port = SC_PORT(sc);
11368         int func = SC_FUNC(sc);
11369         int i;
11370
11371         /* Disable the function in the FW */
11372         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11373         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11374         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11375         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11376
11377         /* FP SBs */
11378         FOR_EACH_ETH_QUEUE(sc, i) {
11379                 fp = &sc->fp[i];
11380                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11381                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11382                         SB_DISABLED);
11383         }
11384
11385         /* SP SB */
11386         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11387                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11388
11389         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11390                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11391                        0);
11392         }
11393
11394         /* Configure IGU */
11395         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11396                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11397                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11398         } else {
11399                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11400                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11401         }
11402
11403         if (CNIC_LOADED(sc)) {
11404 /* Disable Timer scan */
11405                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11406 /*
11407  * Wait for at least 10ms and up to 2 second for the timers
11408  * scan to complete
11409  */
11410                 for (i = 0; i < 200; i++) {
11411                         DELAY(10000);
11412                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11413                                 break;
11414                 }
11415         }
11416
11417         /* Clear ILT */
11418         bnx2x_clear_func_ilt(sc, func);
11419
11420         /*
11421          * Timers workaround bug for E2: if this is vnic-3,
11422          * we need to set the entire ilt range for this timers.
11423          */
11424         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11425                 struct ilt_client_info ilt_cli;
11426 /* use dummy TM client */
11427                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11428                 ilt_cli.start = 0;
11429                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11430                 ilt_cli.client_num = ILT_CLIENT_TM;
11431
11432                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11433         }
11434
11435         /* this assumes that reset_port() called before reset_func() */
11436         if (!CHIP_IS_E1x(sc)) {
11437                 bnx2x_pf_disable(sc);
11438         }
11439
11440         sc->dmae_ready = 0;
11441 }
11442
11443 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11444 {
11445         rte_free(sc->init_ops);
11446         rte_free(sc->init_ops_offsets);
11447         rte_free(sc->init_data);
11448         rte_free(sc->iro_array);
11449 }
11450
11451 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11452 {
11453         uint32_t len, i;
11454         uint8_t *p = sc->firmware;
11455         uint32_t off[24];
11456
11457         for (i = 0; i < 24; ++i)
11458                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11459
11460         len = off[0];
11461         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11462         if (!sc->init_ops)
11463                 goto alloc_failed;
11464         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11465
11466         len = off[2];
11467         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11468         if (!sc->init_ops_offsets)
11469                 goto alloc_failed;
11470         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11471
11472         len = off[4];
11473         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11474         if (!sc->init_data)
11475                 goto alloc_failed;
11476         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11477
11478         sc->tsem_int_table_data = p + off[7];
11479         sc->tsem_pram_data = p + off[9];
11480         sc->usem_int_table_data = p + off[11];
11481         sc->usem_pram_data = p + off[13];
11482         sc->csem_int_table_data = p + off[15];
11483         sc->csem_pram_data = p + off[17];
11484         sc->xsem_int_table_data = p + off[19];
11485         sc->xsem_pram_data = p + off[21];
11486
11487         len = off[22];
11488         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11489         if (!sc->iro_array)
11490                 goto alloc_failed;
11491         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11492
11493         return 0;
11494
11495 alloc_failed:
11496         bnx2x_release_firmware(sc);
11497         return -1;
11498 }
11499
11500 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11501 {
11502 #define MIN_PREFIX_SIZE (10)
11503
11504         int n = MIN_PREFIX_SIZE;
11505         uint16_t xlen;
11506
11507         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11508             len <= MIN_PREFIX_SIZE) {
11509                 return -1;
11510         }
11511
11512         /* optional extra fields are present */
11513         if (zbuf[3] & 0x4) {
11514                 xlen = zbuf[13];
11515                 xlen <<= 8;
11516                 xlen += zbuf[12];
11517
11518                 n += xlen;
11519         }
11520         /* file name is present */
11521         if (zbuf[3] & 0x8) {
11522                 while ((zbuf[n++] != 0) && (n < len)) ;
11523         }
11524
11525         return n;
11526 }
11527
11528 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11529 {
11530         int ret;
11531         int data_begin = cut_gzip_prefix(zbuf, len);
11532
11533         PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11534
11535         if (data_begin <= 0) {
11536                 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11537                 return -1;
11538         }
11539
11540         memset(&zlib_stream, 0, sizeof(zlib_stream));
11541         zlib_stream.next_in = zbuf + data_begin;
11542         zlib_stream.avail_in = len - data_begin;
11543         zlib_stream.next_out = sc->gz_buf;
11544         zlib_stream.avail_out = FW_BUF_SIZE;
11545
11546         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11547         if (ret != Z_OK) {
11548                 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11549                 return ret;
11550         }
11551
11552         ret = inflate(&zlib_stream, Z_FINISH);
11553         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11554                 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11555                             zlib_stream.msg);
11556         }
11557
11558         sc->gz_outlen = zlib_stream.total_out;
11559         if (sc->gz_outlen & 0x3) {
11560                 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11561                             sc->gz_outlen);
11562         }
11563         sc->gz_outlen >>= 2;
11564
11565         inflateEnd(&zlib_stream);
11566
11567         if (ret == Z_STREAM_END)
11568                 return 0;
11569
11570         return ret;
11571 }
11572
11573 static void
11574 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11575                           uint32_t addr, uint32_t len)
11576 {
11577         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11578 }
11579
11580 void
11581 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11582                           uint32_t * data)
11583 {
11584         uint8_t i;
11585         for (i = 0; i < size / 4; i++) {
11586                 REG_WR(sc, addr + (i * 4), data[i]);
11587         }
11588 }
11589
11590 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11591 {
11592         uint32_t phy_type_idx = ext_phy_type >> 8;
11593         static const char *types[] =
11594             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11595                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11596                 "BNX2X-8727",
11597                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11598         };
11599
11600         if (phy_type_idx < 12)
11601                 return types[phy_type_idx];
11602         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11603                 return types[12];
11604         else
11605                 return types[13];
11606 }
11607
11608 static const char *get_state(uint32_t state)
11609 {
11610         uint32_t state_idx = state >> 12;
11611         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11612                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11613                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11614                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11615                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11616         };
11617
11618         if (state_idx <= 0xF)
11619                 return states[state_idx];
11620         else
11621                 return states[0x10];
11622 }
11623
11624 static const char *get_recovery_state(uint32_t state)
11625 {
11626         static const char *states[] = { "NONE", "DONE", "INIT",
11627                 "WAIT", "FAILED", "NIC_LOADING"
11628         };
11629         return states[state];
11630 }
11631
11632 static const char *get_rx_mode(uint32_t mode)
11633 {
11634         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11635                 "PROMISC", "MAX_MULTICAST", "ERROR"
11636         };
11637
11638         if (mode < 0x4)
11639                 return modes[mode];
11640         else if (BNX2X_MAX_MULTICAST == mode)
11641                 return modes[4];
11642         else
11643                 return modes[5];
11644 }
11645
11646 #define BNX2X_INFO_STR_MAX 256
11647 static const char *get_bnx2x_flags(uint32_t flags)
11648 {
11649         int i;
11650         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11651                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11652                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11653                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11654         };
11655         static char flag_str[BNX2X_INFO_STR_MAX];
11656         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11657
11658         for (i = 0; i < 5; i++)
11659                 if (flags & (1 << i)) {
11660                         strcat(flag_str, flag[i]);
11661                         flags ^= (1 << i);
11662                 }
11663         if (flags) {
11664                 static char unknown[BNX2X_INFO_STR_MAX];
11665                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11666                 strcat(flag_str, unknown);
11667         }
11668         return flag_str;
11669 }
11670
11671 /*
11672  * Prints useful adapter info.
11673  */
11674 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11675 {
11676         int i = 0;
11677         __rte_unused uint32_t ext_phy_type;
11678
11679         PMD_INIT_FUNC_TRACE();
11680         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11681                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11682                                                               sc->
11683                                                               devinfo.shmem_base
11684                                                               + offsetof(struct
11685                                                                          shmem_region,
11686                                                                          dev_info.port_hw_config
11687                                                                          [0].external_phy_config)));
11688         else
11689                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11690                                                                 sc->
11691                                                                 devinfo.shmem_base
11692                                                                 +
11693                                                                 offsetof(struct
11694                                                                          shmem_region,
11695                                                                          dev_info.port_hw_config
11696                                                                          [0].external_phy_config)));
11697
11698         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11699         /* Hardware chip info. */
11700         PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11701         PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11702                      (CHIP_METAL(sc) >> 4));
11703
11704         /* Bus info. */
11705         PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11706         switch (sc->devinfo.pcie_link_speed) {
11707         case 1:
11708                 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11709                 break;
11710         case 2:
11711                 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11712                 break;
11713         case 4:
11714                 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11715                 break;
11716         default:
11717                 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11718         }
11719
11720         /* Device features. */
11721         PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11722
11723         /* Miscellaneous flags. */
11724         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11725                 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11726                 i++;
11727         }
11728
11729         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11730                 if (i > 0)
11731                         PMD_INIT_LOG(DEBUG, "|");
11732                 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11733                 i++;
11734         }
11735
11736         if (IS_PF(sc)) {
11737                 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11738                 switch (sc->sp->rss_rdata.rss_mode) {
11739                 case ETH_RSS_MODE_DISABLED:
11740                         PMD_INIT_LOG(DEBUG, "%19s", "None");
11741                         break;
11742                 case ETH_RSS_MODE_REGULAR:
11743                         PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11744                         break;
11745                 default:
11746                         PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11747                         break;
11748                 }
11749         }
11750
11751         /* RTE and Driver versions */
11752         PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11753                      rte_version());
11754         PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11755                      bnx2x_pmd_version());
11756
11757         /* Firmware versions and device features. */
11758         PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11759                      "Firmware",
11760                      BNX2X_5710_FW_MAJOR_VERSION,
11761                      BNX2X_5710_FW_MINOR_VERSION,
11762                      BNX2X_5710_FW_REVISION_VERSION);
11763         PMD_INIT_LOG(DEBUG, "%12s : %s",
11764                      "Bootcode", sc->devinfo.bc_ver_str);
11765
11766         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11767         PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11768         PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11769         PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11770                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11771         PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11772         PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11773         PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11774         PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11775         PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11776                         sc->link_params.mac_addr[0],
11777                         sc->link_params.mac_addr[1],
11778                         sc->link_params.mac_addr[2],
11779                         sc->link_params.mac_addr[3],
11780                         sc->link_params.mac_addr[4],
11781                         sc->link_params.mac_addr[5]);
11782         PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11783         PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11784         if (sc->recovery_state)
11785                 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11786                              get_recovery_state(sc->recovery_state));
11787         PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11788                      sc->cq_spq_left, sc->eq_spq_left);
11789         PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11790         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11791 }