drivers/net/bnx2x/bnx2x.c

   1 /*-
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
   9  * Copyright (c) 2015 QLogic Corporation.
  10  * All rights reserved.
  11  * www.qlogic.com
  12  *
  13  * See LICENSE.bnx2x_pmd for copyright and licensing details.
  14  */
  15
  16 #define BNX2X_DRIVER_VERSION "1.78.18"
  17
  18 #include "bnx2x.h"
  19 #include "bnx2x_vfpf.h"
  20 #include "ecore_sp.h"
  21 #include "ecore_init.h"
  22 #include "ecore_init_ops.h"
  23
  24 #include "rte_version.h"
  25
  26 #include <sys/types.h>
  27 #include <sys/stat.h>
  28 #include <fcntl.h>
  29 #include <zlib.h>
  30
  31 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
  32 #define BNX2X_PMD_VERSION_MAJOR 1
  33 #define BNX2X_PMD_VERSION_MINOR 0
  34 #define BNX2X_PMD_VERSION_REVISION 1
  35 #define BNX2X_PMD_VERSION_PATCH 1
  36
  37 static inline const char *
  38 bnx2x_pmd_version(void)
  39 {
  40         static char version[32];
  41
  42         snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
  43                         BNX2X_PMD_VER_PREFIX,
  44                         BNX2X_DRIVER_VERSION,
  45                         BNX2X_PMD_VERSION_MAJOR,
  46                         BNX2X_PMD_VERSION_MINOR,
  47                         BNX2X_PMD_VERSION_REVISION,
  48                         BNX2X_PMD_VERSION_PATCH);
  49
  50         return version;
  51 }
  52
  53 static z_stream zlib_stream;
  54
  55 #define EVL_VLID_MASK 0x0FFF
  56
  57 #define BNX2X_DEF_SB_ATT_IDX 0x0001
  58 #define BNX2X_DEF_SB_IDX     0x0002
  59
  60 /*
  61  * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
  62  * function HW initialization.
  63  */
  64 #define FLR_WAIT_USEC     10000 /* 10 msecs */
  65 #define FLR_WAIT_INTERVAL 50    /* usecs */
  66 #define FLR_POLL_CNT      (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)   /* 200 */
  67
  68 struct pbf_pN_buf_regs {
  69         int pN;
  70         uint32_t init_crd;
  71         uint32_t crd;
  72         uint32_t crd_freed;
  73 };
  74
  75 struct pbf_pN_cmd_regs {
  76         int pN;
  77         uint32_t lines_occup;
  78         uint32_t lines_freed;
  79 };
  80
  81 /* resources needed for unloading a previously loaded device */
  82
  83 #define BNX2X_PREV_WAIT_NEEDED 1
  84 rte_spinlock_t bnx2x_prev_mtx;
  85 struct bnx2x_prev_list_node {
  86         LIST_ENTRY(bnx2x_prev_list_node) node;
  87         uint8_t bus;
  88         uint8_t slot;
  89         uint8_t path;
  90         uint8_t aer;
  91         uint8_t undi;
  92 };
  93
  94 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
  95         = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
  96
  97 static int load_count[2][3] = { { 0 } };
  98         /* per-path: 0-common, 1-port0, 2-port1 */
  99
 100 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
 101                                 uint8_t cmng_type);
 102 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
 103 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
 104                               uint8_t port);
 105 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
 106 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
 107 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
 108 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
 109 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
 110                                      uint8_t print);
 111 static void bnx2x_int_disable(struct bnx2x_softc *sc);
 112 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
 113 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
 114 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
 115                                  struct bnx2x_fastpath *fp,
 116                                  uint16_t rx_bd_prod, uint16_t rx_cq_prod);
 117 static void bnx2x_link_report(struct bnx2x_softc *sc);
 118 void bnx2x_link_status_update(struct bnx2x_softc *sc);
 119 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
 120 static void bnx2x_free_mem(struct bnx2x_softc *sc);
 121 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
 122 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
 123 static __attribute__ ((noinline))
 124 int bnx2x_nic_load(struct bnx2x_softc *sc);
 125
 126 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
 127 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
 128 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
 129 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
 130                          uint8_t storm, uint16_t index, uint8_t op,
 131                          uint8_t update);
 132
 133 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
 134 {
 135         int res;
 136
 137         mb();
 138         res = ((*addr) & (1UL << nr)) != 0;
 139         mb();
 140         return res;
 141 }
 142
 143 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
 144 {
 145         __sync_fetch_and_or(addr, (1UL << nr));
 146 }
 147
 148 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
 149 {
 150         __sync_fetch_and_and(addr, ~(1UL << nr));
 151 }
 152
 153 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
 154 {
 155         unsigned long mask = (1UL << nr);
 156         return __sync_fetch_and_and(addr, ~mask) & mask;
 157 }
 158
 159 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
 160 {
 161         return __sync_val_compare_and_swap(addr, old, new);
 162 }
 163
 164 int
 165 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
 166               const char *msg, uint32_t align)
 167 {
 168         char mz_name[RTE_MEMZONE_NAMESIZE];
 169         const struct rte_memzone *z;
 170
 171         dma->sc = sc;
 172         if (IS_PF(sc))
 173                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
 174                         rte_get_timer_cycles());
 175         else
 176                 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
 177                         rte_get_timer_cycles());
 178
 179         /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
 180         z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
 181                                         SOCKET_ID_ANY,
 182                                         0, align);
 183         if (z == NULL) {
 184                 PMD_DRV_LOG(ERR, "DMA alloc failed for %s", msg);
 185                 return -ENOMEM;
 186         }
 187         dma->paddr = (uint64_t) z->phys_addr;
 188         dma->vaddr = z->addr;
 189
 190         PMD_DRV_LOG(DEBUG, "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
 191
 192         return 0;
 193 }
 194
 195 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 196 {
 197         uint32_t lock_status;
 198         uint32_t resource_bit = (1 << resource);
 199         int func = SC_FUNC(sc);
 200         uint32_t hw_lock_control_reg;
 201         int cnt;
 202
 203         PMD_INIT_FUNC_TRACE();
 204
 205         /* validate the resource is within range */
 206         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 207                 PMD_DRV_LOG(NOTICE,
 208                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 209                             resource);
 210                 return -1;
 211         }
 212
 213         if (func <= 5) {
 214                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 215         } else {
 216                 hw_lock_control_reg =
 217                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 218         }
 219
 220         /* validate the resource is not already taken */
 221         lock_status = REG_RD(sc, hw_lock_control_reg);
 222         if (lock_status & resource_bit) {
 223                 PMD_DRV_LOG(NOTICE,
 224                             "resource in use (status 0x%x bit 0x%x)",
 225                             lock_status, resource_bit);
 226                 return -1;
 227         }
 228
 229         /* try every 5ms for 5 seconds */
 230         for (cnt = 0; cnt < 1000; cnt++) {
 231                 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
 232                 lock_status = REG_RD(sc, hw_lock_control_reg);
 233                 if (lock_status & resource_bit) {
 234                         return 0;
 235                 }
 236                 DELAY(5000);
 237         }
 238
 239         PMD_DRV_LOG(NOTICE, "Resource lock timeout!");
 240         return -1;
 241 }
 242
 243 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
 244 {
 245         uint32_t lock_status;
 246         uint32_t resource_bit = (1 << resource);
 247         int func = SC_FUNC(sc);
 248         uint32_t hw_lock_control_reg;
 249
 250         PMD_INIT_FUNC_TRACE();
 251
 252         /* validate the resource is within range */
 253         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
 254                 PMD_DRV_LOG(NOTICE,
 255                             "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
 256                             resource);
 257                 return -1;
 258         }
 259
 260         if (func <= 5) {
 261                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
 262         } else {
 263                 hw_lock_control_reg =
 264                     (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
 265         }
 266
 267         /* validate the resource is currently taken */
 268         lock_status = REG_RD(sc, hw_lock_control_reg);
 269         if (!(lock_status & resource_bit)) {
 270                 PMD_DRV_LOG(NOTICE,
 271                             "resource not in use (status 0x%x bit 0x%x)",
 272                             lock_status, resource_bit);
 273                 return -1;
 274         }
 275
 276         REG_WR(sc, hw_lock_control_reg, resource_bit);
 277         return 0;
 278 }
 279
 280 /* copy command into DMAE command memory and set DMAE command Go */
 281 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
 282 {
 283         uint32_t cmd_offset;
 284         uint32_t i;
 285
 286         cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
 287         for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
 288                 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
 289         }
 290
 291         REG_WR(sc, dmae_reg_go_c[idx], 1);
 292 }
 293
 294 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
 295 {
 296         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 297                           DMAE_COMMAND_C_TYPE_ENABLE);
 298 }
 299
 300 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
 301 {
 302         return opcode & ~DMAE_COMMAND_SRC_RESET;
 303 }
 304
 305 uint32_t
 306 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
 307                 uint8_t with_comp, uint8_t comp_type)
 308 {
 309         uint32_t opcode = 0;
 310
 311         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 312                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 313
 314         opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
 315
 316         opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 317
 318         opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
 319                    (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
 320
 321         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 322
 323 #ifdef __BIG_ENDIAN
 324         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 325 #else
 326         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 327 #endif
 328
 329         if (with_comp) {
 330                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 331         }
 332
 333         return opcode;
 334 }
 335
 336 static void
 337 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
 338                         uint8_t src_type, uint8_t dst_type)
 339 {
 340         memset(dmae, 0, sizeof(struct dmae_command));
 341
 342         /* set the opcode */
 343         dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
 344                                        TRUE, DMAE_COMP_PCI);
 345
 346         /* fill in the completion parameters */
 347         dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
 348         dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
 349         dmae->comp_val = DMAE_COMP_VAL;
 350 }
 351
 352 /* issue a DMAE command over the init channel and wait for completion */
 353 static int
 354 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
 355 {
 356         uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
 357         int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
 358
 359         /* reset completion */
 360         *wb_comp = 0;
 361
 362         /* post the command on the channel used for initializations */
 363         bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
 364
 365         /* wait for completion */
 366         DELAY(500);
 367
 368         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 369                 if (!timeout ||
 370                     (sc->recovery_state != BNX2X_RECOVERY_DONE &&
 371                      sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 372                         PMD_DRV_LOG(INFO, "DMAE timeout!");
 373                         return DMAE_TIMEOUT;
 374                 }
 375
 376                 timeout--;
 377                 DELAY(50);
 378         }
 379
 380         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 381                 PMD_DRV_LOG(INFO, "DMAE PCI error!");
 382                 return DMAE_PCI_ERROR;
 383         }
 384
 385         return 0;
 386 }
 387
 388 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
 389 {
 390         struct dmae_command dmae;
 391         uint32_t *data;
 392         uint32_t i;
 393         int rc;
 394
 395         if (!sc->dmae_ready) {
 396                 data = BNX2X_SP(sc, wb_data[0]);
 397
 398                 for (i = 0; i < len32; i++) {
 399                         data[i] = REG_RD(sc, (src_addr + (i * 4)));
 400                 }
 401
 402                 return;
 403         }
 404
 405         /* set opcode and fixed command fields */
 406         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 407
 408         /* fill in addresses and len */
 409         dmae.src_addr_lo = (src_addr >> 2);     /* GRC addr has dword resolution */
 410         dmae.src_addr_hi = 0;
 411         dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
 412         dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
 413         dmae.len = len32;
 414
 415         /* issue the command and wait for completion */
 416         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 417                 rte_panic("DMAE failed (%d)", rc);
 418         };
 419 }
 420
 421 void
 422 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
 423                uint32_t len32)
 424 {
 425         struct dmae_command dmae;
 426         int rc;
 427
 428         if (!sc->dmae_ready) {
 429                 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
 430                 return;
 431         }
 432
 433         /* set opcode and fixed command fields */
 434         bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 435
 436         /* fill in addresses and len */
 437         dmae.src_addr_lo = U64_LO(dma_addr);
 438         dmae.src_addr_hi = U64_HI(dma_addr);
 439         dmae.dst_addr_lo = (dst_addr >> 2);     /* GRC addr has dword resolution */
 440         dmae.dst_addr_hi = 0;
 441         dmae.len = len32;
 442
 443         /* issue the command and wait for completion */
 444         if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
 445                 rte_panic("DMAE failed (%d)", rc);
 446         }
 447 }
 448
 449 static void
 450 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
 451                         uint32_t addr, uint32_t len)
 452 {
 453         uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
 454         uint32_t offset = 0;
 455
 456         while (len > dmae_wr_max) {
 457                 bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 458                                (addr + offset), /* dst GRC address */
 459                                dmae_wr_max);
 460                 offset += (dmae_wr_max * 4);
 461                 len -= dmae_wr_max;
 462         }
 463
 464         bnx2x_write_dmae(sc, (phys_addr + offset),      /* src DMA address */
 465                        (addr + offset), /* dst GRC address */
 466                        len);
 467 }
 468
 469 void
 470 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
 471                        uint32_t cid)
 472 {
 473         /* ustorm cxt validation */
 474         cxt->ustorm_ag_context.cdu_usage =
 475             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 476                                    CDU_REGION_NUMBER_UCM_AG,
 477                                    ETH_CONNECTION_TYPE);
 478         /* xcontext validation */
 479         cxt->xstorm_ag_context.cdu_reserved =
 480             CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
 481                                    CDU_REGION_NUMBER_XCM_AG,
 482                                    ETH_CONNECTION_TYPE);
 483 }
 484
 485 static void
 486 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 487                             uint8_t sb_index, uint8_t ticks)
 488 {
 489         uint32_t addr =
 490             (BAR_CSTRORM_INTMEM +
 491              CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
 492
 493         REG_WR8(sc, addr, ticks);
 494 }
 495
 496 static void
 497 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
 498                             uint8_t sb_index, uint8_t disable)
 499 {
 500         uint32_t enable_flag =
 501             (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
 502         uint32_t addr =
 503             (BAR_CSTRORM_INTMEM +
 504              CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
 505         uint8_t flags;
 506
 507         /* clear and set */
 508         flags = REG_RD8(sc, addr);
 509         flags &= ~HC_INDEX_DATA_HC_ENABLED;
 510         flags |= enable_flag;
 511         REG_WR8(sc, addr, flags);
 512 }
 513
 514 void
 515 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
 516                              uint8_t sb_index, uint8_t disable, uint16_t usec)
 517 {
 518         uint8_t ticks = (usec / 4);
 519
 520         bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
 521
 522         disable = (disable) ? 1 : ((usec) ? 0 : 1);
 523         bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
 524 }
 525
 526 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
 527 {
 528         return REG_RD(sc, reg_addr);
 529 }
 530
 531 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
 532 {
 533         REG_WR(sc, reg_addr, val);
 534 }
 535
 536 void
 537 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
 538                    __rte_unused const elink_log_id_t elink_log_id, ...)
 539 {
 540         PMD_DRV_LOG(DEBUG, "ELINK EVENT LOG (%d)", elink_log_id);
 541 }
 542
 543 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
 544 {
 545         uint32_t spio_reg;
 546
 547         /* Only 2 SPIOs are configurable */
 548         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
 549                 PMD_DRV_LOG(NOTICE, "Invalid SPIO 0x%x", spio);
 550                 return -1;
 551         }
 552
 553         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 554
 555         /* read SPIO and mask except the float bits */
 556         spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
 557
 558         switch (mode) {
 559         case MISC_SPIO_OUTPUT_LOW:
 560                 /* clear FLOAT and set CLR */
 561                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 562                 spio_reg |= (spio << MISC_SPIO_CLR_POS);
 563                 break;
 564
 565         case MISC_SPIO_OUTPUT_HIGH:
 566                 /* clear FLOAT and set SET */
 567                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
 568                 spio_reg |= (spio << MISC_SPIO_SET_POS);
 569                 break;
 570
 571         case MISC_SPIO_INPUT_HI_Z:
 572                 /* set FLOAT */
 573                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
 574                 break;
 575
 576         default:
 577                 break;
 578         }
 579
 580         REG_WR(sc, MISC_REG_SPIO, spio_reg);
 581         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
 582
 583         return 0;
 584 }
 585
 586 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
 587 {
 588         /* The GPIO should be swapped if swap register is set and active */
 589         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 590                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 591         int gpio_shift = gpio_num;
 592         if (gpio_port)
 593                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 594
 595         uint32_t gpio_mask = (1 << gpio_shift);
 596         uint32_t gpio_reg;
 597
 598         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 599                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 600                 return -1;
 601         }
 602
 603         /* read GPIO value */
 604         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 605
 606         /* get the requested pin value */
 607         return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
 608 }
 609
 610 static int
 611 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
 612 {
 613         /* The GPIO should be swapped if swap register is set and active */
 614         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 615                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 616         int gpio_shift = gpio_num;
 617         if (gpio_port)
 618                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 619
 620         uint32_t gpio_mask = (1 << gpio_shift);
 621         uint32_t gpio_reg;
 622
 623         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 624                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 625                 return -1;
 626         }
 627
 628         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 629
 630         /* read GPIO and mask except the float bits */
 631         gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
 632
 633         switch (mode) {
 634         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 635                 /* clear FLOAT and set CLR */
 636                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 637                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
 638                 break;
 639
 640         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 641                 /* clear FLOAT and set SET */
 642                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 643                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
 644                 break;
 645
 646         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 647                 /* set FLOAT */
 648                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
 649                 break;
 650
 651         default:
 652                 break;
 653         }
 654
 655         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 656         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 657
 658         return 0;
 659 }
 660
 661 static int
 662 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
 663 {
 664         uint32_t gpio_reg;
 665
 666         /* any port swapping should be handled by caller */
 667
 668         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 669
 670         /* read GPIO and mask except the float bits */
 671         gpio_reg = REG_RD(sc, MISC_REG_GPIO);
 672         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 673         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
 674         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
 675
 676         switch (mode) {
 677         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
 678                 /* set CLR */
 679                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
 680                 break;
 681
 682         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
 683                 /* set SET */
 684                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
 685                 break;
 686
 687         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
 688                 /* set FLOAT */
 689                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
 690                 break;
 691
 692         default:
 693                 PMD_DRV_LOG(NOTICE, "Invalid GPIO mode assignment %d", mode);
 694                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 695                 return -1;
 696         }
 697
 698         REG_WR(sc, MISC_REG_GPIO, gpio_reg);
 699         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 700
 701         return 0;
 702 }
 703
 704 static int
 705 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
 706                    uint8_t port)
 707 {
 708         /* The GPIO should be swapped if swap register is set and active */
 709         int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
 710                           REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
 711         int gpio_shift = gpio_num;
 712         if (gpio_port)
 713                 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
 714
 715         uint32_t gpio_mask = (1 << gpio_shift);
 716         uint32_t gpio_reg;
 717
 718         if (gpio_num > MISC_REGISTERS_GPIO_3) {
 719                 PMD_DRV_LOG(NOTICE, "Invalid GPIO %d", gpio_num);
 720                 return -1;
 721         }
 722
 723         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 724
 725         /* read GPIO int */
 726         gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
 727
 728         switch (mode) {
 729         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
 730                 /* clear SET and set CLR */
 731                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 732                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 733                 break;
 734
 735         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
 736                 /* clear CLR and set SET */
 737                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
 738                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
 739                 break;
 740
 741         default:
 742                 break;
 743         }
 744
 745         REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
 746         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
 747
 748         return 0;
 749 }
 750
 751 uint32_t
 752 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
 753 {
 754         return bnx2x_gpio_read(sc, gpio_num, port);
 755 }
 756
 757 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,   /* 0=low 1=high */
 758                             uint8_t port)
 759 {
 760         return bnx2x_gpio_write(sc, gpio_num, mode, port);
 761 }
 762
 763 uint8_t
 764 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
 765                          uint8_t mode /* 0=low 1=high */ )
 766 {
 767         return bnx2x_gpio_mult_write(sc, pins, mode);
 768 }
 769
 770 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,       /* 0=low 1=high */
 771                                 uint8_t port)
 772 {
 773         return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
 774 }
 775
 776 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
 777 {
 778         REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
 779                     (SC_FUNC(sc) * sizeof(uint32_t))), 1);
 780 }
 781
 782 /* send the MCP a request, block until there is a reply */
 783 uint32_t
 784 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 785 {
 786         int mb_idx = SC_FW_MB_IDX(sc);
 787         uint32_t seq;
 788         uint32_t rc = 0;
 789         uint32_t cnt = 1;
 790         uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
 791
 792         seq = ++sc->fw_seq;
 793         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
 794         SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
 795
 796         PMD_DRV_LOG(DEBUG,
 797                     "wrote command 0x%08x to FW MB param 0x%08x",
 798                     (command | seq), param);
 799
 800         /* Let the FW do it's magic. GIve it up to 5 seconds... */
 801         do {
 802                 DELAY(delay * 1000);
 803                 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
 804         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
 805
 806         /* is this a reply to our command? */
 807         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
 808                 rc &= FW_MSG_CODE_MASK;
 809         } else {
 810                 /* Ruh-roh! */
 811                 PMD_DRV_LOG(NOTICE, "FW failed to respond!");
 812                 rc = 0;
 813         }
 814
 815         return rc;
 816 }
 817
 818 static uint32_t
 819 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
 820 {
 821         return elink_cb_fw_command(sc, command, param);
 822 }
 823
 824 static void
 825 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
 826                            phys_addr_t mapping)
 827 {
 828         REG_WR(sc, addr, U64_LO(mapping));
 829         REG_WR(sc, (addr + 4), U64_HI(mapping));
 830 }
 831
 832 static void
 833 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
 834                       uint16_t abs_fid)
 835 {
 836         uint32_t addr = (XSEM_REG_FAST_MEMORY +
 837                          XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
 838         __storm_memset_dma_mapping(sc, addr, mapping);
 839 }
 840
 841 static void
 842 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
 843 {
 844         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
 845                 pf_id);
 846         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
 847                 pf_id);
 848         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
 849                 pf_id);
 850         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
 851                 pf_id);
 852 }
 853
 854 static void
 855 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
 856 {
 857         REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
 858                 enable);
 859         REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
 860                 enable);
 861         REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
 862                 enable);
 863         REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
 864                 enable);
 865 }
 866
 867 static void
 868 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
 869                      uint16_t pfid)
 870 {
 871         uint32_t addr;
 872         size_t size;
 873
 874         addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
 875         size = sizeof(struct event_ring_data);
 876         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
 877 }
 878
 879 static void
 880 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
 881 {
 882         uint32_t addr = (BAR_CSTRORM_INTMEM +
 883                          CSTORM_EVENT_RING_PROD_OFFSET(pfid));
 884         REG_WR16(sc, addr, eq_prod);
 885 }
 886
 887 /*
 888  * Post a slowpath command.
 889  *
 890  * A slowpath command is used to propogate a configuration change through
 891  * the controller in a controlled manner, allowing each STORM processor and
 892  * other H/W blocks to phase in the change.  The commands sent on the
 893  * slowpath are referred to as ramrods.  Depending on the ramrod used the
 894  * completion of the ramrod will occur in different ways.  Here's a
 895  * breakdown of ramrods and how they complete:
 896  *
 897  * RAMROD_CMD_ID_ETH_PORT_SETUP
 898  *   Used to setup the leading connection on a port.  Completes on the
 899  *   Receive Completion Queue (RCQ) of that port (typically fp[0]).
 900  *
 901  * RAMROD_CMD_ID_ETH_CLIENT_SETUP
 902  *   Used to setup an additional connection on a port.  Completes on the
 903  *   RCQ of the multi-queue/RSS connection being initialized.
 904  *
 905  * RAMROD_CMD_ID_ETH_STAT_QUERY
 906  *   Used to force the storm processors to update the statistics database
 907  *   in host memory.  This ramrod is send on the leading connection CID and
 908  *   completes as an index increment of the CSTORM on the default status
 909  *   block.
 910  *
 911  * RAMROD_CMD_ID_ETH_UPDATE
 912  *   Used to update the state of the leading connection, usually to udpate
 913  *   the RSS indirection table.  Completes on the RCQ of the leading
 914  *   connection. (Not currently used under FreeBSD until OS support becomes
 915  *   available.)
 916  *
 917  * RAMROD_CMD_ID_ETH_HALT
 918  *   Used when tearing down a connection prior to driver unload.  Completes
 919  *   on the RCQ of the multi-queue/RSS connection being torn down.  Don't
 920  *   use this on the leading connection.
 921  *
 922  * RAMROD_CMD_ID_ETH_SET_MAC
 923  *   Sets the Unicast/Broadcast/Multicast used by the port.  Completes on
 924  *   the RCQ of the leading connection.
 925  *
 926  * RAMROD_CMD_ID_ETH_CFC_DEL
 927  *   Used when tearing down a conneciton prior to driver unload.  Completes
 928  *   on the RCQ of the leading connection (since the current connection
 929  *   has been completely removed from controller memory).
 930  *
 931  * RAMROD_CMD_ID_ETH_PORT_DEL
 932  *   Used to tear down the leading connection prior to driver unload,
 933  *   typically fp[0].  Completes as an index increment of the CSTORM on the
 934  *   default status block.
 935  *
 936  * RAMROD_CMD_ID_ETH_FORWARD_SETUP
 937  *   Used for connection offload.  Completes on the RCQ of the multi-queue
 938  *   RSS connection that is being offloaded.  (Not currently used under
 939  *   FreeBSD.)
 940  *
 941  * There can only be one command pending per function.
 942  *
 943  * Returns:
 944  *   0 = Success, !0 = Failure.
 945  */
 946
 947 /* must be called under the spq lock */
 948 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
 949 {
 950         struct eth_spe *next_spe = sc->spq_prod_bd;
 951
 952         if (sc->spq_prod_bd == sc->spq_last_bd) {
 953                 /* wrap back to the first eth_spq */
 954                 sc->spq_prod_bd = sc->spq;
 955                 sc->spq_prod_idx = 0;
 956         } else {
 957                 sc->spq_prod_bd++;
 958                 sc->spq_prod_idx++;
 959         }
 960
 961         return next_spe;
 962 }
 963
 964 /* must be called under the spq lock */
 965 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
 966 {
 967         int func = SC_FUNC(sc);
 968
 969         /*
 970          * Make sure that BD data is updated before writing the producer.
 971          * BD data is written to the memory, the producer is read from the
 972          * memory, thus we need a full memory barrier to ensure the ordering.
 973          */
 974         mb();
 975
 976         REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
 977                  sc->spq_prod_idx);
 978
 979         mb();
 980 }
 981
 982 /**
 983  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
 984  *
 985  * @cmd:      command to check
 986  * @cmd_type: command type
 987  */
 988 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
 989 {
 990         if ((cmd_type == NONE_CONNECTION_TYPE) ||
 991             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
 992             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
 993             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
 994             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
 995             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
 996             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
 997                 return TRUE;
 998         } else {
 999                 return FALSE;
1000         }
1001 }
1002
1003 /**
1004  * bnx2x_sp_post - place a single command on an SP ring
1005  *
1006  * @sc:         driver handle
1007  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
1008  * @cid:        SW CID the command is related to
1009  * @data_hi:    command private data address (high 32 bits)
1010  * @data_lo:    command private data address (low 32 bits)
1011  * @cmd_type:   command type (e.g. NONE, ETH)
1012  *
1013  * SP data is handled as if it's always an address pair, thus data fields are
1014  * not swapped to little endian in upper functions. Instead this function swaps
1015  * data as if it's two uint32 fields.
1016  */
1017 int
1018 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1019             uint32_t data_lo, int cmd_type)
1020 {
1021         struct eth_spe *spe;
1022         uint16_t type;
1023         int common;
1024
1025         common = bnx2x_is_contextless_ramrod(command, cmd_type);
1026
1027         if (common) {
1028                 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1029                         PMD_DRV_LOG(INFO, "EQ ring is full!");
1030                         return -1;
1031                 }
1032         } else {
1033                 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1034                         PMD_DRV_LOG(INFO, "SPQ ring is full!");
1035                         return -1;
1036                 }
1037         }
1038
1039         spe = bnx2x_sp_get_next(sc);
1040
1041         /* CID needs port number to be encoded int it */
1042         spe->hdr.conn_and_cmd_data =
1043             htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1044
1045         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1046
1047         /* TBD: Check if it works for VFs */
1048         type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1049                  SPE_HDR_FUNCTION_ID);
1050
1051         spe->hdr.type = htole16(type);
1052
1053         spe->data.update_data_addr.hi = htole32(data_hi);
1054         spe->data.update_data_addr.lo = htole32(data_lo);
1055
1056         /*
1057          * It's ok if the actual decrement is issued towards the memory
1058          * somewhere between the lock and unlock. Thus no more explict
1059          * memory barrier is needed.
1060          */
1061         if (common) {
1062                 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1063         } else {
1064                 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1065         }
1066
1067         PMD_DRV_LOG(DEBUG,
1068                     "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1069                     "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1070                     sc->spq_prod_idx,
1071                     (uint32_t) U64_HI(sc->spq_dma.paddr),
1072                     (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1073                                 (uint8_t *) sc->spq_prod_bd -
1074                                 (uint8_t *) sc->spq), command, common,
1075                     HW_CID(sc, cid), data_hi, data_lo, type,
1076                     atomic_load_acq_long(&sc->cq_spq_left),
1077                     atomic_load_acq_long(&sc->eq_spq_left));
1078
1079         bnx2x_sp_prod_update(sc);
1080
1081         return 0;
1082 }
1083
1084 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1085 {
1086         SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1087                  sc->fw_drv_pulse_wr_seq);
1088 }
1089
1090 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1091 {
1092         uint16_t hw_cons;
1093         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1094
1095         if (unlikely(!txq)) {
1096                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1097                 return 0;
1098         }
1099
1100         mb();                   /* status block fields can change */
1101         hw_cons = le16toh(*fp->tx_cons_sb);
1102         return hw_cons != txq->tx_pkt_head;
1103 }
1104
1105 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1106 {
1107         /* expand this for multi-cos if ever supported */
1108         return bnx2x_tx_queue_has_work(fp);
1109 }
1110
1111 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1112 {
1113         uint16_t rx_cq_cons_sb;
1114         struct bnx2x_rx_queue *rxq;
1115         rxq = fp->sc->rx_queues[fp->index];
1116         if (unlikely(!rxq)) {
1117                 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1118                 return 0;
1119         }
1120
1121         mb();                   /* status block fields can change */
1122         rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1123         if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1124                      MAX_RCQ_ENTRIES(rxq)))
1125                 rx_cq_cons_sb++;
1126         return rxq->rx_cq_head != rx_cq_cons_sb;
1127 }
1128
1129 static void
1130 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1131              union eth_rx_cqe *rr_cqe)
1132 {
1133 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1134         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1135 #endif
1136         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1137         enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1138         struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1139
1140         PMD_DRV_LOG(DEBUG,
1141                     "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1142                     fp->index, cid, command, sc->state,
1143                     rr_cqe->ramrod_cqe.ramrod_type);
1144
1145         switch (command) {
1146         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1147                 PMD_DRV_LOG(DEBUG, "got UPDATE ramrod. CID %d", cid);
1148                 drv_cmd = ECORE_Q_CMD_UPDATE;
1149                 break;
1150
1151         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1152                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] setup ramrod", cid);
1153                 drv_cmd = ECORE_Q_CMD_SETUP;
1154                 break;
1155
1156         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1157                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] tx-only setup ramrod", cid);
1158                 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1159                 break;
1160
1161         case (RAMROD_CMD_ID_ETH_HALT):
1162                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] halt ramrod", cid);
1163                 drv_cmd = ECORE_Q_CMD_HALT;
1164                 break;
1165
1166         case (RAMROD_CMD_ID_ETH_TERMINATE):
1167                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] teminate ramrod", cid);
1168                 drv_cmd = ECORE_Q_CMD_TERMINATE;
1169                 break;
1170
1171         case (RAMROD_CMD_ID_ETH_EMPTY):
1172                 PMD_DRV_LOG(DEBUG, "got MULTI[%d] empty ramrod", cid);
1173                 drv_cmd = ECORE_Q_CMD_EMPTY;
1174                 break;
1175
1176         default:
1177                 PMD_DRV_LOG(DEBUG,
1178                             "ERROR: unexpected MC reply (%d)"
1179                             "on fp[%d]", command, fp->index);
1180                 return;
1181         }
1182
1183         if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1184             q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1185                 /*
1186                  * q_obj->complete_cmd() failure means that this was
1187                  * an unexpected completion.
1188                  *
1189                  * In this case we don't want to increase the sc->spq_left
1190                  * because apparently we haven't sent this command the first
1191                  * place.
1192                  */
1193                 // rte_panic("Unexpected SP completion");
1194                 return;
1195         }
1196
1197         atomic_add_acq_long(&sc->cq_spq_left, 1);
1198
1199         PMD_DRV_LOG(DEBUG, "sc->cq_spq_left 0x%lx",
1200                     atomic_load_acq_long(&sc->cq_spq_left));
1201 }
1202
1203 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1204 {
1205         struct bnx2x_rx_queue *rxq;
1206         uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1207         uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1208
1209         rxq = sc->rx_queues[fp->index];
1210         if (!rxq) {
1211                 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1212                 return 0;
1213         }
1214
1215         /* CQ "next element" is of the size of the regular element */
1216         hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1217         if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1218                      USABLE_RCQ_ENTRIES_PER_PAGE)) {
1219                 hw_cq_cons++;
1220         }
1221
1222         bd_cons = rxq->rx_bd_head;
1223         bd_prod = rxq->rx_bd_tail;
1224         bd_prod_fw = bd_prod;
1225         sw_cq_cons = rxq->rx_cq_head;
1226         sw_cq_prod = rxq->rx_cq_tail;
1227
1228         /*
1229          * Memory barrier necessary as speculative reads of the rx
1230          * buffer can be ahead of the index in the status block
1231          */
1232         rmb();
1233
1234         while (sw_cq_cons != hw_cq_cons) {
1235                 union eth_rx_cqe *cqe;
1236                 struct eth_fast_path_rx_cqe *cqe_fp;
1237                 uint8_t cqe_fp_flags;
1238                 enum eth_rx_cqe_type cqe_fp_type;
1239
1240                 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1241                 bd_prod = RX_BD(bd_prod, rxq);
1242                 bd_cons = RX_BD(bd_cons, rxq);
1243
1244                 cqe = &rxq->cq_ring[comp_ring_cons];
1245                 cqe_fp = &cqe->fast_path_cqe;
1246                 cqe_fp_flags = cqe_fp->type_error_flags;
1247                 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1248
1249                 /* is this a slowpath msg? */
1250                 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1251                         bnx2x_sp_event(sc, fp, cqe);
1252                         goto next_cqe;
1253                 }
1254
1255                 /* is this an error packet? */
1256                 if (unlikely(cqe_fp_flags &
1257                              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1258                         PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1259                                    cqe_fp_flags, sw_cq_cons);
1260                         goto next_rx;
1261                 }
1262
1263                 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1264
1265 next_rx:
1266                 bd_cons = NEXT_RX_BD(bd_cons);
1267                 bd_prod = NEXT_RX_BD(bd_prod);
1268                 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1269
1270 next_cqe:
1271                 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1272                 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1273
1274         }                       /* while work to do */
1275
1276         rxq->rx_bd_head = bd_cons;
1277         rxq->rx_bd_tail = bd_prod_fw;
1278         rxq->rx_cq_head = sw_cq_cons;
1279         rxq->rx_cq_tail = sw_cq_prod;
1280
1281         /* Update producers */
1282         bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1283
1284         return sw_cq_cons != hw_cq_cons;
1285 }
1286
1287 static uint16_t
1288 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1289                 uint16_t pkt_idx, uint16_t bd_idx)
1290 {
1291         struct eth_tx_start_bd *tx_start_bd =
1292             &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1293         uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1294         struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1295
1296         if (likely(tx_mbuf != NULL)) {
1297                 rte_pktmbuf_free_seg(tx_mbuf);
1298         } else {
1299                 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1300                            fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1301         }
1302
1303         txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1304         txq->nb_tx_avail += nbd;
1305
1306         while (nbd--)
1307                 bd_idx = NEXT_TX_BD(bd_idx);
1308
1309         return bd_idx;
1310 }
1311
1312 /* processes transmit completions */
1313 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1314 {
1315         uint16_t bd_cons, hw_cons, sw_cons;
1316         __rte_unused uint16_t tx_bd_avail;
1317
1318         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1319
1320         if (unlikely(!txq)) {
1321                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1322                 return 0;
1323         }
1324
1325         bd_cons = txq->tx_bd_head;
1326         hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1327         sw_cons = txq->tx_pkt_head;
1328
1329         while (sw_cons != hw_cons) {
1330                 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1331                 sw_cons++;
1332         }
1333
1334         txq->tx_pkt_head = sw_cons;
1335         txq->tx_bd_head = bd_cons;
1336
1337         tx_bd_avail = txq->nb_tx_avail;
1338
1339         PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1340                    "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1341                    fp->index, tx_bd_avail, hw_cons,
1342                    txq->tx_pkt_head, txq->tx_pkt_tail,
1343                    txq->tx_bd_head, txq->tx_bd_tail);
1344         return TRUE;
1345 }
1346
1347 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1348 {
1349         struct bnx2x_fastpath *fp;
1350         int i, count;
1351
1352         /* wait until all TX fastpath tasks have completed */
1353         for (i = 0; i < sc->num_queues; i++) {
1354                 fp = &sc->fp[i];
1355
1356                 count = 1000;
1357
1358                 while (bnx2x_has_tx_work(fp)) {
1359                         bnx2x_txeof(sc, fp);
1360
1361                         if (count == 0) {
1362                                 PMD_TX_LOG(ERR,
1363                                            "Timeout waiting for fp[%d] "
1364                                            "transmits to complete!", i);
1365                                 rte_panic("tx drain failure");
1366                                 return;
1367                         }
1368
1369                         count--;
1370                         DELAY(1000);
1371                         rmb();
1372                 }
1373         }
1374
1375         return;
1376 }
1377
1378 static int
1379 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1380                  int mac_type, uint8_t wait_for_comp)
1381 {
1382         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1383         int rc;
1384
1385         /* wait for completion of requested */
1386         if (wait_for_comp) {
1387                 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1388         }
1389
1390         /* Set the mac type of addresses we want to clear */
1391         bnx2x_set_bit(mac_type, &vlan_mac_flags);
1392
1393         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1394         if (rc < 0)
1395                 PMD_DRV_LOG(ERR, "Failed to delete MACs (%d)", rc);
1396
1397         return rc;
1398 }
1399
1400 static int
1401 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1402                         unsigned long *rx_accept_flags,
1403                         unsigned long *tx_accept_flags)
1404 {
1405         /* Clear the flags first */
1406         *rx_accept_flags = 0;
1407         *tx_accept_flags = 0;
1408
1409         switch (rx_mode) {
1410         case BNX2X_RX_MODE_NONE:
1411                 /*
1412                  * 'drop all' supersedes any accept flags that may have been
1413                  * passed to the function.
1414                  */
1415                 break;
1416
1417         case BNX2X_RX_MODE_NORMAL:
1418                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1419                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1420                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1421
1422                 /* internal switching mode */
1423                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1424                 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1425                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1426
1427                 break;
1428
1429         case BNX2X_RX_MODE_ALLMULTI:
1430                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1431                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1432                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1433
1434                 /* internal switching mode */
1435                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1436                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1437                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1438
1439                 break;
1440
1441         case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1442         case BNX2X_RX_MODE_PROMISC:
1443                 /*
1444                  * According to deffinition of SI mode, iface in promisc mode
1445                  * should receive matched and unmatched (in resolution of port)
1446                  * unicast packets.
1447                  */
1448                 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1449                 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1450                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1451                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1452
1453                 /* internal switching mode */
1454                 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1455                 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1456
1457                 if (IS_MF_SI(sc)) {
1458                         bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1459                 } else {
1460                         bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1461                 }
1462
1463                 break;
1464
1465         default:
1466                 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1467                 return -1;
1468         }
1469
1470         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1471         if (rx_mode != BNX2X_RX_MODE_NONE) {
1472                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1473                 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1474         }
1475
1476         return 0;
1477 }
1478
1479 static int
1480 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1481                   unsigned long rx_mode_flags,
1482                   unsigned long rx_accept_flags,
1483                   unsigned long tx_accept_flags, unsigned long ramrod_flags)
1484 {
1485         struct ecore_rx_mode_ramrod_params ramrod_param;
1486         int rc;
1487
1488         memset(&ramrod_param, 0, sizeof(ramrod_param));
1489
1490         /* Prepare ramrod parameters */
1491         ramrod_param.cid = 0;
1492         ramrod_param.cl_id = cl_id;
1493         ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1494         ramrod_param.func_id = SC_FUNC(sc);
1495
1496         ramrod_param.pstate = &sc->sp_state;
1497         ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1498
1499         ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1500         ramrod_param.rdata_mapping =
1501             (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1502             bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1503
1504         ramrod_param.ramrod_flags = ramrod_flags;
1505         ramrod_param.rx_mode_flags = rx_mode_flags;
1506
1507         ramrod_param.rx_accept_flags = rx_accept_flags;
1508         ramrod_param.tx_accept_flags = tx_accept_flags;
1509
1510         rc = ecore_config_rx_mode(sc, &ramrod_param);
1511         if (rc < 0) {
1512                 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1513                 return rc;
1514         }
1515
1516         return 0;
1517 }
1518
1519 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1520 {
1521         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1522         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1523         int rc;
1524
1525         rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1526                                    &tx_accept_flags);
1527         if (rc) {
1528                 return rc;
1529         }
1530
1531         bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1532         bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1533         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1534
1535         return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1536                                  rx_accept_flags, tx_accept_flags,
1537                                  ramrod_flags);
1538 }
1539
1540 /* returns the "mcp load_code" according to global load_count array */
1541 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1542 {
1543         int path = SC_PATH(sc);
1544         int port = SC_PORT(sc);
1545
1546         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1547                     path, load_count[path][0], load_count[path][1],
1548                     load_count[path][2]);
1549
1550         load_count[path][0]++;
1551         load_count[path][1 + port]++;
1552         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1553                     path, load_count[path][0], load_count[path][1],
1554                     load_count[path][2]);
1555         if (load_count[path][0] == 1)
1556                 return FW_MSG_CODE_DRV_LOAD_COMMON;
1557         else if (load_count[path][1 + port] == 1)
1558                 return FW_MSG_CODE_DRV_LOAD_PORT;
1559         else
1560                 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1561 }
1562
1563 /* returns the "mcp load_code" according to global load_count array */
1564 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1565 {
1566         int port = SC_PORT(sc);
1567         int path = SC_PATH(sc);
1568
1569         PMD_DRV_LOG(INFO, "NO MCP - load counts[%d]      %d, %d, %d",
1570                     path, load_count[path][0], load_count[path][1],
1571                     load_count[path][2]);
1572         load_count[path][0]--;
1573         load_count[path][1 + port]--;
1574         PMD_DRV_LOG(INFO, "NO MCP - new load counts[%d]  %d, %d, %d",
1575                     path, load_count[path][0], load_count[path][1],
1576                     load_count[path][2]);
1577         if (load_count[path][0] == 0) {
1578                 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1579         } else if (load_count[path][1 + port] == 0) {
1580                 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1581         } else {
1582                 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1583         }
1584 }
1585
1586 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1587 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1588 {
1589         uint32_t reset_code = 0;
1590
1591         /* Select the UNLOAD request mode */
1592         if (unload_mode == UNLOAD_NORMAL) {
1593                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1594         } else {
1595                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1596         }
1597
1598         /* Send the request to the MCP */
1599         if (!BNX2X_NOMCP(sc)) {
1600                 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1601         } else {
1602                 reset_code = bnx2x_nic_unload_no_mcp(sc);
1603         }
1604
1605         return reset_code;
1606 }
1607
1608 /* send UNLOAD_DONE command to the MCP */
1609 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1610 {
1611         uint32_t reset_param =
1612             keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1613
1614         /* Report UNLOAD_DONE to MCP */
1615         if (!BNX2X_NOMCP(sc)) {
1616                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1617         }
1618 }
1619
1620 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1621 {
1622         int tout = 50;
1623
1624         if (!sc->port.pmf) {
1625                 return 0;
1626         }
1627
1628         /*
1629          * (assumption: No Attention from MCP at this stage)
1630          * PMF probably in the middle of TX disable/enable transaction
1631          * 1. Sync IRS for default SB
1632          * 2. Sync SP queue - this guarantees us that attention handling started
1633          * 3. Wait, that TX disable/enable transaction completes
1634          *
1635          * 1+2 guarantee that if DCBX attention was scheduled it already changed
1636          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1637          * received completion for the transaction the state is TX_STOPPED.
1638          * State will return to STARTED after completion of TX_STOPPED-->STARTED
1639          * transaction.
1640          */
1641
1642         while (ecore_func_get_state(sc, &sc->func_obj) !=
1643                ECORE_F_STATE_STARTED && tout--) {
1644                 DELAY(20000);
1645         }
1646
1647         if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1648                 /*
1649                  * Failed to complete the transaction in a "good way"
1650                  * Force both transactions with CLR bit.
1651                  */
1652                 struct ecore_func_state_params func_params = { NULL };
1653
1654                 PMD_DRV_LOG(NOTICE, "Unexpected function state! "
1655                             "Forcing STARTED-->TX_STOPPED-->STARTED");
1656
1657                 func_params.f_obj = &sc->func_obj;
1658                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1659
1660                 /* STARTED-->TX_STOPPED */
1661                 func_params.cmd = ECORE_F_CMD_TX_STOP;
1662                 ecore_func_state_change(sc, &func_params);
1663
1664                 /* TX_STOPPED-->STARTED */
1665                 func_params.cmd = ECORE_F_CMD_TX_START;
1666                 return ecore_func_state_change(sc, &func_params);
1667         }
1668
1669         return 0;
1670 }
1671
1672 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1673 {
1674         struct bnx2x_fastpath *fp = &sc->fp[index];
1675         struct ecore_queue_state_params q_params = { NULL };
1676         int rc;
1677
1678         PMD_DRV_LOG(DEBUG, "stopping queue %d cid %d", index, fp->index);
1679
1680         q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1681         /* We want to wait for completion in this context */
1682         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1683
1684         /* Stop the primary connection: */
1685
1686         /* ...halt the connection */
1687         q_params.cmd = ECORE_Q_CMD_HALT;
1688         rc = ecore_queue_state_change(sc, &q_params);
1689         if (rc) {
1690                 return rc;
1691         }
1692
1693         /* ...terminate the connection */
1694         q_params.cmd = ECORE_Q_CMD_TERMINATE;
1695         memset(&q_params.params.terminate, 0,
1696                sizeof(q_params.params.terminate));
1697         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1698         rc = ecore_queue_state_change(sc, &q_params);
1699         if (rc) {
1700                 return rc;
1701         }
1702
1703         /* ...delete cfc entry */
1704         q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1705         memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1706         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1707         return ecore_queue_state_change(sc, &q_params);
1708 }
1709
1710 /* wait for the outstanding SP commands */
1711 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1712 {
1713         unsigned long tmp;
1714         int tout = 5000;        /* wait for 5 secs tops */
1715
1716         while (tout--) {
1717                 mb();
1718                 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1719                         return TRUE;
1720                 }
1721
1722                 DELAY(1000);
1723         }
1724
1725         mb();
1726
1727         tmp = atomic_load_acq_long(&sc->sp_state);
1728         if (tmp & mask) {
1729                 PMD_DRV_LOG(INFO, "Filtering completion timed out: "
1730                             "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1731                 return FALSE;
1732         }
1733
1734         return FALSE;
1735 }
1736
1737 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1738 {
1739         struct ecore_func_state_params func_params = { NULL };
1740         int rc;
1741
1742         /* prepare parameters for function state transitions */
1743         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1744         func_params.f_obj = &sc->func_obj;
1745         func_params.cmd = ECORE_F_CMD_STOP;
1746
1747         /*
1748          * Try to stop the function the 'good way'. If it fails (in case
1749          * of a parity error during bnx2x_chip_cleanup()) and we are
1750          * not in a debug mode, perform a state transaction in order to
1751          * enable further HW_RESET transaction.
1752          */
1753         rc = ecore_func_state_change(sc, &func_params);
1754         if (rc) {
1755                 PMD_DRV_LOG(NOTICE, "FUNC_STOP ramrod failed. "
1756                             "Running a dry transaction");
1757                 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1758                 return ecore_func_state_change(sc, &func_params);
1759         }
1760
1761         return 0;
1762 }
1763
1764 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1765 {
1766         struct ecore_func_state_params func_params = { NULL };
1767
1768         /* Prepare parameters for function state transitions */
1769         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1770
1771         func_params.f_obj = &sc->func_obj;
1772         func_params.cmd = ECORE_F_CMD_HW_RESET;
1773
1774         func_params.params.hw_init.load_phase = load_code;
1775
1776         return ecore_func_state_change(sc, &func_params);
1777 }
1778
1779 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1780 {
1781         if (disable_hw) {
1782                 /* prevent the HW from sending interrupts */
1783                 bnx2x_int_disable(sc);
1784         }
1785 }
1786
1787 static void
1788 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1789 {
1790         int port = SC_PORT(sc);
1791         struct ecore_mcast_ramrod_params rparam = { NULL };
1792         uint32_t reset_code;
1793         int i, rc = 0;
1794
1795         bnx2x_drain_tx_queues(sc);
1796
1797         /* give HW time to discard old tx messages */
1798         DELAY(1000);
1799
1800         /* Clean all ETH MACs */
1801         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1802                               FALSE);
1803         if (rc < 0) {
1804                 PMD_DRV_LOG(NOTICE, "Failed to delete all ETH MACs (%d)", rc);
1805         }
1806
1807         /* Clean up UC list  */
1808         rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1809                               TRUE);
1810         if (rc < 0) {
1811                 PMD_DRV_LOG(NOTICE, "Failed to delete UC MACs list (%d)", rc);
1812         }
1813
1814         /* Disable LLH */
1815         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1816
1817         /* Set "drop all" to stop Rx */
1818
1819         /*
1820          * We need to take the if_maddr_lock() here in order to prevent
1821          * a race between the completion code and this code.
1822          */
1823
1824         if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1825                 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1826         } else {
1827                 bnx2x_set_storm_rx_mode(sc);
1828         }
1829
1830         /* Clean up multicast configuration */
1831         rparam.mcast_obj = &sc->mcast_obj;
1832         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1833         if (rc < 0) {
1834                 PMD_DRV_LOG(NOTICE,
1835                             "Failed to send DEL MCAST command (%d)", rc);
1836         }
1837
1838         /*
1839          * Send the UNLOAD_REQUEST to the MCP. This will return if
1840          * this function should perform FUNCTION, PORT, or COMMON HW
1841          * reset.
1842          */
1843         reset_code = bnx2x_send_unload_req(sc, unload_mode);
1844
1845         /*
1846          * (assumption: No Attention from MCP at this stage)
1847          * PMF probably in the middle of TX disable/enable transaction
1848          */
1849         rc = bnx2x_func_wait_started(sc);
1850         if (rc) {
1851                 PMD_DRV_LOG(NOTICE, "bnx2x_func_wait_started failed");
1852         }
1853
1854         /*
1855          * Close multi and leading connections
1856          * Completions for ramrods are collected in a synchronous way
1857          */
1858         for (i = 0; i < sc->num_queues; i++) {
1859                 if (bnx2x_stop_queue(sc, i)) {
1860                         goto unload_error;
1861                 }
1862         }
1863
1864         /*
1865          * If SP settings didn't get completed so far - something
1866          * very wrong has happen.
1867          */
1868         if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1869                 PMD_DRV_LOG(NOTICE, "Common slow path ramrods got stuck!");
1870         }
1871
1872 unload_error:
1873
1874         rc = bnx2x_func_stop(sc);
1875         if (rc) {
1876                 PMD_DRV_LOG(NOTICE, "Function stop failed!");
1877         }
1878
1879         /* disable HW interrupts */
1880         bnx2x_int_disable_sync(sc, TRUE);
1881
1882         /* Reset the chip */
1883         rc = bnx2x_reset_hw(sc, reset_code);
1884         if (rc) {
1885                 PMD_DRV_LOG(NOTICE, "Hardware reset failed");
1886         }
1887
1888         /* Report UNLOAD_DONE to MCP */
1889         bnx2x_send_unload_done(sc, keep_link);
1890 }
1891
1892 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1893 {
1894         uint32_t val;
1895
1896         PMD_DRV_LOG(DEBUG, "Disabling 'close the gates'");
1897
1898         val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1899         val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1900                  MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1901         REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1902 }
1903
1904 /*
1905  * Cleans the object that have internal lists without sending
1906  * ramrods. Should be run when interrutps are disabled.
1907  */
1908 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1909 {
1910         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1911         struct ecore_mcast_ramrod_params rparam = { NULL };
1912         struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1913         int rc;
1914
1915         /* Cleanup MACs' object first... */
1916
1917         /* Wait for completion of requested */
1918         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1919         /* Perform a dry cleanup */
1920         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1921
1922         /* Clean ETH primary MAC */
1923         bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1924         rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1925                                  &ramrod_flags);
1926         if (rc != 0) {
1927                 PMD_DRV_LOG(NOTICE, "Failed to clean ETH MACs (%d)", rc);
1928         }
1929
1930         /* Cleanup UC list */
1931         vlan_mac_flags = 0;
1932         bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1933         rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1934         if (rc != 0) {
1935                 PMD_DRV_LOG(NOTICE, "Failed to clean UC list MACs (%d)", rc);
1936         }
1937
1938         /* Now clean mcast object... */
1939
1940         rparam.mcast_obj = &sc->mcast_obj;
1941         bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1942
1943         /* Add a DEL command... */
1944         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1945         if (rc < 0) {
1946                 PMD_DRV_LOG(NOTICE,
1947                             "Failed to send DEL MCAST command (%d)", rc);
1948         }
1949
1950         /* now wait until all pending commands are cleared */
1951
1952         rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1953         while (rc != 0) {
1954                 if (rc < 0) {
1955                         PMD_DRV_LOG(NOTICE,
1956                                     "Failed to clean MCAST object (%d)", rc);
1957                         return;
1958                 }
1959
1960                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1961         }
1962 }
1963
1964 /* stop the controller */
1965 __attribute__ ((noinline))
1966 int
1967 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1968 {
1969         uint8_t global = FALSE;
1970         uint32_t val;
1971
1972         PMD_DRV_LOG(DEBUG, "Starting NIC unload...");
1973
1974         /* stop the periodic callout */
1975         bnx2x_periodic_stop(sc);
1976
1977         /* mark driver as unloaded in shmem2 */
1978         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
1979                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
1980                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
1981                           val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
1982         }
1983
1984         if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
1985             (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
1986                 /*
1987                  * We can get here if the driver has been unloaded
1988                  * during parity error recovery and is either waiting for a
1989                  * leader to complete or for other functions to unload and
1990                  * then ifconfig down has been issued. In this case we want to
1991                  * unload and let other functions to complete a recovery
1992                  * process.
1993                  */
1994                 sc->recovery_state = BNX2X_RECOVERY_DONE;
1995                 sc->is_leader = 0;
1996                 bnx2x_release_leader_lock(sc);
1997                 mb();
1998
1999                 PMD_DRV_LOG(NOTICE, "Can't unload in closed or error state");
2000                 return -1;
2001         }
2002
2003         /*
2004          * Nothing to do during unload if previous bnx2x_nic_load()
2005          * did not completed succesfully - all resourses are released.
2006          */
2007         if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2008                 return 0;
2009         }
2010
2011         sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2012         mb();
2013
2014         sc->rx_mode = BNX2X_RX_MODE_NONE;
2015         bnx2x_set_rx_mode(sc);
2016         mb();
2017
2018         if (IS_PF(sc)) {
2019                 /* set ALWAYS_ALIVE bit in shmem */
2020                 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2021
2022                 bnx2x_drv_pulse(sc);
2023
2024                 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2025                 bnx2x_save_statistics(sc);
2026         }
2027
2028         /* wait till consumers catch up with producers in all queues */
2029         bnx2x_drain_tx_queues(sc);
2030
2031         /* if VF indicate to PF this function is going down (PF will delete sp
2032          * elements and clear initializations
2033          */
2034         if (IS_VF(sc)) {
2035                 bnx2x_vf_unload(sc);
2036         } else if (unload_mode != UNLOAD_RECOVERY) {
2037                 /* if this is a normal/close unload need to clean up chip */
2038                 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2039         } else {
2040                 /* Send the UNLOAD_REQUEST to the MCP */
2041                 bnx2x_send_unload_req(sc, unload_mode);
2042
2043                 /*
2044                  * Prevent transactions to host from the functions on the
2045                  * engine that doesn't reset global blocks in case of global
2046                  * attention once gloabl blocks are reset and gates are opened
2047                  * (the engine which leader will perform the recovery
2048                  * last).
2049                  */
2050                 if (!CHIP_IS_E1x(sc)) {
2051                         bnx2x_pf_disable(sc);
2052                 }
2053
2054                 /* disable HW interrupts */
2055                 bnx2x_int_disable_sync(sc, TRUE);
2056
2057                 /* Report UNLOAD_DONE to MCP */
2058                 bnx2x_send_unload_done(sc, FALSE);
2059         }
2060
2061         /*
2062          * At this stage no more interrupts will arrive so we may safely clean
2063          * the queue'able objects here in case they failed to get cleaned so far.
2064          */
2065         if (IS_PF(sc)) {
2066                 bnx2x_squeeze_objects(sc);
2067         }
2068
2069         /* There should be no more pending SP commands at this stage */
2070         sc->sp_state = 0;
2071
2072         sc->port.pmf = 0;
2073
2074         if (IS_PF(sc)) {
2075                 bnx2x_free_mem(sc);
2076         }
2077
2078         bnx2x_free_fw_stats_mem(sc);
2079
2080         sc->state = BNX2X_STATE_CLOSED;
2081
2082         /*
2083          * Check if there are pending parity attentions. If there are - set
2084          * RECOVERY_IN_PROGRESS.
2085          */
2086         if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2087                 bnx2x_set_reset_in_progress(sc);
2088
2089                 /* Set RESET_IS_GLOBAL if needed */
2090                 if (global) {
2091                         bnx2x_set_reset_global(sc);
2092                 }
2093         }
2094
2095         /*
2096          * The last driver must disable a "close the gate" if there is no
2097          * parity attention or "process kill" pending.
2098          */
2099         if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2100             bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2101                 bnx2x_disable_close_the_gate(sc);
2102         }
2103
2104         PMD_DRV_LOG(DEBUG, "Ended NIC unload");
2105
2106         return 0;
2107 }
2108
2109 /*
2110  * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2111  * visible to the controller.
2112  *
2113  * If an mbuf is submitted to this routine and cannot be given to the
2114  * controller (e.g. it has too many fragments) then the function may free
2115  * the mbuf and return to the caller.
2116  *
2117  * Returns:
2118  *     int: Number of TX BDs used for the mbuf
2119  *
2120  *   Note the side effect that an mbuf may be freed if it causes a problem.
2121  */
2122 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2123 {
2124         struct eth_tx_start_bd *tx_start_bd;
2125         uint16_t bd_prod, pkt_prod;
2126         struct bnx2x_softc *sc;
2127         uint32_t nbds = 0;
2128
2129         sc = txq->sc;
2130         bd_prod = txq->tx_bd_tail;
2131         pkt_prod = txq->tx_pkt_tail;
2132
2133         txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2134
2135         tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2136
2137         tx_start_bd->addr =
2138             rte_cpu_to_le_64(rte_mbuf_data_dma_addr(m0));
2139         tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2140         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2141         tx_start_bd->general_data =
2142             (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2143
2144         tx_start_bd->nbd = rte_cpu_to_le_16(2);
2145
2146         if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2147                 tx_start_bd->vlan_or_ethertype =
2148                     rte_cpu_to_le_16(m0->vlan_tci);
2149                 tx_start_bd->bd_flags.as_bitfield |=
2150                     (X_ETH_OUTBAND_VLAN <<
2151                      ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2152         } else {
2153                 if (IS_PF(sc))
2154                         tx_start_bd->vlan_or_ethertype =
2155                             rte_cpu_to_le_16(pkt_prod);
2156                 else {
2157                         struct ether_hdr *eh =
2158                             rte_pktmbuf_mtod(m0, struct ether_hdr *);
2159
2160                         tx_start_bd->vlan_or_ethertype =
2161                             rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2162                 }
2163         }
2164
2165         bd_prod = NEXT_TX_BD(bd_prod);
2166         if (IS_VF(sc)) {
2167                 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2168                 const struct ether_hdr *eh =
2169                     rte_pktmbuf_mtod(m0, struct ether_hdr *);
2170                 uint8_t mac_type = UNICAST_ADDRESS;
2171
2172                 tx_parse_bd =
2173                     &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2174                 if (is_multicast_ether_addr(&eh->d_addr)) {
2175                         if (is_broadcast_ether_addr(&eh->d_addr))
2176                                 mac_type = BROADCAST_ADDRESS;
2177                         else
2178                                 mac_type = MULTICAST_ADDRESS;
2179                 }
2180                 tx_parse_bd->parsing_data =
2181                     (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2182
2183                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2184                            &eh->d_addr.addr_bytes[0], 2);
2185                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2186                            &eh->d_addr.addr_bytes[2], 2);
2187                 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2188                            &eh->d_addr.addr_bytes[4], 2);
2189                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2190                            &eh->s_addr.addr_bytes[0], 2);
2191                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2192                            &eh->s_addr.addr_bytes[2], 2);
2193                 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2194                            &eh->s_addr.addr_bytes[4], 2);
2195
2196                 tx_parse_bd->data.mac_addr.dst_hi =
2197                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2198                 tx_parse_bd->data.mac_addr.dst_mid =
2199                     rte_cpu_to_be_16(tx_parse_bd->data.
2200                                      mac_addr.dst_mid);
2201                 tx_parse_bd->data.mac_addr.dst_lo =
2202                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2203                 tx_parse_bd->data.mac_addr.src_hi =
2204                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2205                 tx_parse_bd->data.mac_addr.src_mid =
2206                     rte_cpu_to_be_16(tx_parse_bd->data.
2207                                      mac_addr.src_mid);
2208                 tx_parse_bd->data.mac_addr.src_lo =
2209                     rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2210
2211                 PMD_TX_LOG(DEBUG,
2212                            "PBD dst %x %x %x src %x %x %x p_data %x",
2213                            tx_parse_bd->data.mac_addr.dst_hi,
2214                            tx_parse_bd->data.mac_addr.dst_mid,
2215                            tx_parse_bd->data.mac_addr.dst_lo,
2216                            tx_parse_bd->data.mac_addr.src_hi,
2217                            tx_parse_bd->data.mac_addr.src_mid,
2218                            tx_parse_bd->data.mac_addr.src_lo,
2219                            tx_parse_bd->parsing_data);
2220         }
2221
2222         PMD_TX_LOG(DEBUG,
2223                    "start bd: nbytes %d flags %x vlan %x\n",
2224                    tx_start_bd->nbytes,
2225                    tx_start_bd->bd_flags.as_bitfield,
2226                    tx_start_bd->vlan_or_ethertype);
2227
2228         bd_prod = NEXT_TX_BD(bd_prod);
2229         pkt_prod++;
2230
2231         if (TX_IDX(bd_prod) < 2)
2232                 nbds++;
2233
2234         txq->nb_tx_avail -= 2;
2235         txq->tx_bd_tail = bd_prod;
2236         txq->tx_pkt_tail = pkt_prod;
2237
2238         return nbds + 2;
2239 }
2240
2241 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2242 {
2243         return L2_ILT_LINES(sc);
2244 }
2245
2246 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2247 {
2248         struct ilt_client_info *ilt_client;
2249         struct ecore_ilt *ilt = sc->ilt;
2250         uint16_t line = 0;
2251
2252         PMD_INIT_FUNC_TRACE();
2253
2254         ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2255
2256         /* CDU */
2257         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2258         ilt_client->client_num = ILT_CLIENT_CDU;
2259         ilt_client->page_size = CDU_ILT_PAGE_SZ;
2260         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2261         ilt_client->start = line;
2262         line += bnx2x_cid_ilt_lines(sc);
2263
2264         if (CNIC_SUPPORT(sc)) {
2265                 line += CNIC_ILT_LINES;
2266         }
2267
2268         ilt_client->end = (line - 1);
2269
2270         /* QM */
2271         if (QM_INIT(sc->qm_cid_count)) {
2272                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2273                 ilt_client->client_num = ILT_CLIENT_QM;
2274                 ilt_client->page_size = QM_ILT_PAGE_SZ;
2275                 ilt_client->flags = 0;
2276                 ilt_client->start = line;
2277
2278                 /* 4 bytes for each cid */
2279                 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2280                                      QM_ILT_PAGE_SZ);
2281
2282                 ilt_client->end = (line - 1);
2283         }
2284
2285         if (CNIC_SUPPORT(sc)) {
2286                 /* SRC */
2287                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2288                 ilt_client->client_num = ILT_CLIENT_SRC;
2289                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2290                 ilt_client->flags = 0;
2291                 ilt_client->start = line;
2292                 line += SRC_ILT_LINES;
2293                 ilt_client->end = (line - 1);
2294
2295                 /* TM */
2296                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2297                 ilt_client->client_num = ILT_CLIENT_TM;
2298                 ilt_client->page_size = TM_ILT_PAGE_SZ;
2299                 ilt_client->flags = 0;
2300                 ilt_client->start = line;
2301                 line += TM_ILT_LINES;
2302                 ilt_client->end = (line - 1);
2303         }
2304
2305         assert((line <= ILT_MAX_LINES));
2306 }
2307
2308 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2309 {
2310         int i;
2311
2312         for (i = 0; i < sc->num_queues; i++) {
2313                 /* get the Rx buffer size for RX frames */
2314                 sc->fp[i].rx_buf_size =
2315                     (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2316         }
2317 }
2318
2319 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2320 {
2321
2322         sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2323
2324         return sc->ilt == NULL;
2325 }
2326
2327 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2328 {
2329         sc->ilt->lines = rte_calloc("",
2330                                     sizeof(struct ilt_line), ILT_MAX_LINES,
2331                                     RTE_CACHE_LINE_SIZE);
2332         return sc->ilt->lines == NULL;
2333 }
2334
2335 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2336 {
2337         rte_free(sc->ilt);
2338         sc->ilt = NULL;
2339 }
2340
2341 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2342 {
2343         if (sc->ilt->lines != NULL) {
2344                 rte_free(sc->ilt->lines);
2345                 sc->ilt->lines = NULL;
2346         }
2347 }
2348
2349 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2350 {
2351         uint32_t i;
2352
2353         for (i = 0; i < L2_ILT_LINES(sc); i++) {
2354                 sc->context[i].vcxt = NULL;
2355                 sc->context[i].size = 0;
2356         }
2357
2358         ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2359
2360         bnx2x_free_ilt_lines_mem(sc);
2361 }
2362
2363 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2364 {
2365         int context_size;
2366         int allocated;
2367         int i;
2368         char cdu_name[RTE_MEMZONE_NAMESIZE];
2369
2370         /*
2371          * Allocate memory for CDU context:
2372          * This memory is allocated separately and not in the generic ILT
2373          * functions because CDU differs in few aspects:
2374          * 1. There can be multiple entities allocating memory for context -
2375          * regular L2, CNIC, and SRIOV drivers. Each separately controls
2376          * its own ILT lines.
2377          * 2. Since CDU page-size is not a single 4KB page (which is the case
2378          * for the other ILT clients), to be efficient we want to support
2379          * allocation of sub-page-size in the last entry.
2380          * 3. Context pointers are used by the driver to pass to FW / update
2381          * the context (for the other ILT clients the pointers are used just to
2382          * free the memory during unload).
2383          */
2384         context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2385         for (i = 0, allocated = 0; allocated < context_size; i++) {
2386                 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2387                                           (context_size - allocated));
2388
2389                 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2390                 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2391                                   &sc->context[i].vcxt_dma,
2392                                   cdu_name, BNX2X_PAGE_SIZE) != 0) {
2393                         bnx2x_free_mem(sc);
2394                         return -1;
2395                 }
2396
2397                 sc->context[i].vcxt =
2398                     (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2399
2400                 allocated += sc->context[i].size;
2401         }
2402
2403         bnx2x_alloc_ilt_lines_mem(sc);
2404
2405         if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2406                 PMD_DRV_LOG(NOTICE, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2407                 bnx2x_free_mem(sc);
2408                 return -1;
2409         }
2410
2411         return 0;
2412 }
2413
2414 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2415 {
2416         sc->fw_stats_num = 0;
2417
2418         sc->fw_stats_req_size = 0;
2419         sc->fw_stats_req = NULL;
2420         sc->fw_stats_req_mapping = 0;
2421
2422         sc->fw_stats_data_size = 0;
2423         sc->fw_stats_data = NULL;
2424         sc->fw_stats_data_mapping = 0;
2425 }
2426
2427 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2428 {
2429         uint8_t num_queue_stats;
2430         int num_groups, vf_headroom = 0;
2431
2432         /* number of queues for statistics is number of eth queues */
2433         num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2434
2435         /*
2436          * Total number of FW statistics requests =
2437          *   1 for port stats + 1 for PF stats + num of queues
2438          */
2439         sc->fw_stats_num = (2 + num_queue_stats);
2440
2441         /*
2442          * Request is built from stats_query_header and an array of
2443          * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2444          * rules. The real number or requests is configured in the
2445          * stats_query_header.
2446          */
2447         num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2448         if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2449                 num_groups++;
2450
2451         sc->fw_stats_req_size =
2452             (sizeof(struct stats_query_header) +
2453              (num_groups * sizeof(struct stats_query_cmd_group)));
2454
2455         /*
2456          * Data for statistics requests + stats_counter.
2457          * stats_counter holds per-STORM counters that are incremented when
2458          * STORM has finished with the current request. Memory for FCoE
2459          * offloaded statistics are counted anyway, even if they will not be sent.
2460          * VF stats are not accounted for here as the data of VF stats is stored
2461          * in memory allocated by the VF, not here.
2462          */
2463         sc->fw_stats_data_size =
2464             (sizeof(struct stats_counter) +
2465              sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2466              /* sizeof(struct fcoe_statistics_params) + */
2467              (sizeof(struct per_queue_stats) * num_queue_stats));
2468
2469         if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2470                           &sc->fw_stats_dma, "fw_stats",
2471                           RTE_CACHE_LINE_SIZE) != 0) {
2472                 bnx2x_free_fw_stats_mem(sc);
2473                 return -1;
2474         }
2475
2476         /* set up the shortcuts */
2477
2478         sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2479         sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2480
2481         sc->fw_stats_data =
2482             (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2483                                          sc->fw_stats_req_size);
2484         sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2485                                      sc->fw_stats_req_size);
2486
2487         return 0;
2488 }
2489
2490 /*
2491  * Bits map:
2492  * 0-7  - Engine0 load counter.
2493  * 8-15 - Engine1 load counter.
2494  * 16   - Engine0 RESET_IN_PROGRESS bit.
2495  * 17   - Engine1 RESET_IN_PROGRESS bit.
2496  * 18   - Engine0 ONE_IS_LOADED. Set when there is at least one active
2497  *        function on the engine
2498  * 19   - Engine1 ONE_IS_LOADED.
2499  * 20   - Chip reset flow bit. When set none-leader must wait for both engines
2500  *        leader to complete (check for both RESET_IN_PROGRESS bits and not
2501  *        for just the one belonging to its engine).
2502  */
2503 #define BNX2X_RECOVERY_GLOB_REG     MISC_REG_GENERIC_POR_1
2504 #define BNX2X_PATH0_LOAD_CNT_MASK   0x000000ff
2505 #define BNX2X_PATH0_LOAD_CNT_SHIFT  0
2506 #define BNX2X_PATH1_LOAD_CNT_MASK   0x0000ff00
2507 #define BNX2X_PATH1_LOAD_CNT_SHIFT  8
2508 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2509 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2510 #define BNX2X_GLOBAL_RESET_BIT      0x00040000
2511
2512 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2513 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2514 {
2515         uint32_t val;
2516         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2517         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2518         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2519         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2520 }
2521
2522 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2523 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2524 {
2525         uint32_t val;
2526         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2527         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2528         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2529         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2530 }
2531
2532 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2533 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2534 {
2535         return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2536 }
2537
2538 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2539 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2540 {
2541         uint32_t val;
2542         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2543             BNX2X_PATH0_RST_IN_PROG_BIT;
2544
2545         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2546
2547         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2548         /* Clear the bit */
2549         val &= ~bit;
2550         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2551
2552         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2553 }
2554
2555 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2556 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2557 {
2558         uint32_t val;
2559         uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2560             BNX2X_PATH0_RST_IN_PROG_BIT;
2561
2562         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2563
2564         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2565         /* Set the bit */
2566         val |= bit;
2567         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2568
2569         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2570 }
2571
2572 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2573 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2574 {
2575         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2576         uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2577             BNX2X_PATH0_RST_IN_PROG_BIT;
2578
2579         /* return false if bit is set */
2580         return (val & bit) ? FALSE : TRUE;
2581 }
2582
2583 /* get the load status for an engine, should be run under rtnl lock */
2584 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2585 {
2586         uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2587             BNX2X_PATH0_LOAD_CNT_MASK;
2588         uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2589             BNX2X_PATH0_LOAD_CNT_SHIFT;
2590         uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2591
2592         val = ((val & mask) >> shift);
2593
2594         return val != 0;
2595 }
2596
2597 /* set pf load mark */
2598 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2599 {
2600         uint32_t val;
2601         uint32_t val1;
2602         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2603             BNX2X_PATH0_LOAD_CNT_MASK;
2604         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2605             BNX2X_PATH0_LOAD_CNT_SHIFT;
2606
2607         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2608
2609         PMD_INIT_FUNC_TRACE();
2610
2611         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2612
2613         /* get the current counter value */
2614         val1 = ((val & mask) >> shift);
2615
2616         /* set bit of this PF */
2617         val1 |= (1 << SC_ABS_FUNC(sc));
2618
2619         /* clear the old value */
2620         val &= ~mask;
2621
2622         /* set the new one */
2623         val |= ((val1 << shift) & mask);
2624
2625         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2626
2627         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2628 }
2629
2630 /* clear pf load mark */
2631 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2632 {
2633         uint32_t val1, val;
2634         uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2635             BNX2X_PATH0_LOAD_CNT_MASK;
2636         uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2637             BNX2X_PATH0_LOAD_CNT_SHIFT;
2638
2639         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2640         val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2641
2642         /* get the current counter value */
2643         val1 = (val & mask) >> shift;
2644
2645         /* clear bit of that PF */
2646         val1 &= ~(1 << SC_ABS_FUNC(sc));
2647
2648         /* clear the old value */
2649         val &= ~mask;
2650
2651         /* set the new one */
2652         val |= ((val1 << shift) & mask);
2653
2654         REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2655         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2656         return val1 != 0;
2657 }
2658
2659 /* send load requrest to mcp and analyze response */
2660 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2661 {
2662         PMD_INIT_FUNC_TRACE();
2663
2664         /* init fw_seq */
2665         sc->fw_seq =
2666             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2667              DRV_MSG_SEQ_NUMBER_MASK);
2668
2669         PMD_DRV_LOG(DEBUG, "initial fw_seq 0x%04x", sc->fw_seq);
2670
2671 #ifdef BNX2X_PULSE
2672         /* get the current FW pulse sequence */
2673         sc->fw_drv_pulse_wr_seq =
2674             (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2675              DRV_PULSE_SEQ_MASK);
2676 #else
2677         /* set ALWAYS_ALIVE bit in shmem */
2678         sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2679         bnx2x_drv_pulse(sc);
2680 #endif
2681
2682         /* load request */
2683         (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2684                                       DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2685
2686         /* if the MCP fails to respond we must abort */
2687         if (!(*load_code)) {
2688                 PMD_DRV_LOG(NOTICE, "MCP response failure!");
2689                 return -1;
2690         }
2691
2692         /* if MCP refused then must abort */
2693         if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2694                 PMD_DRV_LOG(NOTICE, "MCP refused load request");
2695                 return -1;
2696         }
2697
2698         return 0;
2699 }
2700
2701 /*
2702  * Check whether another PF has already loaded FW to chip. In virtualized
2703  * environments a pf from anoth VM may have already initialized the device
2704  * including loading FW.
2705  */
2706 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2707 {
2708         uint32_t my_fw, loaded_fw;
2709
2710         /* is another pf loaded on this engine? */
2711         if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2712             (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2713                 /* build my FW version dword */
2714                 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2715                          (BNX2X_5710_FW_MINOR_VERSION << 8) +
2716                          (BNX2X_5710_FW_REVISION_VERSION << 16) +
2717                          (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2718
2719                 /* read loaded FW from chip */
2720                 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2721                 PMD_DRV_LOG(DEBUG, "loaded FW 0x%08x / my FW 0x%08x",
2722                             loaded_fw, my_fw);
2723
2724                 /* abort nic load if version mismatch */
2725                 if (my_fw != loaded_fw) {
2726                         PMD_DRV_LOG(NOTICE,
2727                                     "FW 0x%08x already loaded (mine is 0x%08x)",
2728                                     loaded_fw, my_fw);
2729                         return -1;
2730                 }
2731         }
2732
2733         return 0;
2734 }
2735
2736 /* mark PMF if applicable */
2737 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2738 {
2739         uint32_t ncsi_oem_data_addr;
2740
2741         PMD_INIT_FUNC_TRACE();
2742
2743         if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2744             (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2745             (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2746                 /*
2747                  * Barrier here for ordering between the writing to sc->port.pmf here
2748                  * and reading it from the periodic task.
2749                  */
2750                 sc->port.pmf = 1;
2751                 mb();
2752         } else {
2753                 sc->port.pmf = 0;
2754         }
2755
2756         PMD_DRV_LOG(DEBUG, "pmf %d", sc->port.pmf);
2757
2758         if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2759                 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2760                         ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2761                         if (ncsi_oem_data_addr) {
2762                                 REG_WR(sc,
2763                                        (ncsi_oem_data_addr +
2764                                         offsetof(struct glob_ncsi_oem_data,
2765                                                  driver_version)), 0);
2766                         }
2767                 }
2768         }
2769 }
2770
2771 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2772 {
2773         int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2774         int abs_func;
2775         int vn;
2776
2777         if (BNX2X_NOMCP(sc)) {
2778                 return;         /* what should be the default bvalue in this case */
2779         }
2780
2781         /*
2782          * The formula for computing the absolute function number is...
2783          * For 2 port configuration (4 functions per port):
2784          *   abs_func = 2 * vn + SC_PORT + SC_PATH
2785          * For 4 port configuration (2 functions per port):
2786          *   abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2787          */
2788         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2789                 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2790                 if (abs_func >= E1H_FUNC_MAX) {
2791                         break;
2792                 }
2793                 sc->devinfo.mf_info.mf_config[vn] =
2794                     MFCFG_RD(sc, func_mf_config[abs_func].config);
2795         }
2796
2797         if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2798             FUNC_MF_CFG_FUNC_DISABLED) {
2799                 PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
2800                 sc->flags |= BNX2X_MF_FUNC_DIS;
2801         } else {
2802                 PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
2803                 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2804         }
2805 }
2806
2807 /* acquire split MCP access lock register */
2808 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2809 {
2810         uint32_t j, val;
2811
2812         for (j = 0; j < 1000; j++) {
2813                 val = (1UL << 31);
2814                 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2815                 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2816                 if (val & (1L << 31))
2817                         break;
2818
2819                 DELAY(5000);
2820         }
2821
2822         if (!(val & (1L << 31))) {
2823                 PMD_DRV_LOG(NOTICE, "Cannot acquire MCP access lock register");
2824                 return -1;
2825         }
2826
2827         return 0;
2828 }
2829
2830 /* release split MCP access lock register */
2831 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2832 {
2833         REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2834 }
2835
2836 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2837 {
2838         int port = SC_PORT(sc);
2839         uint32_t ext_phy_config;
2840
2841         /* mark the failure */
2842         ext_phy_config =
2843             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2844
2845         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2846         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2847         SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2848                  ext_phy_config);
2849
2850         /* log the failure */
2851         PMD_DRV_LOG(INFO,
2852                     "Fan Failure has caused the driver to shutdown "
2853                     "the card to prevent permanent damage. "
2854                     "Please contact OEM Support for assistance");
2855
2856         rte_panic("Schedule task to handle fan failure");
2857 }
2858
2859 /* this function is called upon a link interrupt */
2860 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2861 {
2862         uint32_t pause_enabled = 0;
2863         struct host_port_stats *pstats;
2864         int cmng_fns;
2865
2866         /* Make sure that we are synced with the current statistics */
2867         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2868
2869         elink_link_update(&sc->link_params, &sc->link_vars);
2870
2871         if (sc->link_vars.link_up) {
2872
2873                 /* dropless flow control */
2874                 if (sc->dropless_fc) {
2875                         pause_enabled = 0;
2876
2877                         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2878                                 pause_enabled = 1;
2879                         }
2880
2881                         REG_WR(sc,
2882                                (BAR_USTRORM_INTMEM +
2883                                 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2884                                pause_enabled);
2885                 }
2886
2887                 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2888                         pstats = BNX2X_SP(sc, port_stats);
2889                         /* reset old mac stats */
2890                         memset(&(pstats->mac_stx[0]), 0,
2891                                sizeof(struct mac_stx));
2892                 }
2893
2894                 if (sc->state == BNX2X_STATE_OPEN) {
2895                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2896                 }
2897         }
2898
2899         if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2900                 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2901
2902                 if (cmng_fns != CMNG_FNS_NONE) {
2903                         bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2904                         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2905                 }
2906         }
2907
2908         bnx2x_link_report(sc);
2909
2910         if (IS_MF(sc)) {
2911                 bnx2x_link_sync_notify(sc);
2912         }
2913 }
2914
2915 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2916 {
2917         int port = SC_PORT(sc);
2918         uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2919             MISC_REG_AEU_MASK_ATTN_FUNC_0;
2920         uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2921             NIG_REG_MASK_INTERRUPT_PORT0;
2922         uint32_t aeu_mask;
2923         uint32_t nig_mask = 0;
2924         uint32_t reg_addr;
2925         uint32_t igu_acked;
2926         uint32_t cnt;
2927
2928         if (sc->attn_state & asserted) {
2929                 PMD_DRV_LOG(ERR, "IGU ERROR attn=0x%08x", asserted);
2930         }
2931
2932         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2933
2934         aeu_mask = REG_RD(sc, aeu_addr);
2935
2936         aeu_mask &= ~(asserted & 0x3ff);
2937
2938         REG_WR(sc, aeu_addr, aeu_mask);
2939
2940         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2941
2942         sc->attn_state |= asserted;
2943
2944         if (asserted & ATTN_HARD_WIRED_MASK) {
2945                 if (asserted & ATTN_NIG_FOR_FUNC) {
2946
2947                         /* save nig interrupt mask */
2948                         nig_mask = REG_RD(sc, nig_int_mask_addr);
2949
2950                         /* If nig_mask is not set, no need to call the update function */
2951                         if (nig_mask) {
2952                                 REG_WR(sc, nig_int_mask_addr, 0);
2953
2954                                 bnx2x_link_attn(sc);
2955                         }
2956
2957                         /* handle unicore attn? */
2958                 }
2959
2960                 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2961                         PMD_DRV_LOG(DEBUG, "ATTN_SW_TIMER_4_FUNC!");
2962                 }
2963
2964                 if (asserted & GPIO_2_FUNC) {
2965                         PMD_DRV_LOG(DEBUG, "GPIO_2_FUNC!");
2966                 }
2967
2968                 if (asserted & GPIO_3_FUNC) {
2969                         PMD_DRV_LOG(DEBUG, "GPIO_3_FUNC!");
2970                 }
2971
2972                 if (asserted & GPIO_4_FUNC) {
2973                         PMD_DRV_LOG(DEBUG, "GPIO_4_FUNC!");
2974                 }
2975
2976                 if (port == 0) {
2977                         if (asserted & ATTN_GENERAL_ATTN_1) {
2978                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_1!");
2979                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2980                         }
2981                         if (asserted & ATTN_GENERAL_ATTN_2) {
2982                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_2!");
2983                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2984                         }
2985                         if (asserted & ATTN_GENERAL_ATTN_3) {
2986                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_3!");
2987                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2988                         }
2989                 } else {
2990                         if (asserted & ATTN_GENERAL_ATTN_4) {
2991                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_4!");
2992                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2993                         }
2994                         if (asserted & ATTN_GENERAL_ATTN_5) {
2995                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_5!");
2996                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2997                         }
2998                         if (asserted & ATTN_GENERAL_ATTN_6) {
2999                                 PMD_DRV_LOG(DEBUG, "ATTN_GENERAL_ATTN_6!");
3000                                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3001                         }
3002                 }
3003         }
3004         /* hardwired */
3005         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3006                 reg_addr =
3007                     (HC_REG_COMMAND_REG + port * 32 +
3008                      COMMAND_REG_ATTN_BITS_SET);
3009         } else {
3010                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3011         }
3012
3013         PMD_DRV_LOG(DEBUG, "about to mask 0x%08x at %s addr 0x%08x",
3014                     asserted,
3015                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3016                     reg_addr);
3017         REG_WR(sc, reg_addr, asserted);
3018
3019         /* now set back the mask */
3020         if (asserted & ATTN_NIG_FOR_FUNC) {
3021                 /*
3022                  * Verify that IGU ack through BAR was written before restoring
3023                  * NIG mask. This loop should exit after 2-3 iterations max.
3024                  */
3025                 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3026                         cnt = 0;
3027
3028                         do {
3029                                 igu_acked =
3030                                     REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3031                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3032                                  && (++cnt < MAX_IGU_ATTN_ACK_TO));
3033
3034                         if (!igu_acked) {
3035                                 PMD_DRV_LOG(ERR,
3036                                             "Failed to verify IGU ack on time");
3037                         }
3038
3039                         mb();
3040                 }
3041
3042                 REG_WR(sc, nig_int_mask_addr, nig_mask);
3043
3044         }
3045 }
3046
3047 static void
3048 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3049                      __rte_unused const char *blk)
3050 {
3051         PMD_DRV_LOG(INFO, "%s%s", idx ? ", " : "", blk);
3052 }
3053
3054 static int
3055 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3056                               uint8_t print)
3057 {
3058         uint32_t cur_bit = 0;
3059         int i = 0;
3060
3061         for (i = 0; sig; i++) {
3062                 cur_bit = ((uint32_t) 0x1 << i);
3063                 if (sig & cur_bit) {
3064                         switch (cur_bit) {
3065                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3066                                 if (print)
3067                                         bnx2x_print_next_block(sc, par_num++,
3068                                                              "BRB");
3069                                 break;
3070                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3071                                 if (print)
3072                                         bnx2x_print_next_block(sc, par_num++,
3073                                                              "PARSER");
3074                                 break;
3075                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3076                                 if (print)
3077                                         bnx2x_print_next_block(sc, par_num++,
3078                                                              "TSDM");
3079                                 break;
3080                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3081                                 if (print)
3082                                         bnx2x_print_next_block(sc, par_num++,
3083                                                              "SEARCHER");
3084                                 break;
3085                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3086                                 if (print)
3087                                         bnx2x_print_next_block(sc, par_num++,
3088                                                              "TCM");
3089                                 break;
3090                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3091                                 if (print)
3092                                         bnx2x_print_next_block(sc, par_num++,
3093                                                              "TSEMI");
3094                                 break;
3095                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3096                                 if (print)
3097                                         bnx2x_print_next_block(sc, par_num++,
3098                                                              "XPB");
3099                                 break;
3100                         }
3101
3102                         /* Clear the bit */
3103                         sig &= ~cur_bit;
3104                 }
3105         }
3106
3107         return par_num;
3108 }
3109
3110 static int
3111 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3112                               uint8_t * global, uint8_t print)
3113 {
3114         int i = 0;
3115         uint32_t cur_bit = 0;
3116         for (i = 0; sig; i++) {
3117                 cur_bit = ((uint32_t) 0x1 << i);
3118                 if (sig & cur_bit) {
3119                         switch (cur_bit) {
3120                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3121                                 if (print)
3122                                         bnx2x_print_next_block(sc, par_num++,
3123                                                              "PBF");
3124                                 break;
3125                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3126                                 if (print)
3127                                         bnx2x_print_next_block(sc, par_num++,
3128                                                              "QM");
3129                                 break;
3130                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3131                                 if (print)
3132                                         bnx2x_print_next_block(sc, par_num++,
3133                                                              "TM");
3134                                 break;
3135                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3136                                 if (print)
3137                                         bnx2x_print_next_block(sc, par_num++,
3138                                                              "XSDM");
3139                                 break;
3140                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3141                                 if (print)
3142                                         bnx2x_print_next_block(sc, par_num++,
3143                                                              "XCM");
3144                                 break;
3145                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3146                                 if (print)
3147                                         bnx2x_print_next_block(sc, par_num++,
3148                                                              "XSEMI");
3149                                 break;
3150                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3151                                 if (print)
3152                                         bnx2x_print_next_block(sc, par_num++,
3153                                                              "DOORBELLQ");
3154                                 break;
3155                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3156                                 if (print)
3157                                         bnx2x_print_next_block(sc, par_num++,
3158                                                              "NIG");
3159                                 break;
3160                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3161                                 if (print)
3162                                         bnx2x_print_next_block(sc, par_num++,
3163                                                              "VAUX PCI CORE");
3164                                 *global = TRUE;
3165                                 break;
3166                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3167                                 if (print)
3168                                         bnx2x_print_next_block(sc, par_num++,
3169                                                              "DEBUG");
3170                                 break;
3171                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3172                                 if (print)
3173                                         bnx2x_print_next_block(sc, par_num++,
3174                                                              "USDM");
3175                                 break;
3176                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3177                                 if (print)
3178                                         bnx2x_print_next_block(sc, par_num++,
3179                                                              "UCM");
3180                                 break;
3181                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3182                                 if (print)
3183                                         bnx2x_print_next_block(sc, par_num++,
3184                                                              "USEMI");
3185                                 break;
3186                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3187                                 if (print)
3188                                         bnx2x_print_next_block(sc, par_num++,
3189                                                              "UPB");
3190                                 break;
3191                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3192                                 if (print)
3193                                         bnx2x_print_next_block(sc, par_num++,
3194                                                              "CSDM");
3195                                 break;
3196                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3197                                 if (print)
3198                                         bnx2x_print_next_block(sc, par_num++,
3199                                                              "CCM");
3200                                 break;
3201                         }
3202
3203                         /* Clear the bit */
3204                         sig &= ~cur_bit;
3205                 }
3206         }
3207
3208         return par_num;
3209 }
3210
3211 static int
3212 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3213                               uint8_t print)
3214 {
3215         uint32_t cur_bit = 0;
3216         int i = 0;
3217
3218         for (i = 0; sig; i++) {
3219                 cur_bit = ((uint32_t) 0x1 << i);
3220                 if (sig & cur_bit) {
3221                         switch (cur_bit) {
3222                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3223                                 if (print)
3224                                         bnx2x_print_next_block(sc, par_num++,
3225                                                              "CSEMI");
3226                                 break;
3227                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3228                                 if (print)
3229                                         bnx2x_print_next_block(sc, par_num++,
3230                                                              "PXP");
3231                                 break;
3232                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3233                                 if (print)
3234                                         bnx2x_print_next_block(sc, par_num++,
3235                                                              "PXPPCICLOCKCLIENT");
3236                                 break;
3237                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3238                                 if (print)
3239                                         bnx2x_print_next_block(sc, par_num++,
3240                                                              "CFC");
3241                                 break;
3242                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3243                                 if (print)
3244                                         bnx2x_print_next_block(sc, par_num++,
3245                                                              "CDU");
3246                                 break;
3247                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3248                                 if (print)
3249                                         bnx2x_print_next_block(sc, par_num++,
3250                                                              "DMAE");
3251                                 break;
3252                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3253                                 if (print)
3254                                         bnx2x_print_next_block(sc, par_num++,
3255                                                              "IGU");
3256                                 break;
3257                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3258                                 if (print)
3259                                         bnx2x_print_next_block(sc, par_num++,
3260                                                              "MISC");
3261                                 break;
3262                         }
3263
3264                         /* Clear the bit */
3265                         sig &= ~cur_bit;
3266                 }
3267         }
3268
3269         return par_num;
3270 }
3271
3272 static int
3273 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3274                               uint8_t * global, uint8_t print)
3275 {
3276         uint32_t cur_bit = 0;
3277         int i = 0;
3278
3279         for (i = 0; sig; i++) {
3280                 cur_bit = ((uint32_t) 0x1 << i);
3281                 if (sig & cur_bit) {
3282                         switch (cur_bit) {
3283                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3284                                 if (print)
3285                                         bnx2x_print_next_block(sc, par_num++,
3286                                                              "MCP ROM");
3287                                 *global = TRUE;
3288                                 break;
3289                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3290                                 if (print)
3291                                         bnx2x_print_next_block(sc, par_num++,
3292                                                              "MCP UMP RX");
3293                                 *global = TRUE;
3294                                 break;
3295                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3296                                 if (print)
3297                                         bnx2x_print_next_block(sc, par_num++,
3298                                                              "MCP UMP TX");
3299                                 *global = TRUE;
3300                                 break;
3301                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3302                                 if (print)
3303                                         bnx2x_print_next_block(sc, par_num++,
3304                                                              "MCP SCPAD");
3305                                 *global = TRUE;
3306                                 break;
3307                         }
3308
3309                         /* Clear the bit */
3310                         sig &= ~cur_bit;
3311                 }
3312         }
3313
3314         return par_num;
3315 }
3316
3317 static int
3318 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3319                               uint8_t print)
3320 {
3321         uint32_t cur_bit = 0;
3322         int i = 0;
3323
3324         for (i = 0; sig; i++) {
3325                 cur_bit = ((uint32_t) 0x1 << i);
3326                 if (sig & cur_bit) {
3327                         switch (cur_bit) {
3328                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3329                                 if (print)
3330                                         bnx2x_print_next_block(sc, par_num++,
3331                                                              "PGLUE_B");
3332                                 break;
3333                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3334                                 if (print)
3335                                         bnx2x_print_next_block(sc, par_num++,
3336                                                              "ATC");
3337                                 break;
3338                         }
3339
3340                         /* Clear the bit */
3341                         sig &= ~cur_bit;
3342                 }
3343         }
3344
3345         return par_num;
3346 }
3347
3348 static uint8_t
3349 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3350                 uint32_t * sig)
3351 {
3352         int par_num = 0;
3353
3354         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3355             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3356             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3357             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3358             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3359                 PMD_DRV_LOG(ERR,
3360                             "Parity error: HW block parity attention:"
3361                             "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3362                             (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3363                             (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3364                             (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3365                             (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3366                             (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3367
3368                 if (print)
3369                         PMD_DRV_LOG(INFO, "Parity errors detected in blocks: ");
3370
3371                 par_num =
3372                     bnx2x_check_blocks_with_parity0(sc, sig[0] &
3373                                                   HW_PRTY_ASSERT_SET_0,
3374                                                   par_num, print);
3375                 par_num =
3376                     bnx2x_check_blocks_with_parity1(sc, sig[1] &
3377                                                   HW_PRTY_ASSERT_SET_1,
3378                                                   par_num, global, print);
3379                 par_num =
3380                     bnx2x_check_blocks_with_parity2(sc, sig[2] &
3381                                                   HW_PRTY_ASSERT_SET_2,
3382                                                   par_num, print);
3383                 par_num =
3384                     bnx2x_check_blocks_with_parity3(sc, sig[3] &
3385                                                   HW_PRTY_ASSERT_SET_3,
3386                                                   par_num, global, print);
3387                 par_num =
3388                     bnx2x_check_blocks_with_parity4(sc, sig[4] &
3389                                                   HW_PRTY_ASSERT_SET_4,
3390                                                   par_num, print);
3391
3392                 if (print)
3393                         PMD_DRV_LOG(INFO, "");
3394
3395                 return TRUE;
3396         }
3397
3398         return FALSE;
3399 }
3400
3401 static uint8_t
3402 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3403 {
3404         struct attn_route attn = { {0} };
3405         int port = SC_PORT(sc);
3406
3407         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3408         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3409         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3410         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3411
3412         if (!CHIP_IS_E1x(sc))
3413                 attn.sig[4] =
3414                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3415
3416         return bnx2x_parity_attn(sc, global, print, attn.sig);
3417 }
3418
3419 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3420 {
3421         uint32_t val;
3422
3423         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3424                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3425                 PMD_DRV_LOG(INFO, "ERROR: PGLUE hw attention 0x%08x", val);
3426                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3427                         PMD_DRV_LOG(INFO,
3428                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3429                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3430                         PMD_DRV_LOG(INFO,
3431                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3432                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3433                         PMD_DRV_LOG(INFO,
3434                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3435                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3436                         PMD_DRV_LOG(INFO,
3437                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3438                 if (val &
3439                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3440                         PMD_DRV_LOG(INFO,
3441                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3442                 if (val &
3443                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3444                         PMD_DRV_LOG(INFO,
3445                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3446                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3447                         PMD_DRV_LOG(INFO,
3448                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3449                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3450                         PMD_DRV_LOG(INFO,
3451                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3452                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3453                         PMD_DRV_LOG(INFO,
3454                                     "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3455         }
3456
3457         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3458                 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3459                 PMD_DRV_LOG(INFO, "ERROR: ATC hw attention 0x%08x", val);
3460                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3461                         PMD_DRV_LOG(INFO,
3462                                     "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3463                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3464                         PMD_DRV_LOG(INFO,
3465                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3466                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3467                         PMD_DRV_LOG(INFO,
3468                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3469                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3470                         PMD_DRV_LOG(INFO,
3471                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3472                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3473                         PMD_DRV_LOG(INFO,
3474                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3475                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3476                         PMD_DRV_LOG(INFO,
3477                                     "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3478         }
3479
3480         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3481                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3482                 PMD_DRV_LOG(INFO,
3483                             "ERROR: FATAL parity attention set4 0x%08x",
3484                             (uint32_t) (attn &
3485                                         (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3486                                          |
3487                                          AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3488         }
3489 }
3490
3491 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3492 {
3493         int port = SC_PORT(sc);
3494
3495         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3496 }
3497
3498 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3499 {
3500         int port = SC_PORT(sc);
3501
3502         REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3503 }
3504
3505 /*
3506  * called due to MCP event (on pmf):
3507  *   reread new bandwidth configuration
3508  *   configure FW
3509  *   notify others function about the change
3510  */
3511 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3512 {
3513         if (sc->link_vars.link_up) {
3514                 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3515                 bnx2x_link_sync_notify(sc);
3516         }
3517
3518         storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3519 }
3520
3521 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3522 {
3523         bnx2x_config_mf_bw(sc);
3524         bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3525 }
3526
3527 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3528 {
3529         bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3530 }
3531
3532 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3533
3534 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3535 {
3536         struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3537
3538         strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3539                 ETH_STAT_INFO_VERSION_LEN);
3540
3541         sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3542                                               DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3543                                               ether_stat->mac_local + MAC_PAD,
3544                                               MAC_PAD, ETH_ALEN);
3545
3546         ether_stat->mtu_size = sc->mtu;
3547
3548         ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3549         ether_stat->promiscuous_mode = 0;       // (flags & PROMISC) ? 1 : 0;
3550
3551         ether_stat->txq_size = sc->tx_ring_size;
3552         ether_stat->rxq_size = sc->rx_ring_size;
3553 }
3554
3555 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3556 {
3557         enum drv_info_opcode op_code;
3558         uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3559
3560         /* if drv_info version supported by MFW doesn't match - send NACK */
3561         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3562                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3563                 return;
3564         }
3565
3566         op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3567                    DRV_INFO_CONTROL_OP_CODE_SHIFT);
3568
3569         memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3570
3571         switch (op_code) {
3572         case ETH_STATS_OPCODE:
3573                 bnx2x_drv_info_ether_stat(sc);
3574                 break;
3575         case FCOE_STATS_OPCODE:
3576         case ISCSI_STATS_OPCODE:
3577         default:
3578                 /* if op code isn't supported - send NACK */
3579                 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3580                 return;
3581         }
3582
3583         /*
3584          * If we got drv_info attn from MFW then these fields are defined in
3585          * shmem2 for sure
3586          */
3587         SHMEM2_WR(sc, drv_info_host_addr_lo,
3588                   U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3589         SHMEM2_WR(sc, drv_info_host_addr_hi,
3590                   U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3591
3592         bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3593 }
3594
3595 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3596 {
3597         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3598 /*
3599  * This is the only place besides the function initialization
3600  * where the sc->flags can change so it is done without any
3601  * locks
3602  */
3603                 if (sc->devinfo.
3604                     mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3605                         PMD_DRV_LOG(DEBUG, "mf_cfg function disabled");
3606                         sc->flags |= BNX2X_MF_FUNC_DIS;
3607                         bnx2x_e1h_disable(sc);
3608                 } else {
3609                         PMD_DRV_LOG(DEBUG, "mf_cfg function enabled");
3610                         sc->flags &= ~BNX2X_MF_FUNC_DIS;
3611                         bnx2x_e1h_enable(sc);
3612                 }
3613                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3614         }
3615
3616         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3617                 bnx2x_config_mf_bw(sc);
3618                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3619         }
3620
3621         /* Report results to MCP */
3622         if (dcc_event)
3623                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3624         else
3625                 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3626 }
3627
3628 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3629 {
3630         int port = SC_PORT(sc);
3631         uint32_t val;
3632
3633         sc->port.pmf = 1;
3634
3635         /*
3636          * We need the mb() to ensure the ordering between the writing to
3637          * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3638          */
3639         mb();
3640
3641         /* enable nig attention */
3642         val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3643         if (sc->devinfo.int_block == INT_BLOCK_HC) {
3644                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3645                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3646         } else if (!CHIP_IS_E1x(sc)) {
3647                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3648                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3649         }
3650
3651         bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3652 }
3653
3654 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3655 {
3656         char last_idx;
3657         int i, rc = 0;
3658         __rte_unused uint32_t row0, row1, row2, row3;
3659
3660         /* XSTORM */
3661         last_idx =
3662             REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3663         if (last_idx)
3664                 PMD_DRV_LOG(ERR, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3665
3666         /* print the asserts */
3667         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3668
3669                 row0 =
3670                     REG_RD(sc,
3671                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3672                 row1 =
3673                     REG_RD(sc,
3674                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3675                            4);
3676                 row2 =
3677                     REG_RD(sc,
3678                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3679                            8);
3680                 row3 =
3681                     REG_RD(sc,
3682                            BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3683                            12);
3684
3685                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3686                         PMD_DRV_LOG(ERR,
3687                                     "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3688                                     i, row3, row2, row1, row0);
3689                         rc++;
3690                 } else {
3691                         break;
3692                 }
3693         }
3694
3695         /* TSTORM */
3696         last_idx =
3697             REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3698         if (last_idx) {
3699                 PMD_DRV_LOG(ERR, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3700         }
3701
3702         /* print the asserts */
3703         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3704
3705                 row0 =
3706                     REG_RD(sc,
3707                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3708                 row1 =
3709                     REG_RD(sc,
3710                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3711                            4);
3712                 row2 =
3713                     REG_RD(sc,
3714                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3715                            8);
3716                 row3 =
3717                     REG_RD(sc,
3718                            BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3719                            12);
3720
3721                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3722                         PMD_DRV_LOG(ERR,
3723                                     "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3724                                     i, row3, row2, row1, row0);
3725                         rc++;
3726                 } else {
3727                         break;
3728                 }
3729         }
3730
3731         /* CSTORM */
3732         last_idx =
3733             REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3734         if (last_idx) {
3735                 PMD_DRV_LOG(ERR, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3736         }
3737
3738         /* print the asserts */
3739         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3740
3741                 row0 =
3742                     REG_RD(sc,
3743                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3744                 row1 =
3745                     REG_RD(sc,
3746                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3747                            4);
3748                 row2 =
3749                     REG_RD(sc,
3750                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3751                            8);
3752                 row3 =
3753                     REG_RD(sc,
3754                            BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3755                            12);
3756
3757                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3758                         PMD_DRV_LOG(ERR,
3759                                     "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3760                                     i, row3, row2, row1, row0);
3761                         rc++;
3762                 } else {
3763                         break;
3764                 }
3765         }
3766
3767         /* USTORM */
3768         last_idx =
3769             REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3770         if (last_idx) {
3771                 PMD_DRV_LOG(ERR, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3772         }
3773
3774         /* print the asserts */
3775         for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3776
3777                 row0 =
3778                     REG_RD(sc,
3779                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3780                 row1 =
3781                     REG_RD(sc,
3782                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3783                            4);
3784                 row2 =
3785                     REG_RD(sc,
3786                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3787                            8);
3788                 row3 =
3789                     REG_RD(sc,
3790                            BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3791                            12);
3792
3793                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3794                         PMD_DRV_LOG(ERR,
3795                                     "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3796                                     i, row3, row2, row1, row0);
3797                         rc++;
3798                 } else {
3799                         break;
3800                 }
3801         }
3802
3803         return rc;
3804 }
3805
3806 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3807 {
3808         int func = SC_FUNC(sc);
3809         uint32_t val;
3810
3811         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3812
3813                 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3814
3815                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3816                         bnx2x_read_mf_cfg(sc);
3817                         sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3818                             MFCFG_RD(sc,
3819                                      func_mf_config[SC_ABS_FUNC(sc)].config);
3820                         val =
3821                             SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3822
3823                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3824                                 bnx2x_dcc_event(sc,
3825                                               (val &
3826                                                DRV_STATUS_DCC_EVENT_MASK));
3827
3828                         if (val & DRV_STATUS_SET_MF_BW)
3829                                 bnx2x_set_mf_bw(sc);
3830
3831                         if (val & DRV_STATUS_DRV_INFO_REQ)
3832                                 bnx2x_handle_drv_info_req(sc);
3833
3834                         if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3835                                 bnx2x_pmf_update(sc);
3836
3837                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3838                                 bnx2x_handle_eee_event(sc);
3839
3840                         if (sc->link_vars.periodic_flags &
3841                             ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3842                                 /* sync with link */
3843                                 sc->link_vars.periodic_flags &=
3844                                     ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3845                                 if (IS_MF(sc)) {
3846                                         bnx2x_link_sync_notify(sc);
3847                                 }
3848                                 bnx2x_link_report(sc);
3849                         }
3850
3851                         /*
3852                          * Always call it here: bnx2x_link_report() will
3853                          * prevent the link indication duplication.
3854                          */
3855                         bnx2x_link_status_update(sc);
3856
3857                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3858
3859                         PMD_DRV_LOG(ERR, "MC assert!");
3860                         bnx2x_mc_assert(sc);
3861                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3862                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3863                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3864                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3865                         rte_panic("MC assert!");
3866
3867                 } else if (attn & BNX2X_MCP_ASSERT) {
3868
3869                         PMD_DRV_LOG(ERR, "MCP assert!");
3870                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3871
3872                 } else {
3873                         PMD_DRV_LOG(ERR,
3874                                     "Unknown HW assert! (attn 0x%08x)", attn);
3875                 }
3876         }
3877
3878         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3879                 PMD_DRV_LOG(ERR, "LATCHED attention 0x%08x (masked)", attn);
3880                 if (attn & BNX2X_GRC_TIMEOUT) {
3881                         val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3882                         PMD_DRV_LOG(ERR, "GRC time-out 0x%08x", val);
3883                 }
3884                 if (attn & BNX2X_GRC_RSV) {
3885                         val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3886                         PMD_DRV_LOG(ERR, "GRC reserved 0x%08x", val);
3887                 }
3888                 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3889         }
3890 }
3891
3892 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3893 {
3894         int port = SC_PORT(sc);
3895         int reg_offset;
3896         uint32_t val0, mask0, val1, mask1;
3897         uint32_t val;
3898
3899         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3900                 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3901                 PMD_DRV_LOG(ERR, "CFC hw attention 0x%08x", val);
3902 /* CFC error attention */
3903                 if (val & 0x2) {
3904                         PMD_DRV_LOG(ERR, "FATAL error from CFC");
3905                 }
3906         }
3907
3908         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3909                 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3910                 PMD_DRV_LOG(ERR, "PXP hw attention-0 0x%08x", val);
3911 /* RQ_USDMDP_FIFO_OVERFLOW */
3912                 if (val & 0x18000) {
3913                         PMD_DRV_LOG(ERR, "FATAL error from PXP");
3914                 }
3915
3916                 if (!CHIP_IS_E1x(sc)) {
3917                         val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3918                         PMD_DRV_LOG(ERR, "PXP hw attention-1 0x%08x", val);
3919                 }
3920         }
3921 #define PXP2_EOP_ERROR_BIT  PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3922 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3923
3924         if (attn & AEU_PXP2_HW_INT_BIT) {
3925 /*  CQ47854 workaround do not panic on
3926  *  PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3927  */
3928                 if (!CHIP_IS_E1x(sc)) {
3929                         mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3930                         val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3931                         mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3932                         val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3933                         /*
3934                          * If the olny PXP2_EOP_ERROR_BIT is set in
3935                          * STS0 and STS1 - clear it
3936                          *
3937                          * probably we lose additional attentions between
3938                          * STS0 and STS_CLR0, in this case user will not
3939                          * be notified about them
3940                          */
3941                         if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3942                             !(val1 & mask1))
3943                                 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3944
3945                         /* print the register, since no one can restore it */
3946                         PMD_DRV_LOG(ERR,
3947                                     "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3948
3949                         /*
3950                          * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3951                          * then notify
3952                          */
3953                         if (val0 & PXP2_EOP_ERROR_BIT) {
3954                                 PMD_DRV_LOG(ERR, "PXP2_WR_PGLUE_EOP_ERROR");
3955
3956                                 /*
3957                                  * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3958                                  * set then clear attention from PXP2 block without panic
3959                                  */
3960                                 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3961                                     ((val1 & mask1) == 0))
3962                                         attn &= ~AEU_PXP2_HW_INT_BIT;
3963                         }
3964                 }
3965         }
3966
3967         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3968                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3969                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3970
3971                 val = REG_RD(sc, reg_offset);
3972                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3973                 REG_WR(sc, reg_offset, val);
3974
3975                 PMD_DRV_LOG(ERR,
3976                             "FATAL HW block attention set2 0x%x",
3977                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
3978                 rte_panic("HW block attention set2");
3979         }
3980 }
3981
3982 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
3983 {
3984         int port = SC_PORT(sc);
3985         int reg_offset;
3986         uint32_t val;
3987
3988         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3989                 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
3990                 PMD_DRV_LOG(ERR, "DB hw attention 0x%08x", val);
3991 /* DORQ discard attention */
3992                 if (val & 0x2) {
3993                         PMD_DRV_LOG(ERR, "FATAL error from DORQ");
3994                 }
3995         }
3996
3997         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3998                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3999                               MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4000
4001                 val = REG_RD(sc, reg_offset);
4002                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4003                 REG_WR(sc, reg_offset, val);
4004
4005                 PMD_DRV_LOG(ERR,
4006                             "FATAL HW block attention set1 0x%08x",
4007                             (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4008                 rte_panic("HW block attention set1");
4009         }
4010 }
4011
4012 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4013 {
4014         int port = SC_PORT(sc);
4015         int reg_offset;
4016         uint32_t val;
4017
4018         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4019             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4020
4021         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4022                 val = REG_RD(sc, reg_offset);
4023                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4024                 REG_WR(sc, reg_offset, val);
4025
4026                 PMD_DRV_LOG(WARNING, "SPIO5 hw attention");
4027
4028 /* Fan failure attention */
4029                 elink_hw_reset_phy(&sc->link_params);
4030                 bnx2x_fan_failure(sc);
4031         }
4032
4033         if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4034                 elink_handle_module_detect_int(&sc->link_params);
4035         }
4036
4037         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4038                 val = REG_RD(sc, reg_offset);
4039                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4040                 REG_WR(sc, reg_offset, val);
4041
4042                 rte_panic("FATAL HW block attention set0 0x%lx",
4043                           (attn & HW_INTERRUT_ASSERT_SET_0));
4044         }
4045 }
4046
4047 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4048 {
4049         struct attn_route attn;
4050         struct attn_route *group_mask;
4051         int port = SC_PORT(sc);
4052         int index;
4053         uint32_t reg_addr;
4054         uint32_t val;
4055         uint32_t aeu_mask;
4056         uint8_t global = FALSE;
4057
4058         /*
4059          * Need to take HW lock because MCP or other port might also
4060          * try to handle this event.
4061          */
4062         bnx2x_acquire_alr(sc);
4063
4064         if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4065                 sc->recovery_state = BNX2X_RECOVERY_INIT;
4066
4067 /* disable HW interrupts */
4068                 bnx2x_int_disable(sc);
4069                 bnx2x_release_alr(sc);
4070                 return;
4071         }
4072
4073         attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4074         attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4075         attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4076         attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4077         if (!CHIP_IS_E1x(sc)) {
4078                 attn.sig[4] =
4079                     REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4080         } else {
4081                 attn.sig[4] = 0;
4082         }
4083
4084         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4085                 if (deasserted & (1 << index)) {
4086                         group_mask = &sc->attn_group[index];
4087
4088                         bnx2x_attn_int_deasserted4(sc,
4089                                                  attn.
4090                                                  sig[4] & group_mask->sig[4]);
4091                         bnx2x_attn_int_deasserted3(sc,
4092                                                  attn.
4093                                                  sig[3] & group_mask->sig[3]);
4094                         bnx2x_attn_int_deasserted1(sc,
4095                                                  attn.
4096                                                  sig[1] & group_mask->sig[1]);
4097                         bnx2x_attn_int_deasserted2(sc,
4098                                                  attn.
4099                                                  sig[2] & group_mask->sig[2]);
4100                         bnx2x_attn_int_deasserted0(sc,
4101                                                  attn.
4102                                                  sig[0] & group_mask->sig[0]);
4103                 }
4104         }
4105
4106         bnx2x_release_alr(sc);
4107
4108         if (sc->devinfo.int_block == INT_BLOCK_HC) {
4109                 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4110                             COMMAND_REG_ATTN_BITS_CLR);
4111         } else {
4112                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4113         }
4114
4115         val = ~deasserted;
4116         PMD_DRV_LOG(DEBUG,
4117                     "about to mask 0x%08x at %s addr 0x%08x", val,
4118                     (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4119                     reg_addr);
4120         REG_WR(sc, reg_addr, val);
4121
4122         if (~sc->attn_state & deasserted) {
4123                 PMD_DRV_LOG(ERR, "IGU error");
4124         }
4125
4126         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4127             MISC_REG_AEU_MASK_ATTN_FUNC_0;
4128
4129         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4130
4131         aeu_mask = REG_RD(sc, reg_addr);
4132
4133         aeu_mask |= (deasserted & 0x3ff);
4134
4135         REG_WR(sc, reg_addr, aeu_mask);
4136         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4137
4138         sc->attn_state &= ~deasserted;
4139 }
4140
4141 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4142 {
4143         /* read local copy of bits */
4144         uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4145         uint32_t attn_ack =
4146             le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4147         uint32_t attn_state = sc->attn_state;
4148
4149         /* look for changed bits */
4150         uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4151         uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4152
4153         PMD_DRV_LOG(DEBUG,
4154                     "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4155                     attn_bits, attn_ack, asserted, deasserted);
4156
4157         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4158                 PMD_DRV_LOG(ERR, "BAD attention state");
4159         }
4160
4161         /* handle bits that were raised */
4162         if (asserted) {
4163                 bnx2x_attn_int_asserted(sc, asserted);
4164         }
4165
4166         if (deasserted) {
4167                 bnx2x_attn_int_deasserted(sc, deasserted);
4168         }
4169 }
4170
4171 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4172 {
4173         struct host_sp_status_block *def_sb = sc->def_sb;
4174         uint16_t rc = 0;
4175
4176         mb();                   /* status block is written to by the chip */
4177
4178         if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4179                 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4180                 rc |= BNX2X_DEF_SB_ATT_IDX;
4181         }
4182
4183         if (sc->def_idx != def_sb->sp_sb.running_index) {
4184                 sc->def_idx = def_sb->sp_sb.running_index;
4185                 rc |= BNX2X_DEF_SB_IDX;
4186         }
4187
4188         mb();
4189
4190         return rc;
4191 }
4192
4193 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4194                                                           uint32_t cid)
4195 {
4196         return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4197 }
4198
4199 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4200 {
4201         struct ecore_mcast_ramrod_params rparam;
4202         int rc;
4203
4204         memset(&rparam, 0, sizeof(rparam));
4205
4206         rparam.mcast_obj = &sc->mcast_obj;
4207
4208         /* clear pending state for the last command */
4209         sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4210
4211         /* if there are pending mcast commands - send them */
4212         if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4213                 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4214                 if (rc < 0) {
4215                         PMD_DRV_LOG(INFO,
4216                                     "Failed to send pending mcast commands (%d)",
4217                                     rc);
4218                 }
4219         }
4220 }
4221
4222 static void
4223 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4224 {
4225         unsigned long ramrod_flags = 0;
4226         int rc = 0;
4227         uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4228         struct ecore_vlan_mac_obj *vlan_mac_obj;
4229
4230         /* always push next commands out, don't wait here */
4231         bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4232
4233         switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4234         case ECORE_FILTER_MAC_PENDING:
4235                 PMD_DRV_LOG(DEBUG, "Got SETUP_MAC completions");
4236                 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4237                 break;
4238
4239         case ECORE_FILTER_MCAST_PENDING:
4240                 PMD_DRV_LOG(DEBUG, "Got SETUP_MCAST completions");
4241                 bnx2x_handle_mcast_eqe(sc);
4242                 return;
4243
4244         default:
4245                 PMD_DRV_LOG(NOTICE, "Unsupported classification command: %d",
4246                             elem->message.data.eth_event.echo);
4247                 return;
4248         }
4249
4250         rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4251
4252         if (rc < 0) {
4253                 PMD_DRV_LOG(NOTICE, "Failed to schedule new commands (%d)", rc);
4254         } else if (rc > 0) {
4255                 PMD_DRV_LOG(DEBUG, "Scheduled next pending commands...");
4256         }
4257 }
4258
4259 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4260 {
4261         bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4262
4263         /* send rx_mode command again if was requested */
4264         if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4265                 bnx2x_set_storm_rx_mode(sc);
4266         }
4267 }
4268
4269 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4270 {
4271         storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4272         wmb();                  /* keep prod updates ordered */
4273 }
4274
4275 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4276 {
4277         uint16_t hw_cons, sw_cons, sw_prod;
4278         union event_ring_elem *elem;
4279         uint8_t echo;
4280         uint32_t cid;
4281         uint8_t opcode;
4282         int spqe_cnt = 0;
4283         struct ecore_queue_sp_obj *q_obj;
4284         struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4285         struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4286
4287         hw_cons = le16toh(*sc->eq_cons_sb);
4288
4289         /*
4290          * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4291          * when we get to the next-page we need to adjust so the loop
4292          * condition below will be met. The next element is the size of a
4293          * regular element and hence incrementing by 1
4294          */
4295         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4296                 hw_cons++;
4297         }
4298
4299         /*
4300          * This function may never run in parallel with itself for a
4301          * specific sc and no need for a read memory barrier here.
4302          */
4303         sw_cons = sc->eq_cons;
4304         sw_prod = sc->eq_prod;
4305
4306         for (;
4307              sw_cons != hw_cons;
4308              sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4309
4310                 elem = &sc->eq[EQ_DESC(sw_cons)];
4311
4312 /* elem CID originates from FW, actually LE */
4313                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4314                 opcode = elem->message.opcode;
4315
4316 /* handle eq element */
4317                 switch (opcode) {
4318                 case EVENT_RING_OPCODE_STAT_QUERY:
4319                         PMD_DEBUG_PERIODIC_LOG(DEBUG, "got statistics completion event %d",
4320                                     sc->stats_comp++);
4321                         /* nothing to do with stats comp */
4322                         goto next_spqe;
4323
4324                 case EVENT_RING_OPCODE_CFC_DEL:
4325                         /* handle according to cid range */
4326                         /* we may want to verify here that the sc state is HALTING */
4327                         PMD_DRV_LOG(DEBUG, "got delete ramrod for MULTI[%d]",
4328                                     cid);
4329                         q_obj = bnx2x_cid_to_q_obj(sc, cid);
4330                         if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4331                                 break;
4332                         }
4333                         goto next_spqe;
4334
4335                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4336                         PMD_DRV_LOG(DEBUG, "got STOP TRAFFIC");
4337                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4338                                 break;
4339                         }
4340                         goto next_spqe;
4341
4342                 case EVENT_RING_OPCODE_START_TRAFFIC:
4343                         PMD_DRV_LOG(DEBUG, "got START TRAFFIC");
4344                         if (f_obj->complete_cmd
4345                             (sc, f_obj, ECORE_F_CMD_TX_START)) {
4346                                 break;
4347                         }
4348                         goto next_spqe;
4349
4350                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4351                         echo = elem->message.data.function_update_event.echo;
4352                         if (echo == SWITCH_UPDATE) {
4353                                 PMD_DRV_LOG(DEBUG,
4354                                             "got FUNC_SWITCH_UPDATE ramrod");
4355                                 if (f_obj->complete_cmd(sc, f_obj,
4356                                                         ECORE_F_CMD_SWITCH_UPDATE))
4357                                 {
4358                                         break;
4359                                 }
4360                         } else {
4361                                 PMD_DRV_LOG(DEBUG,
4362                                             "AFEX: ramrod completed FUNCTION_UPDATE");
4363                                 f_obj->complete_cmd(sc, f_obj,
4364                                                     ECORE_F_CMD_AFEX_UPDATE);
4365                         }
4366                         goto next_spqe;
4367
4368                 case EVENT_RING_OPCODE_FORWARD_SETUP:
4369                         q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4370                         if (q_obj->complete_cmd(sc, q_obj,
4371                                                 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4372                                 break;
4373                         }
4374                         goto next_spqe;
4375
4376                 case EVENT_RING_OPCODE_FUNCTION_START:
4377                         PMD_DRV_LOG(DEBUG, "got FUNC_START ramrod");
4378                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4379                                 break;
4380                         }
4381                         goto next_spqe;
4382
4383                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4384                         PMD_DRV_LOG(DEBUG, "got FUNC_STOP ramrod");
4385                         if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4386                                 break;
4387                         }
4388                         goto next_spqe;
4389                 }
4390
4391                 switch (opcode | sc->state) {
4392                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4393                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4394                         cid =
4395                             elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4396                         PMD_DRV_LOG(DEBUG, "got RSS_UPDATE ramrod. CID %d",
4397                                     cid);
4398                         rss_raw->clear_pending(rss_raw);
4399                         break;
4400
4401                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4402                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4403                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4404                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4405                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4406                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4407                         PMD_DRV_LOG(DEBUG,
4408                                     "got (un)set mac ramrod");
4409                         bnx2x_handle_classification_eqe(sc, elem);
4410                         break;
4411
4412                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4413                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4414                 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4415                         PMD_DRV_LOG(DEBUG,
4416                                     "got mcast ramrod");
4417                         bnx2x_handle_mcast_eqe(sc);
4418                         break;
4419
4420                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4421                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4422                 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4423                         PMD_DRV_LOG(DEBUG,
4424                                     "got rx_mode ramrod");
4425                         bnx2x_handle_rx_mode_eqe(sc);
4426                         break;
4427
4428                 default:
4429                         /* unknown event log error and continue */
4430                         PMD_DRV_LOG(INFO, "Unknown EQ event %d, sc->state 0x%x",
4431                                     elem->message.opcode, sc->state);
4432                 }
4433
4434 next_spqe:
4435                 spqe_cnt++;
4436         }                       /* for */
4437
4438         mb();
4439         atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4440
4441         sc->eq_cons = sw_cons;
4442         sc->eq_prod = sw_prod;
4443
4444         /* make sure that above mem writes were issued towards the memory */
4445         wmb();
4446
4447         /* update producer */
4448         bnx2x_update_eq_prod(sc, sc->eq_prod);
4449 }
4450
4451 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4452 {
4453         uint16_t status;
4454         int rc = 0;
4455
4456         /* what work needs to be performed? */
4457         status = bnx2x_update_dsb_idx(sc);
4458
4459         /* HW attentions */
4460         if (status & BNX2X_DEF_SB_ATT_IDX) {
4461                 PMD_DRV_LOG(DEBUG, "---> ATTN INTR <---");
4462                 bnx2x_attn_int(sc);
4463                 status &= ~BNX2X_DEF_SB_ATT_IDX;
4464                 rc = 1;
4465         }
4466
4467         /* SP events: STAT_QUERY and others */
4468         if (status & BNX2X_DEF_SB_IDX) {
4469 /* handle EQ completions */
4470                 PMD_DEBUG_PERIODIC_LOG(DEBUG, "---> EQ INTR <---");
4471                 bnx2x_eq_int(sc);
4472                 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4473                            le16toh(sc->def_idx), IGU_INT_NOP, 1);
4474                 status &= ~BNX2X_DEF_SB_IDX;
4475         }
4476
4477         /* if status is non zero then something went wrong */
4478         if (unlikely(status)) {
4479                 PMD_DRV_LOG(INFO,
4480                             "Got an unknown SP interrupt! (0x%04x)", status);
4481         }
4482
4483         /* ack status block only if something was actually handled */
4484         bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4485                    le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4486
4487         return rc;
4488 }
4489
4490 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4491 {
4492         struct bnx2x_softc *sc = fp->sc;
4493         uint8_t more_rx = FALSE;
4494
4495         PMD_DRV_LOG(DEBUG, "---> FP TASK QUEUE (%d) <--", fp->index);
4496
4497         /* update the fastpath index */
4498         bnx2x_update_fp_sb_idx(fp);
4499
4500         if (scan_fp) {
4501                 if (bnx2x_has_rx_work(fp)) {
4502                         more_rx = bnx2x_rxeof(sc, fp);
4503                 }
4504
4505                 if (more_rx) {
4506                         /* still more work to do */
4507                         bnx2x_handle_fp_tq(fp, scan_fp);
4508                         return;
4509                 }
4510         }
4511
4512         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4513                    le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4514 }
4515
4516 /*
4517  * Legacy interrupt entry point.
4518  *
4519  * Verifies that the controller generated the interrupt and
4520  * then calls a separate routine to handle the various
4521  * interrupt causes: link, RX, and TX.
4522  */
4523 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4524 {
4525         struct bnx2x_fastpath *fp;
4526         uint32_t status, mask;
4527         int i, rc = 0;
4528
4529         /*
4530          * 0 for ustorm, 1 for cstorm
4531          * the bits returned from ack_int() are 0-15
4532          * bit 0 = attention status block
4533          * bit 1 = fast path status block
4534          * a mask of 0x2 or more = tx/rx event
4535          * a mask of 1 = slow path event
4536          */
4537
4538         status = bnx2x_ack_int(sc);
4539
4540         /* the interrupt is not for us */
4541         if (unlikely(status == 0)) {
4542                 return 0;
4543         }
4544
4545         PMD_DEBUG_PERIODIC_LOG(DEBUG, "Interrupt status 0x%04x", status);
4546         //bnx2x_dump_status_block(sc);
4547
4548         FOR_EACH_ETH_QUEUE(sc, i) {
4549                 fp = &sc->fp[i];
4550                 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4551                 if (status & mask) {
4552                         bnx2x_handle_fp_tq(fp, scan_fp);
4553                         status &= ~mask;
4554                 }
4555         }
4556
4557         if (unlikely(status & 0x1)) {
4558                 rc = bnx2x_handle_sp_tq(sc);
4559                 status &= ~0x1;
4560         }
4561
4562         if (unlikely(status)) {
4563                 PMD_DRV_LOG(WARNING,
4564                             "Unexpected fastpath status (0x%08x)!", status);
4565         }
4566
4567         return rc;
4568 }
4569
4570 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4571 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4572 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4573 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4574 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4575 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4576 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4577 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4578 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4579
4580 static struct
4581 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4582         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4583         .init_hw_cmn = bnx2x_init_hw_common,
4584         .init_hw_port = bnx2x_init_hw_port,
4585         .init_hw_func = bnx2x_init_hw_func,
4586
4587         .reset_hw_cmn = bnx2x_reset_common,
4588         .reset_hw_port = bnx2x_reset_port,
4589         .reset_hw_func = bnx2x_reset_func,
4590
4591         .init_fw = bnx2x_init_firmware,
4592         .release_fw = bnx2x_release_firmware,
4593 };
4594
4595 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4596 {
4597         sc->dmae_ready = 0;
4598
4599         PMD_INIT_FUNC_TRACE();
4600
4601         ecore_init_func_obj(sc,
4602                             &sc->func_obj,
4603                             BNX2X_SP(sc, func_rdata),
4604                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4605                             BNX2X_SP(sc, func_afex_rdata),
4606                             (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4607                             &bnx2x_func_sp_drv);
4608 }
4609
4610 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4611 {
4612         struct ecore_func_state_params func_params = { NULL };
4613         int rc;
4614
4615         PMD_INIT_FUNC_TRACE();
4616
4617         /* prepare the parameters for function state transitions */
4618         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4619
4620         func_params.f_obj = &sc->func_obj;
4621         func_params.cmd = ECORE_F_CMD_HW_INIT;
4622
4623         func_params.params.hw_init.load_phase = load_code;
4624
4625         /*
4626          * Via a plethora of function pointers, we will eventually reach
4627          * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4628          */
4629         rc = ecore_func_state_change(sc, &func_params);
4630
4631         return rc;
4632 }
4633
4634 static void
4635 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4636 {
4637         uint32_t i;
4638
4639         if (!(len % 4) && !(addr % 4)) {
4640                 for (i = 0; i < len; i += 4) {
4641                         REG_WR(sc, (addr + i), fill);
4642                 }
4643         } else {
4644                 for (i = 0; i < len; i++) {
4645                         REG_WR8(sc, (addr + i), fill);
4646                 }
4647         }
4648 }
4649
4650 /* writes FP SP data to FW - data_size in dwords */
4651 static void
4652 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4653                   uint32_t data_size)
4654 {
4655         uint32_t index;
4656
4657         for (index = 0; index < data_size; index++) {
4658                 REG_WR(sc,
4659                        (BAR_CSTRORM_INTMEM +
4660                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4661                         (sizeof(uint32_t) * index)), *(sb_data_p + index));
4662         }
4663 }
4664
4665 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4666 {
4667         struct hc_status_block_data_e2 sb_data_e2;
4668         struct hc_status_block_data_e1x sb_data_e1x;
4669         uint32_t *sb_data_p;
4670         uint32_t data_size = 0;
4671
4672         if (!CHIP_IS_E1x(sc)) {
4673                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4674                 sb_data_e2.common.state = SB_DISABLED;
4675                 sb_data_e2.common.p_func.vf_valid = FALSE;
4676                 sb_data_p = (uint32_t *) & sb_data_e2;
4677                 data_size = (sizeof(struct hc_status_block_data_e2) /
4678                              sizeof(uint32_t));
4679         } else {
4680                 memset(&sb_data_e1x, 0,
4681                        sizeof(struct hc_status_block_data_e1x));
4682                 sb_data_e1x.common.state = SB_DISABLED;
4683                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4684                 sb_data_p = (uint32_t *) & sb_data_e1x;
4685                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4686                              sizeof(uint32_t));
4687         }
4688
4689         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4690
4691         bnx2x_fill(sc,
4692                  (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4693                  CSTORM_STATUS_BLOCK_SIZE);
4694         bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4695                  0, CSTORM_SYNC_BLOCK_SIZE);
4696 }
4697
4698 static void
4699 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4700                   struct hc_sp_status_block_data *sp_sb_data)
4701 {
4702         uint32_t i;
4703
4704         for (i = 0;
4705              i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4706              i++) {
4707                 REG_WR(sc,
4708                        (BAR_CSTRORM_INTMEM +
4709                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4710                         (i * sizeof(uint32_t))),
4711                        *((uint32_t *) sp_sb_data + i));
4712         }
4713 }
4714
4715 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4716 {
4717         struct hc_sp_status_block_data sp_sb_data;
4718
4719         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4720
4721         sp_sb_data.state = SB_DISABLED;
4722         sp_sb_data.p_func.vf_valid = FALSE;
4723
4724         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4725
4726         bnx2x_fill(sc,
4727                  (BAR_CSTRORM_INTMEM +
4728                   CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4729                  0, CSTORM_SP_STATUS_BLOCK_SIZE);
4730         bnx2x_fill(sc,
4731                  (BAR_CSTRORM_INTMEM +
4732                   CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4733                  0, CSTORM_SP_SYNC_BLOCK_SIZE);
4734 }
4735
4736 static void
4737 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4738                              int igu_seg_id)
4739 {
4740         hc_sm->igu_sb_id = igu_sb_id;
4741         hc_sm->igu_seg_id = igu_seg_id;
4742         hc_sm->timer_value = 0xFF;
4743         hc_sm->time_to_expire = 0xFFFFFFFF;
4744 }
4745
4746 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4747 {
4748         /* zero out state machine indices */
4749
4750         /* rx indices */
4751         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4752
4753         /* tx indices */
4754         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4755         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4756         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4757         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4758
4759         /* map indices */
4760
4761         /* rx indices */
4762         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4763             (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4764
4765         /* tx indices */
4766         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4767             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4768         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4769             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4770         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4771             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4772         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4773             (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4774 }
4775
4776 static void
4777 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4778             uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4779 {
4780         struct hc_status_block_data_e2 sb_data_e2;
4781         struct hc_status_block_data_e1x sb_data_e1x;
4782         struct hc_status_block_sm *hc_sm_p;
4783         uint32_t *sb_data_p;
4784         int igu_seg_id;
4785         int data_size;
4786
4787         if (CHIP_INT_MODE_IS_BC(sc)) {
4788                 igu_seg_id = HC_SEG_ACCESS_NORM;
4789         } else {
4790                 igu_seg_id = IGU_SEG_ACCESS_NORM;
4791         }
4792
4793         bnx2x_zero_fp_sb(sc, fw_sb_id);
4794
4795         if (!CHIP_IS_E1x(sc)) {
4796                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4797                 sb_data_e2.common.state = SB_ENABLED;
4798                 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4799                 sb_data_e2.common.p_func.vf_id = vfid;
4800                 sb_data_e2.common.p_func.vf_valid = vf_valid;
4801                 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4802                 sb_data_e2.common.same_igu_sb_1b = TRUE;
4803                 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4804                 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4805                 hc_sm_p = sb_data_e2.common.state_machine;
4806                 sb_data_p = (uint32_t *) & sb_data_e2;
4807                 data_size = (sizeof(struct hc_status_block_data_e2) /
4808                              sizeof(uint32_t));
4809                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4810         } else {
4811                 memset(&sb_data_e1x, 0,
4812                        sizeof(struct hc_status_block_data_e1x));
4813                 sb_data_e1x.common.state = SB_ENABLED;
4814                 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4815                 sb_data_e1x.common.p_func.vf_id = 0xff;
4816                 sb_data_e1x.common.p_func.vf_valid = FALSE;
4817                 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4818                 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4819                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4820                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4821                 hc_sm_p = sb_data_e1x.common.state_machine;
4822                 sb_data_p = (uint32_t *) & sb_data_e1x;
4823                 data_size = (sizeof(struct hc_status_block_data_e1x) /
4824                              sizeof(uint32_t));
4825                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4826         }
4827
4828         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4829         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4830
4831         /* write indices to HW - PCI guarantees endianity of regpairs */
4832         bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4833 }
4834
4835 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4836 {
4837         if (CHIP_IS_E1x(fp->sc)) {
4838                 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4839         } else {
4840                 return fp->cl_id;
4841         }
4842 }
4843
4844 static uint32_t
4845 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4846 {
4847         uint32_t offset = BAR_USTRORM_INTMEM;
4848
4849         if (IS_VF(sc)) {
4850                 return PXP_VF_ADDR_USDM_QUEUES_START +
4851                         (sc->acquire_resp.resc.hw_qid[fp->index] *
4852                          sizeof(struct ustorm_queue_zone_data));
4853         } else if (!CHIP_IS_E1x(sc)) {
4854                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4855         } else {
4856                 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4857         }
4858
4859         return offset;
4860 }
4861
4862 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4863 {
4864         struct bnx2x_fastpath *fp = &sc->fp[idx];
4865         uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4866         unsigned long q_type = 0;
4867         int cos;
4868
4869         fp->sc = sc;
4870         fp->index = idx;
4871
4872         fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4873         fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4874
4875         if (CHIP_IS_E1x(sc))
4876                 fp->cl_id = SC_L_ID(sc) + idx;
4877         else
4878 /* want client ID same as IGU SB ID for non-E1 */
4879                 fp->cl_id = fp->igu_sb_id;
4880         fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4881
4882         /* setup sb indices */
4883         if (!CHIP_IS_E1x(sc)) {
4884                 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4885                 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4886         } else {
4887                 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4888                 fp->sb_running_index =
4889                     fp->status_block.e1x_sb->sb.running_index;
4890         }
4891
4892         /* init shortcut */
4893         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4894
4895         fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4896
4897         for (cos = 0; cos < sc->max_cos; cos++) {
4898                 cids[cos] = idx;
4899         }
4900         fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4901
4902         /* nothing more for a VF to do */
4903         if (IS_VF(sc)) {
4904                 return;
4905         }
4906
4907         bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4908                     fp->fw_sb_id, fp->igu_sb_id);
4909
4910         bnx2x_update_fp_sb_idx(fp);
4911
4912         /* Configure Queue State object */
4913         bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4914         bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4915
4916         ecore_init_queue_obj(sc,
4917                              &sc->sp_objs[idx].q_obj,
4918                              fp->cl_id,
4919                              cids,
4920                              sc->max_cos,
4921                              SC_FUNC(sc),
4922                              BNX2X_SP(sc, q_rdata),
4923                              (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4924                              q_type);
4925
4926         /* configure classification DBs */
4927         ecore_init_mac_obj(sc,
4928                            &sc->sp_objs[idx].mac_obj,
4929                            fp->cl_id,
4930                            idx,
4931                            SC_FUNC(sc),
4932                            BNX2X_SP(sc, mac_rdata),
4933                            (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4934                            ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4935                            ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4936 }
4937
4938 static void
4939 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4940                    uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4941 {
4942         union ustorm_eth_rx_producers rx_prods;
4943         uint32_t i;
4944
4945         /* update producers */
4946         rx_prods.prod.bd_prod = rx_bd_prod;
4947         rx_prods.prod.cqe_prod = rx_cq_prod;
4948         rx_prods.prod.reserved = 0;
4949
4950         /*
4951          * Make sure that the BD and SGE data is updated before updating the
4952          * producers since FW might read the BD/SGE right after the producer
4953          * is updated.
4954          * This is only applicable for weak-ordered memory model archs such
4955          * as IA-64. The following barrier is also mandatory since FW will
4956          * assumes BDs must have buffers.
4957          */
4958         wmb();
4959
4960         for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
4961                 REG_WR(sc,
4962                        (fp->ustorm_rx_prods_offset + (i * 4)),
4963                        rx_prods.raw_data[i]);
4964         }
4965
4966         wmb();                  /* keep prod updates ordered */
4967 }
4968
4969 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
4970 {
4971         struct bnx2x_fastpath *fp;
4972         int i;
4973         struct bnx2x_rx_queue *rxq;
4974
4975         for (i = 0; i < sc->num_queues; i++) {
4976                 fp = &sc->fp[i];
4977                 rxq = sc->rx_queues[fp->index];
4978                 if (!rxq) {
4979                         PMD_RX_LOG(ERR, "RX queue is NULL");
4980                         return;
4981                 }
4982
4983                 rxq->rx_bd_head = 0;
4984                 rxq->rx_bd_tail = rxq->nb_rx_desc;
4985                 rxq->rx_cq_head = 0;
4986                 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
4987                 *fp->rx_cq_cons_sb = 0;
4988
4989                 /*
4990                  * Activate the BD ring...
4991                  * Warning, this will generate an interrupt (to the TSTORM)
4992                  * so this can only be done after the chip is initialized
4993                  */
4994                 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
4995
4996                 if (i != 0) {
4997                         continue;
4998                 }
4999         }
5000 }
5001
5002 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5003 {
5004         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5005
5006         fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5007         fp->tx_db.data.zero_fill1 = 0;
5008         fp->tx_db.data.prod = 0;
5009
5010         if (!txq) {
5011                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5012                 return;
5013         }
5014
5015         txq->tx_pkt_tail = 0;
5016         txq->tx_pkt_head = 0;
5017         txq->tx_bd_tail = 0;
5018         txq->tx_bd_head = 0;
5019 }
5020
5021 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5022 {
5023         int i;
5024
5025         for (i = 0; i < sc->num_queues; i++) {
5026                 bnx2x_init_tx_ring_one(&sc->fp[i]);
5027         }
5028 }
5029
5030 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5031 {
5032         struct host_sp_status_block *def_sb = sc->def_sb;
5033         phys_addr_t mapping = sc->def_sb_dma.paddr;
5034         int igu_sp_sb_index;
5035         int igu_seg_id;
5036         int port = SC_PORT(sc);
5037         int func = SC_FUNC(sc);
5038         int reg_offset, reg_offset_en5;
5039         uint64_t section;
5040         int index, sindex;
5041         struct hc_sp_status_block_data sp_sb_data;
5042
5043         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5044
5045         if (CHIP_INT_MODE_IS_BC(sc)) {
5046                 igu_sp_sb_index = DEF_SB_IGU_ID;
5047                 igu_seg_id = HC_SEG_ACCESS_DEF;
5048         } else {
5049                 igu_sp_sb_index = sc->igu_dsb_id;
5050                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5051         }
5052
5053         /* attentions */
5054         section = ((uint64_t) mapping +
5055                    offsetof(struct host_sp_status_block, atten_status_block));
5056         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5057         sc->attn_state = 0;
5058
5059         reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5060             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5061
5062         reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5063             MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5064
5065         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5066 /* take care of sig[0]..sig[4] */
5067                 for (sindex = 0; sindex < 4; sindex++) {
5068                         sc->attn_group[index].sig[sindex] =
5069                             REG_RD(sc,
5070                                    (reg_offset + (sindex * 0x4) +
5071                                     (0x10 * index)));
5072                 }
5073
5074                 if (!CHIP_IS_E1x(sc)) {
5075                         /*
5076                          * enable5 is separate from the rest of the registers,
5077                          * and the address skip is 4 and not 16 between the
5078                          * different groups
5079                          */
5080                         sc->attn_group[index].sig[4] =
5081                             REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5082                 } else {
5083                         sc->attn_group[index].sig[4] = 0;
5084                 }
5085         }
5086
5087         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5088                 reg_offset =
5089                     port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5090                 REG_WR(sc, reg_offset, U64_LO(section));
5091                 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5092         } else if (!CHIP_IS_E1x(sc)) {
5093                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5094                 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5095         }
5096
5097         section = ((uint64_t) mapping +
5098                    offsetof(struct host_sp_status_block, sp_sb));
5099
5100         bnx2x_zero_sp_sb(sc);
5101
5102         /* PCI guarantees endianity of regpair */
5103         sp_sb_data.state = SB_ENABLED;
5104         sp_sb_data.host_sb_addr.lo = U64_LO(section);
5105         sp_sb_data.host_sb_addr.hi = U64_HI(section);
5106         sp_sb_data.igu_sb_id = igu_sp_sb_index;
5107         sp_sb_data.igu_seg_id = igu_seg_id;
5108         sp_sb_data.p_func.pf_id = func;
5109         sp_sb_data.p_func.vnic_id = SC_VN(sc);
5110         sp_sb_data.p_func.vf_id = 0xff;
5111
5112         bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5113
5114         bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5115 }
5116
5117 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5118 {
5119         atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5120         sc->spq_prod_idx = 0;
5121         sc->dsb_sp_prod =
5122             &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5123         sc->spq_prod_bd = sc->spq;
5124         sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5125 }
5126
5127 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5128 {
5129         union event_ring_elem *elem;
5130         int i;
5131
5132         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5133                 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5134
5135                 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5136                                                          BNX2X_PAGE_SIZE *
5137                                                          (i % NUM_EQ_PAGES)));
5138                 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5139                                                          BNX2X_PAGE_SIZE *
5140                                                          (i % NUM_EQ_PAGES)));
5141         }
5142
5143         sc->eq_cons = 0;
5144         sc->eq_prod = NUM_EQ_DESC;
5145         sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5146
5147         atomic_store_rel_long(&sc->eq_spq_left,
5148                               (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5149                                    NUM_EQ_DESC) - 1));
5150 }
5151
5152 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5153 {
5154         int i;
5155
5156         if (IS_MF_SI(sc)) {
5157 /*
5158  * In switch independent mode, the TSTORM needs to accept
5159  * packets that failed classification, since approximate match
5160  * mac addresses aren't written to NIG LLH.
5161  */
5162                 REG_WR8(sc,
5163                         (BAR_TSTRORM_INTMEM +
5164                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5165         } else
5166                 REG_WR8(sc,
5167                         (BAR_TSTRORM_INTMEM +
5168                          TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5169
5170         /*
5171          * Zero this manually as its initialization is currently missing
5172          * in the initTool.
5173          */
5174         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5175                 REG_WR(sc,
5176                        (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5177                        0);
5178         }
5179
5180         if (!CHIP_IS_E1x(sc)) {
5181                 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5182                         CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5183                         HC_IGU_NBC_MODE);
5184         }
5185 }
5186
5187 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5188 {
5189         switch (load_code) {
5190         case FW_MSG_CODE_DRV_LOAD_COMMON:
5191         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5192                 bnx2x_init_internal_common(sc);
5193                 /* no break */
5194
5195         case FW_MSG_CODE_DRV_LOAD_PORT:
5196                 /* nothing to do */
5197                 /* no break */
5198
5199         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5200                 /* internal memory per function is initialized inside bnx2x_pf_init */
5201                 break;
5202
5203         default:
5204                 PMD_DRV_LOG(NOTICE, "Unknown load_code (0x%x) from MCP",
5205                             load_code);
5206                 break;
5207         }
5208 }
5209
5210 static void
5211 storm_memset_func_cfg(struct bnx2x_softc *sc,
5212                       struct tstorm_eth_function_common_config *tcfg,
5213                       uint16_t abs_fid)
5214 {
5215         uint32_t addr;
5216         size_t size;
5217
5218         addr = (BAR_TSTRORM_INTMEM +
5219                 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5220         size = sizeof(struct tstorm_eth_function_common_config);
5221         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5222 }
5223
5224 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5225 {
5226         struct tstorm_eth_function_common_config tcfg = { 0 };
5227
5228         if (CHIP_IS_E1x(sc)) {
5229                 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5230         }
5231
5232         /* Enable the function in the FW */
5233         storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5234         storm_memset_func_en(sc, p->func_id, 1);
5235
5236         /* spq */
5237         if (p->func_flgs & FUNC_FLG_SPQ) {
5238                 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5239                 REG_WR(sc,
5240                        (XSEM_REG_FAST_MEMORY +
5241                         XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5242         }
5243 }
5244
5245 /*
5246  * Calculates the sum of vn_min_rates.
5247  * It's needed for further normalizing of the min_rates.
5248  * Returns:
5249  *   sum of vn_min_rates.
5250  *     or
5251  *   0 - if all the min_rates are 0.
5252  * In the later case fainess algorithm should be deactivated.
5253  * If all min rates are not zero then those that are zeroes will be set to 1.
5254  */
5255 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5256 {
5257         uint32_t vn_cfg;
5258         uint32_t vn_min_rate;
5259         int all_zero = 1;
5260         int vn;
5261
5262         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5263                 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5264                 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5265                                 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5266
5267                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5268                         /* skip hidden VNs */
5269                         vn_min_rate = 0;
5270                 } else if (!vn_min_rate) {
5271                         /* If min rate is zero - set it to 100 */
5272                         vn_min_rate = DEF_MIN_RATE;
5273                 } else {
5274                         all_zero = 0;
5275                 }
5276
5277                 input->vnic_min_rate[vn] = vn_min_rate;
5278         }
5279
5280         /* if ETS or all min rates are zeros - disable fairness */
5281         if (all_zero) {
5282                 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5283         } else {
5284                 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5285         }
5286 }
5287
5288 static uint16_t
5289 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5290 {
5291         uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5292                             FUNC_MF_CFG_MAX_BW_SHIFT);
5293
5294         if (!max_cfg) {
5295                 PMD_DRV_LOG(DEBUG,
5296                             "Max BW configured to 0 - using 100 instead");
5297                 max_cfg = 100;
5298         }
5299
5300         return max_cfg;
5301 }
5302
5303 static void
5304 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5305 {
5306         uint16_t vn_max_rate;
5307         uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5308         uint32_t max_cfg;
5309
5310         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5311                 vn_max_rate = 0;
5312         } else {
5313                 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5314
5315                 if (IS_MF_SI(sc)) {
5316                         /* max_cfg in percents of linkspeed */
5317                         vn_max_rate =
5318                             ((sc->link_vars.line_speed * max_cfg) / 100);
5319                 } else {        /* SD modes */
5320                         /* max_cfg is absolute in 100Mb units */
5321                         vn_max_rate = (max_cfg * 100);
5322                 }
5323         }
5324
5325         input->vnic_max_rate[vn] = vn_max_rate;
5326 }
5327
5328 static void
5329 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5330 {
5331         struct cmng_init_input input;
5332         int vn;
5333
5334         memset(&input, 0, sizeof(struct cmng_init_input));
5335
5336         input.port_rate = sc->link_vars.line_speed;
5337
5338         if (cmng_type == CMNG_FNS_MINMAX) {
5339 /* read mf conf from shmem */
5340                 if (read_cfg) {
5341                         bnx2x_read_mf_cfg(sc);
5342                 }
5343
5344 /* get VN min rate and enable fairness if not 0 */
5345                 bnx2x_calc_vn_min(sc, &input);
5346
5347 /* get VN max rate */
5348                 if (sc->port.pmf) {
5349                         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5350                                 bnx2x_calc_vn_max(sc, vn, &input);
5351                         }
5352                 }
5353
5354 /* always enable rate shaping and fairness */
5355                 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5356
5357                 ecore_init_cmng(&input, &sc->cmng);
5358                 return;
5359         }
5360 }
5361
5362 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5363 {
5364         if (CHIP_REV_IS_SLOW(sc)) {
5365                 return CMNG_FNS_NONE;
5366         }
5367
5368         if (IS_MF(sc)) {
5369                 return CMNG_FNS_MINMAX;
5370         }
5371
5372         return CMNG_FNS_NONE;
5373 }
5374
5375 static void
5376 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5377 {
5378         int vn;
5379         int func;
5380         uint32_t addr;
5381         size_t size;
5382
5383         addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5384         size = sizeof(struct cmng_struct_per_port);
5385         ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5386
5387         for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5388                 func = func_by_vn(sc, vn);
5389
5390                 addr = (BAR_XSTRORM_INTMEM +
5391                         XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5392                 size = sizeof(struct rate_shaping_vars_per_vn);
5393                 ecore_storm_memset_struct(sc, addr, size,
5394                                           (uint32_t *) & cmng->
5395                                           vnic.vnic_max_rate[vn]);
5396
5397                 addr = (BAR_XSTRORM_INTMEM +
5398                         XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5399                 size = sizeof(struct fairness_vars_per_vn);
5400                 ecore_storm_memset_struct(sc, addr, size,
5401                                           (uint32_t *) & cmng->
5402                                           vnic.vnic_min_rate[vn]);
5403         }
5404 }
5405
5406 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5407 {
5408         struct bnx2x_func_init_params func_init;
5409         struct event_ring_data eq_data;
5410         uint16_t flags;
5411
5412         memset(&eq_data, 0, sizeof(struct event_ring_data));
5413         memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5414
5415         if (!CHIP_IS_E1x(sc)) {
5416 /* reset IGU PF statistics: MSIX + ATTN */
5417 /* PF */
5418                 REG_WR(sc,
5419                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5420                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5421                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5422                          4)), 0);
5423 /* ATTN */
5424                 REG_WR(sc,
5425                        (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5426                         (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5427                         (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5428                         ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5429                          4)), 0);
5430         }
5431
5432         /* function setup flags */
5433         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5434
5435         func_init.func_flgs = flags;
5436         func_init.pf_id = SC_FUNC(sc);
5437         func_init.func_id = SC_FUNC(sc);
5438         func_init.spq_map = sc->spq_dma.paddr;
5439         func_init.spq_prod = sc->spq_prod_idx;
5440
5441         bnx2x_func_init(sc, &func_init);
5442
5443         memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5444
5445         /*
5446          * Congestion management values depend on the link rate.
5447          * There is no active link so initial link rate is set to 10Gbps.
5448          * When the link comes up the congestion management values are
5449          * re-calculated according to the actual link rate.
5450          */
5451         sc->link_vars.line_speed = SPEED_10000;
5452         bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5453
5454         /* Only the PMF sets the HW */
5455         if (sc->port.pmf) {
5456                 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5457         }
5458
5459         /* init Event Queue - PCI bus guarantees correct endainity */
5460         eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5461         eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5462         eq_data.producer = sc->eq_prod;
5463         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5464         eq_data.sb_id = DEF_SB_ID;
5465         storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5466 }
5467
5468 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5469 {
5470         int port = SC_PORT(sc);
5471         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5472         uint32_t val = REG_RD(sc, addr);
5473         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5474             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5475         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5476         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5477
5478         if (msix) {
5479                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5480                          HC_CONFIG_0_REG_INT_LINE_EN_0);
5481                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5482                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5483                 if (single_msix) {
5484                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5485                 }
5486         } else if (msi) {
5487                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5488                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5489                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5490                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5491         } else {
5492                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5493                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5494                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
5495                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5496
5497                 REG_WR(sc, addr, val);
5498
5499                 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5500         }
5501
5502         REG_WR(sc, addr, val);
5503
5504         /* ensure that HC_CONFIG is written before leading/trailing edge config */
5505         mb();
5506
5507         /* init leading/trailing edge */
5508         if (IS_MF(sc)) {
5509                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5510                 if (sc->port.pmf) {
5511                         /* enable nig and gpio3 attention */
5512                         val |= 0x1100;
5513                 }
5514         } else {
5515                 val = 0xffff;
5516         }
5517
5518         REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5519         REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5520
5521         /* make sure that interrupts are indeed enabled from here on */
5522         mb();
5523 }
5524
5525 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5526 {
5527         uint32_t val;
5528         uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5529             || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5530         uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5531         uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5532
5533         val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5534
5535         if (msix) {
5536                 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5537                 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5538                 if (single_msix) {
5539                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
5540                 }
5541         } else if (msi) {
5542                 val &= ~IGU_PF_CONF_INT_LINE_EN;
5543                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5544                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5545         } else {
5546                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5547                 val |= (IGU_PF_CONF_INT_LINE_EN |
5548                         IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5549         }
5550
5551         /* clean previous status - need to configure igu prior to ack */
5552         if ((!msix) || single_msix) {
5553                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5554                 bnx2x_ack_int(sc);
5555         }
5556
5557         val |= IGU_PF_CONF_FUNC_EN;
5558
5559         PMD_DRV_LOG(DEBUG, "write 0x%x to IGU mode %s",
5560                     val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5561
5562         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5563
5564         mb();
5565
5566         /* init leading/trailing edge */
5567         if (IS_MF(sc)) {
5568                 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5569                 if (sc->port.pmf) {
5570                         /* enable nig and gpio3 attention */
5571                         val |= 0x1100;
5572                 }
5573         } else {
5574                 val = 0xffff;
5575         }
5576
5577         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5578         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5579
5580         /* make sure that interrupts are indeed enabled from here on */
5581         mb();
5582 }
5583
5584 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5585 {
5586         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5587                 bnx2x_hc_int_enable(sc);
5588         } else {
5589                 bnx2x_igu_int_enable(sc);
5590         }
5591 }
5592
5593 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5594 {
5595         int port = SC_PORT(sc);
5596         uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5597         uint32_t val = REG_RD(sc, addr);
5598
5599         val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5600                  HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5601                  HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5602         /* flush all outstanding writes */
5603         mb();
5604
5605         REG_WR(sc, addr, val);
5606         if (REG_RD(sc, addr) != val) {
5607                 PMD_DRV_LOG(ERR, "proper val not read from HC IGU!");
5608         }
5609 }
5610
5611 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5612 {
5613         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5614
5615         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5616                  IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5617
5618         PMD_DRV_LOG(DEBUG, "write %x to IGU", val);
5619
5620         /* flush all outstanding writes */
5621         mb();
5622
5623         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5624         if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5625                 PMD_DRV_LOG(ERR, "proper val not read from IGU!");
5626         }
5627 }
5628
5629 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5630 {
5631         if (sc->devinfo.int_block == INT_BLOCK_HC) {
5632                 bnx2x_hc_int_disable(sc);
5633         } else {
5634                 bnx2x_igu_int_disable(sc);
5635         }
5636 }
5637
5638 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5639 {
5640         int i;
5641
5642         PMD_INIT_FUNC_TRACE();
5643
5644         for (i = 0; i < sc->num_queues; i++) {
5645                 bnx2x_init_eth_fp(sc, i);
5646         }
5647
5648         rmb();                  /* ensure status block indices were read */
5649
5650         bnx2x_init_rx_rings(sc);
5651         bnx2x_init_tx_rings(sc);
5652
5653         if (IS_VF(sc)) {
5654                 bnx2x_memset_stats(sc);
5655                 return;
5656         }
5657
5658         /* initialize MOD_ABS interrupts */
5659         elink_init_mod_abs_int(sc, &sc->link_vars,
5660                                sc->devinfo.chip_id,
5661                                sc->devinfo.shmem_base,
5662                                sc->devinfo.shmem2_base, SC_PORT(sc));
5663
5664         bnx2x_init_def_sb(sc);
5665         bnx2x_update_dsb_idx(sc);
5666         bnx2x_init_sp_ring(sc);
5667         bnx2x_init_eq_ring(sc);
5668         bnx2x_init_internal(sc, load_code);
5669         bnx2x_pf_init(sc);
5670         bnx2x_stats_init(sc);
5671
5672         /* flush all before enabling interrupts */
5673         mb();
5674
5675         bnx2x_int_enable(sc);
5676
5677         /* check for SPIO5 */
5678         bnx2x_attn_int_deasserted0(sc,
5679                                  REG_RD(sc,
5680                                         (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5681                                          SC_PORT(sc) * 4)) &
5682                                  AEU_INPUTS_ATTN_BITS_SPIO5);
5683 }
5684
5685 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5686 {
5687         /* mcast rules must be added to tx if tx switching is enabled */
5688         ecore_obj_type o_type;
5689         if (sc->flags & BNX2X_TX_SWITCHING)
5690                 o_type = ECORE_OBJ_TYPE_RX_TX;
5691         else
5692                 o_type = ECORE_OBJ_TYPE_RX;
5693
5694         /* RX_MODE controlling object */
5695         ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5696
5697         /* multicast configuration controlling object */
5698         ecore_init_mcast_obj(sc,
5699                              &sc->mcast_obj,
5700                              sc->fp[0].cl_id,
5701                              sc->fp[0].index,
5702                              SC_FUNC(sc),
5703                              SC_FUNC(sc),
5704                              BNX2X_SP(sc, mcast_rdata),
5705                              (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5706                              ECORE_FILTER_MCAST_PENDING,
5707                              &sc->sp_state, o_type);
5708
5709         /* Setup CAM credit pools */
5710         ecore_init_mac_credit_pool(sc,
5711                                    &sc->macs_pool,
5712                                    SC_FUNC(sc),
5713                                    CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5714                                    VNICS_PER_PATH(sc));
5715
5716         ecore_init_vlan_credit_pool(sc,
5717                                     &sc->vlans_pool,
5718                                     SC_ABS_FUNC(sc) >> 1,
5719                                     CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5720                                     VNICS_PER_PATH(sc));
5721
5722         /* RSS configuration object */
5723         ecore_init_rss_config_obj(&sc->rss_conf_obj,
5724                                   sc->fp[0].cl_id,
5725                                   sc->fp[0].index,
5726                                   SC_FUNC(sc),
5727                                   SC_FUNC(sc),
5728                                   BNX2X_SP(sc, rss_rdata),
5729                                   (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5730                                   ECORE_FILTER_RSS_CONF_PENDING,
5731                                   &sc->sp_state, ECORE_OBJ_TYPE_RX);
5732 }
5733
5734 /*
5735  * Initialize the function. This must be called before sending CLIENT_SETUP
5736  * for the first client.
5737  */
5738 static int bnx2x_func_start(struct bnx2x_softc *sc)
5739 {
5740         struct ecore_func_state_params func_params = { NULL };
5741         struct ecore_func_start_params *start_params =
5742             &func_params.params.start;
5743
5744         /* Prepare parameters for function state transitions */
5745         bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5746
5747         func_params.f_obj = &sc->func_obj;
5748         func_params.cmd = ECORE_F_CMD_START;
5749
5750         /* Function parameters */
5751         start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5752         start_params->sd_vlan_tag = OVLAN(sc);
5753
5754         if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5755                 start_params->network_cos_mode = STATIC_COS;
5756         } else {                /* CHIP_IS_E1X */
5757                 start_params->network_cos_mode = FW_WRR;
5758         }
5759
5760         start_params->gre_tunnel_mode = 0;
5761         start_params->gre_tunnel_rss = 0;
5762
5763         return ecore_func_state_change(sc, &func_params);
5764 }
5765
5766 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5767 {
5768         uint16_t pmcsr;
5769
5770         /* If there is no power capability, silently succeed */
5771         if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5772                 PMD_DRV_LOG(WARNING, "No power capability");
5773                 return 0;
5774         }
5775
5776         pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5777                  2);
5778
5779         switch (state) {
5780         case PCI_PM_D0:
5781                 pci_write_word(sc,
5782                                (sc->devinfo.pcie_pm_cap_reg +
5783                                 PCIR_POWER_STATUS),
5784                                ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5785
5786                 if (pmcsr & PCIM_PSTAT_DMASK) {
5787                         /* delay required during transition out of D3hot */
5788                         DELAY(20000);
5789                 }
5790
5791                 break;
5792
5793         case PCI_PM_D3hot:
5794                 /* don't shut down the power for emulation and FPGA */
5795                 if (CHIP_REV_IS_SLOW(sc)) {
5796                         return 0;
5797                 }
5798
5799                 pmcsr &= ~PCIM_PSTAT_DMASK;
5800                 pmcsr |= PCIM_PSTAT_D3;
5801
5802                 if (sc->wol) {
5803                         pmcsr |= PCIM_PSTAT_PMEENABLE;
5804                 }
5805
5806                 pci_write_long(sc,
5807                                (sc->devinfo.pcie_pm_cap_reg +
5808                                 PCIR_POWER_STATUS), pmcsr);
5809
5810                 /*
5811                  * No more memory access after this point until device is brought back
5812                  * to D0 state.
5813                  */
5814                 break;
5815
5816         default:
5817                 PMD_DRV_LOG(NOTICE, "Can't support PCI power state = %d",
5818                             state);
5819                 return -1;
5820         }
5821
5822         return 0;
5823 }
5824
5825 /* return true if succeeded to acquire the lock */
5826 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5827 {
5828         uint32_t lock_status;
5829         uint32_t resource_bit = (1 << resource);
5830         int func = SC_FUNC(sc);
5831         uint32_t hw_lock_control_reg;
5832
5833         /* Validating that the resource is within range */
5834         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5835                 PMD_DRV_LOG(INFO,
5836                             "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5837                             resource, HW_LOCK_MAX_RESOURCE_VALUE);
5838                 return FALSE;
5839         }
5840
5841         if (func <= 5) {
5842                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5843         } else {
5844                 hw_lock_control_reg =
5845                     (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5846         }
5847
5848         /* try to acquire the lock */
5849         REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5850         lock_status = REG_RD(sc, hw_lock_control_reg);
5851         if (lock_status & resource_bit) {
5852                 return TRUE;
5853         }
5854
5855         PMD_DRV_LOG(NOTICE, "Failed to get a resource lock 0x%x", resource);
5856
5857         return FALSE;
5858 }
5859
5860 /*
5861  * Get the recovery leader resource id according to the engine this function
5862  * belongs to. Currently only only 2 engines is supported.
5863  */
5864 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5865 {
5866         if (SC_PATH(sc)) {
5867                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5868         } else {
5869                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5870         }
5871 }
5872
5873 /* try to acquire a leader lock for current engine */
5874 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5875 {
5876         return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5877 }
5878
5879 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5880 {
5881         return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5882 }
5883
5884 /* close gates #2, #3 and #4 */
5885 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5886 {
5887         uint32_t val;
5888
5889         /* gates #2 and #4a are closed/opened */
5890         /* #4 */
5891         REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5892         /* #2 */
5893         REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5894
5895         /* #3 */
5896         if (CHIP_IS_E1x(sc)) {
5897 /* prevent interrupts from HC on both ports */
5898                 val = REG_RD(sc, HC_REG_CONFIG_1);
5899                 if (close)
5900                         REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5901                                                      HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5902                 else
5903                         REG_WR(sc, HC_REG_CONFIG_1,
5904                                (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5905
5906                 val = REG_RD(sc, HC_REG_CONFIG_0);
5907                 if (close)
5908                         REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5909                                                      HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5910                 else
5911                         REG_WR(sc, HC_REG_CONFIG_0,
5912                                (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5913
5914         } else {
5915 /* Prevent incomming interrupts in IGU */
5916                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5917
5918                 if (close)
5919                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5920                                (val & ~(uint32_t)
5921                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5922                 else
5923                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5924                                (val |
5925                                 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5926         }
5927
5928         wmb();
5929 }
5930
5931 /* poll for pending writes bit, it should get cleared in no more than 1s */
5932 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5933 {
5934         uint32_t cnt = 1000;
5935         uint32_t pend_bits = 0;
5936
5937         do {
5938                 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5939
5940                 if (pend_bits == 0) {
5941                         break;
5942                 }
5943
5944                 DELAY(1000);
5945         } while (cnt-- > 0);
5946
5947         if (cnt <= 0) {
5948                 PMD_DRV_LOG(NOTICE, "Still pending IGU requests bits=0x%08x!",
5949                             pend_bits);
5950                 return -1;
5951         }
5952
5953         return 0;
5954 }
5955
5956 #define SHARED_MF_CLP_MAGIC  0x80000000 /* 'magic' bit */
5957
5958 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5959 {
5960         /* Do some magic... */
5961         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5962         *magic_val = val & SHARED_MF_CLP_MAGIC;
5963         MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
5964 }
5965
5966 /* restore the value of the 'magic' bit */
5967 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
5968 {
5969         /* Restore the 'magic' bit value... */
5970         uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
5971         MFCFG_WR(sc, shared_mf_config.clp_mb,
5972                  (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
5973 }
5974
5975 /* prepare for MCP reset, takes care of CLP configurations */
5976 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
5977 {
5978         uint32_t shmem;
5979         uint32_t validity_offset;
5980
5981         /* set `magic' bit in order to save MF config */
5982         bnx2x_clp_reset_prep(sc, magic_val);
5983
5984         /* get shmem offset */
5985         shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
5986         validity_offset =
5987             offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
5988
5989         /* Clear validity map flags */
5990         if (shmem > 0) {
5991                 REG_WR(sc, shmem + validity_offset, 0);
5992         }
5993 }
5994
5995 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
5996 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
5997
5998 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
5999 {
6000         /* special handling for emulation and FPGA (10 times longer) */
6001         if (CHIP_REV_IS_SLOW(sc)) {
6002                 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6003         } else {
6004                 DELAY((MCP_ONE_TIMEOUT) * 1000);
6005         }
6006 }
6007
6008 /* initialize shmem_base and waits for validity signature to appear */
6009 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6010 {
6011         int cnt = 0;
6012         uint32_t val = 0;
6013
6014         do {
6015                 sc->devinfo.shmem_base =
6016                     sc->link_params.shmem_base =
6017                     REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6018
6019                 if (sc->devinfo.shmem_base) {
6020                         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6021                         if (val & SHR_MEM_VALIDITY_MB)
6022                                 return 0;
6023                 }
6024
6025                 bnx2x_mcp_wait_one(sc);
6026
6027         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6028
6029         PMD_DRV_LOG(NOTICE, "BAD MCP validity signature");
6030
6031         return -1;
6032 }
6033
6034 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6035 {
6036         int rc = bnx2x_init_shmem(sc);
6037
6038         /* Restore the `magic' bit value */
6039         bnx2x_clp_reset_done(sc, magic_val);
6040
6041         return rc;
6042 }
6043
6044 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6045 {
6046         REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6047         REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6048         wmb();
6049 }
6050
6051 /*
6052  * Reset the whole chip except for:
6053  *      - PCIE core
6054  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6055  *      - IGU
6056  *      - MISC (including AEU)
6057  *      - GRC
6058  *      - RBCN, RBCP
6059  */
6060 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6061 {
6062         uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6063         uint32_t global_bits2, stay_reset2;
6064
6065         /*
6066          * Bits that have to be set in reset_mask2 if we want to reset 'global'
6067          * (per chip) blocks.
6068          */
6069         global_bits2 =
6070             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6071             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6072
6073         /*
6074          * Don't reset the following blocks.
6075          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6076          *            reset, as in 4 port device they might still be owned
6077          *            by the MCP (there is only one leader per path).
6078          */
6079         not_reset_mask1 =
6080             MISC_REGISTERS_RESET_REG_1_RST_HC |
6081             MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6082             MISC_REGISTERS_RESET_REG_1_RST_PXP;
6083
6084         not_reset_mask2 =
6085             MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6086             MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6087             MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6088             MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6089             MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6090             MISC_REGISTERS_RESET_REG_2_RST_GRC |
6091             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6092             MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6093             MISC_REGISTERS_RESET_REG_2_RST_ATC |
6094             MISC_REGISTERS_RESET_REG_2_PGLC |
6095             MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6096             MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6097             MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6098             MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6099             MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6100
6101         /*
6102          * Keep the following blocks in reset:
6103          *  - all xxMACs are handled by the elink code.
6104          */
6105         stay_reset2 =
6106             MISC_REGISTERS_RESET_REG_2_XMAC |
6107             MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6108
6109         /* Full reset masks according to the chip */
6110         reset_mask1 = 0xffffffff;
6111
6112         if (CHIP_IS_E1H(sc))
6113                 reset_mask2 = 0x1ffff;
6114         else if (CHIP_IS_E2(sc))
6115                 reset_mask2 = 0xfffff;
6116         else                    /* CHIP_IS_E3 */
6117                 reset_mask2 = 0x3ffffff;
6118
6119         /* Don't reset global blocks unless we need to */
6120         if (!global)
6121                 reset_mask2 &= ~global_bits2;
6122
6123         /*
6124          * In case of attention in the QM, we need to reset PXP
6125          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6126          * because otherwise QM reset would release 'close the gates' shortly
6127          * before resetting the PXP, then the PSWRQ would send a write
6128          * request to PGLUE. Then when PXP is reset, PGLUE would try to
6129          * read the payload data from PSWWR, but PSWWR would not
6130          * respond. The write queue in PGLUE would stuck, dmae commands
6131          * would not return. Therefore it's important to reset the second
6132          * reset register (containing the
6133          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6134          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6135          * bit).
6136          */
6137         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6138                reset_mask2 & (~not_reset_mask2));
6139
6140         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6141                reset_mask1 & (~not_reset_mask1));
6142
6143         mb();
6144         wmb();
6145
6146         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6147                reset_mask2 & (~stay_reset2));
6148
6149         mb();
6150         wmb();
6151
6152         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6153         wmb();
6154 }
6155
6156 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6157 {
6158         int cnt = 1000;
6159         uint32_t val = 0;
6160         uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6161         uint32_t tags_63_32 = 0;
6162
6163         /* Empty the Tetris buffer, wait for 1s */
6164         do {
6165                 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6166                 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6167                 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6168                 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6169                 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6170                 if (CHIP_IS_E3(sc)) {
6171                         tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6172                 }
6173
6174                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6175                     ((port_is_idle_0 & 0x1) == 0x1) &&
6176                     ((port_is_idle_1 & 0x1) == 0x1) &&
6177                     (pgl_exp_rom2 == 0xffffffff) &&
6178                     (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6179                         break;
6180                 DELAY(1000);
6181         } while (cnt-- > 0);
6182
6183         if (cnt <= 0) {
6184                 PMD_DRV_LOG(NOTICE,
6185                             "ERROR: Tetris buffer didn't get empty or there "
6186                             "are still outstanding read requests after 1s! "
6187                             "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6188                             "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6189                             sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6190                             pgl_exp_rom2);
6191                 return -1;
6192         }
6193
6194         mb();
6195
6196         /* Close gates #2, #3 and #4 */
6197         bnx2x_set_234_gates(sc, TRUE);
6198
6199         /* Poll for IGU VQs for 57712 and newer chips */
6200         if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6201                 return -1;
6202         }
6203
6204         /* clear "unprepared" bit */
6205         REG_WR(sc, MISC_REG_UNPREPARED, 0);
6206         mb();
6207
6208         /* Make sure all is written to the chip before the reset */
6209         wmb();
6210
6211         /*
6212          * Wait for 1ms to empty GLUE and PCI-E core queues,
6213          * PSWHST, GRC and PSWRD Tetris buffer.
6214          */
6215         DELAY(1000);
6216
6217         /* Prepare to chip reset: */
6218         /* MCP */
6219         if (global) {
6220                 bnx2x_reset_mcp_prep(sc, &val);
6221         }
6222
6223         /* PXP */
6224         bnx2x_pxp_prep(sc);
6225         mb();
6226
6227         /* reset the chip */
6228         bnx2x_process_kill_chip_reset(sc, global);
6229         mb();
6230
6231         /* Recover after reset: */
6232         /* MCP */
6233         if (global && bnx2x_reset_mcp_comp(sc, val)) {
6234                 return -1;
6235         }
6236
6237         /* Open the gates #2, #3 and #4 */
6238         bnx2x_set_234_gates(sc, FALSE);
6239
6240         return 0;
6241 }
6242
6243 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6244 {
6245         int rc = 0;
6246         uint8_t global = bnx2x_reset_is_global(sc);
6247         uint32_t load_code;
6248
6249         /*
6250          * If not going to reset MCP, load "fake" driver to reset HW while
6251          * driver is owner of the HW.
6252          */
6253         if (!global && !BNX2X_NOMCP(sc)) {
6254                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6255                                            DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6256                 if (!load_code) {
6257                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6258                         rc = -1;
6259                         goto exit_leader_reset;
6260                 }
6261
6262                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6263                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6264                         PMD_DRV_LOG(NOTICE,
6265                                     "MCP unexpected response, aborting");
6266                         rc = -1;
6267                         goto exit_leader_reset2;
6268                 }
6269
6270                 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6271                 if (!load_code) {
6272                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
6273                         rc = -1;
6274                         goto exit_leader_reset2;
6275                 }
6276         }
6277
6278         /* try to recover after the failure */
6279         if (bnx2x_process_kill(sc, global)) {
6280                 PMD_DRV_LOG(NOTICE, "Something bad occurred on engine %d!",
6281                             SC_PATH(sc));
6282                 rc = -1;
6283                 goto exit_leader_reset2;
6284         }
6285
6286         /*
6287          * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6288          * state.
6289          */
6290         bnx2x_set_reset_done(sc);
6291         if (global) {
6292                 bnx2x_clear_reset_global(sc);
6293         }
6294
6295 exit_leader_reset2:
6296
6297         /* unload "fake driver" if it was loaded */
6298         if (!global &&!BNX2X_NOMCP(sc)) {
6299                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6300                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6301         }
6302
6303 exit_leader_reset:
6304
6305         sc->is_leader = 0;
6306         bnx2x_release_leader_lock(sc);
6307
6308         mb();
6309         return rc;
6310 }
6311
6312 /*
6313  * prepare INIT transition, parameters configured:
6314  *   - HC configuration
6315  *   - Queue's CDU context
6316  */
6317 static void
6318 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6319                    struct ecore_queue_init_params *init_params)
6320 {
6321         uint8_t cos;
6322         int cxt_index, cxt_offset;
6323
6324         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6325         bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6326
6327         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6328         bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6329
6330         /* HC rate */
6331         init_params->rx.hc_rate =
6332             sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6333         init_params->tx.hc_rate =
6334             sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6335
6336         /* FW SB ID */
6337         init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6338
6339         /* CQ index among the SB indices */
6340         init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6341         init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6342
6343         /* set maximum number of COSs supported by this queue */
6344         init_params->max_cos = sc->max_cos;
6345
6346         /* set the context pointers queue object */
6347         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6348                 cxt_index = fp->index / ILT_PAGE_CIDS;
6349                 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6350                 init_params->cxts[cos] =
6351                     &sc->context[cxt_index].vcxt[cxt_offset].eth;
6352         }
6353 }
6354
6355 /* set flags that are common for the Tx-only and not normal connections */
6356 static unsigned long
6357 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6358 {
6359         unsigned long flags = 0;
6360
6361         /* PF driver will always initialize the Queue to an ACTIVE state */
6362         bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6363
6364         /*
6365          * tx only connections collect statistics (on the same index as the
6366          * parent connection). The statistics are zeroed when the parent
6367          * connection is initialized.
6368          */
6369
6370         bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6371         if (zero_stats) {
6372                 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6373         }
6374
6375         /*
6376          * tx only connections can support tx-switching, though their
6377          * CoS-ness doesn't survive the loopback
6378          */
6379         if (sc->flags & BNX2X_TX_SWITCHING) {
6380                 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6381         }
6382
6383         bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6384
6385         return flags;
6386 }
6387
6388 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6389 {
6390         unsigned long flags = 0;
6391
6392         if (IS_MF_SD(sc)) {
6393                 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6394         }
6395
6396         if (leading) {
6397                 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6398                 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6399         }
6400
6401         bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6402
6403         /* merge with common flags */
6404         return flags | bnx2x_get_common_flags(sc, TRUE);
6405 }
6406
6407 static void
6408 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6409                       struct ecore_general_setup_params *gen_init, uint8_t cos)
6410 {
6411         gen_init->stat_id = bnx2x_stats_id(fp);
6412         gen_init->spcl_id = fp->cl_id;
6413         gen_init->mtu = sc->mtu;
6414         gen_init->cos = cos;
6415 }
6416
6417 static void
6418 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6419                  struct rxq_pause_params *pause,
6420                  struct ecore_rxq_setup_params *rxq_init)
6421 {
6422         struct bnx2x_rx_queue *rxq;
6423
6424         rxq = sc->rx_queues[fp->index];
6425         if (!rxq) {
6426                 PMD_RX_LOG(ERR, "RX queue is NULL");
6427                 return;
6428         }
6429         /* pause */
6430         pause->bd_th_lo = BD_TH_LO(sc);
6431         pause->bd_th_hi = BD_TH_HI(sc);
6432
6433         pause->rcq_th_lo = RCQ_TH_LO(sc);
6434         pause->rcq_th_hi = RCQ_TH_HI(sc);
6435
6436         /* validate rings have enough entries to cross high thresholds */
6437         if (sc->dropless_fc &&
6438             pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6439                 PMD_DRV_LOG(WARNING, "rx bd ring threshold limit");
6440         }
6441
6442         if (sc->dropless_fc &&
6443             pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6444                 PMD_DRV_LOG(WARNING, "rcq ring threshold limit");
6445         }
6446
6447         pause->pri_map = 1;
6448
6449         /* rxq setup */
6450         rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6451         rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6452         rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6453                                               BNX2X_PAGE_SIZE);
6454
6455         /*
6456          * This should be a maximum number of data bytes that may be
6457          * placed on the BD (not including paddings).
6458          */
6459         rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6460
6461         rxq_init->cl_qzone_id = fp->cl_qzone_id;
6462         rxq_init->rss_engine_id = SC_FUNC(sc);
6463         rxq_init->mcast_engine_id = SC_FUNC(sc);
6464
6465         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6466         rxq_init->fw_sb_id = fp->fw_sb_id;
6467
6468         rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6469
6470         /*
6471          * configure silent vlan removal
6472          * if multi function mode is afex, then mask default vlan
6473          */
6474         if (IS_MF_AFEX(sc)) {
6475                 rxq_init->silent_removal_value =
6476                     sc->devinfo.mf_info.afex_def_vlan_tag;
6477                 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6478         }
6479 }
6480
6481 static void
6482 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6483                  struct ecore_txq_setup_params *txq_init, uint8_t cos)
6484 {
6485         struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6486
6487         if (!txq) {
6488                 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6489                 return;
6490         }
6491         txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6492         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6493         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6494         txq_init->fw_sb_id = fp->fw_sb_id;
6495
6496         /*
6497          * set the TSS leading client id for TX classfication to the
6498          * leading RSS client id
6499          */
6500         txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6501 }
6502
6503 /*
6504  * This function performs 2 steps in a queue state machine:
6505  *   1) RESET->INIT
6506  *   2) INIT->SETUP
6507  */
6508 static int
6509 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6510 {
6511         struct ecore_queue_state_params q_params = { NULL };
6512         struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6513         int rc;
6514
6515         PMD_DRV_LOG(DEBUG, "setting up queue %d", fp->index);
6516
6517         bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6518
6519         q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6520
6521         /* we want to wait for completion in this context */
6522         bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6523
6524         /* prepare the INIT parameters */
6525         bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6526
6527         /* Set the command */
6528         q_params.cmd = ECORE_Q_CMD_INIT;
6529
6530         /* Change the state to INIT */
6531         rc = ecore_queue_state_change(sc, &q_params);
6532         if (rc) {
6533                 PMD_DRV_LOG(NOTICE, "Queue(%d) INIT failed", fp->index);
6534                 return rc;
6535         }
6536
6537         PMD_DRV_LOG(DEBUG, "init complete");
6538
6539         /* now move the Queue to the SETUP state */
6540         memset(setup_params, 0, sizeof(*setup_params));
6541
6542         /* set Queue flags */
6543         setup_params->flags = bnx2x_get_q_flags(sc, leading);
6544
6545         /* set general SETUP parameters */
6546         bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6547                               FIRST_TX_COS_INDEX);
6548
6549         bnx2x_pf_rx_q_prep(sc, fp,
6550                          &setup_params->pause_params,
6551                          &setup_params->rxq_params);
6552
6553         bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6554
6555         /* Set the command */
6556         q_params.cmd = ECORE_Q_CMD_SETUP;
6557
6558         /* change the state to SETUP */
6559         rc = ecore_queue_state_change(sc, &q_params);
6560         if (rc) {
6561                 PMD_DRV_LOG(NOTICE, "Queue(%d) SETUP failed", fp->index);
6562                 return rc;
6563         }
6564
6565         return rc;
6566 }
6567
6568 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6569 {
6570         if (IS_PF(sc))
6571                 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6572         else                    /* VF */
6573                 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6574 }
6575
6576 static int
6577 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6578                   uint8_t config_hash)
6579 {
6580         struct ecore_config_rss_params params = { NULL };
6581         uint32_t i;
6582
6583         /*
6584          * Although RSS is meaningless when there is a single HW queue we
6585          * still need it enabled in order to have HW Rx hash generated.
6586          */
6587
6588         params.rss_obj = rss_obj;
6589
6590         bnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
6591
6592         bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);
6593
6594         /* RSS configuration */
6595         bnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);
6596         bnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);
6597         bnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);
6598         bnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);
6599         if (rss_obj->udp_rss_v4) {
6600                 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);
6601         }
6602         if (rss_obj->udp_rss_v6) {
6603                 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);
6604         }
6605
6606         /* Hash bits */
6607         params.rss_result_mask = MULTI_MASK;
6608
6609         (void)rte_memcpy(params.ind_table, rss_obj->ind_table,
6610                          sizeof(params.ind_table));
6611
6612         if (config_hash) {
6613 /* RSS keys */
6614                 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6615                         params.rss_key[i] = (uint32_t) rte_rand();
6616                 }
6617
6618                 bnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);
6619         }
6620
6621         if (IS_PF(sc))
6622                 return ecore_config_rss(sc, &params);
6623         else
6624                 return bnx2x_vf_config_rss(sc, &params);
6625 }
6626
6627 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6628 {
6629         return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6630 }
6631
6632 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6633 {
6634         uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6635         uint32_t i;
6636
6637         /*
6638          * Prepare the initial contents of the indirection table if
6639          * RSS is enabled
6640          */
6641         for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6642                 sc->rss_conf_obj.ind_table[i] =
6643                     (sc->fp->cl_id + (i % num_eth_queues));
6644         }
6645
6646         if (sc->udp_rss) {
6647                 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6648         }
6649
6650         /*
6651          * For 57711 SEARCHER configuration (rss_keys) is
6652          * per-port, so if explicit configuration is needed, do it only
6653          * for a PMF.
6654          *
6655          * For 57712 and newer it's a per-function configuration.
6656          */
6657         return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6658 }
6659
6660 static int
6661 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6662                 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6663                 unsigned long *ramrod_flags)
6664 {
6665         struct ecore_vlan_mac_ramrod_params ramrod_param;
6666         int rc;
6667
6668         memset(&ramrod_param, 0, sizeof(ramrod_param));
6669
6670         /* fill in general parameters */
6671         ramrod_param.vlan_mac_obj = obj;
6672         ramrod_param.ramrod_flags = *ramrod_flags;
6673
6674         /* fill a user request section if needed */
6675         if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6676                 (void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6677                                  ETH_ALEN);
6678
6679                 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6680
6681 /* Set the command: ADD or DEL */
6682                 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6683                     ECORE_VLAN_MAC_DEL;
6684         }
6685
6686         rc = ecore_config_vlan_mac(sc, &ramrod_param);
6687
6688         if (rc == ECORE_EXISTS) {
6689                 PMD_DRV_LOG(INFO, "Failed to schedule ADD operations (EEXIST)");
6690 /* do not treat adding same MAC as error */
6691                 rc = 0;
6692         } else if (rc < 0) {
6693                 PMD_DRV_LOG(ERR,
6694                             "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6695         }
6696
6697         return rc;
6698 }
6699
6700 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6701 {
6702         unsigned long ramrod_flags = 0;
6703
6704         PMD_DRV_LOG(DEBUG, "Adding Ethernet MAC");
6705
6706         bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6707
6708         /* Eth MAC is set on RSS leading client (fp[0]) */
6709         return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6710                                &sc->sp_objs->mac_obj,
6711                                set, ECORE_ETH_MAC, &ramrod_flags);
6712 }
6713
6714 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6715 {
6716         uint32_t sel_phy_idx = 0;
6717
6718         if (sc->link_params.num_phys <= 1) {
6719                 return ELINK_INT_PHY;
6720         }
6721
6722         if (sc->link_vars.link_up) {
6723                 sel_phy_idx = ELINK_EXT_PHY1;
6724 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6725                 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6726                     (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6727                      ELINK_SUPPORTED_FIBRE))
6728                         sel_phy_idx = ELINK_EXT_PHY2;
6729         } else {
6730                 switch (elink_phy_selection(&sc->link_params)) {
6731                 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6732                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6733                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6734                         sel_phy_idx = ELINK_EXT_PHY1;
6735                         break;
6736                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6737                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6738                         sel_phy_idx = ELINK_EXT_PHY2;
6739                         break;
6740                 }
6741         }
6742
6743         return sel_phy_idx;
6744 }
6745
6746 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6747 {
6748         uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6749
6750         /*
6751          * The selected activated PHY is always after swapping (in case PHY
6752          * swapping is enabled). So when swapping is enabled, we need to reverse
6753          * the configuration
6754          */
6755
6756         if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6757                 if (sel_phy_idx == ELINK_EXT_PHY1)
6758                         sel_phy_idx = ELINK_EXT_PHY2;
6759                 else if (sel_phy_idx == ELINK_EXT_PHY2)
6760                         sel_phy_idx = ELINK_EXT_PHY1;
6761         }
6762
6763         return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6764 }
6765
6766 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6767 {
6768         /*
6769          * Initialize link parameters structure variables
6770          * It is recommended to turn off RX FC for jumbo frames
6771          * for better performance
6772          */
6773         if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6774                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6775         } else {
6776                 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6777         }
6778 }
6779
6780 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6781 {
6782         uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6783         switch (sc->link_vars.ieee_fc &
6784                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6785         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6786         default:
6787                 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6788                                                    ADVERTISED_Pause);
6789                 break;
6790
6791         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6792                 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6793                                                   ADVERTISED_Pause);
6794                 break;
6795
6796         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6797                 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6798                 break;
6799         }
6800 }
6801
6802 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6803 {
6804         uint16_t line_speed = sc->link_vars.line_speed;
6805         if (IS_MF(sc)) {
6806                 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6807                                                       sc->devinfo.
6808                                                       mf_info.mf_config[SC_VN
6809                                                                         (sc)]);
6810
6811 /* calculate the current MAX line speed limit for the MF devices */
6812                 if (IS_MF_SI(sc)) {
6813                         line_speed = (line_speed * maxCfg) / 100;
6814                 } else {        /* SD mode */
6815                         uint16_t vn_max_rate = maxCfg * 100;
6816
6817                         if (vn_max_rate < line_speed) {
6818                                 line_speed = vn_max_rate;
6819                         }
6820                 }
6821         }
6822
6823         return line_speed;
6824 }
6825
6826 static void
6827 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6828 {
6829         uint16_t line_speed = bnx2x_get_mf_speed(sc);
6830
6831         memset(data, 0, sizeof(*data));
6832
6833         /* fill the report data with the effective line speed */
6834         data->line_speed = line_speed;
6835
6836         /* Link is down */
6837         if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6838                 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6839                             &data->link_report_flags);
6840         }
6841
6842         /* Full DUPLEX */
6843         if (sc->link_vars.duplex == DUPLEX_FULL) {
6844                 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6845                             &data->link_report_flags);
6846         }
6847
6848         /* Rx Flow Control is ON */
6849         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6850                 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6851         }
6852
6853         /* Tx Flow Control is ON */
6854         if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6855                 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6856         }
6857 }
6858
6859 /* report link status to OS, should be called under phy_lock */
6860 static void bnx2x_link_report(struct bnx2x_softc *sc)
6861 {
6862         struct bnx2x_link_report_data cur_data;
6863
6864         /* reread mf_cfg */
6865         if (IS_PF(sc)) {
6866                 bnx2x_read_mf_cfg(sc);
6867         }
6868
6869         /* Read the current link report info */
6870         bnx2x_fill_report_data(sc, &cur_data);
6871
6872         /* Don't report link down or exactly the same link status twice */
6873         if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6874             (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6875                           &sc->last_reported_link.link_report_flags) &&
6876              bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6877                           &cur_data.link_report_flags))) {
6878                 return;
6879         }
6880
6881         sc->link_cnt++;
6882
6883         /* report new link params and remember the state for the next time */
6884         (void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6885
6886         if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6887                          &cur_data.link_report_flags)) {
6888                 PMD_DRV_LOG(INFO, "NIC Link is Down");
6889         } else {
6890                 __rte_unused const char *duplex;
6891                 __rte_unused const char *flow;
6892
6893                 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6894                                            &cur_data.link_report_flags)) {
6895                         duplex = "full";
6896                 } else {
6897                         duplex = "half";
6898                 }
6899
6900 /*
6901  * Handle the FC at the end so that only these flags would be
6902  * possibly set. This way we may easily check if there is no FC
6903  * enabled.
6904  */
6905                 if (cur_data.link_report_flags) {
6906                         if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6907                                          &cur_data.link_report_flags) &&
6908                             bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6909                                          &cur_data.link_report_flags)) {
6910                                 flow = "ON - receive & transmit";
6911                         } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6912                                                 &cur_data.link_report_flags) &&
6913                                    !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6914                                                  &cur_data.link_report_flags)) {
6915                                 flow = "ON - receive";
6916                         } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6917                                                  &cur_data.link_report_flags) &&
6918                                    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6919                                                 &cur_data.link_report_flags)) {
6920                                 flow = "ON - transmit";
6921                         } else {
6922                                 flow = "none";  /* possible? */
6923                         }
6924                 } else {
6925                         flow = "none";
6926                 }
6927
6928                 PMD_DRV_LOG(INFO,
6929                             "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6930                             cur_data.line_speed, duplex, flow);
6931         }
6932 }
6933
6934 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6935 {
6936         if (sc->state != BNX2X_STATE_OPEN) {
6937                 return;
6938         }
6939
6940         if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
6941                 elink_link_status_update(&sc->link_params, &sc->link_vars);
6942         } else {
6943                 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
6944                                           ELINK_SUPPORTED_10baseT_Full |
6945                                           ELINK_SUPPORTED_100baseT_Half |
6946                                           ELINK_SUPPORTED_100baseT_Full |
6947                                           ELINK_SUPPORTED_1000baseT_Full |
6948                                           ELINK_SUPPORTED_2500baseX_Full |
6949                                           ELINK_SUPPORTED_10000baseT_Full |
6950                                           ELINK_SUPPORTED_TP |
6951                                           ELINK_SUPPORTED_FIBRE |
6952                                           ELINK_SUPPORTED_Autoneg |
6953                                           ELINK_SUPPORTED_Pause |
6954                                           ELINK_SUPPORTED_Asym_Pause);
6955                 sc->port.advertising[0] = sc->port.supported[0];
6956
6957                 sc->link_params.sc = sc;
6958                 sc->link_params.port = SC_PORT(sc);
6959                 sc->link_params.req_duplex[0] = DUPLEX_FULL;
6960                 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
6961                 sc->link_params.req_line_speed[0] = SPEED_10000;
6962                 sc->link_params.speed_cap_mask[0] = 0x7f0000;
6963                 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
6964
6965                 if (CHIP_REV_IS_FPGA(sc)) {
6966                         sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
6967                         sc->link_vars.line_speed = ELINK_SPEED_1000;
6968                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6969                                                      LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
6970                 } else {
6971                         sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
6972                         sc->link_vars.line_speed = ELINK_SPEED_10000;
6973                         sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
6974                                                      LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
6975                 }
6976
6977                 sc->link_vars.link_up = 1;
6978
6979                 sc->link_vars.duplex = DUPLEX_FULL;
6980                 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
6981
6982                 if (IS_PF(sc)) {
6983                         REG_WR(sc,
6984                                NIG_REG_EGRESS_DRAIN0_MODE +
6985                                sc->link_params.port * 4, 0);
6986                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6987                         bnx2x_link_report(sc);
6988                 }
6989         }
6990
6991         if (IS_PF(sc)) {
6992                 if (sc->link_vars.link_up) {
6993                         bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
6994                 } else {
6995                         bnx2x_stats_handle(sc, STATS_EVENT_STOP);
6996                 }
6997                 bnx2x_link_report(sc);
6998         } else {
6999                 bnx2x_link_report(sc);
7000                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7001         }
7002 }
7003
7004 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7005 {
7006         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7007 }
7008
7009 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7010 {
7011         atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7012 }
7013
7014 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7015 {
7016         int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7017         uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7018         struct elink_params *lp = &sc->link_params;
7019
7020         bnx2x_set_requested_fc(sc);
7021
7022         if (load_mode == LOAD_DIAG) {
7023                 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7024 /* Prefer doing PHY loopback at 10G speed, if possible */
7025                 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7026                         if (lp->speed_cap_mask[cfg_idx] &
7027                             PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7028                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7029                         } else {
7030                                 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7031                         }
7032                 }
7033         }
7034
7035         if (load_mode == LOAD_LOOPBACK_EXT) {
7036                 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7037         }
7038
7039         rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7040
7041         bnx2x_calc_fc_adv(sc);
7042
7043         if (sc->link_vars.link_up) {
7044                 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7045                 bnx2x_link_report(sc);
7046         }
7047
7048         if (!CHIP_REV_IS_SLOW(sc)) {
7049                 bnx2x_periodic_start(sc);
7050         }
7051
7052         sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7053         return rc;
7054 }
7055
7056 /* update flags in shmem */
7057 static void
7058 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7059 {
7060         uint32_t drv_flags;
7061
7062         if (SHMEM2_HAS(sc, drv_flags)) {
7063                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7064                 drv_flags = SHMEM2_RD(sc, drv_flags);
7065
7066                 if (set) {
7067                         drv_flags |= flags;
7068                 } else {
7069                         drv_flags &= ~flags;
7070                 }
7071
7072                 SHMEM2_WR(sc, drv_flags, drv_flags);
7073
7074                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7075         }
7076 }
7077
7078 /* periodic timer callout routine, only runs when the interface is up */
7079 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7080 {
7081         if ((sc->state != BNX2X_STATE_OPEN) ||
7082             (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7083                 PMD_DRV_LOG(WARNING, "periodic callout exit (state=0x%x)",
7084                             sc->state);
7085                 return;
7086         }
7087         if (!CHIP_REV_IS_SLOW(sc)) {
7088 /*
7089  * This barrier is needed to ensure the ordering between the writing
7090  * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7091  * the reading here.
7092  */
7093                 mb();
7094                 if (sc->port.pmf) {
7095                         elink_period_func(&sc->link_params, &sc->link_vars);
7096                 }
7097         }
7098 #ifdef BNX2X_PULSE
7099         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7100                 int mb_idx = SC_FW_MB_IDX(sc);
7101                 uint32_t drv_pulse;
7102                 uint32_t mcp_pulse;
7103
7104                 ++sc->fw_drv_pulse_wr_seq;
7105                 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7106
7107                 drv_pulse = sc->fw_drv_pulse_wr_seq;
7108                 bnx2x_drv_pulse(sc);
7109
7110                 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7111                              MCP_PULSE_SEQ_MASK);
7112
7113 /*
7114  * The delta between driver pulse and mcp response should
7115  * be 1 (before mcp response) or 0 (after mcp response).
7116  */
7117                 if ((drv_pulse != mcp_pulse) &&
7118                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7119                         /* someone lost a heartbeat... */
7120                         PMD_DRV_LOG(ERR,
7121                                     "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7122                                     drv_pulse, mcp_pulse);
7123                 }
7124         }
7125 #endif
7126 }
7127
7128 /* start the controller */
7129 static __attribute__ ((noinline))
7130 int bnx2x_nic_load(struct bnx2x_softc *sc)
7131 {
7132         uint32_t val;
7133         uint32_t load_code = 0;
7134         int i, rc = 0;
7135
7136         PMD_INIT_FUNC_TRACE();
7137
7138         sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7139
7140         if (IS_PF(sc)) {
7141 /* must be called before memory allocation and HW init */
7142                 bnx2x_ilt_set_info(sc);
7143         }
7144
7145         bnx2x_set_fp_rx_buf_size(sc);
7146
7147         if (IS_PF(sc)) {
7148                 if (bnx2x_alloc_mem(sc) != 0) {
7149                         sc->state = BNX2X_STATE_CLOSED;
7150                         rc = -ENOMEM;
7151                         goto bnx2x_nic_load_error0;
7152                 }
7153         }
7154
7155         if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7156                 sc->state = BNX2X_STATE_CLOSED;
7157                 rc = -ENOMEM;
7158                 goto bnx2x_nic_load_error0;
7159         }
7160
7161         if (IS_VF(sc)) {
7162                 rc = bnx2x_vf_init(sc);
7163                 if (rc) {
7164                         sc->state = BNX2X_STATE_ERROR;
7165                         goto bnx2x_nic_load_error0;
7166                 }
7167         }
7168
7169         if (IS_PF(sc)) {
7170 /* set pf load just before approaching the MCP */
7171                 bnx2x_set_pf_load(sc);
7172
7173 /* if MCP exists send load request and analyze response */
7174                 if (!BNX2X_NOMCP(sc)) {
7175                         /* attempt to load pf */
7176                         if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7177                                 sc->state = BNX2X_STATE_CLOSED;
7178                                 rc = -ENXIO;
7179                                 goto bnx2x_nic_load_error1;
7180                         }
7181
7182                         /* what did the MCP say? */
7183                         if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7184                                 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7185                                 sc->state = BNX2X_STATE_CLOSED;
7186                                 rc = -ENXIO;
7187                                 goto bnx2x_nic_load_error2;
7188                         }
7189                 } else {
7190                         PMD_DRV_LOG(INFO, "Device has no MCP!");
7191                         load_code = bnx2x_nic_load_no_mcp(sc);
7192                 }
7193
7194 /* mark PMF if applicable */
7195                 bnx2x_nic_load_pmf(sc, load_code);
7196
7197 /* Init Function state controlling object */
7198                 bnx2x_init_func_obj(sc);
7199
7200 /* Initialize HW */
7201                 if (bnx2x_init_hw(sc, load_code) != 0) {
7202                         PMD_DRV_LOG(NOTICE, "HW init failed");
7203                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7204                         sc->state = BNX2X_STATE_CLOSED;
7205                         rc = -ENXIO;
7206                         goto bnx2x_nic_load_error2;
7207                 }
7208         }
7209
7210         bnx2x_nic_init(sc, load_code);
7211
7212         /* Init per-function objects */
7213         if (IS_PF(sc)) {
7214                 bnx2x_init_objs(sc);
7215
7216 /* set AFEX default VLAN tag to an invalid value */
7217                 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7218
7219                 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7220                 rc = bnx2x_func_start(sc);
7221                 if (rc) {
7222                         PMD_DRV_LOG(NOTICE, "Function start failed!");
7223                         bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7224                         sc->state = BNX2X_STATE_ERROR;
7225                         goto bnx2x_nic_load_error3;
7226                 }
7227
7228 /* send LOAD_DONE command to MCP */
7229                 if (!BNX2X_NOMCP(sc)) {
7230                         load_code =
7231                             bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7232                         if (!load_code) {
7233                                 PMD_DRV_LOG(NOTICE,
7234                                             "MCP response failure, aborting");
7235                                 sc->state = BNX2X_STATE_ERROR;
7236                                 rc = -ENXIO;
7237                                 goto bnx2x_nic_load_error3;
7238                         }
7239                 }
7240         }
7241
7242         rc = bnx2x_setup_leading(sc);
7243         if (rc) {
7244                 PMD_DRV_LOG(NOTICE, "Setup leading failed!");
7245                 sc->state = BNX2X_STATE_ERROR;
7246                 goto bnx2x_nic_load_error3;
7247         }
7248
7249         FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7250                 if (IS_PF(sc))
7251                         rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7252                 else            /* IS_VF(sc) */
7253                         rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7254
7255                 if (rc) {
7256                         PMD_DRV_LOG(NOTICE, "Queue(%d) setup failed", i);
7257                         sc->state = BNX2X_STATE_ERROR;
7258                         goto bnx2x_nic_load_error3;
7259                 }
7260         }
7261
7262         rc = bnx2x_init_rss_pf(sc);
7263         if (rc) {
7264                 PMD_DRV_LOG(NOTICE, "PF RSS init failed");
7265                 sc->state = BNX2X_STATE_ERROR;
7266                 goto bnx2x_nic_load_error3;
7267         }
7268
7269         /* now when Clients are configured we are ready to work */
7270         sc->state = BNX2X_STATE_OPEN;
7271
7272         /* Configure a ucast MAC */
7273         if (IS_PF(sc)) {
7274                 rc = bnx2x_set_eth_mac(sc, TRUE);
7275         } else {                /* IS_VF(sc) */
7276                 rc = bnx2x_vf_set_mac(sc, TRUE);
7277         }
7278
7279         if (rc) {
7280                 PMD_DRV_LOG(NOTICE, "Setting Ethernet MAC failed");
7281                 sc->state = BNX2X_STATE_ERROR;
7282                 goto bnx2x_nic_load_error3;
7283         }
7284
7285         if (sc->port.pmf) {
7286                 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7287                 if (rc) {
7288                         sc->state = BNX2X_STATE_ERROR;
7289                         goto bnx2x_nic_load_error3;
7290                 }
7291         }
7292
7293         sc->link_params.feature_config_flags &=
7294             ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7295
7296         /* start the Tx */
7297         switch (LOAD_OPEN) {
7298         case LOAD_NORMAL:
7299         case LOAD_OPEN:
7300                 break;
7301
7302         case LOAD_DIAG:
7303         case LOAD_LOOPBACK_EXT:
7304                 sc->state = BNX2X_STATE_DIAG;
7305                 break;
7306
7307         default:
7308                 break;
7309         }
7310
7311         if (sc->port.pmf) {
7312                 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7313         } else {
7314                 bnx2x_link_status_update(sc);
7315         }
7316
7317         if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7318 /* mark driver is loaded in shmem2 */
7319                 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7320                 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7321                           (val |
7322                            DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7323                            DRV_FLAGS_CAPABILITIES_LOADED_L2));
7324         }
7325
7326         /* start fast path */
7327         /* Initialize Rx filter */
7328         bnx2x_set_rx_mode(sc);
7329
7330         /* wait for all pending SP commands to complete */
7331         if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7332                 PMD_DRV_LOG(NOTICE, "Timeout waiting for all SPs to complete!");
7333                 bnx2x_periodic_stop(sc);
7334                 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7335                 return -ENXIO;
7336         }
7337
7338         PMD_DRV_LOG(DEBUG, "NIC successfully loaded");
7339
7340         return 0;
7341
7342 bnx2x_nic_load_error3:
7343
7344         if (IS_PF(sc)) {
7345                 bnx2x_int_disable_sync(sc, 1);
7346
7347 /* clean out queued objects */
7348                 bnx2x_squeeze_objects(sc);
7349         }
7350
7351 bnx2x_nic_load_error2:
7352
7353         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7354                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7355                 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7356         }
7357
7358         sc->port.pmf = 0;
7359
7360 bnx2x_nic_load_error1:
7361
7362         /* clear pf_load status, as it was already set */
7363         if (IS_PF(sc)) {
7364                 bnx2x_clear_pf_load(sc);
7365         }
7366
7367 bnx2x_nic_load_error0:
7368
7369         bnx2x_free_fw_stats_mem(sc);
7370         bnx2x_free_mem(sc);
7371
7372         return rc;
7373 }
7374
7375 /*
7376 * Handles controller initialization.
7377 */
7378 int bnx2x_init(struct bnx2x_softc *sc)
7379 {
7380         int other_engine = SC_PATH(sc) ? 0 : 1;
7381         uint8_t other_load_status, load_status;
7382         uint8_t global = FALSE;
7383         int rc;
7384
7385         /* Check if the driver is still running and bail out if it is. */
7386         if (sc->state != BNX2X_STATE_CLOSED) {
7387                 PMD_DRV_LOG(DEBUG, "Init called while driver is running!");
7388                 rc = 0;
7389                 goto bnx2x_init_done;
7390         }
7391
7392         bnx2x_set_power_state(sc, PCI_PM_D0);
7393
7394         /*
7395          * If parity occurred during the unload, then attentions and/or
7396          * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7397          * loaded on the current engine to complete the recovery. Parity recovery
7398          * is only relevant for PF driver.
7399          */
7400         if (IS_PF(sc)) {
7401                 other_load_status = bnx2x_get_load_status(sc, other_engine);
7402                 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7403
7404                 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7405                     bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7406                         do {
7407                                 /*
7408                                  * If there are attentions and they are in global blocks, set
7409                                  * the GLOBAL_RESET bit regardless whether it will be this
7410                                  * function that will complete the recovery or not.
7411                                  */
7412                                 if (global) {
7413                                         bnx2x_set_reset_global(sc);
7414                                 }
7415
7416                                 /*
7417                                  * Only the first function on the current engine should try
7418                                  * to recover in open. In case of attentions in global blocks
7419                                  * only the first in the chip should try to recover.
7420                                  */
7421                                 if ((!load_status
7422                                      && (!global ||!other_load_status))
7423                                     && bnx2x_trylock_leader_lock(sc)
7424                                     && !bnx2x_leader_reset(sc)) {
7425                                         PMD_DRV_LOG(INFO,
7426                                                     "Recovered during init");
7427                                         break;
7428                                 }
7429
7430                                 /* recovery has failed... */
7431                                 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7432
7433                                 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7434
7435                                 PMD_DRV_LOG(NOTICE,
7436                                             "Recovery flow hasn't properly "
7437                                             "completed yet, try again later. "
7438                                             "If you still see this message after a "
7439                                             "few retries then power cycle is required.");
7440
7441                                 rc = -ENXIO;
7442                                 goto bnx2x_init_done;
7443                         } while (0);
7444                 }
7445         }
7446
7447         sc->recovery_state = BNX2X_RECOVERY_DONE;
7448
7449         rc = bnx2x_nic_load(sc);
7450
7451 bnx2x_init_done:
7452
7453         if (rc) {
7454                 PMD_DRV_LOG(NOTICE, "Initialization failed, "
7455                             "stack notified driver is NOT running!");
7456         }
7457
7458         return rc;
7459 }
7460
7461 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7462 {
7463         uint32_t val = 0;
7464
7465         /*
7466          * Read the ME register to get the function number. The ME register
7467          * holds the relative-function number and absolute-function number. The
7468          * absolute-function number appears only in E2 and above. Before that
7469          * these bits always contained zero, therefore we cannot blindly use them.
7470          */
7471
7472         val = REG_RD(sc, BAR_ME_REGISTER);
7473
7474         sc->pfunc_rel =
7475             (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7476         sc->path_id =
7477             (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7478             1;
7479
7480         if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7481                 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7482         } else {
7483                 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7484         }
7485
7486         PMD_DRV_LOG(DEBUG,
7487                     "Relative function %d, Absolute function %d, Path %d",
7488                     sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7489 }
7490
7491 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7492 {
7493         uint32_t shmem2_size;
7494         uint32_t offset;
7495         uint32_t mf_cfg_offset_value;
7496
7497         /* Non 57712 */
7498         offset = (SHMEM_ADDR(sc, func_mb) +
7499                   (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7500
7501         /* 57712 plus */
7502         if (sc->devinfo.shmem2_base != 0) {
7503                 shmem2_size = SHMEM2_RD(sc, size);
7504                 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7505                         mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7506                         if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7507                                 offset = mf_cfg_offset_value;
7508                         }
7509                 }
7510         }
7511
7512         return offset;
7513 }
7514
7515 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7516 {
7517         uint32_t ret;
7518         struct bnx2x_pci_cap *caps;
7519
7520         /* ensure PCIe capability is enabled */
7521         caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7522         if (NULL != caps) {
7523                 PMD_DRV_LOG(DEBUG, "Found PCIe capability: "
7524                             "id=0x%04X type=0x%04X addr=0x%08X",
7525                             caps->id, caps->type, caps->addr);
7526                 pci_read(sc, (caps->addr + reg), &ret, 2);
7527                 return ret;
7528         }
7529
7530         PMD_DRV_LOG(WARNING, "PCIe capability NOT FOUND!!!");
7531
7532         return 0;
7533 }
7534
7535 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7536 {
7537         return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7538                 PCIM_EXP_STA_TRANSACTION_PND;
7539 }
7540
7541 /*
7542 * Walk the PCI capabiites list for the device to find what features are
7543 * supported. These capabilites may be enabled/disabled by firmware so it's
7544 * best to walk the list rather than make assumptions.
7545 */
7546 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7547 {
7548         PMD_INIT_FUNC_TRACE();
7549
7550         struct bnx2x_pci_cap *caps;
7551         uint16_t link_status;
7552 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7553         int reg = 0;
7554 #endif
7555
7556         /* check if PCI Power Management is enabled */
7557         caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7558         if (NULL != caps) {
7559                 PMD_DRV_LOG(DEBUG, "Found PM capability: "
7560                             "id=0x%04X type=0x%04X addr=0x%08X",
7561                             caps->id, caps->type, caps->addr);
7562
7563                 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7564                 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7565         }
7566
7567         link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7568
7569         sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7570         sc->devinfo.pcie_link_width =
7571             ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7572
7573         PMD_DRV_LOG(DEBUG, "PCIe link speed=%d width=%d",
7574                     sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7575
7576         sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7577
7578         /* check if MSI capability is enabled */
7579         caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7580         if (NULL != caps) {
7581                 PMD_DRV_LOG(DEBUG, "Found MSI capability at 0x%04x", reg);
7582
7583                 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7584                 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7585         }
7586
7587         /* check if MSI-X capability is enabled */
7588         caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7589         if (NULL != caps) {
7590                 PMD_DRV_LOG(DEBUG, "Found MSI-X capability at 0x%04x", reg);
7591
7592                 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7593                 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7594         }
7595 }
7596
7597 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7598 {
7599         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7600         uint32_t val;
7601
7602         /* get the outer vlan if we're in switch-dependent mode */
7603
7604         val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7605         mf_info->ext_id = (uint16_t) val;
7606
7607         mf_info->multi_vnics_mode = 1;
7608
7609         if (!VALID_OVLAN(mf_info->ext_id)) {
7610                 PMD_DRV_LOG(NOTICE, "Invalid VLAN (%d)", mf_info->ext_id);
7611                 return 1;
7612         }
7613
7614         /* get the capabilities */
7615         if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7616             FUNC_MF_CFG_PROTOCOL_ISCSI) {
7617                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7618         } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7619                    == FUNC_MF_CFG_PROTOCOL_FCOE) {
7620                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7621         } else {
7622                 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7623         }
7624
7625         mf_info->vnics_per_port =
7626             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7627
7628         return 0;
7629 }
7630
7631 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7632 {
7633         uint32_t retval = 0;
7634         uint32_t val;
7635
7636         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7637
7638         if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7639                 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7640                         retval |= MF_PROTO_SUPPORT_ETHERNET;
7641                 }
7642                 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7643                         retval |= MF_PROTO_SUPPORT_ISCSI;
7644                 }
7645                 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7646                         retval |= MF_PROTO_SUPPORT_FCOE;
7647                 }
7648         }
7649
7650         return retval;
7651 }
7652
7653 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7654 {
7655         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7656         uint32_t val;
7657
7658         /*
7659          * There is no outer vlan if we're in switch-independent mode.
7660          * If the mac is valid then assume multi-function.
7661          */
7662
7663         val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7664
7665         mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7666
7667         mf_info->mf_protos_supported =
7668             bnx2x_get_shmem_ext_proto_support_flags(sc);
7669
7670         mf_info->vnics_per_port =
7671             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7672
7673         return 0;
7674 }
7675
7676 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7677 {
7678         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7679         uint32_t e1hov_tag;
7680         uint32_t func_config;
7681         uint32_t niv_config;
7682
7683         mf_info->multi_vnics_mode = 1;
7684
7685         e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7686         func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7687         niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7688
7689         mf_info->ext_id =
7690             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7691                         FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7692
7693         mf_info->default_vlan =
7694             (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7695                         FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7696
7697         mf_info->niv_allowed_priorities =
7698             (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7699                        FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7700
7701         mf_info->niv_default_cos =
7702             (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7703                        FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7704
7705         mf_info->afex_vlan_mode =
7706             ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7707              FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7708
7709         mf_info->niv_mba_enabled =
7710             ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7711              FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7712
7713         mf_info->mf_protos_supported =
7714             bnx2x_get_shmem_ext_proto_support_flags(sc);
7715
7716         mf_info->vnics_per_port =
7717             (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7718
7719         return 0;
7720 }
7721
7722 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7723 {
7724         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7725         uint32_t mf_cfg1;
7726         uint32_t mf_cfg2;
7727         uint32_t ovlan1;
7728         uint32_t ovlan2;
7729         uint8_t i, j;
7730
7731         /* various MF mode sanity checks... */
7732
7733         if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7734                 PMD_DRV_LOG(NOTICE,
7735                             "Enumerated function %d is marked as hidden",
7736                             SC_PORT(sc));
7737                 return 1;
7738         }
7739
7740         if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7741                 PMD_DRV_LOG(NOTICE, "vnics_per_port=%d multi_vnics_mode=%d",
7742                             mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7743                 return 1;
7744         }
7745
7746         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7747 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7748                 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7749                         PMD_DRV_LOG(NOTICE, "mf_mode=SD vnic_id=%d ovlan=%d",
7750                                     SC_VN(sc), OVLAN(sc));
7751                         return 1;
7752                 }
7753
7754                 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7755                         PMD_DRV_LOG(NOTICE,
7756                                     "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7757                                     mf_info->multi_vnics_mode, OVLAN(sc));
7758                         return 1;
7759                 }
7760
7761 /*
7762  * Verify all functions are either MF or SF mode. If MF, make sure
7763  * sure that all non-hidden functions have a valid ovlan. If SF,
7764  * make sure that all non-hidden functions have an invalid ovlan.
7765  */
7766                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7767                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7768                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7769                         if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7770                             (((mf_info->multi_vnics_mode)
7771                               && !VALID_OVLAN(ovlan1))
7772                              || ((!mf_info->multi_vnics_mode)
7773                                  && VALID_OVLAN(ovlan1)))) {
7774                                 PMD_DRV_LOG(NOTICE,
7775                                             "mf_mode=SD function %d MF config "
7776                                             "mismatch, multi_vnics_mode=%d ovlan=%d",
7777                                             i, mf_info->multi_vnics_mode,
7778                                             ovlan1);
7779                                 return 1;
7780                         }
7781                 }
7782
7783 /* Verify all funcs on the same port each have a different ovlan. */
7784                 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7785                         mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7786                         ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7787                         /* iterate from the next function on the port to the max func */
7788                         for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7789                                 mf_cfg2 =
7790                                     MFCFG_RD(sc, func_mf_config[j].config);
7791                                 ovlan2 =
7792                                     MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7793                                 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7794                                     && VALID_OVLAN(ovlan1)
7795                                     && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7796                                     && VALID_OVLAN(ovlan2)
7797                                     && (ovlan1 == ovlan2)) {
7798                                         PMD_DRV_LOG(NOTICE,
7799                                                     "mf_mode=SD functions %d and %d "
7800                                                     "have the same ovlan (%d)",
7801                                                     i, j, ovlan1);
7802                                         return 1;
7803                                 }
7804                         }
7805                 }
7806         }
7807         /* MULTI_FUNCTION_SD */
7808         return 0;
7809 }
7810
7811 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7812 {
7813         struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7814         uint32_t val, mac_upper;
7815         uint8_t i, vnic;
7816
7817         /* initialize mf_info defaults */
7818         mf_info->vnics_per_port = 1;
7819         mf_info->multi_vnics_mode = FALSE;
7820         mf_info->path_has_ovlan = FALSE;
7821         mf_info->mf_mode = SINGLE_FUNCTION;
7822
7823         if (!CHIP_IS_MF_CAP(sc)) {
7824                 return 0;
7825         }
7826
7827         if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7828                 PMD_DRV_LOG(NOTICE, "Invalid mf_cfg_base!");
7829                 return 1;
7830         }
7831
7832         /* get the MF mode (switch dependent / independent / single-function) */
7833
7834         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7835
7836         switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7837         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7838
7839                 mac_upper =
7840                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7841
7842                 /* check for legal upper mac bytes */
7843                 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7844                         mf_info->mf_mode = MULTI_FUNCTION_SI;
7845                 } else {
7846                         PMD_DRV_LOG(NOTICE,
7847                                     "Invalid config for Switch Independent mode");
7848                 }
7849
7850                 break;
7851
7852         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7853         case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7854
7855                 /* get outer vlan configuration */
7856                 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7857
7858                 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7859                     FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7860                         mf_info->mf_mode = MULTI_FUNCTION_SD;
7861                 } else {
7862                         PMD_DRV_LOG(NOTICE,
7863                                     "Invalid config for Switch Dependent mode");
7864                 }
7865
7866                 break;
7867
7868         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7869
7870                 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7871                 return 0;
7872
7873         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7874
7875                 /*
7876                  * Mark MF mode as NIV if MCP version includes NPAR-SD support
7877                  * and the MAC address is valid.
7878                  */
7879                 mac_upper =
7880                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7881
7882                 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7883                     (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7884                         mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7885                 } else {
7886                         PMD_DRV_LOG(NOTICE, "Invalid config for AFEX mode");
7887                 }
7888
7889                 break;
7890
7891         default:
7892
7893                 PMD_DRV_LOG(NOTICE, "Unknown MF mode (0x%08x)",
7894                             (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7895
7896                 return 1;
7897         }
7898
7899         /* set path mf_mode (which could be different than function mf_mode) */
7900         if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7901                 mf_info->path_has_ovlan = TRUE;
7902         } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7903 /*
7904  * Decide on path multi vnics mode. If we're not in MF mode and in
7905  * 4-port mode, this is good enough to check vnic-0 of the other port
7906  * on the same path
7907  */
7908                 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7909                         uint8_t other_port = !(PORT_ID(sc) & 1);
7910                         uint8_t abs_func_other_port =
7911                             (SC_PATH(sc) + (2 * other_port));
7912
7913                         val =
7914                             MFCFG_RD(sc,
7915                                      func_mf_config
7916                                      [abs_func_other_port].e1hov_tag);
7917
7918                         mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7919                 }
7920         }
7921
7922         if (mf_info->mf_mode == SINGLE_FUNCTION) {
7923 /* invalid MF config */
7924                 if (SC_VN(sc) >= 1) {
7925                         PMD_DRV_LOG(NOTICE, "VNIC ID >= 1 in SF mode");
7926                         return 1;
7927                 }
7928
7929                 return 0;
7930         }
7931
7932         /* get the MF configuration */
7933         mf_info->mf_config[SC_VN(sc)] =
7934             MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7935
7936         switch (mf_info->mf_mode) {
7937         case MULTI_FUNCTION_SD:
7938
7939                 bnx2x_get_shmem_mf_cfg_info_sd(sc);
7940                 break;
7941
7942         case MULTI_FUNCTION_SI:
7943
7944                 bnx2x_get_shmem_mf_cfg_info_si(sc);
7945                 break;
7946
7947         case MULTI_FUNCTION_AFEX:
7948
7949                 bnx2x_get_shmem_mf_cfg_info_niv(sc);
7950                 break;
7951
7952         default:
7953
7954                 PMD_DRV_LOG(NOTICE, "Get MF config failed (mf_mode=0x%08x)",
7955                             mf_info->mf_mode);
7956                 return 1;
7957         }
7958
7959         /* get the congestion management parameters */
7960
7961         vnic = 0;
7962         FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7963 /* get min/max bw */
7964                 val = MFCFG_RD(sc, func_mf_config[i].config);
7965                 mf_info->min_bw[vnic] =
7966                     ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
7967                      FUNC_MF_CFG_MIN_BW_SHIFT);
7968                 mf_info->max_bw[vnic] =
7969                     ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
7970                      FUNC_MF_CFG_MAX_BW_SHIFT);
7971                 vnic++;
7972         }
7973
7974         return bnx2x_check_valid_mf_cfg(sc);
7975 }
7976
7977 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
7978 {
7979         int port;
7980         uint32_t mac_hi, mac_lo, val;
7981
7982         PMD_INIT_FUNC_TRACE();
7983
7984         port = SC_PORT(sc);
7985         mac_hi = mac_lo = 0;
7986
7987         sc->link_params.sc = sc;
7988         sc->link_params.port = port;
7989
7990         /* get the hardware config info */
7991         sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
7992         sc->devinfo.hw_config2 =
7993             SHMEM_RD(sc, dev_info.shared_hw_config.config2);
7994
7995         sc->link_params.hw_led_mode =
7996             ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
7997              SHARED_HW_CFG_LED_MODE_SHIFT);
7998
7999         /* get the port feature config */
8000         sc->port.config =
8001             SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8002
8003         /* get the link params */
8004         sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8005             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8006             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8007         sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8008             SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8009             & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8010
8011         /* get the lane config */
8012         sc->link_params.lane_config =
8013             SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8014
8015         /* get the link config */
8016         val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8017         sc->port.link_config[ELINK_INT_PHY] = val;
8018         sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8019         sc->port.link_config[ELINK_EXT_PHY1] =
8020             SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8021
8022         /* get the override preemphasis flag and enable it or turn it off */
8023         val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8024         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8025                 sc->link_params.feature_config_flags |=
8026                     ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8027         } else {
8028                 sc->link_params.feature_config_flags &=
8029                     ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8030         }
8031
8032         /* get the initial value of the link params */
8033         sc->link_params.multi_phy_config =
8034             SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8035
8036         /* get external phy info */
8037         sc->port.ext_phy_config =
8038             SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8039
8040         /* get the multifunction configuration */
8041         bnx2x_get_mf_cfg_info(sc);
8042
8043         /* get the mac address */
8044         if (IS_MF(sc)) {
8045                 mac_hi =
8046                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8047                 mac_lo =
8048                     MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8049         } else {
8050                 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8051                 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8052         }
8053
8054         if ((mac_lo == 0) && (mac_hi == 0)) {
8055                 *sc->mac_addr_str = 0;
8056                 PMD_DRV_LOG(NOTICE, "No Ethernet address programmed!");
8057         } else {
8058                 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8059                 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8060                 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8061                 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8062                 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8063                 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8064                 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8065                          "%02x:%02x:%02x:%02x:%02x:%02x",
8066                          sc->link_params.mac_addr[0],
8067                          sc->link_params.mac_addr[1],
8068                          sc->link_params.mac_addr[2],
8069                          sc->link_params.mac_addr[3],
8070                          sc->link_params.mac_addr[4],
8071                          sc->link_params.mac_addr[5]);
8072                 PMD_DRV_LOG(DEBUG, "Ethernet address: %s", sc->mac_addr_str);
8073         }
8074
8075         return 0;
8076 }
8077
8078 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8079 {
8080         uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8081         switch (sc->link_params.phy[phy_idx].media_type) {
8082         case ELINK_ETH_PHY_SFPP_10G_FIBER:
8083         case ELINK_ETH_PHY_SFP_1G_FIBER:
8084         case ELINK_ETH_PHY_XFP_FIBER:
8085         case ELINK_ETH_PHY_KR:
8086         case ELINK_ETH_PHY_CX4:
8087                 PMD_DRV_LOG(INFO, "Found 10GBase-CX4 media.");
8088                 sc->media = IFM_10G_CX4;
8089                 break;
8090         case ELINK_ETH_PHY_DA_TWINAX:
8091                 PMD_DRV_LOG(INFO, "Found 10Gb Twinax media.");
8092                 sc->media = IFM_10G_TWINAX;
8093                 break;
8094         case ELINK_ETH_PHY_BASE_T:
8095                 PMD_DRV_LOG(INFO, "Found 10GBase-T media.");
8096                 sc->media = IFM_10G_T;
8097                 break;
8098         case ELINK_ETH_PHY_NOT_PRESENT:
8099                 PMD_DRV_LOG(INFO, "Media not present.");
8100                 sc->media = 0;
8101                 break;
8102         case ELINK_ETH_PHY_UNSPECIFIED:
8103         default:
8104                 PMD_DRV_LOG(INFO, "Unknown media!");
8105                 sc->media = 0;
8106                 break;
8107         }
8108 }
8109
8110 #define GET_FIELD(value, fname)                     \
8111 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8112 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8113 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8114
8115 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8116 {
8117         int pfid = SC_FUNC(sc);
8118         int igu_sb_id;
8119         uint32_t val;
8120         uint8_t fid, igu_sb_cnt = 0;
8121
8122         sc->igu_base_sb = 0xff;
8123
8124         if (CHIP_INT_MODE_IS_BC(sc)) {
8125                 int vn = SC_VN(sc);
8126                 igu_sb_cnt = sc->igu_sb_cnt;
8127                 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8128                                    FP_SB_MAX_E1x);
8129                 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8130                                   (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8131                 return 0;
8132         }
8133
8134         /* IGU in normal mode - read CAM */
8135         for (igu_sb_id = 0;
8136              igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8137                 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8138                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8139                         continue;
8140                 }
8141                 fid = IGU_FID(val);
8142                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8143                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8144                                 continue;
8145                         }
8146                         if (IGU_VEC(val) == 0) {
8147                                 /* default status block */
8148                                 sc->igu_dsb_id = igu_sb_id;
8149                         } else {
8150                                 if (sc->igu_base_sb == 0xff) {
8151                                         sc->igu_base_sb = igu_sb_id;
8152                                 }
8153                                 igu_sb_cnt++;
8154                         }
8155                 }
8156         }
8157
8158         /*
8159          * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8160          * that number of CAM entries will not be equal to the value advertised in
8161          * PCI. Driver should use the minimal value of both as the actual status
8162          * block count
8163          */
8164         sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8165
8166         if (igu_sb_cnt == 0) {
8167                 PMD_DRV_LOG(ERR, "CAM configuration error");
8168                 return -1;
8169         }
8170
8171         return 0;
8172 }
8173
8174 /*
8175 * Gather various information from the device config space, the device itself,
8176 * shmem, and the user input.
8177 */
8178 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8179 {
8180         uint32_t val;
8181         int rc;
8182
8183         /* get the chip revision (chip metal comes from pci config space) */
8184         sc->devinfo.chip_id = sc->link_params.chip_id =
8185             (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8186              ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8187              (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8188              ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8189
8190         /* force 57811 according to MISC register */
8191         if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8192                 if (CHIP_IS_57810(sc)) {
8193                         sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8194                                                (sc->
8195                                                 devinfo.chip_id & 0x0000ffff));
8196                 } else if (CHIP_IS_57810_MF(sc)) {
8197                         sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8198                                                (sc->
8199                                                 devinfo.chip_id & 0x0000ffff));
8200                 }
8201                 sc->devinfo.chip_id |= 0x1;
8202         }
8203
8204         PMD_DRV_LOG(DEBUG,
8205                     "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8206                     sc->devinfo.chip_id,
8207                     ((sc->devinfo.chip_id >> 16) & 0xffff),
8208                     ((sc->devinfo.chip_id >> 12) & 0xf),
8209                     ((sc->devinfo.chip_id >> 4) & 0xff),
8210                     ((sc->devinfo.chip_id >> 0) & 0xf));
8211
8212         val = (REG_RD(sc, 0x2874) & 0x55);
8213         if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8214                 sc->flags |= BNX2X_ONE_PORT_FLAG;
8215                 PMD_DRV_LOG(DEBUG, "single port device");
8216         }
8217
8218         /* set the doorbell size */
8219         sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8220
8221         /* determine whether the device is in 2 port or 4 port mode */
8222         sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;       /* E1h */
8223         if (CHIP_IS_E2E3(sc)) {
8224 /*
8225  * Read port4mode_en_ovwr[0]:
8226  *   If 1, four port mode is in port4mode_en_ovwr[1].
8227  *   If 0, four port mode is in port4mode_en[0].
8228  */
8229                 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8230                 if (val & 1) {
8231                         val = ((val >> 1) & 1);
8232                 } else {
8233                         val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8234                 }
8235
8236                 sc->devinfo.chip_port_mode =
8237                     (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8238
8239                 PMD_DRV_LOG(DEBUG, "Port mode = %s", (val) ? "4" : "2");
8240         }
8241
8242         /* get the function and path info for the device */
8243         bnx2x_get_function_num(sc);
8244
8245         /* get the shared memory base address */
8246         sc->devinfo.shmem_base =
8247             sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8248         sc->devinfo.shmem2_base =
8249             REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8250                         MISC_REG_GENERIC_CR_0));
8251
8252         if (!sc->devinfo.shmem_base) {
8253 /* this should ONLY prevent upcoming shmem reads */
8254                 PMD_DRV_LOG(INFO, "MCP not active");
8255                 sc->flags |= BNX2X_NO_MCP_FLAG;
8256                 return 0;
8257         }
8258
8259         /* make sure the shared memory contents are valid */
8260         val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8261         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8262             (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8263                 PMD_DRV_LOG(NOTICE, "Invalid SHMEM validity signature: 0x%08x",
8264                             val);
8265                 return 0;
8266         }
8267
8268         /* get the bootcode version */
8269         sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8270         snprintf(sc->devinfo.bc_ver_str,
8271                  sizeof(sc->devinfo.bc_ver_str),
8272                  "%d.%d.%d",
8273                  ((sc->devinfo.bc_ver >> 24) & 0xff),
8274                  ((sc->devinfo.bc_ver >> 16) & 0xff),
8275                  ((sc->devinfo.bc_ver >> 8) & 0xff));
8276         PMD_DRV_LOG(INFO, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8277
8278         /* get the bootcode shmem address */
8279         sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8280
8281         /* clean indirect addresses as they're not used */
8282         pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8283         if (IS_PF(sc)) {
8284                 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8285                 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8286                 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8287                 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8288                 if (CHIP_IS_E1x(sc)) {
8289                         REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8290                         REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8291                         REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8292                         REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8293                 }
8294         }
8295
8296         /* get the nvram size */
8297         val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8298         sc->devinfo.flash_size =
8299             (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8300
8301         bnx2x_set_power_state(sc, PCI_PM_D0);
8302         /* get various configuration parameters from shmem */
8303         bnx2x_get_shmem_info(sc);
8304
8305         /* initialize IGU parameters */
8306         if (CHIP_IS_E1x(sc)) {
8307                 sc->devinfo.int_block = INT_BLOCK_HC;
8308                 sc->igu_dsb_id = DEF_SB_IGU_ID;
8309                 sc->igu_base_sb = 0;
8310         } else {
8311                 sc->devinfo.int_block = INT_BLOCK_IGU;
8312
8313 /* do not allow device reset during IGU info preocessing */
8314                 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8315
8316                 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8317
8318                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8319                         int tout = 5000;
8320
8321                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8322                         REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8323                         REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8324
8325                         while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8326                                 tout--;
8327                                 DELAY(1000);
8328                         }
8329
8330                         if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8331                                 PMD_DRV_LOG(NOTICE,
8332                                             "FORCING IGU Normal Mode failed!!!");
8333                                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8334                                 return -1;
8335                         }
8336                 }
8337
8338                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8339                         PMD_DRV_LOG(DEBUG, "IGU Backward Compatible Mode");
8340                         sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8341                 } else {
8342                         PMD_DRV_LOG(DEBUG, "IGU Normal Mode");
8343                 }
8344
8345                 rc = bnx2x_get_igu_cam_info(sc);
8346
8347                 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8348
8349                 if (rc) {
8350                         return rc;
8351                 }
8352         }
8353
8354         /*
8355          * Get base FW non-default (fast path) status block ID. This value is
8356          * used to initialize the fw_sb_id saved on the fp/queue structure to
8357          * determine the id used by the FW.
8358          */
8359         if (CHIP_IS_E1x(sc)) {
8360                 sc->base_fw_ndsb =
8361                     ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8362         } else {
8363 /*
8364  * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8365  * the same queue are indicated on the same IGU SB). So we prefer
8366  * FW and IGU SBs to be the same value.
8367  */
8368                 sc->base_fw_ndsb = sc->igu_base_sb;
8369         }
8370
8371         elink_phy_probe(&sc->link_params);
8372
8373         return 0;
8374 }
8375
8376 static void
8377 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8378 {
8379         uint32_t cfg_size = 0;
8380         uint32_t idx;
8381         uint8_t port = SC_PORT(sc);
8382
8383         /* aggregation of supported attributes of all external phys */
8384         sc->port.supported[0] = 0;
8385         sc->port.supported[1] = 0;
8386
8387         switch (sc->link_params.num_phys) {
8388         case 1:
8389                 sc->port.supported[0] =
8390                     sc->link_params.phy[ELINK_INT_PHY].supported;
8391                 cfg_size = 1;
8392                 break;
8393         case 2:
8394                 sc->port.supported[0] =
8395                     sc->link_params.phy[ELINK_EXT_PHY1].supported;
8396                 cfg_size = 1;
8397                 break;
8398         case 3:
8399                 if (sc->link_params.multi_phy_config &
8400                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8401                         sc->port.supported[1] =
8402                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8403                         sc->port.supported[0] =
8404                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8405                 } else {
8406                         sc->port.supported[0] =
8407                             sc->link_params.phy[ELINK_EXT_PHY1].supported;
8408                         sc->port.supported[1] =
8409                             sc->link_params.phy[ELINK_EXT_PHY2].supported;
8410                 }
8411                 cfg_size = 2;
8412                 break;
8413         }
8414
8415         if (!(sc->port.supported[0] || sc->port.supported[1])) {
8416                 PMD_DRV_LOG(ERR,
8417                             "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8418                             SHMEM_RD(sc,
8419                                      dev_info.port_hw_config
8420                                      [port].external_phy_config),
8421                             SHMEM_RD(sc,
8422                                      dev_info.port_hw_config
8423                                      [port].external_phy_config2));
8424                 return;
8425         }
8426
8427         if (CHIP_IS_E3(sc))
8428                 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8429         else {
8430                 switch (switch_cfg) {
8431                 case ELINK_SWITCH_CFG_1G:
8432                         sc->port.phy_addr =
8433                             REG_RD(sc,
8434                                    NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8435                         break;
8436                 case ELINK_SWITCH_CFG_10G:
8437                         sc->port.phy_addr =
8438                             REG_RD(sc,
8439                                    NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8440                         break;
8441                 default:
8442                         PMD_DRV_LOG(ERR,
8443                                     "Invalid switch config in"
8444                                     "link_config=0x%08x",
8445                                     sc->port.link_config[0]);
8446                         return;
8447                 }
8448         }
8449
8450         PMD_DRV_LOG(INFO, "PHY addr 0x%08x", sc->port.phy_addr);
8451
8452         /* mask what we support according to speed_cap_mask per configuration */
8453         for (idx = 0; idx < cfg_size; idx++) {
8454                 if (!(sc->link_params.speed_cap_mask[idx] &
8455                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8456                         sc->port.supported[idx] &=
8457                             ~ELINK_SUPPORTED_10baseT_Half;
8458                 }
8459
8460                 if (!(sc->link_params.speed_cap_mask[idx] &
8461                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8462                         sc->port.supported[idx] &=
8463                             ~ELINK_SUPPORTED_10baseT_Full;
8464                 }
8465
8466                 if (!(sc->link_params.speed_cap_mask[idx] &
8467                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8468                         sc->port.supported[idx] &=
8469                             ~ELINK_SUPPORTED_100baseT_Half;
8470                 }
8471
8472                 if (!(sc->link_params.speed_cap_mask[idx] &
8473                       PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8474                         sc->port.supported[idx] &=
8475                             ~ELINK_SUPPORTED_100baseT_Full;
8476                 }
8477
8478                 if (!(sc->link_params.speed_cap_mask[idx] &
8479                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8480                         sc->port.supported[idx] &=
8481                             ~ELINK_SUPPORTED_1000baseT_Full;
8482                 }
8483
8484                 if (!(sc->link_params.speed_cap_mask[idx] &
8485                       PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8486                         sc->port.supported[idx] &=
8487                             ~ELINK_SUPPORTED_2500baseX_Full;
8488                 }
8489
8490                 if (!(sc->link_params.speed_cap_mask[idx] &
8491                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8492                         sc->port.supported[idx] &=
8493                             ~ELINK_SUPPORTED_10000baseT_Full;
8494                 }
8495
8496                 if (!(sc->link_params.speed_cap_mask[idx] &
8497                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8498                         sc->port.supported[idx] &=
8499                             ~ELINK_SUPPORTED_20000baseKR2_Full;
8500                 }
8501         }
8502
8503         PMD_DRV_LOG(INFO, "PHY supported 0=0x%08x 1=0x%08x",
8504                     sc->port.supported[0], sc->port.supported[1]);
8505 }
8506
8507 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8508 {
8509         uint32_t link_config;
8510         uint32_t idx;
8511         uint32_t cfg_size = 0;
8512
8513         sc->port.advertising[0] = 0;
8514         sc->port.advertising[1] = 0;
8515
8516         switch (sc->link_params.num_phys) {
8517         case 1:
8518         case 2:
8519                 cfg_size = 1;
8520                 break;
8521         case 3:
8522                 cfg_size = 2;
8523                 break;
8524         }
8525
8526         for (idx = 0; idx < cfg_size; idx++) {
8527                 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8528                 link_config = sc->port.link_config[idx];
8529
8530                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8531                 case PORT_FEATURE_LINK_SPEED_AUTO:
8532                         if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8533                                 sc->link_params.req_line_speed[idx] =
8534                                     ELINK_SPEED_AUTO_NEG;
8535                                 sc->port.advertising[idx] |=
8536                                     sc->port.supported[idx];
8537                                 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8538                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8539                                         sc->port.advertising[idx] |=
8540                                             (ELINK_SUPPORTED_100baseT_Half |
8541                                              ELINK_SUPPORTED_100baseT_Full);
8542                         } else {
8543                                 /* force 10G, no AN */
8544                                 sc->link_params.req_line_speed[idx] =
8545                                     ELINK_SPEED_10000;
8546                                 sc->port.advertising[idx] |=
8547                                     (ADVERTISED_10000baseT_Full |
8548                                      ADVERTISED_FIBRE);
8549                                 continue;
8550                         }
8551                         break;
8552
8553                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8554                         if (sc->
8555                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8556                         {
8557                                 sc->link_params.req_line_speed[idx] =
8558                                     ELINK_SPEED_10;
8559                                 sc->port.advertising[idx] |=
8560                                     (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8561                         } else {
8562                                 PMD_DRV_LOG(ERR,
8563                                             "Invalid NVRAM config link_config=0x%08x "
8564                                             "speed_cap_mask=0x%08x",
8565                                             link_config,
8566                                             sc->
8567                                             link_params.speed_cap_mask[idx]);
8568                                 return;
8569                         }
8570                         break;
8571
8572                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8573                         if (sc->
8574                             port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8575                         {
8576                                 sc->link_params.req_line_speed[idx] =
8577                                     ELINK_SPEED_10;
8578                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8579                                 sc->port.advertising[idx] |=
8580                                     (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8581                         } else {
8582                                 PMD_DRV_LOG(ERR,
8583                                             "Invalid NVRAM config link_config=0x%08x "
8584                                             "speed_cap_mask=0x%08x",
8585                                             link_config,
8586                                             sc->
8587                                             link_params.speed_cap_mask[idx]);
8588                                 return;
8589                         }
8590                         break;
8591
8592                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8593                         if (sc->
8594                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8595                         {
8596                                 sc->link_params.req_line_speed[idx] =
8597                                     ELINK_SPEED_100;
8598                                 sc->port.advertising[idx] |=
8599                                     (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8600                         } else {
8601                                 PMD_DRV_LOG(ERR,
8602                                             "Invalid NVRAM config link_config=0x%08x "
8603                                             "speed_cap_mask=0x%08x",
8604                                             link_config,
8605                                             sc->
8606                                             link_params.speed_cap_mask[idx]);
8607                                 return;
8608                         }
8609                         break;
8610
8611                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8612                         if (sc->
8613                             port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8614                         {
8615                                 sc->link_params.req_line_speed[idx] =
8616                                     ELINK_SPEED_100;
8617                                 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8618                                 sc->port.advertising[idx] |=
8619                                     (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8620                         } else {
8621                                 PMD_DRV_LOG(ERR,
8622                                             "Invalid NVRAM config link_config=0x%08x "
8623                                             "speed_cap_mask=0x%08x",
8624                                             link_config,
8625                                             sc->
8626                                             link_params.speed_cap_mask[idx]);
8627                                 return;
8628                         }
8629                         break;
8630
8631                 case PORT_FEATURE_LINK_SPEED_1G:
8632                         if (sc->port.supported[idx] &
8633                             ELINK_SUPPORTED_1000baseT_Full) {
8634                                 sc->link_params.req_line_speed[idx] =
8635                                     ELINK_SPEED_1000;
8636                                 sc->port.advertising[idx] |=
8637                                     (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8638                         } else {
8639                                 PMD_DRV_LOG(ERR,
8640                                             "Invalid NVRAM config link_config=0x%08x "
8641                                             "speed_cap_mask=0x%08x",
8642                                             link_config,
8643                                             sc->
8644                                             link_params.speed_cap_mask[idx]);
8645                                 return;
8646                         }
8647                         break;
8648
8649                 case PORT_FEATURE_LINK_SPEED_2_5G:
8650                         if (sc->port.supported[idx] &
8651                             ELINK_SUPPORTED_2500baseX_Full) {
8652                                 sc->link_params.req_line_speed[idx] =
8653                                     ELINK_SPEED_2500;
8654                                 sc->port.advertising[idx] |=
8655                                     (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8656                         } else {
8657                                 PMD_DRV_LOG(ERR,
8658                                             "Invalid NVRAM config link_config=0x%08x "
8659                                             "speed_cap_mask=0x%08x",
8660                                             link_config,
8661                                             sc->
8662                                             link_params.speed_cap_mask[idx]);
8663                                 return;
8664                         }
8665                         break;
8666
8667                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8668                         if (sc->port.supported[idx] &
8669                             ELINK_SUPPORTED_10000baseT_Full) {
8670                                 sc->link_params.req_line_speed[idx] =
8671                                     ELINK_SPEED_10000;
8672                                 sc->port.advertising[idx] |=
8673                                     (ADVERTISED_10000baseT_Full |
8674                                      ADVERTISED_FIBRE);
8675                         } else {
8676                                 PMD_DRV_LOG(ERR,
8677                                             "Invalid NVRAM config link_config=0x%08x "
8678                                             "speed_cap_mask=0x%08x",
8679                                             link_config,
8680                                             sc->
8681                                             link_params.speed_cap_mask[idx]);
8682                                 return;
8683                         }
8684                         break;
8685
8686                 case PORT_FEATURE_LINK_SPEED_20G:
8687                         sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8688                         break;
8689
8690                 default:
8691                         PMD_DRV_LOG(ERR,
8692                                     "Invalid NVRAM config link_config=0x%08x "
8693                                     "speed_cap_mask=0x%08x", link_config,
8694                                     sc->link_params.speed_cap_mask[idx]);
8695                         sc->link_params.req_line_speed[idx] =
8696                             ELINK_SPEED_AUTO_NEG;
8697                         sc->port.advertising[idx] = sc->port.supported[idx];
8698                         break;
8699                 }
8700
8701                 sc->link_params.req_flow_ctrl[idx] =
8702                     (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8703
8704                 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8705                         if (!
8706                             (sc->
8707                              port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8708                                 sc->link_params.req_flow_ctrl[idx] =
8709                                     ELINK_FLOW_CTRL_NONE;
8710                         } else {
8711                                 bnx2x_set_requested_fc(sc);
8712                         }
8713                 }
8714         }
8715 }
8716
8717 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8718 {
8719         uint8_t port = SC_PORT(sc);
8720         uint32_t eee_mode;
8721
8722         PMD_INIT_FUNC_TRACE();
8723
8724         /* shmem data already read in bnx2x_get_shmem_info() */
8725
8726         bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8727         bnx2x_link_settings_requested(sc);
8728
8729         /* configure link feature according to nvram value */
8730         eee_mode =
8731             (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8732               & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8733              PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8734         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8735                 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8736                                             ELINK_EEE_MODE_ENABLE_LPI |
8737                                             ELINK_EEE_MODE_OUTPUT_TIME);
8738         } else {
8739                 sc->link_params.eee_mode = 0;
8740         }
8741
8742         /* get the media type */
8743         bnx2x_media_detect(sc);
8744 }
8745
8746 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8747 {
8748         uint32_t flags = MODE_ASIC | MODE_PORT2;
8749
8750         if (CHIP_IS_E2(sc)) {
8751                 flags |= MODE_E2;
8752         } else if (CHIP_IS_E3(sc)) {
8753                 flags |= MODE_E3;
8754                 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8755                         flags |= MODE_E3_A0;
8756                 } else {        /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8757
8758                         flags |= MODE_E3_B0 | MODE_COS3;
8759                 }
8760         }
8761
8762         if (IS_MF(sc)) {
8763                 flags |= MODE_MF;
8764                 switch (sc->devinfo.mf_info.mf_mode) {
8765                 case MULTI_FUNCTION_SD:
8766                         flags |= MODE_MF_SD;
8767                         break;
8768                 case MULTI_FUNCTION_SI:
8769                         flags |= MODE_MF_SI;
8770                         break;
8771                 case MULTI_FUNCTION_AFEX:
8772                         flags |= MODE_MF_AFEX;
8773                         break;
8774                 }
8775         } else {
8776                 flags |= MODE_SF;
8777         }
8778
8779 #if defined(__LITTLE_ENDIAN)
8780         flags |= MODE_LITTLE_ENDIAN;
8781 #else /* __BIG_ENDIAN */
8782         flags |= MODE_BIG_ENDIAN;
8783 #endif
8784
8785         INIT_MODE_FLAGS(sc) = flags;
8786 }
8787
8788 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8789 {
8790         struct bnx2x_fastpath *fp;
8791         char buf[32];
8792         uint32_t i;
8793
8794         if (IS_PF(sc)) {
8795 /************************/
8796 /* DEFAULT STATUS BLOCK */
8797 /************************/
8798
8799                 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8800                                   &sc->def_sb_dma, "def_sb",
8801                                   RTE_CACHE_LINE_SIZE) != 0) {
8802                         return -1;
8803                 }
8804
8805                 sc->def_sb =
8806                     (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8807 /***************/
8808 /* EVENT QUEUE */
8809 /***************/
8810
8811                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8812                                   &sc->eq_dma, "ev_queue",
8813                                   RTE_CACHE_LINE_SIZE) != 0) {
8814                         sc->def_sb = NULL;
8815                         return -1;
8816                 }
8817
8818                 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8819
8820 /*************/
8821 /* SLOW PATH */
8822 /*************/
8823
8824                 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8825                                   &sc->sp_dma, "sp",
8826                                   RTE_CACHE_LINE_SIZE) != 0) {
8827                         sc->eq = NULL;
8828                         sc->def_sb = NULL;
8829                         return -1;
8830                 }
8831
8832                 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8833
8834 /*******************/
8835 /* SLOW PATH QUEUE */
8836 /*******************/
8837
8838                 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8839                                   &sc->spq_dma, "sp_queue",
8840                                   RTE_CACHE_LINE_SIZE) != 0) {
8841                         sc->sp = NULL;
8842                         sc->eq = NULL;
8843                         sc->def_sb = NULL;
8844                         return -1;
8845                 }
8846
8847                 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8848
8849 /***************************/
8850 /* FW DECOMPRESSION BUFFER */
8851 /***************************/
8852
8853                 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8854                                   "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8855                         sc->spq = NULL;
8856                         sc->sp = NULL;
8857                         sc->eq = NULL;
8858                         sc->def_sb = NULL;
8859                         return -1;
8860                 }
8861
8862                 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8863         }
8864
8865         /*************/
8866         /* FASTPATHS */
8867         /*************/
8868
8869         /* allocate DMA memory for each fastpath structure */
8870         for (i = 0; i < sc->num_queues; i++) {
8871                 fp = &sc->fp[i];
8872                 fp->sc = sc;
8873                 fp->index = i;
8874
8875 /*******************/
8876 /* FP STATUS BLOCK */
8877 /*******************/
8878
8879                 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8880                 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8881                                   &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8882                         PMD_DRV_LOG(NOTICE, "Failed to alloc %s", buf);
8883                         return -1;
8884                 } else {
8885                         if (CHIP_IS_E2E3(sc)) {
8886                                 fp->status_block.e2_sb =
8887                                     (struct host_hc_status_block_e2 *)
8888                                     fp->sb_dma.vaddr;
8889                         } else {
8890                                 fp->status_block.e1x_sb =
8891                                     (struct host_hc_status_block_e1x *)
8892                                     fp->sb_dma.vaddr;
8893                         }
8894                 }
8895         }
8896
8897         return 0;
8898 }
8899
8900 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8901 {
8902         struct bnx2x_fastpath *fp;
8903         int i;
8904
8905         for (i = 0; i < sc->num_queues; i++) {
8906                 fp = &sc->fp[i];
8907
8908 /*******************/
8909 /* FP STATUS BLOCK */
8910 /*******************/
8911
8912                 memset(&fp->status_block, 0, sizeof(fp->status_block));
8913         }
8914
8915         /***************************/
8916         /* FW DECOMPRESSION BUFFER */
8917         /***************************/
8918
8919         sc->gz_buf = NULL;
8920
8921         /*******************/
8922         /* SLOW PATH QUEUE */
8923         /*******************/
8924
8925         sc->spq = NULL;
8926
8927         /*************/
8928         /* SLOW PATH */
8929         /*************/
8930
8931         sc->sp = NULL;
8932
8933         /***************/
8934         /* EVENT QUEUE */
8935         /***************/
8936
8937         sc->eq = NULL;
8938
8939         /************************/
8940         /* DEFAULT STATUS BLOCK */
8941         /************************/
8942
8943         sc->def_sb = NULL;
8944
8945 }
8946
8947 /*
8948 * Previous driver DMAE transaction may have occurred when pre-boot stage
8949 * ended and boot began. This would invalidate the addresses of the
8950 * transaction, resulting in was-error bit set in the PCI causing all
8951 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
8952 * the interrupt which detected this from the pglueb and the was-done bit
8953 */
8954 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
8955 {
8956         uint32_t val;
8957
8958         if (!CHIP_IS_E1x(sc)) {
8959                 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
8960                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
8961                         REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
8962                                1 << SC_FUNC(sc));
8963                 }
8964         }
8965 }
8966
8967 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
8968 {
8969         uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
8970                                      DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
8971         if (!rc) {
8972                 PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
8973                 return -1;
8974         }
8975
8976         return 0;
8977 }
8978
8979 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
8980 {
8981         struct bnx2x_prev_list_node *tmp;
8982
8983         LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
8984                 if ((sc->pcie_bus == tmp->bus) &&
8985                     (sc->pcie_device == tmp->slot) &&
8986                     (SC_PATH(sc) == tmp->path)) {
8987                         return tmp;
8988                 }
8989         }
8990
8991         return NULL;
8992 }
8993
8994 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
8995 {
8996         struct bnx2x_prev_list_node *tmp;
8997         int rc = FALSE;
8998
8999         rte_spinlock_lock(&bnx2x_prev_mtx);
9000
9001         tmp = bnx2x_prev_path_get_entry(sc);
9002         if (tmp) {
9003                 if (tmp->aer) {
9004                         PMD_DRV_LOG(DEBUG,
9005                                     "Path %d/%d/%d was marked by AER",
9006                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9007                 } else {
9008                         rc = TRUE;
9009                         PMD_DRV_LOG(DEBUG,
9010                                     "Path %d/%d/%d was already cleaned from previous drivers",
9011                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9012                 }
9013         }
9014
9015         rte_spinlock_unlock(&bnx2x_prev_mtx);
9016
9017         return rc;
9018 }
9019
9020 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9021 {
9022         struct bnx2x_prev_list_node *tmp;
9023
9024         rte_spinlock_lock(&bnx2x_prev_mtx);
9025
9026         /* Check whether the entry for this path already exists */
9027         tmp = bnx2x_prev_path_get_entry(sc);
9028         if (tmp) {
9029                 if (!tmp->aer) {
9030                         PMD_DRV_LOG(DEBUG,
9031                                     "Re-marking AER in path %d/%d/%d",
9032                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9033                 } else {
9034                         PMD_DRV_LOG(DEBUG,
9035                                     "Removing AER indication from path %d/%d/%d",
9036                                     sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9037                         tmp->aer = 0;
9038                 }
9039
9040                 rte_spinlock_unlock(&bnx2x_prev_mtx);
9041                 return 0;
9042         }
9043
9044         rte_spinlock_unlock(&bnx2x_prev_mtx);
9045
9046         /* Create an entry for this path and add it */
9047         tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9048                          RTE_CACHE_LINE_SIZE);
9049         if (!tmp) {
9050                 PMD_DRV_LOG(NOTICE, "Failed to allocate 'bnx2x_prev_list_node'");
9051                 return -1;
9052         }
9053
9054         tmp->bus = sc->pcie_bus;
9055         tmp->slot = sc->pcie_device;
9056         tmp->path = SC_PATH(sc);
9057         tmp->aer = 0;
9058         tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9059
9060         rte_spinlock_lock(&bnx2x_prev_mtx);
9061
9062         LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9063
9064         rte_spinlock_unlock(&bnx2x_prev_mtx);
9065
9066         return 0;
9067 }
9068
9069 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9070 {
9071         int i;
9072
9073         /* only E2 and onwards support FLR */
9074         if (CHIP_IS_E1x(sc)) {
9075                 PMD_DRV_LOG(WARNING, "FLR not supported in E1H");
9076                 return -1;
9077         }
9078
9079         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9080         if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9081                 PMD_DRV_LOG(WARNING,
9082                             "FLR not supported by BC_VER: 0x%08x",
9083                             sc->devinfo.bc_ver);
9084                 return -1;
9085         }
9086
9087         /* Wait for Transaction Pending bit clean */
9088         for (i = 0; i < 4; i++) {
9089                 if (i) {
9090                         DELAY(((1 << (i - 1)) * 100) * 1000);
9091                 }
9092
9093                 if (!bnx2x_is_pcie_pending(sc)) {
9094                         goto clear;
9095                 }
9096         }
9097
9098         PMD_DRV_LOG(NOTICE, "PCIE transaction is not cleared, "
9099                     "proceeding with reset anyway");
9100
9101 clear:
9102         bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9103
9104         return 0;
9105 }
9106
9107 struct bnx2x_mac_vals {
9108         uint32_t xmac_addr;
9109         uint32_t xmac_val;
9110         uint32_t emac_addr;
9111         uint32_t emac_val;
9112         uint32_t umac_addr;
9113         uint32_t umac_val;
9114         uint32_t bmac_addr;
9115         uint32_t bmac_val[2];
9116 };
9117
9118 static void
9119 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9120 {
9121         uint32_t val, base_addr, offset, mask, reset_reg;
9122         uint8_t mac_stopped = FALSE;
9123         uint8_t port = SC_PORT(sc);
9124         uint32_t wb_data[2];
9125
9126         /* reset addresses as they also mark which values were changed */
9127         vals->bmac_addr = 0;
9128         vals->umac_addr = 0;
9129         vals->xmac_addr = 0;
9130         vals->emac_addr = 0;
9131
9132         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9133
9134         if (!CHIP_IS_E3(sc)) {
9135                 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9136                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9137                 if ((mask & reset_reg) && val) {
9138                         base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9139                             : NIG_REG_INGRESS_BMAC0_MEM;
9140                         offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9141                             : BIGMAC_REGISTER_BMAC_CONTROL;
9142
9143                         /*
9144                          * use rd/wr since we cannot use dmae. This is safe
9145                          * since MCP won't access the bus due to the request
9146                          * to unload, and no function on the path can be
9147                          * loaded at this time.
9148                          */
9149                         wb_data[0] = REG_RD(sc, base_addr + offset);
9150                         wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9151                         vals->bmac_addr = base_addr + offset;
9152                         vals->bmac_val[0] = wb_data[0];
9153                         vals->bmac_val[1] = wb_data[1];
9154                         wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9155                         REG_WR(sc, vals->bmac_addr, wb_data[0]);
9156                         REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9157                 }
9158
9159                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9160                 vals->emac_val = REG_RD(sc, vals->emac_addr);
9161                 REG_WR(sc, vals->emac_addr, 0);
9162                 mac_stopped = TRUE;
9163         } else {
9164                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9165                         base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9166                         val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9167                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9168                                val & ~(1 << 1));
9169                         REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9170                                val | (1 << 1));
9171                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9172                         vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9173                         REG_WR(sc, vals->xmac_addr, 0);
9174                         mac_stopped = TRUE;
9175                 }
9176
9177                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9178                 if (mask & reset_reg) {
9179                         base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9180                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9181                         vals->umac_val = REG_RD(sc, vals->umac_addr);
9182                         REG_WR(sc, vals->umac_addr, 0);
9183                         mac_stopped = TRUE;
9184                 }
9185         }
9186
9187         if (mac_stopped) {
9188                 DELAY(20000);
9189         }
9190 }
9191
9192 #define BNX2X_PREV_UNDI_PROD_ADDR(p)  (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9193 #define BNX2X_PREV_UNDI_RCQ(val)      ((val) & 0xffff)
9194 #define BNX2X_PREV_UNDI_BD(val)       ((val) >> 16 & 0xffff)
9195 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9196
9197 static void
9198 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9199 {
9200         uint16_t rcq, bd;
9201         uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9202
9203         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9204         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9205
9206         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9207         REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9208 }
9209
9210 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9211 {
9212         uint32_t reset_reg, tmp_reg = 0, rc;
9213         uint8_t prev_undi = FALSE;
9214         struct bnx2x_mac_vals mac_vals;
9215         uint32_t timer_count = 1000;
9216         uint32_t prev_brb;
9217
9218         /*
9219          * It is possible a previous function received 'common' answer,
9220          * but hasn't loaded yet, therefore creating a scenario of
9221          * multiple functions receiving 'common' on the same path.
9222          */
9223         memset(&mac_vals, 0, sizeof(mac_vals));
9224
9225         if (bnx2x_prev_is_path_marked(sc)) {
9226                 return bnx2x_prev_mcp_done(sc);
9227         }
9228
9229         reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9230
9231         /* Reset should be performed after BRB is emptied */
9232         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9233                 /* Close the MAC Rx to prevent BRB from filling up */
9234                 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9235
9236                 /* close LLH filters towards the BRB */
9237                 elink_set_rx_filter(&sc->link_params, 0);
9238
9239                 /*
9240                  * Check if the UNDI driver was previously loaded.
9241                  * UNDI driver initializes CID offset for normal bell to 0x7
9242                  */
9243                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9244                         tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9245                         if (tmp_reg == 0x7) {
9246                                 PMD_DRV_LOG(DEBUG, "UNDI previously loaded");
9247                                 prev_undi = TRUE;
9248                                 /* clear the UNDI indication */
9249                                 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9250                                 /* clear possible idle check errors */
9251                                 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9252                         }
9253                 }
9254
9255                 /* wait until BRB is empty */
9256                 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9257                 while (timer_count) {
9258                         prev_brb = tmp_reg;
9259
9260                         tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9261                         if (!tmp_reg) {
9262                                 break;
9263                         }
9264
9265                         PMD_DRV_LOG(DEBUG, "BRB still has 0x%08x", tmp_reg);
9266
9267                         /* reset timer as long as BRB actually gets emptied */
9268                         if (prev_brb > tmp_reg) {
9269                                 timer_count = 1000;
9270                         } else {
9271                                 timer_count--;
9272                         }
9273
9274                         /* If UNDI resides in memory, manually increment it */
9275                         if (prev_undi) {
9276                                 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9277                         }
9278
9279                         DELAY(10);
9280                 }
9281
9282                 if (!timer_count) {
9283                         PMD_DRV_LOG(NOTICE, "Failed to empty BRB");
9284                 }
9285         }
9286
9287         /* No packets are in the pipeline, path is ready for reset */
9288         bnx2x_reset_common(sc);
9289
9290         if (mac_vals.xmac_addr) {
9291                 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9292         }
9293         if (mac_vals.umac_addr) {
9294                 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9295         }
9296         if (mac_vals.emac_addr) {
9297                 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9298         }
9299         if (mac_vals.bmac_addr) {
9300                 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9301                 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9302         }
9303
9304         rc = bnx2x_prev_mark_path(sc, prev_undi);
9305         if (rc) {
9306                 bnx2x_prev_mcp_done(sc);
9307                 return rc;
9308         }
9309
9310         return bnx2x_prev_mcp_done(sc);
9311 }
9312
9313 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9314 {
9315         int rc;
9316
9317         /* Test if previous unload process was already finished for this path */
9318         if (bnx2x_prev_is_path_marked(sc)) {
9319                 return bnx2x_prev_mcp_done(sc);
9320         }
9321
9322         /*
9323          * If function has FLR capabilities, and existing FW version matches
9324          * the one required, then FLR will be sufficient to clean any residue
9325          * left by previous driver
9326          */
9327         rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9328         if (!rc) {
9329                 /* fw version is good */
9330                 rc = bnx2x_do_flr(sc);
9331         }
9332
9333         if (!rc) {
9334                 /* FLR was performed */
9335                 return 0;
9336         }
9337
9338         PMD_DRV_LOG(INFO, "Could not FLR");
9339
9340         /* Close the MCP request, return failure */
9341         rc = bnx2x_prev_mcp_done(sc);
9342         if (!rc) {
9343                 rc = BNX2X_PREV_WAIT_NEEDED;
9344         }
9345
9346         return rc;
9347 }
9348
9349 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9350 {
9351         int time_counter = 10;
9352         uint32_t fw, hw_lock_reg, hw_lock_val;
9353         uint32_t rc = 0;
9354
9355         /*
9356          * Clear HW from errors which may have resulted from an interrupted
9357          * DMAE transaction.
9358          */
9359         bnx2x_prev_interrupted_dmae(sc);
9360
9361         /* Release previously held locks */
9362         if (SC_FUNC(sc) <= 5)
9363                 hw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);
9364         else
9365                 hw_lock_reg =
9366                     (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9367
9368         hw_lock_val = (REG_RD(sc, hw_lock_reg));
9369         if (hw_lock_val) {
9370                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9371                         REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9372                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9373                 }
9374                 REG_WR(sc, hw_lock_reg, 0xffffffff);
9375         }
9376
9377         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9378                 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9379         }
9380
9381         do {
9382                 /* Lock MCP using an unload request */
9383                 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9384                 if (!fw) {
9385                         PMD_DRV_LOG(NOTICE, "MCP response failure, aborting");
9386                         rc = -1;
9387                         break;
9388                 }
9389
9390                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9391                         rc = bnx2x_prev_unload_common(sc);
9392                         break;
9393                 }
9394
9395                 /* non-common reply from MCP might require looping */
9396                 rc = bnx2x_prev_unload_uncommon(sc);
9397                 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9398                         break;
9399                 }
9400
9401                 DELAY(20000);
9402         } while (--time_counter);
9403
9404         if (!time_counter || rc) {
9405                 PMD_DRV_LOG(NOTICE, "Failed to unload previous driver!");
9406                 rc = -1;
9407         }
9408
9409         return rc;
9410 }
9411
9412 static void
9413 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9414 {
9415         if (!CHIP_IS_E1x(sc)) {
9416                 sc->dcb_state = dcb_on;
9417                 sc->dcbx_enabled = dcbx_enabled;
9418         } else {
9419                 sc->dcb_state = FALSE;
9420                 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9421         }
9422         PMD_DRV_LOG(DEBUG,
9423                     "DCB state [%s:%s]",
9424                     dcb_on ? "ON" : "OFF",
9425                     (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9426                     (dcbx_enabled ==
9427                      BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9428                     : (dcbx_enabled ==
9429                        BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9430                     "on-chip with negotiation" : "invalid");
9431 }
9432
9433 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9434 {
9435         int cid_count = BNX2X_L2_MAX_CID(sc);
9436
9437         if (CNIC_SUPPORT(sc)) {
9438                 cid_count += CNIC_CID_MAX;
9439         }
9440
9441         return roundup(cid_count, QM_CID_ROUND);
9442 }
9443
9444 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9445 {
9446         int pri, cos;
9447
9448         uint32_t pri_map = 0;
9449
9450         for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9451                 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9452                 if (cos < sc->max_cos) {
9453                         sc->prio_to_cos[pri] = cos;
9454                 } else {
9455                         PMD_DRV_LOG(WARNING,
9456                                     "Invalid COS %d for priority %d "
9457                                     "(max COS is %d), setting to 0", cos, pri,
9458                                     (sc->max_cos - 1));
9459                         sc->prio_to_cos[pri] = 0;
9460                 }
9461         }
9462 }
9463
9464 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9465 {
9466         struct {
9467                 uint8_t id;
9468                 uint8_t next;
9469         } pci_cap;
9470         uint16_t status;
9471         struct bnx2x_pci_cap *cap;
9472
9473         cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9474                                          RTE_CACHE_LINE_SIZE);
9475         if (!cap) {
9476                 PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9477                 return -ENOMEM;
9478         }
9479
9480 #ifndef __FreeBSD__
9481         pci_read(sc, PCI_STATUS, &status, 2);
9482         if (!(status & PCI_STATUS_CAP_LIST)) {
9483 #else
9484         pci_read(sc, PCIR_STATUS, &status, 2);
9485         if (!(status & PCIM_STATUS_CAPPRESENT)) {
9486 #endif
9487                 PMD_DRV_LOG(NOTICE, "PCIe capability reading failed");
9488                 return -1;
9489         }
9490
9491 #ifndef __FreeBSD__
9492         pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9493 #else
9494         pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9495 #endif
9496         while (pci_cap.next) {
9497                 cap->addr = pci_cap.next & ~3;
9498                 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9499                 if (pci_cap.id == 0xff)
9500                         break;
9501                 cap->id = pci_cap.id;
9502                 cap->type = BNX2X_PCI_CAP;
9503                 cap->next = rte_zmalloc("pci_cap",
9504                                         sizeof(struct bnx2x_pci_cap),
9505                                         RTE_CACHE_LINE_SIZE);
9506                 if (!cap->next) {
9507                         PMD_DRV_LOG(NOTICE, "Failed to allocate memory");
9508                         return -ENOMEM;
9509                 }
9510                 cap = cap->next;
9511         }
9512
9513         return 0;
9514 }
9515
9516 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9517 {
9518         if (IS_VF(sc)) {
9519                 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9520                                         sc->igu_sb_cnt);
9521                 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9522                                         sc->igu_sb_cnt);
9523         } else {
9524                 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9525                 sc->max_tx_queues = sc->max_rx_queues;
9526         }
9527 }
9528
9529 #define FW_HEADER_LEN 104
9530 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9531 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9532
9533 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9534 {
9535         const char *fwname;
9536         int f;
9537         struct stat st;
9538
9539         fwname = sc->devinfo.device_id == CHIP_NUM_57711
9540                 ? FW_NAME_57711 : FW_NAME_57810;
9541         f = open(fwname, O_RDONLY);
9542         if (f < 0) {
9543                 PMD_DRV_LOG(NOTICE, "Can't open firmware file");
9544                 return;
9545         }
9546
9547         if (fstat(f, &st) < 0) {
9548                 PMD_DRV_LOG(NOTICE, "Can't stat firmware file");
9549                 close(f);
9550                 return;
9551         }
9552
9553         sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9554         if (!sc->firmware) {
9555                 PMD_DRV_LOG(NOTICE, "Can't allocate memory for firmware");
9556                 close(f);
9557                 return;
9558         }
9559
9560         if (read(f, sc->firmware, st.st_size) != st.st_size) {
9561                 PMD_DRV_LOG(NOTICE, "Can't read firmware data");
9562                 close(f);
9563                 return;
9564         }
9565         close(f);
9566
9567         sc->fw_len = st.st_size;
9568         if (sc->fw_len < FW_HEADER_LEN) {
9569                 PMD_DRV_LOG(NOTICE, "Invalid fw size: %" PRIu64, sc->fw_len);
9570                 return;
9571         }
9572         PMD_DRV_LOG(DEBUG, "fw_len = %" PRIu64, sc->fw_len);
9573 }
9574
9575 static void
9576 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9577 {
9578         uint32_t *src = (uint32_t *) data;
9579         uint32_t i, j, tmp;
9580
9581         for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9582                 tmp = rte_be_to_cpu_32(src[j]);
9583                 dst[i].op = (tmp >> 24) & 0xFF;
9584                 dst[i].offset = tmp & 0xFFFFFF;
9585                 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9586         }
9587 }
9588
9589 static void
9590 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9591 {
9592         uint16_t *src = (uint16_t *) data;
9593         uint32_t i;
9594
9595         for (i = 0; i < len / 2; ++i)
9596                 dst[i] = rte_be_to_cpu_16(src[i]);
9597 }
9598
9599 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9600 {
9601         uint32_t *src = (uint32_t *) data;
9602         uint32_t i;
9603
9604         for (i = 0; i < len / 4; ++i)
9605                 dst[i] = rte_be_to_cpu_32(src[i]);
9606 }
9607
9608 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9609 {
9610         uint32_t *src = (uint32_t *) data;
9611         uint32_t i, j, tmp;
9612
9613         for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9614                 dst[i].base = rte_be_to_cpu_32(src[j++]);
9615                 tmp = rte_be_to_cpu_32(src[j]);
9616                 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9617                 dst[i].m2 = tmp & 0xFFFF;
9618                 ++j;
9619                 tmp = rte_be_to_cpu_32(src[j]);
9620                 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9621                 dst[i].size = tmp & 0xFFFF;
9622         }
9623 }
9624
9625 /*
9626 * Device attach function.
9627 *
9628 * Allocates device resources, performs secondary chip identification, and
9629 * initializes driver instance variables. This function is called from driver
9630 * load after a successful probe.
9631 *
9632 * Returns:
9633 *   0 = Success, >0 = Failure
9634 */
9635 int bnx2x_attach(struct bnx2x_softc *sc)
9636 {
9637         int rc;
9638
9639         PMD_DRV_LOG(DEBUG, "Starting attach...");
9640
9641         rc = bnx2x_pci_get_caps(sc);
9642         if (rc) {
9643                 PMD_DRV_LOG(NOTICE, "PCIe caps reading was failed");
9644                 return rc;
9645         }
9646
9647         sc->state = BNX2X_STATE_CLOSED;
9648
9649         pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9650
9651         sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9652
9653         /* get PCI capabilites */
9654         bnx2x_probe_pci_caps(sc);
9655
9656         if (sc->devinfo.pcie_msix_cap_reg != 0) {
9657                 uint32_t val;
9658                 pci_read(sc,
9659                          (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9660                          2);
9661                 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9662         } else {
9663                 sc->igu_sb_cnt = 1;
9664         }
9665
9666         /* Init RTE stuff */
9667         bnx2x_init_rte(sc);
9668
9669         if (IS_PF(sc)) {
9670                 /* Enable internal target-read (in case we are probed after PF
9671                  * FLR). Must be done prior to any BAR read access. Only for
9672                  * 57712 and up
9673                  */
9674                 if (!CHIP_IS_E1x(sc)) {
9675                         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9676                                1);
9677                         DELAY(200000);
9678                 }
9679
9680                 /* get device info and set params */
9681                 if (bnx2x_get_device_info(sc) != 0) {
9682                         PMD_DRV_LOG(NOTICE, "getting device info");
9683                         return -ENXIO;
9684                 }
9685
9686 /* get phy settings from shmem and 'and' against admin settings */
9687                 bnx2x_get_phy_info(sc);
9688         } else {
9689                 /* Left mac of VF unfilled, PF should set it for VF */
9690                 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9691         }
9692
9693         sc->wol = 0;
9694
9695         /* set the default MTU (changed via ifconfig) */
9696         sc->mtu = ETHER_MTU;
9697
9698         bnx2x_set_modes_bitmap(sc);
9699
9700         /* need to reset chip if UNDI was active */
9701         if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9702 /* init fw_seq */
9703                 sc->fw_seq =
9704                     (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9705                      DRV_MSG_SEQ_NUMBER_MASK);
9706                 bnx2x_prev_unload(sc);
9707         }
9708
9709         bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9710
9711         /* calculate qm_cid_count */
9712         sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9713
9714         sc->max_cos = 1;
9715         bnx2x_init_multi_cos(sc);
9716
9717         return 0;
9718 }
9719
9720 static void
9721 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9722                uint16_t index, uint8_t op, uint8_t update)
9723 {
9724         uint32_t igu_addr = sc->igu_base_addr;
9725         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9726         bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9727 }
9728
9729 static void
9730 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9731            uint16_t index, uint8_t op, uint8_t update)
9732 {
9733         if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9734                 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9735         else {
9736                 uint8_t segment;
9737                 if (CHIP_INT_MODE_IS_BC(sc)) {
9738                         segment = storm;
9739                 } else if (igu_sb_id != sc->igu_dsb_id) {
9740                         segment = IGU_SEG_ACCESS_DEF;
9741                 } else if (storm == ATTENTION_ID) {
9742                         segment = IGU_SEG_ACCESS_ATTN;
9743                 } else {
9744                         segment = IGU_SEG_ACCESS_DEF;
9745                 }
9746                 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9747         }
9748 }
9749
9750 static void
9751 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9752                      uint8_t is_pf)
9753 {
9754         uint32_t data, ctl, cnt = 100;
9755         uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9756         uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9757         uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9758             (idu_sb_id / 32) * 4;
9759         uint32_t sb_bit = 1 << (idu_sb_id % 32);
9760         uint32_t func_encode = func |
9761             (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9762         uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9763
9764         /* Not supported in BC mode */
9765         if (CHIP_INT_MODE_IS_BC(sc)) {
9766                 return;
9767         }
9768
9769         data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9770                  IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9771                 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9772
9773         ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9774                (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9775                (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9776
9777         REG_WR(sc, igu_addr_data, data);
9778
9779         mb();
9780
9781         PMD_DRV_LOG(DEBUG, "write 0x%08x to IGU(via GRC) addr 0x%x",
9782                     ctl, igu_addr_ctl);
9783         REG_WR(sc, igu_addr_ctl, ctl);
9784
9785         mb();
9786
9787         /* wait for clean up to finish */
9788         while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9789                 DELAY(20000);
9790         }
9791
9792         if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9793                 PMD_DRV_LOG(DEBUG,
9794                             "Unable to finish IGU cleanup: "
9795                             "idu_sb_id %d offset %d bit %d (cnt %d)",
9796                             idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9797         }
9798 }
9799
9800 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9801 {
9802         bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9803 }
9804
9805 /*******************/
9806 /* ECORE CALLBACKS */
9807 /*******************/
9808
9809 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9810 {
9811         uint32_t val = 0x1400;
9812
9813         PMD_INIT_FUNC_TRACE();
9814
9815         /* reset_common */
9816         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9817                0xd3ffff7f);
9818
9819         if (CHIP_IS_E3(sc)) {
9820                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9821                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9822         }
9823
9824         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9825 }
9826
9827 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9828 {
9829         uint32_t shmem_base[2];
9830         uint32_t shmem2_base[2];
9831
9832         /* Avoid common init in case MFW supports LFA */
9833         if (SHMEM2_RD(sc, size) >
9834             (uint32_t) offsetof(struct shmem2_region,
9835                                 lfa_host_addr[SC_PORT(sc)])) {
9836                 return;
9837         }
9838
9839         shmem_base[0] = sc->devinfo.shmem_base;
9840         shmem2_base[0] = sc->devinfo.shmem2_base;
9841
9842         if (!CHIP_IS_E1x(sc)) {
9843                 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9844                 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9845         }
9846
9847         elink_common_init_phy(sc, shmem_base, shmem2_base,
9848                               sc->devinfo.chip_id, 0);
9849 }
9850
9851 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9852 {
9853         uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9854
9855         val &= ~IGU_PF_CONF_FUNC_EN;
9856
9857         REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9858         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9859         REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9860 }
9861
9862 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9863 {
9864         uint16_t devctl;
9865         int r_order, w_order;
9866
9867         devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9868
9869         w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9870         r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9871
9872         ecore_init_pxp_arb(sc, r_order, w_order);
9873 }
9874
9875 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9876 {
9877         uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9878         uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9879         return base + (SC_ABS_FUNC(sc)) * stride;
9880 }
9881
9882 /*
9883  * Called only on E1H or E2.
9884  * When pretending to be PF, the pretend value is the function number 0..7.
9885  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9886  * combination.
9887  */
9888 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9889 {
9890         uint32_t pretend_reg;
9891
9892         if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9893                 return -1;
9894
9895         /* get my own pretend register */
9896         pretend_reg = bnx2x_get_pretend_reg(sc);
9897         REG_WR(sc, pretend_reg, pretend_func_val);
9898         REG_RD(sc, pretend_reg);
9899         return 0;
9900 }
9901
9902 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9903 {
9904         int is_required;
9905         uint32_t val;
9906         int port;
9907
9908         is_required = 0;
9909         val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9910                SHARED_HW_CFG_FAN_FAILURE_MASK);
9911
9912         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9913                 is_required = 1;
9914         }
9915         /*
9916          * The fan failure mechanism is usually related to the PHY type since
9917          * the power consumption of the board is affected by the PHY. Currently,
9918          * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9919          */
9920         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9921                 for (port = PORT_0; port < PORT_MAX; port++) {
9922                         is_required |= elink_fan_failure_det_req(sc,
9923                                                                  sc->
9924                                                                  devinfo.shmem_base,
9925                                                                  sc->
9926                                                                  devinfo.shmem2_base,
9927                                                                  port);
9928                 }
9929         }
9930
9931         if (is_required == 0) {
9932                 return;
9933         }
9934
9935         /* Fan failure is indicated by SPIO 5 */
9936         bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
9937
9938         /* set to active low mode */
9939         val = REG_RD(sc, MISC_REG_SPIO_INT);
9940         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
9941         REG_WR(sc, MISC_REG_SPIO_INT, val);
9942
9943         /* enable interrupt to signal the IGU */
9944         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
9945         val |= MISC_SPIO_SPIO5;
9946         REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
9947 }
9948
9949 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
9950 {
9951         uint32_t val;
9952
9953         REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
9954         if (!CHIP_IS_E1x(sc)) {
9955                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
9956         } else {
9957                 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
9958         }
9959         REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
9960         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
9961         /*
9962          * mask read length error interrupts in brb for parser
9963          * (parsing unit and 'checksum and crc' unit)
9964          * these errors are legal (PU reads fixed length and CAC can cause
9965          * read length error on truncated packets)
9966          */
9967         REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
9968         REG_WR(sc, QM_REG_QM_INT_MASK, 0);
9969         REG_WR(sc, TM_REG_TM_INT_MASK, 0);
9970         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
9971         REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
9972         REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
9973         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
9974         /*      REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
9975         REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
9976         REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
9977         REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
9978         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
9979         /*      REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
9980         REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
9981         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
9982         REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
9983         REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
9984         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
9985         /*      REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
9986
9987         val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
9988                PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
9989                PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
9990         if (!CHIP_IS_E1x(sc)) {
9991                 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
9992                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
9993         }
9994         REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
9995
9996         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
9997         REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
9998         REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
9999         /*      REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10000
10001         if (!CHIP_IS_E1x(sc)) {
10002 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10003                 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10004         }
10005
10006         REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10007         REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10008         /*      REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10009         REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10010 }
10011
10012 /**
10013  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10014  *
10015  * @sc:     driver handle
10016  */
10017 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10018 {
10019         uint8_t abs_func_id;
10020         uint32_t val;
10021
10022         PMD_DRV_LOG(DEBUG, "starting common init for func %d", SC_ABS_FUNC(sc));
10023
10024         /*
10025          * take the RESET lock to protect undi_unload flow from accessing
10026          * registers while we are resetting the chip
10027          */
10028         bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10029
10030         bnx2x_reset_common(sc);
10031
10032         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10033
10034         val = 0xfffc;
10035         if (CHIP_IS_E3(sc)) {
10036                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10037                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10038         }
10039
10040         REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10041
10042         bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10043
10044         ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10045
10046         if (!CHIP_IS_E1x(sc)) {
10047 /*
10048  * 4-port mode or 2-port mode we need to turn off master-enable for
10049  * everyone. After that we turn it back on for self. So, we disregard
10050  * multi-function, and always disable all functions on the given path,
10051  * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10052  */
10053                 for (abs_func_id = SC_PATH(sc);
10054                      abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10055                         if (abs_func_id == SC_ABS_FUNC(sc)) {
10056                                 REG_WR(sc,
10057                                        PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10058                                        1);
10059                                 continue;
10060                         }
10061
10062                         bnx2x_pretend_func(sc, abs_func_id);
10063
10064                         /* clear pf enable */
10065                         bnx2x_pf_disable(sc);
10066
10067                         bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10068                 }
10069         }
10070
10071         ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10072
10073         ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10074         bnx2x_init_pxp(sc);
10075
10076 #ifdef __BIG_ENDIAN
10077         REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10078         REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10079         REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10080         REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10081         REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10082         /* make sure this value is 0 */
10083         REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10084
10085         //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10086         REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10087         REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10088         REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10089         REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10090 #endif
10091
10092         ecore_ilt_init_page_size(sc, INITOP_SET);
10093
10094         if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10095                 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10096         }
10097
10098         /* let the HW do it's magic... */
10099         DELAY(100000);
10100
10101         /* finish PXP init */
10102
10103         val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10104         if (val != 1) {
10105                 PMD_DRV_LOG(NOTICE, "PXP2 CFG failed");
10106                 return -1;
10107         }
10108         val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10109         if (val != 1) {
10110                 PMD_DRV_LOG(NOTICE, "PXP2 RD_INIT failed");
10111                 return -1;
10112         }
10113
10114         /*
10115          * Timer bug workaround for E2 only. We need to set the entire ILT to have
10116          * entries with value "0" and valid bit on. This needs to be done by the
10117          * first PF that is loaded in a path (i.e. common phase)
10118          */
10119         if (!CHIP_IS_E1x(sc)) {
10120 /*
10121  * In E2 there is a bug in the timers block that can cause function 6 / 7
10122  * (i.e. vnic3) to start even if it is marked as "scan-off".
10123  * This occurs when a different function (func2,3) is being marked
10124  * as "scan-off". Real-life scenario for example: if a driver is being
10125  * load-unloaded while func6,7 are down. This will cause the timer to access
10126  * the ilt, translate to a logical address and send a request to read/write.
10127  * Since the ilt for the function that is down is not valid, this will cause
10128  * a translation error which is unrecoverable.
10129  * The Workaround is intended to make sure that when this happens nothing
10130  * fatal will occur. The workaround:
10131  *  1.  First PF driver which loads on a path will:
10132  *      a.  After taking the chip out of reset, by using pretend,
10133  *          it will write "0" to the following registers of
10134  *          the other vnics.
10135  *          REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10136  *          REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10137  *          REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10138  *          And for itself it will write '1' to
10139  *          PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10140  *          dmae-operations (writing to pram for example.)
10141  *          note: can be done for only function 6,7 but cleaner this
10142  *            way.
10143  *      b.  Write zero+valid to the entire ILT.
10144  *      c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
10145  *          VNIC3 (of that port). The range allocated will be the
10146  *          entire ILT. This is needed to prevent  ILT range error.
10147  *  2.  Any PF driver load flow:
10148  *      a.  ILT update with the physical addresses of the allocated
10149  *          logical pages.
10150  *      b.  Wait 20msec. - note that this timeout is needed to make
10151  *          sure there are no requests in one of the PXP internal
10152  *          queues with "old" ILT addresses.
10153  *      c.  PF enable in the PGLC.
10154  *      d.  Clear the was_error of the PF in the PGLC. (could have
10155  *          occurred while driver was down)
10156  *      e.  PF enable in the CFC (WEAK + STRONG)
10157  *      f.  Timers scan enable
10158  *  3.  PF driver unload flow:
10159  *      a.  Clear the Timers scan_en.
10160  *      b.  Polling for scan_on=0 for that PF.
10161  *      c.  Clear the PF enable bit in the PXP.
10162  *      d.  Clear the PF enable in the CFC (WEAK + STRONG)
10163  *      e.  Write zero+valid to all ILT entries (The valid bit must
10164  *          stay set)
10165  *      f.  If this is VNIC 3 of a port then also init
10166  *          first_timers_ilt_entry to zero and last_timers_ilt_entry
10167  *          to the last enrty in the ILT.
10168  *
10169  *      Notes:
10170  *      Currently the PF error in the PGLC is non recoverable.
10171  *      In the future the there will be a recovery routine for this error.
10172  *      Currently attention is masked.
10173  *      Having an MCP lock on the load/unload process does not guarantee that
10174  *      there is no Timer disable during Func6/7 enable. This is because the
10175  *      Timers scan is currently being cleared by the MCP on FLR.
10176  *      Step 2.d can be done only for PF6/7 and the driver can also check if
10177  *      there is error before clearing it. But the flow above is simpler and
10178  *      more general.
10179  *      All ILT entries are written by zero+valid and not just PF6/7
10180  *      ILT entries since in the future the ILT entries allocation for
10181  *      PF-s might be dynamic.
10182  */
10183                 struct ilt_client_info ilt_cli;
10184                 struct ecore_ilt ilt;
10185
10186                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10187                 memset(&ilt, 0, sizeof(struct ecore_ilt));
10188
10189 /* initialize dummy TM client */
10190                 ilt_cli.start = 0;
10191                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10192                 ilt_cli.client_num = ILT_CLIENT_TM;
10193
10194 /*
10195  * Step 1: set zeroes to all ilt page entries with valid bit on
10196  * Step 2: set the timers first/last ilt entry to point
10197  * to the entire range to prevent ILT range error for 3rd/4th
10198  * vnic (this code assumes existence of the vnic)
10199  *
10200  * both steps performed by call to ecore_ilt_client_init_op()
10201  * with dummy TM client
10202  *
10203  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10204  * and his brother are split registers
10205  */
10206
10207                 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10208                 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10209                 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10210
10211                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10212                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10213                 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10214         }
10215
10216         REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10217         REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10218
10219         if (!CHIP_IS_E1x(sc)) {
10220                 int factor = 0;
10221
10222                 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10223                 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10224
10225 /* let the HW do it's magic... */
10226                 do {
10227                         DELAY(200000);
10228                         val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10229                 } while (factor-- && (val != 1));
10230
10231                 if (val != 1) {
10232                         PMD_DRV_LOG(NOTICE, "ATC_INIT failed");
10233                         return -1;
10234                 }
10235         }
10236
10237         ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10238
10239         /* clean the DMAE memory */
10240         sc->dmae_ready = 1;
10241         ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10242
10243         ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10244
10245         ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10246
10247         ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10248
10249         ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10250
10251         bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10252         bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10253         bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10254         bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10255
10256         ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10257
10258         /* QM queues pointers table */
10259         ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10260
10261         /* soft reset pulse */
10262         REG_WR(sc, QM_REG_SOFT_RESET, 1);
10263         REG_WR(sc, QM_REG_SOFT_RESET, 0);
10264
10265         if (CNIC_SUPPORT(sc))
10266                 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10267
10268         ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10269         REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10270
10271         if (!CHIP_REV_IS_SLOW(sc)) {
10272 /* enable hw interrupt from doorbell Q */
10273                 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10274         }
10275
10276         ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10277
10278         ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10279         REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10280         REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10281
10282         if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10283                 if (IS_MF_AFEX(sc)) {
10284                         /*
10285                          * configure that AFEX and VLAN headers must be
10286                          * received in AFEX mode
10287                          */
10288                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10289                         REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10290                         REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10291                         REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10292                         REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10293                 } else {
10294                         /*
10295                          * Bit-map indicating which L2 hdrs may appear
10296                          * after the basic Ethernet header
10297                          */
10298                         REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10299                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10300                 }
10301         }
10302
10303         ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10304         ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10305         ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10306         ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10307
10308         if (!CHIP_IS_E1x(sc)) {
10309 /* reset VFC memories */
10310                 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10311                        VFC_MEMORIES_RST_REG_CAM_RST |
10312                        VFC_MEMORIES_RST_REG_RAM_RST);
10313                 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10314                        VFC_MEMORIES_RST_REG_CAM_RST |
10315                        VFC_MEMORIES_RST_REG_RAM_RST);
10316
10317                 DELAY(20000);
10318         }
10319
10320         ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10321         ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10322         ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10323         ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10324
10325         /* sync semi rtc */
10326         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10327         REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10328
10329         ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10330         ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10331         ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10332
10333         if (!CHIP_IS_E1x(sc)) {
10334                 if (IS_MF_AFEX(sc)) {
10335                         /*
10336                          * configure that AFEX and VLAN headers must be
10337                          * sent in AFEX mode
10338                          */
10339                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10340                         REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10341                         REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10342                         REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10343                         REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10344                 } else {
10345                         REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10346                                sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10347                 }
10348         }
10349
10350         REG_WR(sc, SRC_REG_SOFT_RST, 1);
10351
10352         ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10353
10354         if (CNIC_SUPPORT(sc)) {
10355                 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10356                 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10357                 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10358                 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10359                 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10360                 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10361                 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10362                 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10363                 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10364                 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10365         }
10366         REG_WR(sc, SRC_REG_SOFT_RST, 0);
10367
10368         if (sizeof(union cdu_context) != 1024) {
10369 /* we currently assume that a context is 1024 bytes */
10370                 PMD_DRV_LOG(NOTICE,
10371                             "please adjust the size of cdu_context(%ld)",
10372                             (long)sizeof(union cdu_context));
10373         }
10374
10375         ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10376         val = (4 << 24) + (0 << 12) + 1024;
10377         REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10378
10379         ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10380
10381         REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10382         /* enable context validation interrupt from CFC */
10383         REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10384
10385         /* set the thresholds to prevent CFC/CDU race */
10386         REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10387         ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10388
10389         if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10390                 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10391         }
10392
10393         ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10394         ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10395
10396         /* Reset PCIE errors for debug */
10397         REG_WR(sc, 0x2814, 0xffffffff);
10398         REG_WR(sc, 0x3820, 0xffffffff);
10399
10400         if (!CHIP_IS_E1x(sc)) {
10401                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10402                        (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10403                         PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10404                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10405                        (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10406                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10407                         PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10408                 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10409                        (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10410                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10411                         PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10412         }
10413
10414         ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10415
10416         /* in E3 this done in per-port section */
10417         if (!CHIP_IS_E3(sc))
10418                 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10419
10420         if (CHIP_IS_E1H(sc)) {
10421 /* not applicable for E2 (and above ...) */
10422                 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10423         }
10424
10425         if (CHIP_REV_IS_SLOW(sc)) {
10426                 DELAY(200000);
10427         }
10428
10429         /* finish CFC init */
10430         val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10431         if (val != 1) {
10432                 PMD_DRV_LOG(NOTICE, "CFC LL_INIT failed");
10433                 return -1;
10434         }
10435         val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10436         if (val != 1) {
10437                 PMD_DRV_LOG(NOTICE, "CFC AC_INIT failed");
10438                 return -1;
10439         }
10440         val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10441         if (val != 1) {
10442                 PMD_DRV_LOG(NOTICE, "CFC CAM_INIT failed");
10443                 return -1;
10444         }
10445         REG_WR(sc, CFC_REG_DEBUG0, 0);
10446
10447         bnx2x_setup_fan_failure_detection(sc);
10448
10449         /* clear PXP2 attentions */
10450         REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10451
10452         bnx2x_enable_blocks_attention(sc);
10453
10454         if (!CHIP_REV_IS_SLOW(sc)) {
10455                 ecore_enable_blocks_parity(sc);
10456         }
10457
10458         if (!BNX2X_NOMCP(sc)) {
10459                 if (CHIP_IS_E1x(sc)) {
10460                         bnx2x_common_init_phy(sc);
10461                 }
10462         }
10463
10464         return 0;
10465 }
10466
10467 /**
10468  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10469  *
10470  * @sc:     driver handle
10471  */
10472 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10473 {
10474         int rc = bnx2x_init_hw_common(sc);
10475
10476         if (rc) {
10477                 return rc;
10478         }
10479
10480         /* In E2 2-PORT mode, same ext phy is used for the two paths */
10481         if (!BNX2X_NOMCP(sc)) {
10482                 bnx2x_common_init_phy(sc);
10483         }
10484
10485         return 0;
10486 }
10487
10488 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10489 {
10490         int port = SC_PORT(sc);
10491         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10492         uint32_t low, high;
10493         uint32_t val;
10494
10495         PMD_DRV_LOG(DEBUG, "starting port init for port %d", port);
10496
10497         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10498
10499         ecore_init_block(sc, BLOCK_MISC, init_phase);
10500         ecore_init_block(sc, BLOCK_PXP, init_phase);
10501         ecore_init_block(sc, BLOCK_PXP2, init_phase);
10502
10503         /*
10504          * Timers bug workaround: disables the pf_master bit in pglue at
10505          * common phase, we need to enable it here before any dmae access are
10506          * attempted. Therefore we manually added the enable-master to the
10507          * port phase (it also happens in the function phase)
10508          */
10509         if (!CHIP_IS_E1x(sc)) {
10510                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10511         }
10512
10513         ecore_init_block(sc, BLOCK_ATC, init_phase);
10514         ecore_init_block(sc, BLOCK_DMAE, init_phase);
10515         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10516         ecore_init_block(sc, BLOCK_QM, init_phase);
10517
10518         ecore_init_block(sc, BLOCK_TCM, init_phase);
10519         ecore_init_block(sc, BLOCK_UCM, init_phase);
10520         ecore_init_block(sc, BLOCK_CCM, init_phase);
10521         ecore_init_block(sc, BLOCK_XCM, init_phase);
10522
10523         /* QM cid (connection) count */
10524         ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10525
10526         if (CNIC_SUPPORT(sc)) {
10527                 ecore_init_block(sc, BLOCK_TM, init_phase);
10528                 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10529                 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10530         }
10531
10532         ecore_init_block(sc, BLOCK_DORQ, init_phase);
10533
10534         ecore_init_block(sc, BLOCK_BRB1, init_phase);
10535
10536         if (CHIP_IS_E1H(sc)) {
10537                 if (IS_MF(sc)) {
10538                         low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10539                 } else if (sc->mtu > 4096) {
10540                         if (BNX2X_ONE_PORT(sc)) {
10541                                 low = 160;
10542                         } else {
10543                                 val = sc->mtu;
10544                                 /* (24*1024 + val*4)/256 */
10545                                 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10546                         }
10547                 } else {
10548                         low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10549                 }
10550                 high = (low + 56);      /* 14*1024/256 */
10551                 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10552                 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10553         }
10554
10555         if (CHIP_IS_MODE_4_PORT(sc)) {
10556                 REG_WR(sc, SC_PORT(sc) ?
10557                        BRB1_REG_MAC_GUARANTIED_1 :
10558                        BRB1_REG_MAC_GUARANTIED_0, 40);
10559         }
10560
10561         ecore_init_block(sc, BLOCK_PRS, init_phase);
10562         if (CHIP_IS_E3B0(sc)) {
10563                 if (IS_MF_AFEX(sc)) {
10564                         /* configure headers for AFEX mode */
10565                         if (SC_PORT(sc)) {
10566                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10567                                        0xE);
10568                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10569                                        0x6);
10570                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10571                         } else {
10572                                 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10573                                        0xE);
10574                                 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10575                                        0x6);
10576                                 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10577                         }
10578                 } else {
10579                         /* Ovlan exists only if we are in multi-function +
10580                          * switch-dependent mode, in switch-independent there
10581                          * is no ovlan headers
10582                          */
10583                         REG_WR(sc, SC_PORT(sc) ?
10584                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10585                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10586                                (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10587                 }
10588         }
10589
10590         ecore_init_block(sc, BLOCK_TSDM, init_phase);
10591         ecore_init_block(sc, BLOCK_CSDM, init_phase);
10592         ecore_init_block(sc, BLOCK_USDM, init_phase);
10593         ecore_init_block(sc, BLOCK_XSDM, init_phase);
10594
10595         ecore_init_block(sc, BLOCK_TSEM, init_phase);
10596         ecore_init_block(sc, BLOCK_USEM, init_phase);
10597         ecore_init_block(sc, BLOCK_CSEM, init_phase);
10598         ecore_init_block(sc, BLOCK_XSEM, init_phase);
10599
10600         ecore_init_block(sc, BLOCK_UPB, init_phase);
10601         ecore_init_block(sc, BLOCK_XPB, init_phase);
10602
10603         ecore_init_block(sc, BLOCK_PBF, init_phase);
10604
10605         if (CHIP_IS_E1x(sc)) {
10606 /* configure PBF to work without PAUSE mtu 9000 */
10607                 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10608
10609 /* update threshold */
10610                 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10611 /* update init credit */
10612                 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10613                        (9040 / 16) + 553 - 22);
10614
10615 /* probe changes */
10616                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10617                 DELAY(50);
10618                 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10619         }
10620
10621         if (CNIC_SUPPORT(sc)) {
10622                 ecore_init_block(sc, BLOCK_SRC, init_phase);
10623         }
10624
10625         ecore_init_block(sc, BLOCK_CDU, init_phase);
10626         ecore_init_block(sc, BLOCK_CFC, init_phase);
10627         ecore_init_block(sc, BLOCK_HC, init_phase);
10628         ecore_init_block(sc, BLOCK_IGU, init_phase);
10629         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10630         /* init aeu_mask_attn_func_0/1:
10631          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10632          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10633          *             bits 4-7 are used for "per vn group attention" */
10634         val = IS_MF(sc) ? 0xF7 : 0x7;
10635         val |= 0x10;
10636         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10637
10638         ecore_init_block(sc, BLOCK_NIG, init_phase);
10639
10640         if (!CHIP_IS_E1x(sc)) {
10641 /* Bit-map indicating which L2 hdrs may appear after the
10642  * basic Ethernet header
10643  */
10644                 if (IS_MF_AFEX(sc)) {
10645                         REG_WR(sc, SC_PORT(sc) ?
10646                                NIG_REG_P1_HDRS_AFTER_BASIC :
10647                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10648                 } else {
10649                         REG_WR(sc, SC_PORT(sc) ?
10650                                NIG_REG_P1_HDRS_AFTER_BASIC :
10651                                NIG_REG_P0_HDRS_AFTER_BASIC,
10652                                IS_MF_SD(sc) ? 7 : 6);
10653                 }
10654
10655                 if (CHIP_IS_E3(sc)) {
10656                         REG_WR(sc, SC_PORT(sc) ?
10657                                NIG_REG_LLH1_MF_MODE :
10658                                NIG_REG_LLH_MF_MODE, IS_MF(sc));
10659                 }
10660         }
10661         if (!CHIP_IS_E3(sc)) {
10662                 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10663         }
10664
10665         /* 0x2 disable mf_ov, 0x1 enable */
10666         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10667                (IS_MF_SD(sc) ? 0x1 : 0x2));
10668
10669         if (!CHIP_IS_E1x(sc)) {
10670                 val = 0;
10671                 switch (sc->devinfo.mf_info.mf_mode) {
10672                 case MULTI_FUNCTION_SD:
10673                         val = 1;
10674                         break;
10675                 case MULTI_FUNCTION_SI:
10676                 case MULTI_FUNCTION_AFEX:
10677                         val = 2;
10678                         break;
10679                 }
10680
10681                 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10682                             NIG_REG_LLH0_CLS_TYPE), val);
10683         }
10684         REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10685         REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10686         REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10687
10688         /* If SPIO5 is set to generate interrupts, enable it for this port */
10689         val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10690         if (val & MISC_SPIO_SPIO5) {
10691                 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10692                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10693                 val = REG_RD(sc, reg_addr);
10694                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10695                 REG_WR(sc, reg_addr, val);
10696         }
10697
10698         return 0;
10699 }
10700
10701 static uint32_t
10702 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10703                        uint32_t expected, uint32_t poll_count)
10704 {
10705         uint32_t cur_cnt = poll_count;
10706         uint32_t val;
10707
10708         while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10709                 DELAY(FLR_WAIT_INTERVAL);
10710         }
10711
10712         return val;
10713 }
10714
10715 static int
10716 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10717                               __rte_unused const char *msg, uint32_t poll_cnt)
10718 {
10719         uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10720
10721         if (val != 0) {
10722                 PMD_DRV_LOG(NOTICE, "%s usage count=%d", msg, val);
10723                 return -1;
10724         }
10725
10726         return 0;
10727 }
10728
10729 /* Common routines with VF FLR cleanup */
10730 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10731 {
10732         /* adjust polling timeout */
10733         if (CHIP_REV_IS_EMUL(sc)) {
10734                 return FLR_POLL_CNT * 2000;
10735         }
10736
10737         if (CHIP_REV_IS_FPGA(sc)) {
10738                 return FLR_POLL_CNT * 120;
10739         }
10740
10741         return FLR_POLL_CNT;
10742 }
10743
10744 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10745 {
10746         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10747         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10748                                           CFC_REG_NUM_LCIDS_INSIDE_PF,
10749                                           "CFC PF usage counter timed out",
10750                                           poll_cnt)) {
10751                 return -1;
10752         }
10753
10754         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10755         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10756                                           DORQ_REG_PF_USAGE_CNT,
10757                                           "DQ PF usage counter timed out",
10758                                           poll_cnt)) {
10759                 return -1;
10760         }
10761
10762         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10763         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10764                                           QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10765                                           "QM PF usage counter timed out",
10766                                           poll_cnt)) {
10767                 return -1;
10768         }
10769
10770         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10771         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10772                                           TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10773                                           "Timers VNIC usage counter timed out",
10774                                           poll_cnt)) {
10775                 return -1;
10776         }
10777
10778         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10779                                           TM_REG_LIN0_NUM_SCANS +
10780                                           4 * SC_PORT(sc),
10781                                           "Timers NUM_SCANS usage counter timed out",
10782                                           poll_cnt)) {
10783                 return -1;
10784         }
10785
10786         /* Wait DMAE PF usage counter to zero */
10787         if (bnx2x_flr_clnup_poll_hw_counter(sc,
10788                                           dmae_reg_go_c[INIT_DMAE_C(sc)],
10789                                           "DMAE dommand register timed out",
10790                                           poll_cnt)) {
10791                 return -1;
10792         }
10793
10794         return 0;
10795 }
10796
10797 #define OP_GEN_PARAM(param)                                            \
10798         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10799 #define OP_GEN_TYPE(type)                                           \
10800         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10801 #define OP_GEN_AGG_VECT(index)                                             \
10802         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10803
10804 static int
10805 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10806                      uint32_t poll_cnt)
10807 {
10808         uint32_t op_gen_command = 0;
10809         uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10810                               CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10811         int ret = 0;
10812
10813         if (REG_RD(sc, comp_addr)) {
10814                 PMD_DRV_LOG(NOTICE,
10815                             "Cleanup complete was not 0 before sending");
10816                 return -1;
10817         }
10818
10819         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10820         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10821         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10822         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10823
10824         REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10825
10826         if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10827                 PMD_DRV_LOG(NOTICE, "FW final cleanup did not succeed");
10828                 PMD_DRV_LOG(DEBUG, "At timeout completion address contained %x",
10829                             (REG_RD(sc, comp_addr)));
10830                 rte_panic("FLR cleanup failed");
10831                 return -1;
10832         }
10833
10834         /* Zero completion for nxt FLR */
10835         REG_WR(sc, comp_addr, 0);
10836
10837         return ret;
10838 }
10839
10840 static void
10841 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10842                        uint32_t poll_count)
10843 {
10844         uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10845         uint32_t cur_cnt = poll_count;
10846
10847         crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10848         crd = crd_start = REG_RD(sc, regs->crd);
10849         init_crd = REG_RD(sc, regs->init_crd);
10850
10851         while ((crd != init_crd) &&
10852                ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10853                 (init_crd - crd_start))) {
10854                 if (cur_cnt--) {
10855                         DELAY(FLR_WAIT_INTERVAL);
10856                         crd = REG_RD(sc, regs->crd);
10857                         crd_freed = REG_RD(sc, regs->crd_freed);
10858                 } else {
10859                         break;
10860                 }
10861         }
10862 }
10863
10864 static void
10865 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10866                        uint32_t poll_count)
10867 {
10868         uint32_t occup, to_free, freed, freed_start;
10869         uint32_t cur_cnt = poll_count;
10870
10871         occup = to_free = REG_RD(sc, regs->lines_occup);
10872         freed = freed_start = REG_RD(sc, regs->lines_freed);
10873
10874         while (occup &&
10875                ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10876                 to_free)) {
10877                 if (cur_cnt--) {
10878                         DELAY(FLR_WAIT_INTERVAL);
10879                         occup = REG_RD(sc, regs->lines_occup);
10880                         freed = REG_RD(sc, regs->lines_freed);
10881                 } else {
10882                         break;
10883                 }
10884         }
10885 }
10886
10887 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10888 {
10889         struct pbf_pN_cmd_regs cmd_regs[] = {
10890                 {0, (CHIP_IS_E3B0(sc)) ?
10891                  PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10892                  (CHIP_IS_E3B0(sc)) ?
10893                  PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10894                 {1, (CHIP_IS_E3B0(sc)) ?
10895                  PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10896                  (CHIP_IS_E3B0(sc)) ?
10897                  PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10898                 {4, (CHIP_IS_E3B0(sc)) ?
10899                  PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10900                  (CHIP_IS_E3B0(sc)) ?
10901                  PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10902                  PBF_REG_P4_TQ_LINES_FREED_CNT}
10903         };
10904
10905         struct pbf_pN_buf_regs buf_regs[] = {
10906                 {0, (CHIP_IS_E3B0(sc)) ?
10907                  PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10908                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10909                  (CHIP_IS_E3B0(sc)) ?
10910                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10911                  PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10912                 {1, (CHIP_IS_E3B0(sc)) ?
10913                  PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10914                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10915                  (CHIP_IS_E3B0(sc)) ?
10916                  PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10917                  PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10918                 {4, (CHIP_IS_E3B0(sc)) ?
10919                  PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10920                  (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10921                  (CHIP_IS_E3B0(sc)) ?
10922                  PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
10923                  PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
10924         };
10925
10926         uint32_t i;
10927
10928         /* Verify the command queues are flushed P0, P1, P4 */
10929         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
10930                 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
10931         }
10932
10933         /* Verify the transmission buffers are flushed P0, P1, P4 */
10934         for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
10935                 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
10936         }
10937 }
10938
10939 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
10940 {
10941         __rte_unused uint32_t val;
10942
10943         val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
10944         PMD_DRV_LOG(DEBUG, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
10945
10946         val = REG_RD(sc, PBF_REG_DISABLE_PF);
10947         PMD_DRV_LOG(DEBUG, "PBF_REG_DISABLE_PF is 0x%x", val);
10948
10949         val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
10950         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
10951
10952         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
10953         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
10954
10955         val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
10956         PMD_DRV_LOG(DEBUG, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
10957
10958         val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
10959         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
10960
10961         val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
10962         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
10963
10964         val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
10965         PMD_DRV_LOG(DEBUG, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
10966                     val);
10967 }
10968
10969 /**
10970  *      bnx2x_pf_flr_clnup
10971  *      a. re-enable target read on the PF
10972  *      b. poll cfc per function usgae counter
10973  *      c. poll the qm perfunction usage counter
10974  *      d. poll the tm per function usage counter
10975  *      e. poll the tm per function scan-done indication
10976  *      f. clear the dmae channel associated wit hthe PF
10977  *      g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
10978  *      h. call the common flr cleanup code with -1 (pf indication)
10979  */
10980 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
10981 {
10982         uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
10983
10984         /* Re-enable PF target read access */
10985         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10986
10987         /* Poll HW usage counters */
10988         if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
10989                 return -1;
10990         }
10991
10992         /* Zero the igu 'trailing edge' and 'leading edge' */
10993
10994         /* Send the FW cleanup command */
10995         if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
10996                 return -1;
10997         }
10998
10999         /* ATC cleanup */
11000
11001         /* Verify TX hw is flushed */
11002         bnx2x_tx_hw_flushed(sc, poll_cnt);
11003
11004         /* Wait 100ms (not adjusted according to platform) */
11005         DELAY(100000);
11006
11007         /* Verify no pending pci transactions */
11008         if (bnx2x_is_pcie_pending(sc)) {
11009                 PMD_DRV_LOG(NOTICE, "PCIE Transactions still pending");
11010         }
11011
11012         /* Debug */
11013         bnx2x_hw_enable_status(sc);
11014
11015         /*
11016          * Master enable - Due to WB DMAE writes performed before this
11017          * register is re-initialized as part of the regular function init
11018          */
11019         REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11020
11021         return 0;
11022 }
11023
11024 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11025 {
11026         int port = SC_PORT(sc);
11027         int func = SC_FUNC(sc);
11028         int init_phase = PHASE_PF0 + func;
11029         struct ecore_ilt *ilt = sc->ilt;
11030         uint16_t cdu_ilt_start;
11031         uint32_t addr, val;
11032         uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11033         int main_mem_width, rc;
11034         uint32_t i;
11035
11036         PMD_DRV_LOG(DEBUG, "starting func init for func %d", func);
11037
11038         /* FLR cleanup */
11039         if (!CHIP_IS_E1x(sc)) {
11040                 rc = bnx2x_pf_flr_clnup(sc);
11041                 if (rc) {
11042                         PMD_DRV_LOG(NOTICE, "FLR cleanup failed!");
11043                         return rc;
11044                 }
11045         }
11046
11047         /* set MSI reconfigure capability */
11048         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11049                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11050                 val = REG_RD(sc, addr);
11051                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11052                 REG_WR(sc, addr, val);
11053         }
11054
11055         ecore_init_block(sc, BLOCK_PXP, init_phase);
11056         ecore_init_block(sc, BLOCK_PXP2, init_phase);
11057
11058         ilt = sc->ilt;
11059         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11060
11061         for (i = 0; i < L2_ILT_LINES(sc); i++) {
11062                 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11063                 ilt->lines[cdu_ilt_start + i].page_mapping =
11064                     (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11065                 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11066         }
11067         ecore_ilt_init_op(sc, INITOP_SET);
11068
11069         REG_WR(sc, PRS_REG_NIC_MODE, 1);
11070
11071         if (!CHIP_IS_E1x(sc)) {
11072                 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11073
11074 /* Turn on a single ISR mode in IGU if driver is going to use
11075  * INT#x or MSI
11076  */
11077                 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11078                     || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11079                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11080                 }
11081
11082 /*
11083  * Timers workaround bug: function init part.
11084  * Need to wait 20msec after initializing ILT,
11085  * needed to make sure there are no requests in
11086  * one of the PXP internal queues with "old" ILT addresses
11087  */
11088                 DELAY(20000);
11089
11090 /*
11091  * Master enable - Due to WB DMAE writes performed before this
11092  * register is re-initialized as part of the regular function
11093  * init
11094  */
11095                 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11096 /* Enable the function in IGU */
11097                 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11098         }
11099
11100         sc->dmae_ready = 1;
11101
11102         ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11103
11104         if (!CHIP_IS_E1x(sc))
11105                 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11106
11107         ecore_init_block(sc, BLOCK_ATC, init_phase);
11108         ecore_init_block(sc, BLOCK_DMAE, init_phase);
11109         ecore_init_block(sc, BLOCK_NIG, init_phase);
11110         ecore_init_block(sc, BLOCK_SRC, init_phase);
11111         ecore_init_block(sc, BLOCK_MISC, init_phase);
11112         ecore_init_block(sc, BLOCK_TCM, init_phase);
11113         ecore_init_block(sc, BLOCK_UCM, init_phase);
11114         ecore_init_block(sc, BLOCK_CCM, init_phase);
11115         ecore_init_block(sc, BLOCK_XCM, init_phase);
11116         ecore_init_block(sc, BLOCK_TSEM, init_phase);
11117         ecore_init_block(sc, BLOCK_USEM, init_phase);
11118         ecore_init_block(sc, BLOCK_CSEM, init_phase);
11119         ecore_init_block(sc, BLOCK_XSEM, init_phase);
11120
11121         if (!CHIP_IS_E1x(sc))
11122                 REG_WR(sc, QM_REG_PF_EN, 1);
11123
11124         if (!CHIP_IS_E1x(sc)) {
11125                 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11126                 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11127                 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11128                 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11129         }
11130         ecore_init_block(sc, BLOCK_QM, init_phase);
11131
11132         ecore_init_block(sc, BLOCK_TM, init_phase);
11133         ecore_init_block(sc, BLOCK_DORQ, init_phase);
11134
11135         ecore_init_block(sc, BLOCK_BRB1, init_phase);
11136         ecore_init_block(sc, BLOCK_PRS, init_phase);
11137         ecore_init_block(sc, BLOCK_TSDM, init_phase);
11138         ecore_init_block(sc, BLOCK_CSDM, init_phase);
11139         ecore_init_block(sc, BLOCK_USDM, init_phase);
11140         ecore_init_block(sc, BLOCK_XSDM, init_phase);
11141         ecore_init_block(sc, BLOCK_UPB, init_phase);
11142         ecore_init_block(sc, BLOCK_XPB, init_phase);
11143         ecore_init_block(sc, BLOCK_PBF, init_phase);
11144         if (!CHIP_IS_E1x(sc))
11145                 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11146
11147         ecore_init_block(sc, BLOCK_CDU, init_phase);
11148
11149         ecore_init_block(sc, BLOCK_CFC, init_phase);
11150
11151         if (!CHIP_IS_E1x(sc))
11152                 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11153
11154         if (IS_MF(sc)) {
11155                 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11156                 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11157         }
11158
11159         ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11160
11161         /* HC init per function */
11162         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11163                 if (CHIP_IS_E1H(sc)) {
11164                         REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11165
11166                         REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11167                         REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11168                 }
11169                 ecore_init_block(sc, BLOCK_HC, init_phase);
11170
11171         } else {
11172                 uint32_t num_segs, sb_idx, prod_offset;
11173
11174                 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11175
11176                 if (!CHIP_IS_E1x(sc)) {
11177                         REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11178                         REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11179                 }
11180
11181                 ecore_init_block(sc, BLOCK_IGU, init_phase);
11182
11183                 if (!CHIP_IS_E1x(sc)) {
11184                         int dsb_idx = 0;
11185         /**
11186          * Producer memory:
11187          * E2 mode: address 0-135 match to the mapping memory;
11188          * 136 - PF0 default prod; 137 - PF1 default prod;
11189          * 138 - PF2 default prod; 139 - PF3 default prod;
11190          * 140 - PF0 attn prod;    141 - PF1 attn prod;
11191          * 142 - PF2 attn prod;    143 - PF3 attn prod;
11192          * 144-147 reserved.
11193          *
11194          * E1.5 mode - In backward compatible mode;
11195          * for non default SB; each even line in the memory
11196          * holds the U producer and each odd line hold
11197          * the C producer. The first 128 producers are for
11198          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11199          * producers are for the DSB for each PF.
11200          * Each PF has five segments: (the order inside each
11201          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11202          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11203          * 144-147 attn prods;
11204          */
11205                         /* non-default-status-blocks */
11206                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11207                             IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11208                         for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11209                                 prod_offset = (sc->igu_base_sb + sb_idx) *
11210                                     num_segs;
11211
11212                                 for (i = 0; i < num_segs; i++) {
11213                                         addr = IGU_REG_PROD_CONS_MEMORY +
11214                                             (prod_offset + i) * 4;
11215                                         REG_WR(sc, addr, 0);
11216                                 }
11217                                 /* send consumer update with value 0 */
11218                                 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11219                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11220                                 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11221                         }
11222
11223                         /* default-status-blocks */
11224                         num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11225                             IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11226
11227                         if (CHIP_IS_MODE_4_PORT(sc))
11228                                 dsb_idx = SC_FUNC(sc);
11229                         else
11230                                 dsb_idx = SC_VN(sc);
11231
11232                         prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11233                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
11234                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
11235
11236                         /*
11237                          * igu prods come in chunks of E1HVN_MAX (4) -
11238                          * does not matters what is the current chip mode
11239                          */
11240                         for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11241                                 addr = IGU_REG_PROD_CONS_MEMORY +
11242                                     (prod_offset + i) * 4;
11243                                 REG_WR(sc, addr, 0);
11244                         }
11245                         /* send consumer update with 0 */
11246                         if (CHIP_INT_MODE_IS_BC(sc)) {
11247                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11248                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11249                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11250                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
11251                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11252                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
11253                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11254                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
11255                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11256                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11257                         } else {
11258                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11259                                            USTORM_ID, 0, IGU_INT_NOP, 1);
11260                                 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11261                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
11262                         }
11263                         bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11264
11265                         /* !!! these should become driver const once
11266                            rf-tool supports split-68 const */
11267                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11268                         REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11269                         REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11270                         REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11271                         REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11272                         REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11273                 }
11274         }
11275
11276         /* Reset PCIE errors for debug */
11277         REG_WR(sc, 0x2114, 0xffffffff);
11278         REG_WR(sc, 0x2120, 0xffffffff);
11279
11280         if (CHIP_IS_E1x(sc)) {
11281                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;    /*dwords */
11282                 main_mem_base = HC_REG_MAIN_MEMORY +
11283                     SC_PORT(sc) * (main_mem_size * 4);
11284                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11285                 main_mem_width = 8;
11286
11287                 val = REG_RD(sc, main_mem_prty_clr);
11288                 if (val) {
11289                         PMD_DRV_LOG(DEBUG,
11290                                     "Parity errors in HC block during function init (0x%x)!",
11291                                     val);
11292                 }
11293
11294 /* Clear "false" parity errors in MSI-X table */
11295                 for (i = main_mem_base;
11296                      i < main_mem_base + main_mem_size * 4;
11297                      i += main_mem_width) {
11298                         bnx2x_read_dmae(sc, i, main_mem_width / 4);
11299                         bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11300                                        i, main_mem_width / 4);
11301                 }
11302 /* Clear HC parity attention */
11303                 REG_RD(sc, main_mem_prty_clr);
11304         }
11305
11306         /* Enable STORMs SP logging */
11307         REG_WR8(sc, BAR_USTRORM_INTMEM +
11308                 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11309         REG_WR8(sc, BAR_TSTRORM_INTMEM +
11310                 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11311         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11312                 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11313         REG_WR8(sc, BAR_XSTRORM_INTMEM +
11314                 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11315
11316         elink_phy_probe(&sc->link_params);
11317
11318         return 0;
11319 }
11320
11321 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11322 {
11323         if (!BNX2X_NOMCP(sc)) {
11324                 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11325         } else {
11326                 if (!CHIP_REV_IS_SLOW(sc)) {
11327                         PMD_DRV_LOG(WARNING,
11328                                     "Bootcode is missing - cannot reset link");
11329                 }
11330         }
11331 }
11332
11333 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11334 {
11335         int port = SC_PORT(sc);
11336         uint32_t val;
11337
11338         /* reset physical Link */
11339         bnx2x_link_reset(sc);
11340
11341         REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11342
11343         /* Do not rcv packets to BRB */
11344         REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11345         /* Do not direct rcv packets that are not for MCP to the BRB */
11346         REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11347                     NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11348
11349         /* Configure AEU */
11350         REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11351
11352         DELAY(100000);
11353
11354         /* Check for BRB port occupancy */
11355         val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11356         if (val) {
11357                 PMD_DRV_LOG(DEBUG,
11358                             "BRB1 is not empty, %d blocks are occupied", val);
11359         }
11360 }
11361
11362 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11363 {
11364         int reg;
11365         uint32_t wb_write[2];
11366
11367         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11368
11369         wb_write[0] = ONCHIP_ADDR1(addr);
11370         wb_write[1] = ONCHIP_ADDR2(addr);
11371         REG_WR_DMAE(sc, reg, wb_write, 2);
11372 }
11373
11374 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11375 {
11376         uint32_t i, base = FUNC_ILT_BASE(func);
11377         for (i = base; i < base + ILT_PER_FUNC; i++) {
11378                 bnx2x_ilt_wr(sc, i, 0);
11379         }
11380 }
11381
11382 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11383 {
11384         struct bnx2x_fastpath *fp;
11385         int port = SC_PORT(sc);
11386         int func = SC_FUNC(sc);
11387         int i;
11388
11389         /* Disable the function in the FW */
11390         REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11391         REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11392         REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11393         REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11394
11395         /* FP SBs */
11396         FOR_EACH_ETH_QUEUE(sc, i) {
11397                 fp = &sc->fp[i];
11398                 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11399                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11400                         SB_DISABLED);
11401         }
11402
11403         /* SP SB */
11404         REG_WR8(sc, BAR_CSTRORM_INTMEM +
11405                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11406
11407         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11408                 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11409                        0);
11410         }
11411
11412         /* Configure IGU */
11413         if (sc->devinfo.int_block == INT_BLOCK_HC) {
11414                 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11415                 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11416         } else {
11417                 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11418                 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11419         }
11420
11421         if (CNIC_LOADED(sc)) {
11422 /* Disable Timer scan */
11423                 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11424 /*
11425  * Wait for at least 10ms and up to 2 second for the timers
11426  * scan to complete
11427  */
11428                 for (i = 0; i < 200; i++) {
11429                         DELAY(10000);
11430                         if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11431                                 break;
11432                 }
11433         }
11434
11435         /* Clear ILT */
11436         bnx2x_clear_func_ilt(sc, func);
11437
11438         /*
11439          * Timers workaround bug for E2: if this is vnic-3,
11440          * we need to set the entire ilt range for this timers.
11441          */
11442         if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11443                 struct ilt_client_info ilt_cli;
11444 /* use dummy TM client */
11445                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11446                 ilt_cli.start = 0;
11447                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11448                 ilt_cli.client_num = ILT_CLIENT_TM;
11449
11450                 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11451         }
11452
11453         /* this assumes that reset_port() called before reset_func() */
11454         if (!CHIP_IS_E1x(sc)) {
11455                 bnx2x_pf_disable(sc);
11456         }
11457
11458         sc->dmae_ready = 0;
11459 }
11460
11461 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11462 {
11463         rte_free(sc->init_ops);
11464         rte_free(sc->init_ops_offsets);
11465         rte_free(sc->init_data);
11466         rte_free(sc->iro_array);
11467 }
11468
11469 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11470 {
11471         uint32_t len, i;
11472         uint8_t *p = sc->firmware;
11473         uint32_t off[24];
11474
11475         for (i = 0; i < 24; ++i)
11476                 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11477
11478         len = off[0];
11479         sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11480         if (!sc->init_ops)
11481                 goto alloc_failed;
11482         bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11483
11484         len = off[2];
11485         sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11486         if (!sc->init_ops_offsets)
11487                 goto alloc_failed;
11488         bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11489
11490         len = off[4];
11491         sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11492         if (!sc->init_data)
11493                 goto alloc_failed;
11494         bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11495
11496         sc->tsem_int_table_data = p + off[7];
11497         sc->tsem_pram_data = p + off[9];
11498         sc->usem_int_table_data = p + off[11];
11499         sc->usem_pram_data = p + off[13];
11500         sc->csem_int_table_data = p + off[15];
11501         sc->csem_pram_data = p + off[17];
11502         sc->xsem_int_table_data = p + off[19];
11503         sc->xsem_pram_data = p + off[21];
11504
11505         len = off[22];
11506         sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11507         if (!sc->iro_array)
11508                 goto alloc_failed;
11509         bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11510
11511         return 0;
11512
11513 alloc_failed:
11514         bnx2x_release_firmware(sc);
11515         return -1;
11516 }
11517
11518 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11519 {
11520 #define MIN_PREFIX_SIZE (10)
11521
11522         int n = MIN_PREFIX_SIZE;
11523         uint16_t xlen;
11524
11525         if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11526             len <= MIN_PREFIX_SIZE) {
11527                 return -1;
11528         }
11529
11530         /* optional extra fields are present */
11531         if (zbuf[3] & 0x4) {
11532                 xlen = zbuf[13];
11533                 xlen <<= 8;
11534                 xlen += zbuf[12];
11535
11536                 n += xlen;
11537         }
11538         /* file name is present */
11539         if (zbuf[3] & 0x8) {
11540                 while ((zbuf[n++] != 0) && (n < len)) ;
11541         }
11542
11543         return n;
11544 }
11545
11546 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11547 {
11548         int ret;
11549         int data_begin = cut_gzip_prefix(zbuf, len);
11550
11551         PMD_DRV_LOG(DEBUG, "ecore_gunzip %d", len);
11552
11553         if (data_begin <= 0) {
11554                 PMD_DRV_LOG(NOTICE, "bad gzip prefix");
11555                 return -1;
11556         }
11557
11558         memset(&zlib_stream, 0, sizeof(zlib_stream));
11559         zlib_stream.next_in = zbuf + data_begin;
11560         zlib_stream.avail_in = len - data_begin;
11561         zlib_stream.next_out = sc->gz_buf;
11562         zlib_stream.avail_out = FW_BUF_SIZE;
11563
11564         ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11565         if (ret != Z_OK) {
11566                 PMD_DRV_LOG(NOTICE, "zlib inflateInit2 error");
11567                 return ret;
11568         }
11569
11570         ret = inflate(&zlib_stream, Z_FINISH);
11571         if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11572                 PMD_DRV_LOG(NOTICE, "zlib inflate error: %d %s", ret,
11573                             zlib_stream.msg);
11574         }
11575
11576         sc->gz_outlen = zlib_stream.total_out;
11577         if (sc->gz_outlen & 0x3) {
11578                 PMD_DRV_LOG(NOTICE, "firmware is not aligned. gz_outlen == %d",
11579                             sc->gz_outlen);
11580         }
11581         sc->gz_outlen >>= 2;
11582
11583         inflateEnd(&zlib_stream);
11584
11585         if (ret == Z_STREAM_END)
11586                 return 0;
11587
11588         return ret;
11589 }
11590
11591 static void
11592 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11593                           uint32_t addr, uint32_t len)
11594 {
11595         bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11596 }
11597
11598 void
11599 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11600                           uint32_t * data)
11601 {
11602         uint8_t i;
11603         for (i = 0; i < size / 4; i++) {
11604                 REG_WR(sc, addr + (i * 4), data[i]);
11605         }
11606 }
11607
11608 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11609 {
11610         uint32_t phy_type_idx = ext_phy_type >> 8;
11611         static const char *types[] =
11612             { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11613                 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11614                 "BNX2X-8727",
11615                 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11616         };
11617
11618         if (phy_type_idx < 12)
11619                 return types[phy_type_idx];
11620         else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11621                 return types[12];
11622         else
11623                 return types[13];
11624 }
11625
11626 static const char *get_state(uint32_t state)
11627 {
11628         uint32_t state_idx = state >> 12;
11629         static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11630                 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11631                 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11632                 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11633                 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11634         };
11635
11636         if (state_idx <= 0xF)
11637                 return states[state_idx];
11638         else
11639                 return states[0x10];
11640 }
11641
11642 static const char *get_recovery_state(uint32_t state)
11643 {
11644         static const char *states[] = { "NONE", "DONE", "INIT",
11645                 "WAIT", "FAILED", "NIC_LOADING"
11646         };
11647         return states[state];
11648 }
11649
11650 static const char *get_rx_mode(uint32_t mode)
11651 {
11652         static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11653                 "PROMISC", "MAX_MULTICAST", "ERROR"
11654         };
11655
11656         if (mode < 0x4)
11657                 return modes[mode];
11658         else if (BNX2X_MAX_MULTICAST == mode)
11659                 return modes[4];
11660         else
11661                 return modes[5];
11662 }
11663
11664 #define BNX2X_INFO_STR_MAX 256
11665 static const char *get_bnx2x_flags(uint32_t flags)
11666 {
11667         int i;
11668         static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11669                 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11670                 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11671                 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11672         };
11673         static char flag_str[BNX2X_INFO_STR_MAX];
11674         memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11675
11676         for (i = 0; i < 5; i++)
11677                 if (flags & (1 << i)) {
11678                         strcat(flag_str, flag[i]);
11679                         flags ^= (1 << i);
11680                 }
11681         if (flags) {
11682                 static char unknown[BNX2X_INFO_STR_MAX];
11683                 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11684                 strcat(flag_str, unknown);
11685         }
11686         return flag_str;
11687 }
11688
11689 /*
11690  * Prints useful adapter info.
11691  */
11692 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11693 {
11694         int i = 0;
11695         __rte_unused uint32_t ext_phy_type;
11696
11697         PMD_INIT_FUNC_TRACE();
11698         if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11699                 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11700                                                               sc->
11701                                                               devinfo.shmem_base
11702                                                               + offsetof(struct
11703                                                                          shmem_region,
11704                                                                          dev_info.port_hw_config
11705                                                                          [0].external_phy_config)));
11706         else
11707                 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11708                                                                 sc->
11709                                                                 devinfo.shmem_base
11710                                                                 +
11711                                                                 offsetof(struct
11712                                                                          shmem_region,
11713                                                                          dev_info.port_hw_config
11714                                                                          [0].external_phy_config)));
11715
11716         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11717         /* Hardware chip info. */
11718         PMD_INIT_LOG(DEBUG, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11719         PMD_INIT_LOG(DEBUG, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11720                      (CHIP_METAL(sc) >> 4));
11721
11722         /* Bus info. */
11723         PMD_INIT_LOG(DEBUG, "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11724         switch (sc->devinfo.pcie_link_speed) {
11725         case 1:
11726                 PMD_INIT_LOG(DEBUG, "%23s", "2.5 Gbps");
11727                 break;
11728         case 2:
11729                 PMD_INIT_LOG(DEBUG, "%21s", "5 Gbps");
11730                 break;
11731         case 4:
11732                 PMD_INIT_LOG(DEBUG, "%21s", "8 Gbps");
11733                 break;
11734         default:
11735                 PMD_INIT_LOG(DEBUG, "%33s", "Unknown link speed");
11736         }
11737
11738         /* Device features. */
11739         PMD_INIT_LOG(DEBUG, "%12s : ", "Flags");
11740
11741         /* Miscellaneous flags. */
11742         if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11743                 PMD_INIT_LOG(DEBUG, "%18s", "MSI");
11744                 i++;
11745         }
11746
11747         if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11748                 if (i > 0)
11749                         PMD_INIT_LOG(DEBUG, "|");
11750                 PMD_INIT_LOG(DEBUG, "%20s", "MSI-X");
11751                 i++;
11752         }
11753
11754         if (IS_PF(sc)) {
11755                 PMD_INIT_LOG(DEBUG, "%12s : ", "Queues");
11756                 switch (sc->sp->rss_rdata.rss_mode) {
11757                 case ETH_RSS_MODE_DISABLED:
11758                         PMD_INIT_LOG(DEBUG, "%19s", "None");
11759                         break;
11760                 case ETH_RSS_MODE_REGULAR:
11761                         PMD_INIT_LOG(DEBUG, "%18s : %d", "RSS", sc->num_queues);
11762                         break;
11763                 default:
11764                         PMD_INIT_LOG(DEBUG, "%22s", "Unknown");
11765                         break;
11766                 }
11767         }
11768
11769         /* RTE and Driver versions */
11770         PMD_INIT_LOG(DEBUG, "%12s : %s", "DPDK",
11771                      rte_version());
11772         PMD_INIT_LOG(DEBUG, "%12s : %s", "Driver",
11773                      bnx2x_pmd_version());
11774
11775         /* Firmware versions and device features. */
11776         PMD_INIT_LOG(DEBUG, "%12s : %d.%d.%d",
11777                      "Firmware",
11778                      BNX2X_5710_FW_MAJOR_VERSION,
11779                      BNX2X_5710_FW_MINOR_VERSION,
11780                      BNX2X_5710_FW_REVISION_VERSION);
11781         PMD_INIT_LOG(DEBUG, "%12s : %s",
11782                      "Bootcode", sc->devinfo.bc_ver_str);
11783
11784         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11785         PMD_INIT_LOG(DEBUG, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11786         PMD_INIT_LOG(DEBUG, "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11787         PMD_INIT_LOG(DEBUG, "%12s : %s", "DMAE Is",
11788                      (sc->dmae_ready ? "Ready" : "Not Ready"));
11789         PMD_INIT_LOG(DEBUG, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11790         PMD_INIT_LOG(DEBUG, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11791         PMD_INIT_LOG(DEBUG, "%12s : %u", "MTU", sc->mtu);
11792         PMD_INIT_LOG(DEBUG, "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11793         PMD_INIT_LOG(DEBUG, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11794                         sc->link_params.mac_addr[0],
11795                         sc->link_params.mac_addr[1],
11796                         sc->link_params.mac_addr[2],
11797                         sc->link_params.mac_addr[3],
11798                         sc->link_params.mac_addr[4],
11799                         sc->link_params.mac_addr[5]);
11800         PMD_INIT_LOG(DEBUG, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11801         PMD_INIT_LOG(DEBUG, "%12s : %s", "State", get_state(sc->state));
11802         if (sc->recovery_state)
11803                 PMD_INIT_LOG(DEBUG, "%12s : %s", "Recovery",
11804                              get_recovery_state(sc->recovery_state));
11805         PMD_INIT_LOG(DEBUG, "%12s : CQ = %lx,  EQ = %lx", "SPQ Left",
11806                      sc->cq_spq_left, sc->eq_spq_left);
11807         PMD_INIT_LOG(DEBUG, "%12s : %x", "Switch", sc->link_params.switch_cfg);
11808         PMD_INIT_LOG(DEBUG, "\n\n===================================\n");
11809 }