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VPP-1692: move NULL pointer check
2019-05-31 Zhiyong Yangbonding: add support for numa awareness
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-30 Zhiyong Yangmpls: leverage vlib_buffer_advance
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-30 Zhiyong Yangosi_input: leverage vlib_buffer_get_current
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-29 Zhiyong Yangvxlan-gbp: prefetch encap header memory area
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-28 Zhiyong Yangsnap_input: simplify code using existing functions
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-28 Zhiyong Yangllc_input: simplify code using existing functions
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-28 Zhiyong Yanghdlc_input: simplify code using existing functions
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-27 Zhiyong Yanggeneve: encap performance enhancement
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-27 Zhiyong Yangrewrite vnet_interface_output_node_inline_gso
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-24 Zhiyong Yangvxlan-gpe: improve encap performance
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-22 Zhiyong Yangvxlan-gpe: fix CLI document error
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-21 Zhiyong Yanggeneve_input: leverage vlib_get_buffers
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-20 Zhiyong Yangbonding: clean up redundant code
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-13 Zhiyong Yangvnet: remove macro definitions
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-09 Zhiyong Yangdpdk: fix return variable size
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-06 Zhiyong Yangip4_load_balance: leverage vlib_get_buffers
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-06 Zhiyong Yangppp: simplify code using existing functions
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-05-01 Zhiyong Yangesp_encrypt: remove unnecessary code
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-04-26 Zhiyong Yangcrypto_ia32: minor change logically
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-04-24 Zhiyong Yangip4_lookup_inline: leverage vlib_get_buffers to improve...
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-04-24 Zhiyong Yangethernet_input_inline: leverage vlib_get_buffers
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-04-23 Zhiyong Yangvnet: clean up calc_checksums()
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-04-23 Zhiyong Yangdpdk_esp_encrypt: add to prefetch data
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-04-23 Zhiyong Yangipsec4-output: add pkt header and data prefetching
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-04-23 Zhiyong Yangvppinfra: fix one macro issue in clib_cpu_supports_aes()
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2019-04-17 Zhiyong YangDefault nums of RX/TX descriptors changed to 512 for...
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2018-12-13 Zhiyong Yangip4_rewrite_inline: fix variable error
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2018-11-15 Zhiyong Yangip4-input: fix prefetch data issue for tunnel decap...
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2018-11-05 Zhiyong Yangvxlan: prefetch extra one cacheline holding external...
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2018-09-07 Zhiyong Yanggeneve: fix variable initial value
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2018-09-06 Zhiyong Yangvxlan: improve encap performance
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2018-09-06 Zhiyong Yangvxlan_gpe: optimize encap performance
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2018-08-20 Zhiyong Yangvxlan_gpe_encap: fix packet len error
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2018-05-31 Zhiyong Yangfix missing void pointer explicit type cast
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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2018-05-26 Zhiyong Yangdpdk: enable RX for no-multi-seg
Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com>
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Vector Packet Processing